Integrated circuit device, method of manufacturing same, and method of generating integrated circuit layout

Abstract

The embodiment of the invention discloses an integrated circuit device, a manufacturing method thereof and a method for generating an integrated circuit layout. The IC device includes a static random access memory (SRAM) device in a substrate, the SRAM device including a first complementary field effect transistor (CFET) including a first pass gate transistor at a first height, a second CFET including a second pass gate transistor at a second height, a third CFET including a third pass gate transistor at a second height, and a fourth CFET including a fourth pass gate transistor at a third height. The second complementary field effect transistor comprises a first pull-down transistor at a first height and a first pull-up transistor at a second height, and the third complementary field effect transistor comprises a second pull-down transistor and a second pull-up transistor at the second height. Each of the first and second pull-down transistors includes a gate extending in a gate direction and including a first work function configuration, and each of the first and second pass-gate transistors includes a gate extending in the gate direction and including a second work function configuration different from the first work function configuration.

Description

Technical Field

[0001] Embodiments of this application relate to integrated circuit devices, methods for manufacturing them, and methods for generating integrated circuit layouts. Background Technology

[0002] The ongoing trend towards miniaturization in integrated circuits (ICs) is resulting in devices becoming smaller, consuming less power, yet delivering more functionality at a higher speed than earlier technologies. This miniaturization is achieved through design and manufacturing innovations related to increasingly stringent specifications. Various electronic design automation (EDA) tools are used to generate, modify, and verify semiconductor device designs while ensuring compliance with IC architecture design and manufacturing specifications. Summary of the Invention

[0003] According to one aspect of the present application, an integrated circuit (IC) device is provided, including a static random access memory (SRAM) device located in a substrate, wherein the SRAM device includes: a first complementary field-effect transistor (CFET) including a first transmission gate transistor positioned at a first height along a first direction; a second CFET including a first pull-down transistor positioned at a first height along the first direction and a first pull-up transistor positioned at a second height; a third CFET including a second pull-down transistor positioned at a first height and a second pull-up transistor positioned at a second height; and a fourth CFET including a second transmission gate transistor positioned at a first height, wherein each of the first pull-down transistor and the second pull-down transistor includes a gate extending in a second direction perpendicular to the first direction and including a first work function configuration, and each of the first transmission gate transistor and the second transmission gate transistor includes a gate extending in the second direction and including a second work function configuration different from the first work function configuration.

[0004] According to another aspect of the embodiments of this application, a method for manufacturing an integrated circuit (IC) device is provided. The method includes constructing a static random access memory (SRAM) device on the front side of a substrate. Constructing the SRAM device includes: constructing a first complementary field-effect transistor (CFET), the first CFET including a first transmission gate transistor positioned at a first height along a first direction; constructing a second CFET, the second CFET including a first pull-down transistor positioned at a first height along the first direction and a first pull-up transistor positioned at a second height; constructing a third CFET, the third CFET including a second pull-down transistor positioned at a first height and a second pull-up transistor positioned at a second height; and constructing a fourth CFET, the fourth CFET including a second transmission gate transistor positioned at a first height. Each of the first and second pull-down transistors includes a gate formed extending in a second direction perpendicular to the first direction and including a first work function configuration; and each of the first and second transmission gate transistors includes a gate formed extending in the second direction and including a second work function configuration different from the first work function configuration.

[0005] According to another aspect of the embodiments of this application, a method for generating an integrated circuit (IC) layout is provided. The method includes locating static random access memory (SRAM) cells in the IC layout, wherein the SRAM cells include: a first complementary field-effect transistor (CFET) including a first transmission gate transistor located at a first height along a first direction; a second CFET including a first pull-down transistor located at a first height along the first direction and a first pull-up transistor located at a second height; a third CFET including a second pull-down transistor located at a first height and a second pull-up transistor located at a second height; and a fourth CFET including a second transmission gate transistor located at a first height; a first pattern arranging a first work function configuration including the gates of each of the first and second pull-down transistors; a second pattern arranging a second work function configuration different from the first work function configuration including the gates of each of the first and second transmission gate transistors; and storing the IC layout including the SRAM cells in a storage device. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 This is a schematic diagram of a memory cell according to some embodiments.

[0008] Figures 2A-2C These are plan views and layout diagrams of IC devices according to some embodiments.

[0009] Figures 3A-3E These are plan views, cross-sectional views, and layout diagrams of IC devices according to some embodiments.

[0010] Figures 4A-4C These are schematic diagrams, plan views, and cross-sectional views of IC devices and layouts according to some embodiments.

[0011] Figure 5A and Figure 5B These are plan views and layout diagrams of IC devices according to some embodiments.

[0012] Figure 6 These are plan views and layout diagrams of IC devices according to some embodiments.

[0013] Figure 7 These are cross-sectional views and layout diagrams of IC devices according to some embodiments.

[0014] Figure 8 This is a flowchart of a method for manufacturing an IC device according to some embodiments.

[0015] Figure 9 This is a flowchart of a method for generating an IC layout diagram according to some embodiments.

[0016] Figure 10 It is a block diagram of a system generated based on IC layout diagrams of some embodiments.

[0017] Figure 11 This is a block diagram of an IC manufacturing system and its associated IC manufacturing process according to some embodiments. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific embodiments or instances of components, values, operations, materials, arrangements, etc., are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. Other components, values, operations, materials, arrangements, etc., may be considered. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0020] In various embodiments, integrated circuit (IC) devices, layouts, and manufacturing methods relate to static random access memory (SRAM) devices including complementary field-effect transistors (CFETs), wherein first and second transmission gate transistors are located at a first height and include gates having a first work function configuration, and first and second pull-down transistors are located at the first height and include gates having a second work function configuration different from the first work function configuration.

[0021] By including gates, transmission gate transistors, and pull-down transistors with different work function configurations, adjustable relative threshold voltage levels are achieved. This allows SRAM devices to have improved read current characteristics compared to other methods, such as those where the transmission gate transistor and pull-down transistor have the same threshold voltage level. Consequently, they can operate at lower supply levels and, for a given supply voltage level, shorten the read window corresponding to relatively higher operating speeds.

[0022] As described below, according to various embodiments, Figure 1 This is a schematic diagram of memory cell 100. Figures 2A-2C This is a plan view of the IC devices and layout diagram 200. Figures 3A-3E These are plan and cross-sectional views of the IC devices and layout diagram 300. Figures 4A-4C These are plan and cross-sectional views of the IC devices and layout diagram 400. Figure 5A and Figure 5B This is a plan view of the IC devices and layout diagram 500. Figure 6 It is a plan view of IC devices and layout diagram 600. Figure 7 It is a cross-sectional view of the IC device and layout diagram 700. Figure 8 This is a flowchart of IC manufacturing method 800. Figure 9 For example, using Figure 10 The IC layout generation system 1000 described in the figure and / or based on Figure 11 The flowchart depicts the IC manufacturing process 1100 to generate an IC layout diagram 900.

[0023] For illustrative purposes, each figure in this article, for example Figures 1-7All have been simplified. These diagrams are views of IC schematics, structures, devices, and layouts, including and excluding various features for the convenience of the discussion below. In various embodiments, except Figures 1-7 In addition to the features shown, ICs, structures, devices and / or layouts also include one or more features corresponding to power distribution structures, metal interconnects, contacts, vias, gate structures, source / drain (S / D) structures, active regions, body connections or other transistor elements, isolation structures, etc.

[0024] In each of the IC layout diagrams / devices 200-700, reference indicators denote IC device components and IC layout features used to at least partially define the corresponding IC device components during manufacturing, for example, as shown below regarding Figure 8 The methods discussed are 800 and / or the following about Figure 11 The discussion pertains to the IC manufacturing process related to the IC manufacturing system 1100. Therefore, each of the IC layout diagrams / devices 200-700 represents a view of the IC layout diagram 200-700 and the corresponding IC device 200-700.

[0025] Each of the IC layout diagrams / devices 200-700 discussed below includes some or all of the arrangements of at least one of the substrates, active regions / areas, S / D regions / structures, contacts and / or interconnect regions / structures, gate regions / structures and / or metal regions / segments, and via regions / structures discussed below.

[0026] A substrate, such as a substrate SUB, is a portion (e.g., a die) of a semiconductor or other wafer (e.g., a silicon (Si) wafer or an epitaxial Si layer) suitable for forming one or more IC devices, such as IC devices 200-600. In each embodiment discussed below, the substrate (e.g., a semiconductor substrate) includes a front side (e.g., a front side FS) and a back side (e.g., a back side BS). Within the front side FS, a first subset of IC device components is formed by a first set of manufacturing processes (e.g., front-end process (FEOL), intermediate process (MEOL), and back-end process (BEOL)). Within the back side BS, a second subset of IC device components is formed by a second set of manufacturing processes (e.g., a back-side metallization process) performed after the first set of manufacturing processes.

[0027] An active region (e.g., active region / area AA) is a region in an IC layout diagram, included during the manufacturing process as part of defining the active region, and in some embodiments also referred to as oxide diffusion or definition (OD), located directly in the substrate or in an n-well or p-well region / area, in which one or more IC device components, such as S / D structures, are formed. In some embodiments, the active region is an n-type or p-type active region of a stacked complementary field-effect transistor (CFET) or another transistor configuration including a gate region / structure.

[0028] In various embodiments, the active region (structure) includes one or more of the following: semiconductor materials (e.g., silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), etc.), dopant materials (e.g., boron (B), aluminum (Al), phosphorus (P), arsenic (As), gallium (Ga)), or other suitable materials.

[0029] In some embodiments, the active region is a region included in the IC layout during the manufacturing process, serving as part of defining a nanosheet structure (e.g., a continuous volume of one or more layers of semiconductor material with n-type or p-type doping). In various embodiments, a single nanosheet layer comprises a single layer or multiple layers of a given semiconductor material.

[0030] An S / D region / structure (e.g., S / D region / structure SD) is a region in an IC layout diagram that, as a part defining the S / D structure (also referred to as a semiconductor structure in some embodiments), is configured to have a doping type opposite to that of the corresponding active region / region. In some embodiments, the S / D region / structure is configured to have a lower resistivity than a portion of the corresponding active region / region of an adjacent channel feature (e.g., a portion of the corresponding active region / region of a CFET or other transistor). In some embodiments, the S / D region / structure includes one or more portions with doping concentrations greater than one or more doping concentrations present in the corresponding channel feature. In some embodiments, the S / D region / structure includes one or more epitaxial regions of a semiconductor material (e.g., Si, SiGe, and / or silicon carbide SiC). An S / D region / structure (also referred to as an S / D terminal in some embodiments) can refer individually or collectively to the source or drain, depending on the context.

[0031] Contact areas / structures or interconnect areas / structures, such as contact areas / structures CT or interconnect areas / structures ND or nodes, are conductive regions in an IC layout included during manufacturing, serving as portions defining contact structures or interconnect structures (also referred to as conductive segments or metal-class defined (MD) wires, traces, or structures in and / or on the substrate). In some embodiments, the contact areas or interconnect areas overlap with active regions at locations of one or more S / D regions in the IC layout, and the corresponding contact structures or interconnect structures contact and are electrically connected to one or more S / D structures in the active regions.

[0032] In some embodiments, the contact structure or interconnect structure includes a portion of at least one metal layer (e.g., a contact layer) that overlays and contacts the substrate and has a sufficiently small thickness to form an insulating layer between the contact structure or interconnect structure and the overlay metal layer (e.g., a first metal layer). In various embodiments, the MD segment includes one or more of copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn), aluminum (Al), or other metals or materials suitable for providing low-resistance electrical connections (i.e., resistance levels below a predetermined threshold, which corresponds to one or more tolerance levels based on the effect of resistance on circuit performance) between IC structural elements.

[0033] In various embodiments, the contact structure or interconnect structure includes portions of a substrate and / or epitaxial layer having a doping level (e.g., based on an implantation process sufficient to give the structure a low resistance level). In various embodiments, the doped contact structure or interconnect structure includes one or more dopant materials with a doping concentration of about 1*10⁻⁶. 16 / cubic centimeter (cm) -3 (or higher).

[0034] In some embodiments, the manufacturing process includes two or more contact structure or interconnect structure layers, contact regions / structures, or interconnect regions / structures, such as contact region / structure CT or interconnect region / structure ND or Node, which refers to one or more of the two or more contact or interconnect structure layers in the manufacturing process. In some embodiments, the contact structure or interconnect structure is configured to be electrically connected to a single S / D structure of a p-type or n-type FET of the CFET and electrically isolated from the S / D structure of another p-type or n-type FET of the CFET. In some embodiments, the contact structure or interconnect structure (also referred to as MD local interconnect (MDLI) or local interconnect (LI)) is configured to be electrically connected to the S / D structures of the p-type FET and the n-type FET of the CFET.

[0035] A gate region / structure (e.g., gate region / structure G), also referred to as gate G in some embodiments, is an area included in the IC layout diagram during the manufacturing process as part of defining the gate structure. A gate structure is a volume comprising one or more conductive segments (e.g., gate electrodes) made of one or more conductive materials, such as polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials, substantially surrounded by one or more insulating materials. These conductive segments are thus configured to control the voltage supplied at one or more adjacent gate dielectric layers (e.g., adjacent to or surrounding one or more channel regions in a corresponding active region).

[0036] The gate dielectric layer, such as the gate dielectric layer GD of the gate structure G, is a volume comprising one or more insulating materials, such as silicon dioxide, silicon nitride (Si3N4), and / or one or more other suitable materials, such as low-k materials with a k value less than 3.8 or high-k materials with a k value greater than 3.8 or 7.0, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), or titanium oxide (TiO2), suitable for providing high resistance, i.e., a resistance level above a predetermined threshold, which corresponds to one or more tolerance levels based on the effect of resistance on circuit performance in the IC structure.

[0037] A work function configuration (e.g., work function configurations WF1-WF4) is one or more regions in an IC layout diagram included in the manufacturing process, defining a layer or multiple layers of work function material located within the transistor gate electrode adjacent to one or more corresponding gate dielectric layers.

[0038] One or more layers of work function materials include n-type and / or p-type work function materials having one or more thicknesses, concentration levels, dopants, impurities, etc., configured to increase or decrease the work function of the gate electrode by a target value compared to the work function of an equivalent gate electrode that does not include one or more layers of work function material. Non-limiting examples of work function materials include Ti, Ag, Al, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, and Zr.

[0039] The threshold voltage level of a transistor is a function of operating conditions (e.g., voltage bias level and / or temperature, and the work function of the corresponding gate electrode). For a predetermined set of operating conditions, such as within a predetermined voltage and / or temperature range, a given target value for an increase or decrease in the work function, compared to the threshold voltage level of an equivalent transistor having an equivalent gate electrode that does not include one or more layers of work function material, translates to an increase or decrease in the threshold current level of the transistor including the corresponding gate.

[0040] Thus, each work function configuration corresponds to a predetermined threshold voltage level of the corresponding transistor, making multiple work function configurations available for defining a predetermined number of threshold voltage levels.

[0041] In some embodiments, the gate region / structure corresponds to a dummy gate region / structure. In some embodiments, the dummy gate region / structure includes a gate electrode electrically connected (e.g., bonded) to one or more features, such as a power rail or other metal segment or an adjacent instance of the S / D region / structure, thereby designing to turn off transistors corresponding to the dummy gate region / structure and the overlying / underlying active region / region. In some embodiments, the dummy gate region / structure overlapping / covering the edge of the active region / region is referred to as a continuous polysilicon-defined edge (CPODE) region / structure on oxide.

[0042] A diced gate region (e.g., diced gate region CPO), also referred to in some embodiments as a diced polysilicon region, is a region in the IC layout diagram included in the manufacturing process, serving as a portion defining a discontinuity in a given gate structure, such as a portion etched away after the gate electrode is formed, thereby resulting in adjacent and aligned gate electrode segments being electrically isolated from each other.

[0043] Metal lines or regions, such as front metal regions / segments VSS, BL, or BLB, or back metal regions / segments BMO_VDD or BMO_WL, are regions in an IC layout diagram included in a manufacturing process. As part of defining a metal line or segment, it includes one or more conductive materials in a given front or back metal layer of the manufacturing process, such as polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials.

[0044] In some embodiments, a metal region / segment, such as metal region / segment VSS, BL, or BLB, corresponds to the first or lowest front metal layer of the manufacturing process (also referred to in some embodiments as metal zero layer or front metal zero layer) (e.g., metal layer M0), or a second or higher level front metal layer. In some embodiments, the second front metal layer is referred to as metal layer one or front metal layer one, and the second back metal region / segment is referred to as metal region one / segment.

[0045] In some embodiments, the back metal region / segment, such as metal region / segment BMO_VDD or BMO_WL, corresponds to the first or lowest back metal layer of the manufacturing process (also referred to as the back metal zero layer in some embodiments), or the second or higher level back metal layer.

[0046] In some embodiments, the metal section / segment corresponds to a component of the power distribution network and is configured to distribute one or both of a power supply voltage (e.g., power supply voltage VDD) and / or a reference or ground voltage (e.g., reference voltage VSS). The power distribution network component is electrically connected to one or more features (e.g., additional metal sections / segments and / or vias / structures) configured to distribute the corresponding power supply or reference voltage and is electrically isolated from IC components outside the power distribution network.

[0047] A via region / structure, such as via region or structure VD, VG, VDR, or BMO_V, also referred to as a via or interconnect in some embodiments, is a region in an IC layout diagram included during manufacturing. As part of defining the via / interconnect structure, it includes one or more conductive materials configured to provide an electrical connection between a first conductive structure (e.g., an overlay conductive structure, such as a front metal segment VSS, BL, or BLB, or a back metal segment BMO_VDD or BMO_WL) and a second conductive structure aligned in the Z direction with the first conductive structure (e.g., an underlay conductive structure, such as a metal segment, the gate electrode of a gate structure G, a contact structure CT, an interconnect structure ND, or an S / D structure SD).

[0048] In some embodiments, the via region / structure VD corresponds to the underlying conductive structure, namely the S / D region / structure SD, the contact region / structure CT, or the interconnect region / structure ND.

[0049] Figure 1 This is a schematic diagram of the SRAM cells 100 included in each IC layout / device 200, 300, and 500. Figures 2A-2C Each of these includes an IC layout / device 200 and planar views in the X and Y directions. Figure 3A and Figure 3E Each of these includes an IC layout / device 300 and planar views in the X and Y directions. Figures 3B-3D Including along Figure 3A IC layout diagrams and cross-sectional views of device 300 along A-A', B-B', and C-C' lines, X and Z directions.

[0050] Figure 4A This is a schematic diagram of SRAM cell 400, also referred to in some embodiments as IC layout diagram / device 400. Figure 4B This includes IC layout diagrams, device 400 diagrams, and planar views in the X and Y directions. Figure 4C Including along Figure 4B IC layout diagram or cross-sectional view of device 400 along lines D-D' and X and Z directions. Figure 5A and Figure 5B Each of these includes an IC layout diagram and device 500, as well as plan views in the X and Y directions. Figure 6 Includes IC layout diagrams and device 600, as well as planar diagrams in the X and X directions. Figure 7 Includes gate structure 700 and cross-sectional views in the X and Z directions (also referred to as IC layout / device 700 in some embodiments).

[0051] In some cases, for clarity, Figures 2A-7 Not all instances of each feature in IC layout diagrams / devices 200-700 are marked.

[0052] like Figures 1-5B As shown, each of the IC layout diagrams / devices 200-500 includes one or more instances of a six-transistor SRAM (6T SRAM) cell, and IC layout diagram / device 600 includes a seven-transistor SRAM (7T SRAM) cell. In each embodiment, each SRAM cell includes a total of four CFETs arranged as described below.

[0053] In some embodiments, IC layout diagrams 200-600 correspond to a single instance of an SRAM cell configured to be stored in a storage device (e.g., a cell library, such as cell library 1007 discussed below with respect to IC layout diagram generation system 1000), which at least partially defines the corresponding SRAM device 200-600 in the corresponding region of an IC manufactured based on that cell.

[0054] In some embodiments, IC layout diagrams 200-600 correspond to multiple instances of SRAM cells configured to be stored in storage devices (e.g., layout libraries, such as layout diagram 1009 discussed below with respect to IC layout diagram generation system 1000), which at least partially define the corresponding multiple instances of SRAM devices 200-600 within one or more corresponding regions of an IC manufactured based on the IC layout diagram.

[0055] The features within a given instance of IC layout / device 200, 300, or 500 are based on Figure 1 The schematic diagram depicts the configuration of the SRAM cell 100. (See attached diagram.) Figure 1 As shown, SRAM cell 100 corresponds to a 6TSRAM device, which includes two series connections of a p-type pull-up transistor PU and an n-type pull-down transistor PD cross-coupled between a power supply voltage node VDD and a reference voltage node VSS. Corresponding instances of internal node ND (corresponding to one or more contacts and / or interconnect regions / structures ND) are coupled to bit lines BL / BLB via instances of n-type transmission gate transistor PG, each instance including a gate coupled to word line WL. In some embodiments, one or both instances of pull-down transistor PD are p-type transistors, and / or one or both instances of transmission gate transistor PG (also referred to as transmission gate PG in some embodiments) are p-type transistors.

[0056] The features within a given instance of the IC layout / device 400 are based on Figure 4A The schematic diagram depicts the configuration of the SRAM cell 400. (See attached diagram.) Figure 4AAs shown, SRAM cell 400 corresponds to a 6T-SRAM device, which includes two series connections of an n-type pull-up transistor PU and a p-type pull-down transistor PD cross-coupled between the power supply voltage node VDD and the reference voltage node VSS. A corresponding instance of the internal node ND is coupled to bit lines BL / BLB via an instance of a p-type transmission gate transistor PG, each instance including a gate coupled to the word line WL.

[0057] The characteristics of a given instance of IC layout diagram / device 600 are based on Figure 1 The schematic diagram of the SRAM cell 100 depicted shows a configuration in which a p-type read transfer gate transistor (RPG), also referred to in some embodiments as a read transfer gate RPG, is added, through which an instance of node ND is coupled to a read bit line (not shown). In some embodiments, the read transfer gate transistor (RPG) is an n-type transistor.

[0058] In operation, instances of IC devices 200-600 are configured to receive data bits from bit lines BL / BLB / output data bits to bit lines BL-BLB via transmission gate transistor PG in response to a word line signal received on word line WL, and store the data bits as complementary pairs on internal node ND. In some embodiments, bit lines BL / BLB are referred to as complementary bit lines BL / B / BLB, bit line pairs BL / BLB, or complementary bit line pairs BL / BLB.

[0059] exist Figures 2A-6 In the illustrated embodiments, each corresponding IC layout / device 200-600 includes a first CFET, which includes a first instance of a transmission gate transistor PG located at a first height along the Z direction; a second CFET, which includes a first pull-down transistor located at a first height along the Z direction and a first pull-up transistor located at a second height; a third CFET, which includes a second pull-down transistor located at a first height and a second pull-up transistor located at a second height; and a fourth CFET, which includes a second transmission gate transistor located at a first height.

[0060] exist Figures 2A-6 In the illustrated embodiment, the first height is farther than the second height along the positive Z-direction. In some embodiments, the second height is farther than the first height along the positive Z-direction.

[0061] Each of the first and second pull-down transistors includes an instance of a gate G extending in the X direction and including a work function configuration WF1, and each of the first and second transmission gate transistors includes a second work function configuration WF2 extending in the X direction and including a work function configuration different from WF1.

[0062] like Figures 2A-7As shown, the given work function configurations WF1-WF4 refer to the patterns in the corresponding IC layout diagrams 200-600, or to the corresponding arrangement of work function materials in the corresponding IC devices 200-600.

[0063] like Figure 2C , Figure 3E , Figure 5B and Figure 6 As shown, the work function configurations WF1-WF4 patterns include one or more regions of the corresponding IC layout diagrams 200-600, wherein each instance of the corresponding n-type or p-type transistor is configured to include one or more corresponding work function materials in the corresponding one or more instances of the IC device 200-600.

[0064] In various embodiments, one or more regions of the work function configuration WF1-WF4 pattern in the IC layout are arranged based on one or more SRAM cells previously configured to include the corresponding work function configuration WF1-WF4 placed on the IC layout, or based on one or more SRAM cells placed on the IC layout, and then the corresponding work function configuration WF1-WF4 is applied to the previously placed one or more SRAM cells.

[0065] Figure 7 An IC layout diagram / device 700 is depicted, which is a non-limiting example of a gate G instance, including one or more work function materials of one of WF1-WF4 configured according to the work function. Figure 7 In this context, it is usually represented as the work function configuration WF.

[0066] exist Figure 7 In the illustrated embodiment, the IC layout / device 700 (also referred to as gate 700 in some embodiments) includes one or more work function materials surrounding three instances of the gate dielectric GD (each instance surrounding a corresponding channel region of the active region / region AA).

[0067] like Figures 2A-2C As shown, the IC layout / device 200 includes four CFETs (corresponding to instances of gate G) arranged in two rows extending along the X direction, wherein the first pull-down transistor PD is aligned with the first transmission gate transistor PG in the X direction and with the second transmission gate transistor PG in the Y direction, and the second pull-down transistor PD is aligned with the first transmission gate transistor in the Y direction and with the second transmission gate transistor PG in the X direction.

[0068] Figure 2A and Figure 2B Each of these depicts a non-limiting example of an IC layout diagram / device 200, including the internal node ND configuration on the back side BS of the substrate SUB (unlabeled). Figure 2AIn the illustrated embodiment, the internal node ND includes instances of the back contact area / structure CT and the via area / structure BMO_V. Figure 2B In the illustrated embodiment, the internal node ND includes instances of interconnect region / structure ND. Other internal node ND configurations are also within the scope of this disclosure.

[0069] like Figures 3A-3E As shown, the IC layout / device 300 includes four CFETs arranged in two rows extending along the X direction (corresponding to an example of a gate G), wherein the first pull-down transistor PD is aligned with the second pull-down transistor PD in the X direction and with the first transmission gate transistor PG in the Y direction, and the second transmission gate transistor PG is aligned with the first transmission gate transistor PG in the X direction and with the second pull-down transistor PD in the Y direction.

[0070] Figure 3A A non-limiting example of an IC layout / device 300 is depicted, including the internal node ND configuration on each of the front FS and back BS sides of the substrate SUB (unlabeled). Figure 3A In the illustrated embodiment, the internal node ND includes corresponding front and back instances of interconnect region / structure ND and via region / structure VG and VDR. Other front and / or back internal node ND configurations are also within the scope of this disclosure.

[0071] Figure 3A Non-limiting examples of the front conductive component reference voltage line VSS and bit lines BL and BLB, and the back conductive component power supply voltage line BM0_VDD and word line BM0_WL are further depicted, each electrically connected to the IC layout / device 300 through corresponding via regions / structures VD and VG.

[0072] like Figures 3B-3D As shown, instances of via regions / structures VD and VDR extend in the Z direction through one or more dielectric layers, such as interlayer dielectric layers ILD1 and ILD2. Each instance of the transmission gate transistor PG and the pull-down transistor PD includes an instance of the gate G and two S / D regions SD (including an n-type epitaxial region / layer n-epi), and each instance of the pull-up transistor PU includes a gate G and two S / D regions SD (including a p-type epitaxial region / layer p-epi). The region of the substrate SUB at the same height as the pull-up transistor PU along the Z direction is not included in the transistor but includes the dielectric layer ILD.

[0073] like Figures 4A-4C As shown, IC layout diagram / device 400 includes four CFETs, which are arranged similarly to IC layout diagram-device 300, except that the transmission gate transistor PG and the pull-down transistor PD are implemented as p-type transistors instead of n-type transistors, and the pull-up transistor PU is also implemented as an n-type transistor instead of a p-type transistor.

[0074] Therefore, the positioning of the transmission gate transistor PG, pull-down transistor PD, and the electrical connections to the power supply voltage VDD, reference voltage VSS, bit lines Bl and BLB, and word line WL relative to the Z-direction is opposite to their positioning in the IC layout diagram / device 300.

[0075] Since IC layout / devices 300 and 400 have the same positioning relative to the X and Y directions, therefore Figure 3E The work function configuration pattern of IC layout diagram / device 300 depicted in the diagram is applicable to IC layout diagram / device 400.

[0076] like Figure 5A and Figure 5B As shown, the IC layout / device 500 includes four CFETs arranged in a single column extending along the Y direction, wherein pull-down transistors PD are located between transmission gate transistors PG.

[0077] like Figure 5A As shown, the IC layout / device 500 includes an internal node ND configuration on each of the front FS and back BS sides of the substrate SUB (unlabeled). Figure 3A In the illustrated embodiment, the internal node ND includes corresponding front and back instances of the contact area / structure CT, interconnect area / structure ND, and via area / structure VD and VG. Other front and / or back internal node ND configurations are also within the scope of this disclosure.

[0078] like Figure 6 As shown, IC layout / device 600 includes four CFETs with an arrangement similar to IC layout / device 500, and a read transmission gate transistor RPG is added at the same height as the pull-up transistor PU. The pull-up transistor PU includes an instance of a gate G with a work function configuration WF3, and the read transmission gate transistor RPG includes an instance of a gate G with a work function configuration WF4, which is different from the work function configuration WF3.

[0079] In various embodiments, the work function configuration WF3 may be the same as or different from the work function configuration WF1, and / or the work function configuration WF4 may be the same as or different from the work function configuration WF2.

[0080] With the above configuration, each of the IC layout diagrams / devices 200-600 includes an SRAM device, which includes a CFET, wherein the first and second pull-down transistors PD are positioned at a first height in the Z direction and include a gate G having a work function configuration WF1, the first and second transmission gate transistors PG are located at the first height and include a gate G having a work function configuration WF2 different from the work function configuration WF1.

[0081] By including gates G with different work function configurations WF1 and WF2, the transmission gate transistor PG and pull-down transistor PD can have adjustable relative threshold voltage levels, enabling each IC layout / device 200-600 to have improved read current characteristics compared to other methods (e.g., methods where the transmission gate and pull-down transistor have the same threshold voltage level). This allows operation at lower supply levels and, for a given supply voltage level, a shorter read window corresponding to a relatively higher operating speed.

[0082] In some embodiments, for a given set of operating conditions, the pull-down transistor PD has a first saturation current IsatPD, the transmission gate transistor PG has a second saturation current IsatPG, and the ratio of IsatPD to IsatPG (referred to as the beta ratio in some embodiments) corresponds to the read window of the SRAM device, and an increase in the beta ratio corresponds to an increase in operating speed.

[0083] For a given set of operating conditions, the values ​​of the saturation currents IsatPD and IsatPG are based on the threshold voltages of the pull-down transistor PD and the transmission gate transistor PG, respectively, controlled by the work function configurations WF1 and WF2. With the above configuration, each of the IC layouts / devices 200-600 can achieve a beta ratio greater than 1, thereby realizing the aforementioned benefits.

[0084] Figure 8 This is a flowchart of a method 800 for manufacturing an IC device according to some embodiments. Method 800 is operable to form the above-described... Figures 1-7 Some or all of one or more instances of the IC devices 200-600 discussed.

[0085] In some embodiments, some or all of the operations of performing method 800 are portions of constructing multiple integrated circuit devices (e.g., transistors, logic gates, memory cells, interconnect structures, and / or other suitable devices) by performing multiple manufacturing operations (e.g., photolithography, diffusion, deposition, etching, planarization, or one or more other operations suitable for constructing multiple IC devices in a semiconductor substrate).

[0086] In some embodiments, the operation of method 800 is as follows: Figure 8 The operations are performed in the order shown. In some embodiments, the operation of method 800 is consistent with... Figure 8 The order shown is different from the sequence of execution. In some embodiments, one or more additional operations are performed before, during, and / or after the operation of method 800. In some embodiments, performing some or all of the operations of method 800 includes performing the following regarding IC manufacturing system 1100 and Figure 11 One or more operations are being discussed.

[0087] At operation 802, in some embodiments, a substrate, such as a semiconductor substrate, is provided. In some embodiments, providing a substrate includes providing the above-mentioned... Figures 1-7 Substrate SUB under discussion.

[0088] At operation 804, an SRAM device is constructed on the front side of the substrate, the SRAM device including first to fourth CFETs. The first to fourth CFETs are constructed by constructing the following structure: a first CFET including a first transmission gate transistor positioned at a first height along a first direction; a second CFET including a first pull-down transistor located at the first height and a first pull-up transistor located at a second height along the first direction; a third CFET including a second pull-down transistor positioned at the first height and a second pull-up transistor positioned at the second height; and a fourth CFET including a second transmission gate transistor positioned at the first height. Each of the first and second pull-down transistors includes a gate formed extending in a second direction perpendicular to the first direction and including a first work function configuration, and each of the first and first transmission gate transistors includes a gate formed extending in the second direction and including a second work function configuration different from the first work function configuration.

[0089] In some embodiments, constructing an SRAM device includes constructing the above-mentioned... Figures 1-7 One of the IC devices 200-600 discussed. In some embodiments, constructing an SRAM device includes constructing a plurality of SRAM devices, such as those mentioned above. Figures 1-7 One or more of the multiple IC devices 200-600 discussed.

[0090] In some embodiments, forming a gate extending along a second direction and including first and second work function configurations includes instances of forming a gate G, wherein instances of gate G include work function configurations WF1 or WF2 and / or include work function configurations WF3 or WF4, as described above. Figures 1-7 The subject of discussion.

[0091] In some embodiments, the first direction extends from the back side of the substrate to the front side of the substrate in a positive direction, and constructing each of the first and second pull-down transistors and the first and second transmission gate transistors includes constructing the first and second pull-down transistors and the first and second transmission gate transistors at a first height, the first height being further along the first direction in the positive direction (e.g., more along the positive Z direction) than the second height, as described above regarding Figures 2A-7 As stated above.

[0092] In some embodiments, constructing each of the first and second pull-up transistors includes constructing a p-type transistor, and constructing the first and second pull-down transistors and each of the first and second transmission gate transistors includes constructing an n-type transistor, for example, as described above regarding Figures 1-7 As stated above.

[0093] In some embodiments, constructing the first and second pull-down transistors includes aligning the first pull-down transistor with the first transmission gate transistor in a second direction and aligning it with the second transmission gate transistor in a third direction perpendicular to each of the first and second directions, and aligning the second pull-down transistor with the first transmission gate transistor in a third direction and aligning it with the second transmission gate transistor in the second direction. For example, as described above regarding IC layout / device 200 and Figures 2A-2C As stated above.

[0094] In some embodiments, constructing the first and second pull-down transistors includes aligning the first pull-down transistor with the second pull-down transistor in a second direction and with the first transmission gate transistor in a third direction upward, and aligning the second transmission gate transistor with the first transmission gate transistor in a second direction and with the second pull-down transistor in a third direction upward, for example, as described above regarding IC layout diagrams / devices 300 and 400. Figures 3A-4C As stated above.

[0095] In some embodiments, constructing the first and second pull-down transistors includes aligning the first and second pull-down transistors and the first and second transmission gate transistors to each other in a third-order direction, with the first and second pull-down transistors located between the first and second transmission gate transistors, for example, as described above regarding IC layout diagrams / devices 500 and 600. Figures 5A-6 As stated above.

[0096] In some embodiments, constructing each of the first and second pull-up transistors includes forming a gate extending along a second direction and including a third work function configuration, and constructing the first CFET includes constructing a read-transfer gate transistor located at a second height (by forming a fourth work function configuration extending along the second direction and including a configuration different from the third work function configuration), for example, as described above regarding IC layout / device 600 and Figure 6 As stated above.

[0097] The construction of an SRAM device including the first to fourth CFETs involves performing one or more of a number of manufacturing processes, including photolithography, diffusion, implantation, deposition, plasma treatment, etching, planarization, spin coating, soft baking, exposure, post-baking, development, rinsing, drying, or other suitable operations.

[0098] At operation 806, in some embodiments, an electrical connection to the SRAM device is formed. In some embodiments, forming the electrical connection includes forming one or more front-side and / or back-side conductors, for example, as described above regarding Figures 1-7 One or more instances of the bit line BL / BLB, word line WL, power supply voltage line VDD, and / or reference voltage line VSS.

[0099] In some embodiments, forming an electrical connection includes forming one or more front and / or back vias, for example, as described above regarding Figures 1-7 The vias corresponding to one or more instances of the bit lines BL / BLB, word lines WL, power supply voltage lines VDD, and / or reference voltage lines VSS discussed.

[0100] Forming an electrical connection involves performing multiple manufacturing operations, including depositing and patterning one or more photoresist layers, performing one or more etching processes, and performing one or more deposition processes, thereby configuring one or more conductive materials to form multiple consecutive low-resistance structures.

[0101] By performing some or all of the operations of method 800, an IC device is manufactured, wherein the SRAM device includes first and second transmission gate transistors located at a first height and including gates having a first work function configuration, and first and second pull-down transistors located at a first height and including gates having a second work function configuration different from the first work function configuration, thereby enabling the aforementioned benefits of IC devices 200-700 to be achieved.

[0102] Figure 9 This is a flowchart of a method 900 for generating an IC layout diagram according to some embodiments, such as those described above. Figures 1-7 One or more instances of one or more of the IC layout diagrams 200-600 discussed.

[0103] In some embodiments, generating an IC layout diagram includes generating an IC layout diagram corresponding to an IC device, for example, manufacturing the aforementioned IC based on the generated IC layout diagram. Figures 1-7 One or more of the IC devices 200-600 discussed.

[0104] In some embodiments, some or all of method 900 is executed by the computer's processor, for example, as shown below. Figure 10 The processor 1002 of the IC layout generation system 1000 discussed.

[0105] Some or all of the operations of method 900 can be performed in the design room (see below for example). Figure 11 The design process is carried out in part of the design room (1120) for discussion.

[0106] In some embodiments, the operation of method 900 is as follows: Figure 9 The operations of method 900 are executed in the order shown. In some embodiments, the operations of method 900 are performed simultaneously and / or in conjunction with... Figure 9 The sequences shown are executed in different orders. In some embodiments, one or more operations are performed before, between, during, and / or after one or more operations of method 900.

[0107] At operation 902, in some embodiments, the first to fourth CFETs of the SRAM cell are arranged by including first and second transmission gate transistors in the first row and first and second pull-down transistors in the second row, for example, as described above regarding IC layout diagrams / devices 300 and 400. Figures 3A-4C The subject of discussion.

[0108] In some embodiments, the first to fourth CFETs of the SRAM cells arranged by including first and second transmission gate transistors in the first row and first and second pull-down transistors in the second row include arranging each of the first and second transmission gate transistors and the first and second pull-down transistors as an n-type transistor, for example, as described above regarding IC layout diagram / device 300 and Figures 3A-3E As stated above.

[0109] In some embodiments, the first to fourth CFETs of the SRAM cells arranged by including first and second transmission gate transistors in the first row and first and second pull-down transistors in the second row include arranging each of the first and second transmission gate transistors and the first and second pull-down transistors as a p-type transistor, for example, as described above regarding IC layout diagram / device 400 and Figures 4A-4C As stated above.

[0110] At operation 904, in some embodiments, an SRAM cell including first to fourth CFETs is positioned in the IC layout diagram, which includes first and second transmission gate transistors and first and second pull-down transistors located at the same height. In some embodiments, positioning the SRAM cell in the IC layout diagram includes positioning the above-mentioned... Figures 1-7 One or more instances of one or more of the IC layout diagrams 200-600 discussed.

[0111] In some embodiments, locating SRAM cells in an IC layout diagram includes locating SRAM cells comprising first to fourth CFETs arranged in two rows and two columns, for example, as described above regarding IC layout diagrams 200-400 and Figures 2A-4C As stated above.

[0112] In some embodiments, locating SRAM cells in an IC layout diagram includes locating SRAM cells comprising first to fourth CFETs arranged in a single column, for example, as described above regarding IC layout diagrams 500 and 600. Figures 5A-6 As stated above.

[0113] In some embodiments, locating SRAM cells in an IC layout diagram includes locating SRAM cells comprising two or more work functions, for example, as described above regarding... Figures 1-7 The work function configurations discussed are two or more of WF1-WF4.

[0114] In some embodiments, as described above regarding Figures 1-7 The method of locating SRAM cells in an IC layout diagram includes locating multiple SRAM cell instances in one or more IC layout diagrams 200-600.

[0115] In some embodiments, locating SRAM cells in an IC layout diagram includes arranging one or more electrical connections to the SRAM cells, such as one or more connections corresponding to power supply voltage VDD, reference voltage VSS, bit lines BL / BLB, and / or word lines WL, as described above regarding... Figures 1-7 As stated above.

[0116] At operation 906, in some embodiments, a first pattern is arranged including a first work function configuration of each of the first and second pull-down transistors. In some embodiments, the first pattern arranged including the first work function configuration of each of the first and second pull-down transistors includes an arrangement consistent with the above description. Figures 1-7 The work function configuration WF1 is discussed, corresponding to the first pattern.

[0117] In some embodiments, the first pattern arranging the first work function configuration of each of the first and second pull-down transistors includes an arrangement consistent with the above description. Figure 6 The third pattern corresponding to the work function configuration WF3 is discussed.

[0118] At operation 908, in some embodiments, a second pattern is arranged including a second work function configuration of each of the first and second transmission gate transistors. In some embodiments, the second pattern arranged including the second work function configuration of each of the first and second transmission gate transistors includes an arrangement consistent with the above description. Figures 1-7 The work function configuration WF2 is discussed in relation to the second pattern.

[0119] In some embodiments, the second pattern arranging the second work function configuration of each of the first and second transmission gate transistors includes an arrangement consistent with the above description. Figure 6 The fourth pattern corresponding to the work function configuration WF4 is discussed.

[0120] At operation 910, in some embodiments, an IC layout diagram including SRAM cells is stored in a storage device. In some embodiments, storing the IC layout diagram in a storage device includes storing the above-mentioned... Figures 1-7 One or more instances of one or more of the IC layout diagrams 200-600 discussed are stored in a storage device.

[0121] In some embodiments, storing an IC layout diagram in a storage device includes storing the IC layout diagram in a non-volatile computer-readable storage medium or a database, and / or includes storing the IC layout diagram via a network. In some embodiments, storing the IC layout diagram in a storage device includes storing the IC layout diagram in a cell library 1007 or layout diagram 1009 and / or storing it via the network 1014 of the IC layout diagram generation system 1000, as will be referred to below. Figure 10 Let's have a discussion.

[0122] At operation 912, in some embodiments, one or more manufacturing operations, one or more photolithography exposures, are performed based on the IC layout diagram. (The above is in conjunction with...) Figure 8 Combined with the following text Figure 11 Non-limiting examples of performing one or more manufacturing operations (e.g., one or more photolithography exposures) based on an IC layout diagram are discussed.

[0123] By performing some or all of the operations of method 900, an IC layout diagram corresponding to the IC device is generated, wherein the first and second transmission gate transistors are located at a first height and include gates having a first work function configuration, and the first and second pull-down transistors are located at a first height and include gates having a second work function configuration different from the first work function configuration, thereby enabling the benefits discussed above regarding IC devices 200-700 to be realized.

[0124] Figure 10 This is a block diagram of an IC layout generation system 1000 according to some embodiments. The method for designing IC layouts described herein is implementable according to one or more embodiments, for example, using the IC layout generation system 1000 according to some embodiments.

[0125] In some embodiments, the IC layout generation system 1000 is a general-purpose computing device including a hardware processor 1002 and a non-transitory computer-readable storage medium 1004. Among other things, the storage medium 1004 is also encoded with computer program code 1006, i.e., a set of executable instructions. Execution of the instructions 1006 by the hardware processor 1002 represents (at least partially) an electronic design automation (EDA) tool that implements part or all of the methods, such as those described above. Figure 6 The method 600 described is for generating IC layout diagrams (hereinafter referred to as the process and / or method).

[0126] Processor 1002 is electrically coupled to computer-readable storage medium 1004 via bus 1008. Processor 1002 is also electrically coupled to I / O interface 1010 via bus 1008. Network interface 1012 is also electrically connected to processor 1002 via bus 1008. Network interface 1012 is connected to network 1014, enabling processor 1002 and computer-readable storage medium 1004 to be connected to external components via network 1014. Processor 1002 is configured to execute computer program code 1006 encoded in computer-readable storage medium 1004 to make IC layout generation system 1000 available for performing part or all of the processes and / or methods. In one or more embodiments, processor 1002 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0127] In one or more embodiments, the computer-readable storage medium 1004 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 1004 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 1004 includes optical disc read-only memory (CD-ROM), optical disc read / write (CD-R / W), and / or digital video optical disc (DVD).

[0128] In one or more embodiments, the computer-readable storage medium 1004 stores computer program code 1006 configured to enable the IC layout generation system 1000 (where such execution representation (at least partially) EDA tool) to perform some or all of the said processes and / or methods. In one or more embodiments, the computer-readable storage medium 1004 also stores information that facilitates the performance of some or all of the said processes and / or methods.

[0129] In one or more embodiments, the computer-readable storage medium 1004 stores units including those disclosed herein (e.g., those mentioned above regarding...). Figures 1-7 The memory cells discussed (200-600) are in cell library 1007.

[0130] In one or more embodiments, the computer-readable storage medium 1004 stores a layout diagram 1009, including the IC layout diagrams disclosed herein, such as those described above. Figures 1-7 IC layout diagram of memory cells 200-600 under discussion.

[0131] The IC layout generation system 1000 includes an I / O interface 1010. The I / O interface 1010 is coupled to external circuitry. In one or more embodiments, the I / O interface 1010 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to the processor 1002.

[0132] The IC layout generation system 1000 also includes a network interface 1012 coupled to a processor 1002. The network interface 1012 allows the system 1000 to communicate with a network 1014 to which one or more other computer systems are connected. The network interface 1012 includes a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the processes and / or methods are implemented in two or more IC layout generation systems 1000.

[0133] The IC layout generation system 1000 is configured to receive information via I / O interface 1010. The information received via I / O interface 1010 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 1002. The information is transmitted to processor 1002 via bus 1008. The IC layout generation system 1000 is also configured to receive UI-related information via I / O interface 1010. This information is stored as a user interface (UI) 1042 in computer-readable medium 1004.

[0134] In some embodiments, part or all of the process and / or method is implemented as a standalone software application executed by a processor. In some embodiments, part or all of the process and / or method is implemented as a software application as part of an additional software application. In some embodiments, part or all of the process and / or method is implemented as a plug-in to a software application. In some embodiments, at least one of the process and / or method is implemented as a software application as part of an EDA tool. In some embodiments, part or all of the process and / or method is implemented as a software application used by an IC layout generation system 1000. In some embodiments, software applications such as those available from CADENCE DESIGN SYSTEMS Inc. are used. Use tools or another suitable layout generation tool to generate layout diagrams that include standard cells.

[0135] In some embodiments, these processes are implemented as the functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, one or more of external / removable and / or internal / built-in storage or memory units, such as optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROMs), RAMs, memory cards, etc.

[0136] Figure 11 This is a block diagram of an IC manufacturing system 1100 and its associated IC manufacturing process according to some embodiments. In some embodiments, based on an IC layout diagram, the manufacturing system 1100 is used to manufacture at least one of the following: (A) one or more semiconductor masks or (B) at least one component in a semiconductor integrated circuit layer.

[0137] exist Figure 11 In this system, IC manufacturing system 1100 includes entities that interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of IC devices 1160, such as design room 1120, mask room 1130, and IC manufacturing plant / manufacturer (“Fab”) 1150. The entities in system 1100 are connected via a communication network. In some embodiments, the communication network is a single network. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design room 1120, mask room 1130, and IC manufacturing plant 1150 are owned by a single, larger company. In some embodiments, two or more of design room 1120, mask room 1130, and IC manufacturing plant 1150 coexist in a shared facility and use shared resources.

[0138] The design studio (or design team) 1120 generates the IC design layout 1122. The IC design layout 1122 includes various geometric patterns, such as those mentioned above. Figures 1-7One or more of the IC layout diagrams 200-700 discussed. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 1160 to be manufactured. These layers combine to form various IC components. For example, a portion of the IC design layout diagram 1122 includes various IC components, such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for pads, which will be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design company 1120 implements appropriate design processes to form the IC design layout diagram 1122. The design processes include one or more of logic design, physical design, or location and routing. The IC design layout diagram 1122 is presented in the form of one or more data files containing geometric pattern information. For example, the IC design layout diagram 1122 can be represented in GDSII or DFII file format.

[0139] Mask chamber 1130 includes data preparation 1132 and mask fabrication 1144. Mask chamber 1130 uses an IC design layout 1122 to fabricate one or more masks 1145 for fabricating various layers of an IC device 1160 according to the IC design layout 1122. Mask chamber 1130 performs mask data preparation 1132, in which the IC design layout 1122 is converted into a representative data file (RDF). Mask data preparation 1132 provides the RDF to mask fabrication 1144. Mask fabrication 1144 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (template) 1145 or a semiconductor wafer 1153. The design layout 1122 is manipulated by mask data preparation 1132 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fabrication plant 1150. Figure 11 In this embodiment, mask data preparation 1132 and mask manufacturing 1144 are shown as separate elements. In some embodiments, mask data preparation 1132 and mask manufacturing 1144 may be collectively referred to as mask data preparation.

[0140] In some embodiments, mask data preparation 1132 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout diagram 1122. In some embodiments, mask data preparation 1132 includes further resolution enhancement techniques (RET), such as off-axis illumination, subresolution auxiliary features, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0141] In some embodiments, mask data preparation 1132 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout 1122, which has been processed by OPC. This set of mask generation rules includes certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1122 to compensate for constraints during mask fabrication 1144, which may undo some modifications performed by OPC to satisfy the mask creation rules.

[0142] In some embodiments, mask data preparation 1132 includes a lithography process check (LPC), which simulates the process to be performed by IC fabrication plant 1150 to manufacture IC device 1160. The LPC simulates this process based on IC design layout 1122 to create a simulated manufactured device, such as IC device 1160. Process parameters in the LPC simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors such as spatial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and combinations thereof. In some embodiments, after the LPC has created the simulated manufactured device, if the shape of the simulated device is not close enough to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 1122.

[0143] It should be understood that, for clarity, the above description of mask data preparation 1132 has been simplified. In some embodiments, data preparation 1132 includes additional features, such as modifying the logic operations (LOPs) of the IC design layout 1122 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1122 during data preparation 1132 can be performed in various different sequences.

[0144] After mask data preparation 1132 and during mask fabrication 1144, a mask 1145 or a set of masks 1145 is fabricated based on a modified IC design layout 1122. In some embodiments, mask fabrication 1144 includes performing one or more photolithographic exposures based on the IC design layout 1122. In some embodiments, a pattern is formed on the mask (photomask or photomask template) 1145 using a mechanism of electron beam (e-beam) or multiple electron beams based on the modified IC design layout 1122. The mask 1145 can be formed using various techniques. In some embodiments, a binary technique is used to form the mask 1145. In some embodiments, the mask pattern includes opaque areas and transparent areas. Radiation beams, such as ultraviolet (UV) or EUV beams, used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer are blocked by the opaque areas and transmitted through the transparent areas. In one example, the binary photomask template of the mask 1145 typically includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask. In another example, a phase-shifting technique is used to form mask 1145. In the phase-shifting mask (PSM) version of mask 1145, various features in the pattern formed on the phase-shifting mask are configured to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase-shifting mask can be attenuated PSM or alternating PSM. The mask generated by mask fabrication 1144 is used in various processes. For example, this mask is used in ion implantation processes to form various doped regions in semiconductor wafer 1153, in etching processes to form various etched regions in semiconductor wafer 1152, and / or in other suitable processes.

[0145] IC manufacturing plant 1150 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC manufacturing plant 1150 is a semiconductor foundry. For example, there may be one manufacturing facility for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, a second manufacturing facility for providing back-end manufacturing (back-end process (BEOL) manufacturing) for the interconnection and packaging of IC products, and a third manufacturing facility for providing other services for foundry operations.

[0146] IC manufacturing plant 1150 includes wafer fabrication tooling 1152 configured to perform various manufacturing operations on semiconductor wafers 1153 to fabricate IC devices 1160 according to a mask (e.g., mask 1145). In various embodiments, fabrication tooling 1152 includes one or more of the following: wafer stepper, ion implanter, photoresist coater, processing chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes described herein.

[0147] IC manufacturing plant 1150 uses a mask 1145, manufactured by mask chamber 1130, to manufacture IC device 1160. Therefore, IC manufacturing plant 1150 uses IC design layout 1122 at least indirectly to manufacture IC device 1160. In some embodiments, semiconductor wafer 1153 is manufactured by IC manufacturing plant 1150 using mask 1145 to form IC device 1160. In some embodiments, IC manufacturing includes performing one or more photolithographic exposures based at least indirectly on IC design layout 1122. Semiconductor wafer 1153 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 1153 also includes one or more of various doped regions, dielectric components, multilevel interconnects, etc. (formed in subsequent manufacturing steps).

[0148] In some embodiments, the IC device includes an SRAM device located in a substrate, wherein the SRAM device includes: a first CFET including a first transmission gate transistor positioned at a first height along a first direction; a second CFET including a first pull-down transistor positioned at the first height along the first direction and a first pull-up transistor positioned at a second height; a third CFET including a second pull-down transistor positioned at the first height and a second pull-up transistor positioned at the second height; and a fourth CFET including a second transmission gate transistor positioned at the first height, wherein each of the first and second pull-down transistors includes a gate extending in a second direction perpendicular to the first direction and including a first work function configuration, and each of the first and second transmission gate transistors includes a gate extending in the second direction and including a second work function configuration different from the first work function configuration. In some embodiments, each of the first and second pull-down transistors and each of the first and second transmission gate transistors includes an n-type transistor, and each of the first and second pull-up transistors includes a p-type transistor. In some embodiments, the first direction extends from the back side of the substrate to the front side of the substrate in a positive direction, and the first height is farther in the positive direction than the second height. In some embodiments, the first pull-down transistor is aligned with the first transmission gate transistor in a second direction and with the second transmission gate transistor in a third direction perpendicular to each of the first and second directions, and the second pull-down transistor is aligned with the first transmission gate transistor in a third direction and with the second transmission gate transistor in the second direction. In some embodiments, the first pull-down transistor is aligned with the second pull-down transistor in a second direction and with the first transmission gate transistor in a third direction perpendicular to each of the first and second directions, and the second transmission gate transistor is aligned with the first transmission gate transistor in a second direction and with the second pull-down transistor in a third direction. In some embodiments, the SRAM device further includes: a first internal node including a first contact structure located on the front side of the substrate; and a second internal node including a second contact structure located on the back side of the substrate. In some embodiments, each of the first pull-down transistor and the second pull-down transistor, as well as each of the first transmission gate transistor and the second transmission gate transistor, includes a p-type transistor, and each of the first pull-up transistor and the second pull-up transistor includes an n-type transistor. In some embodiments, the first pull-down transistor and the second pull-down transistor, as well as the first transmission gate transistor and the second transmission gate transistor, are aligned upwards on a third direction perpendicular to each of the first and second directions, and the first pull-down transistor and the second pull-down transistor are located between the first transmission gate transistor and the second transmission gate transistor.In some embodiments, each of the first pull-up transistor and the second pull-up transistor includes a gate extending in a second direction and including a third work function configuration. The first CFET also includes a read transmission gate transistor positioned at a second height, and the read transmission gate transistor includes a gate extending in the second direction and including a fourth work function configuration different from the third work function configuration. In some embodiments, the ratio of a first saturation current corresponding to the first work function configuration to a second saturation current corresponding to the second work function configuration is greater than 1.

[0149] In some embodiments, a method of manufacturing an IC device includes constructing an SRAM device on the front side of a substrate. Constructing the SRAM device includes: constructing a first complementary field-effect transistor (CFET), the first CFET including a first transmission gate transistor positioned at a first height along a first direction; constructing a second CFET, the second CFET including a first pull-down transistor positioned at the first height along the first direction and a first pull-up transistor positioned at a second height; constructing a third CFET, the third CFET including a second pull-down transistor positioned at the first height and a second pull-up transistor positioned at the second height; and constructing a fourth CFET, the fourth CFET including a second transmission gate transistor positioned at the first height. Each of the first and second pull-down transistors includes a gate formed extending in a second direction perpendicular to the first direction and including a first work function configuration; and each of the first and second transmission gate transistors includes a gate formed extending in the second direction and including a second work function configuration different from the first work function configuration. In some embodiments, a first direction extends along a positive direction from the back side of the substrate to the front side of the substrate. Constructing each of the first pull-up transistor and the second pull-up transistor includes constructing a p-type transistor. Constructing the first pull-down transistor and the second pull-down transistor, as well as each of the first transmission gate transistor and the second transmission gate transistor, includes constructing an n-type transistor at a first height, which is further along the positive direction in the first direction than a second height. In some embodiments, constructing the first pull-down transistor includes aligning it with the first transmission gate transistor in a second direction and aligning it with the second transmission gate transistor upwards perpendicular to each of the first and second directions. Constructing the second pull-down transistor includes aligning it with the first transmission gate transistor upwards in a third direction and aligning it with the second transmission gate transistor in the second direction. In some embodiments, constructing the first pull-down transistor includes aligning it with the second pull-down transistor in a second direction and aligning it with the first transmission gate transistor upwards perpendicular to each of the first and second directions. Constructing the second pull-down transistor includes aligning the second transmission gate transistor with the first transmission gate transistor in a second direction and aligning it with the second pull-down transistor upwards in a third direction. In some embodiments, constructing a first pull-down transistor and a second pull-down transistor, as well as a first transmission gate transistor and a second transmission gate transistor, includes aligning the first pull-down transistor and the second pull-down transistor, as well as the first transmission gate transistor and the second transmission gate transistor, upwards on each other in a direction perpendicular to a first direction and a second direction, wherein the first pull-down transistor and the second pull-down transistor are located between the first transmission gate transistor and the second transmission gate transistor.In some embodiments, constructing each of the first pull-up transistor and the second pull-up transistor includes forming a gate that extends in a second direction and includes a third work function configuration, constructing the first CFET also includes constructing a read transmission gate transistor positioned at a second height, and constructing the read transmission gate transistor includes forming a gate that extends in the second direction and includes a fourth work function configuration different from the third work function configuration.

[0150] In some embodiments, a method of generating an IC layout includes locating SRAM cells in the IC layout, wherein the SRAM cells include: a first CFET including a first transmission gate transistor positioned at a first height along a first direction; a second CFET including a first pull-down transistor positioned at the first height along the first direction and a first pull-up transistor positioned at a second height; a third CFET including a second pull-down transistor positioned at the first height and a second pull-up transistor positioned at the second height; and a fourth CFET including a second transmission gate transistor positioned at the first height; a first pattern arranging a first work function configuration including the gates of each of the first and second pull-down transistors; a second pattern arranging a second work function configuration different from the first work function configuration including the gates of each of the first and second transmission gate transistors; and storing the IC layout including the SRAM cells in a storage device. In some embodiments, locating SRAM cells in the IC layout includes locating SRAM cells including first CFETs to fourth CFETs arranged in two rows and two columns. In some embodiments, locating SRAM cells in the IC layout includes locating SRAM cells including first CFETs to fourth CFETs arranged in a single column. In some embodiments, locating SRAM cells in an IC layout includes locating a plurality of SRAM cells, the plurality of SRAM cells including a plurality of SRAM cells aligned with each other along the gate direction of the plurality of SRAM cells in the IC layout; a first pattern for arranging a first work function configuration includes arranging a first continuous region of the first work function configuration, the first work function configuration including the corresponding gate of each of a corresponding first pull-down transistor and a second pull-down transistor of each of the plurality of SRAM cells; and a second pattern for arranging a second work function configuration includes arranging a second continuous region of the second work function configuration, the second work function configuration including the corresponding gate of each of a corresponding first transmission gate transistor and a second transmission gate transistor of each of the plurality of SRAM cells.

[0151] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them within this disclosure without departing from its spirit and scope.

Claims

1. An integrated circuit device, comprising: A static random access memory (SRAM) device, located in a substrate, wherein the SRAM device comprises: The first CFET includes a first transmission gate transistor positioned at a first height along a first direction. The second CFET includes a first pull-down transistor positioned at the first height along the first direction and a first pull-up transistor positioned at the second height. The third CFET includes a second pull-down transistor positioned at the first height and a second pull-up transistor positioned at the second height, and The fourth CFET includes a second transmission gate transistor positioned at the first height. in, Each of the first pull-down transistor and the second pull-down transistor includes a gate extending in a second direction perpendicular to the first direction and including a first work function configuration, and Each of the first and second transmission gate transistors includes a gate that extends in the second direction and includes a gate with a second work function configuration that is different from the first work function configuration.

2. The integrated circuit device according to claim 1, wherein, The first direction extends along the positive direction from the back side of the substrate to the front side of the substrate, and The first height is farther than the second height in the first direction along the positive direction.

3. The integrated circuit device according to claim 1, wherein, The first pull-down transistor is aligned with the first transmission gate transistor in the second direction, and is aligned with the second transmission gate transistor in a third direction perpendicular to each of the first and second directions. The second pull-down transistor is aligned with the first transmission gate transistor in the third direction and with the second transmission gate transistor in the second direction.

4. The integrated circuit device according to claim 1, wherein, The first pull-down transistor is aligned with the second pull-down transistor in the second direction, and is aligned with the first transmission gate transistor in a third direction perpendicular to each of the first and second directions. The second transmission gate transistor is aligned with the first transmission gate transistor in the second direction and with the second pull-down transistor in the third direction.

5. The integrated circuit device according to claim 1, wherein, The first pull-down transistor and the second pull-down transistor, as well as the first transmission gate transistor and the second transmission gate transistor, are aligned upwards with each other on a third direction perpendicular to each of the first and second directions, and The first pull-down transistor and the second pull-down transistor are located between the first transmission gate transistor and the second transmission gate transistor.

6. The integrated circuit device according to claim 5, wherein, Each of the first pull-up transistor and the second pull-up transistor includes a gate that extends in the second direction and includes a third work function configuration. The first CFET also includes a read transmission gate transistor positioned at the second height, and The read transmission gate transistor includes a gate that extends in the second direction and includes a fourth work function configuration that is different from the third work function configuration.

7. The integrated circuit device according to claim 1, wherein, The ratio of the first saturation current configured corresponding to the first work function to the second saturation current configured corresponding to the second work function is greater than 1.

8. A method for manufacturing an integrated circuit device, the method comprising: Constructing a static random access memory (SRAM) device on the front side of a substrate, wherein constructing the SRAM device includes: Construct a first CFET, the first CFET including a first transmission gate transistor positioned at a first height along a first direction. Construct a second CFET, the second CFET including a first pull-down transistor positioned at the first height along the first direction and a first pull-up transistor positioned at a second height. Construct a third CFET, the third CFET including a second pull-down transistor positioned at the first height and a second pull-up transistor positioned at the second height, and Construct a fourth CFET, the fourth CFET including a second transmission gate transistor positioned at the first height, in, Constructing each of the first pull-down transistor and the second pull-down transistor includes a gate formed extending in a second direction perpendicular to the first direction and including a first work function configuration, and Constructing each of the first and second transmission gate transistors includes forming a gate that extends in the second direction and includes a second work function configuration that is different from the first work function configuration.

9. The method according to claim 8, wherein, The first direction extends along the positive direction from the back side of the substrate to the front side of the substrate. Constructing each of the first pull-up transistor and the second pull-up transistor includes constructing a p-type transistor, and Constructing the first pull-down transistor and the second pull-down transistor, as well as the first transmission gate transistor and the second transmission gate transistor, each includes constructing an n-type transistor at a first height, which is further in the first direction along the positive direction than the second height.

10. A method for generating an integrated circuit layout diagram, the method comprising: Locate static random access memory (SRAM) cells in the integrated circuit layout diagram, wherein the static random access memory (SRAM) cells include: The first CFET includes a first transmission gate transistor positioned at a first height along a first direction; The second CFET includes a first pull-down transistor positioned at the first height along the first direction and a first pull-up transistor positioned at the second height; The third CFET includes a second pull-down transistor positioned at the first height and a second pull-up transistor positioned at the second height; and The fourth CFET includes a second transmission gate transistor positioned at the first height; A first pattern is arranged including a first work function configuration of the gate of each of the first pull-down transistor and the second pull-down transistor; Arranged in a second pattern comprising the gates of each of the first and second transmission gate transistors, with a second work function configuration different from the first work function configuration; and The layout of the integrated circuit, including the static random access memory cell, is stored in the storage device.

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