Turret type chip sorting system

Abstract

The invention discloses a turret type chip sorting system, and relates to the technical field of semiconductors, the turret type chip sorting system comprises a rack, and a feeding unit, a turret unit, a test station, a marking station and a sorting discharging unit which are arranged on the rack, and the turret unit is provided with a plurality of suction nozzles for bearing chips; the visual pre-detection module is arranged behind the feeding unit and in front of the testing station in the rotating direction of the turret unit; and the visual pre-detection module comprises a multispectral light source, a high-resolution camera and an image processing unit, and is used for acquiring a multi-angle image of the chip, extracting at least one characteristic parameter of the surface defect area, the pin coplanarity and the packaging integrity of the chip, and further generating a quality pre-judgment grade of the chip according to a preset threshold value. According to the invention, the visual pre-detection module is introduced before the electrical property test, so that the parameters of the subsequent test and the marking station can be dynamically adjusted according to the actual appearance quality of the chip, and a one-step fixed parameter processing mode is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and more particularly to a turret chip sorting system. BACKGROUND

[0002] The semiconductor industry is one of the core driving forces of modern information technology, and the quality of its products directly affects the performance and reliability of electronic equipment. In the post-process of semiconductor manufacturing, packaging testing is a key link to ensure chip quality. Among them, the turret chip sorting system, also known as the turret sorting machine, is the core automated equipment on the semiconductor post-packaging test line.

[0003] The existing turret chip sorting system is usually composed of the following main functional units: a feeding unit responsible for taking the chips to be tested from the tray or tubular container and sending them into the sorting machine; a turret unit as the core motion mechanism of the device, which is installed with multiple suction nozzles to accurately transport the chips to different workstations in sequence through rotation; a test station, usually including a normal temperature test station, a high temperature test station or a low temperature test station, for detecting various electrical performance parameters of the chips; a marking station, such as a laser marking station, for marking production batch, model, good / bad product identification and other information on the surface of the chip; and a sorting and discharging unit to send the chips to different classified bins according to the test and marking results.

[0004] In this process, although the vision system is also integrated in the device, its role is usually limited. For example, the vision system is mainly used for accurate positioning and alignment of the chips before feeding and testing, to ensure that the chips can be accurately sucked by the suction nozzle or effectively contacted by the test probe. In addition, after testing and marking, the vision system is sometimes used to check the marking quality to verify whether the marking content is clear and the position is accurate. However, this "post-verification" or "auxiliary positioning" vision application mode makes the existing sorting machine face some insurmountable limitations when facing the increasingly complex chip manufacturing process and higher quality requirements.

[0005] In the existing turret sorting chip system, the working parameters of the test station, especially the key link such as constant temperature test, such as test voltage, test current, test signal frequency and test time, are often uniformly set in advance according to product models and standards. No matter the initial appearance quality of the chip, all the chips will be tested according to the same fixed parameters, which are usually designed for normal good products. This "one-size-fits-all" testing strategy leads to significant inefficiency and resource waste. For example, for those chips that have obvious defects in appearance before entering the test station (such as scratches, damage, pin deformation or incomplete packaging on the chip surface), even if the complete electrical test is performed, the final result is also highly likely to be unqualified. However, in the existing system, these "doomed to be unqualified" chips still occupy valuable test resources, such as test machine probes, test time, constant temperature oven energy consumption and operator monitoring time. Especially in the constant temperature test station, the chip is heated or cooled to a certain temperature and maintained at this temperature for a long time of test, and the energy consumption and time cost is considerable. The unnecessary complete test of these poor appearance chips not only wastes electrical energy and time, but also occupies the test channel that can be used to test high-quality chips, thereby reducing the output per unit time of the entire sorting machine and directly affecting the overall efficiency of the production line. In addition, the wear of the test probe is also accelerated due to invalid test, increasing the frequency of consumable replacement and maintenance cost. This fixed parameter setting mechanism lacks the ability to perceive and respond to the state of individual chips, which is an important factor leading to the efficiency bottleneck of the current sorting machine.

[0006] Therefore, it is necessary to propose a turret sorting chip system to solve the above problems. SUMMARY

[0007] The purpose of the present application is to solve the problems raised in the background art.

[0008] The present application specifically adopts the following technical solutions to achieve the above purposes: A turret sorting chip system, comprising a rack, a feeding unit, a turret unit, a test station, a marking station and a sorting and discharging unit arranged on the rack, and a plurality of suction nozzles for carrying chips are arranged on the turret unit; the turret sorting chip system further comprises: The visual pre-checking module is arranged after the feeding unit and before the test station in the rotation direction of the turret unit; The visual pre-checking module comprises a multi-spectral light source, a high-resolution camera and an image processing unit, which are used to collect multi-angle images of the chips and extract at least one feature parameter of the surface defect area, the pin coplanarity and the packaging integrity of the chips, and then generate a quality pre-judgment grade of the chips according to a preset threshold value; The central controller is electrically connected with the visual pre-inspection module, the turret unit, the test station and the marking station. The data tracking and synchronization unit is configured to assign a unique ID to each chip and bind and synchronously track the ID of the chip, the position information of the suction nozzle where the chip is located and the quality pre-judgment level. The central controller pre-stores the parameter configuration mapping table, which defines the test station parameter set and the marking station parameter set corresponding to different quality pre-judgment levels. The central controller is configured to, according to real-time information provided by the data tracking and synchronization unit, when a chip enters the test station or the marking station, call the parameter set corresponding to the quality pre-judgment level of the chip in the parameter configuration mapping table, and send instructions to the corresponding station to adjust the working parameters thereof.

[0009] Further, the test station is a constant-temperature test station.

[0010] Further, the adjustable parameters of the constant-temperature test station include at least one of test voltage, test current, test signal frequency and test time.

[0011] Further, the marking station is a laser marking station.

[0012] Further, the adjustable parameters of the laser marking station include at least one of laser power, marking speed and marking focal length.

[0013] Further, the sorting and discharging unit includes a plurality of classified hoppers.

[0014] Further, the central controller is further configured to, according to the combination of the final electrical test result of the chip and the quality pre-judgment level thereof, control the sorting and discharging unit to sort the chip into different classified hoppers.

[0015] Further, the sorting method of the turret-type sorting chip system includes the following steps: a. Feeding and carrying step: picking up the chip to be sorted by the feeding unit and carrying it by the suction nozzle of the turret unit; b. Visual pre-inspection step: before the chip enters the test station, the visual pre-inspection module is used to perform multi-spectral illumination on the carried chip and collect multi-angle images, and at least one characteristic parameter of the chip, such as surface defect area, pin coplanarity and package integrity, is extracted from the images, and then a quality pre-judgment level of the chip is generated according to a preset threshold; c. Data binding and tracking step: assigning a unique ID to each chip and binding and synchronously tracking the ID of the chip, the position information of the suction nozzle where the chip is located and the quality pre-judgment level; d. Parameter calling and adjustment steps: When the tracked chip is about to enter the test station or marking station, the parameter set corresponding to the chip's quality prediction level is called from the parameter configuration mapping table pre-stored in the central controller; e. Workstation parameter adaptive adjustment steps: Based on the parameter set called, send instructions to the corresponding test station or marking station to dynamically adjust its working parameters; f. Sorting and unloading steps: After the chip completes the electrical test, the sorting and unloading unit is controlled to sort the chip into different classification bins by comprehensively considering the combination of the final electrical test results and the quality prediction level.

[0016] Furthermore, in the visual pre-inspection step, extracting the surface defect area includes the following sub-steps: performing grayscale conversion, noise reduction, contrast enhancement, defect segmentation, and connected component analysis on the acquired chip image.

[0017] Furthermore, in the visual pre-inspection step, extracting the pin coplanarity includes the following sub-steps: obtaining the pin coplanarity through a three-dimensional point cloud or by combining multi-angle two-dimensional projection with pin end plane fitting; The visual pre-inspection step, extracting the packaging integrity includes the following sub-steps: template matching and difference detection or specific defect pattern recognition.

[0018] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention achieves intelligent and adaptive chip sorting processes. By introducing a visual pre-inspection module before electrical testing, the parameters of subsequent testing and marking stations can be dynamically adjusted according to the actual appearance quality of the chips, avoiding the "one-size-fits-all" fixed parameter processing method.

[0019] 2. This invention significantly improves sorting efficiency and resource utilization. For chips judged to have serious defects by visual pre-inspection, the time-consuming electrical testing and marking processes can be skipped, saving testing resources and time. For chips with better appearance quality, more efficient or more accurate testing strategies can be adopted based on the predicted defect level. Attached Figure Description

[0020] Figure 1 This is the overall workflow of the turret-type chip sorting system of the present invention.

[0021] Figure 2 This is a detailed flowchart of the visual pre-inspection and quality level determination in this invention. Detailed Implementation

[0022] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0023] Please see Figures 1-2 This embodiment provides a turret-type chip sorting system. Based on the turret-type chip sorting machine, this application achieves the prediction of chip quality through visual pre-inspection, and based on the prediction result, adaptively adjusts the subsequent testing and marking process parameters, and finally performs fine sorting by combining the electrical test results.

[0024] like Figure 1 As shown, the turret-type chip sorting system in this embodiment mainly includes: a feeding unit, a turret unit, a vision pre-inspection module, a testing station, a marking station, a sorting and unloading unit, a central controller, and a data tracking and synchronization unit.

[0025] 1. Overview of chip processing flow: The chips are first picked up by the loading unit and placed onto the nozzle of the turret unit. As the turret unit rotates, the chips pass sequentially through the vision pre-inspection module, the testing station, and the marking station, finally arriving at the sorting and unloading unit for classification. Throughout the process, the central controller acquires and manages the status and information of each chip in real time through the data tracking and synchronization unit, and issues instructions according to preset logic.

[0026] 2. Working principle and quality prediction of the visual pre-inspection module: The vision pre-inspection module is located after the loading unit and before the testing station. When the chip rotates to this station: Image acquisition: Multispectral light sources (e.g., combining visible, infrared, or ultraviolet light) illuminate the chip from multiple angles, and a high-resolution camera acquires raw image data of the chip from different perspectives, such as top, side, or tilt angles. Multispectral light sources help to discover defects with different material properties or depths, while multi-angle acquisition ensures comprehensive coverage of all surfaces and pins of the chip.

[0027] Traditional visual inspection often uses a single white light source, but for different types of surface defects, such as scratches, foreign objects, package cracks, and pin oxidation, the contrast of a single light source may be insufficient to clearly present all defect features. This invention employs a multispectral light source, which may include, for example: White LED light source: Provides basic illumination for obtaining the overall structure of the chip and general surface features.

[0028] Blue LED light source (wavelength approximately 450-490nm): helps enhance the contrast of certain organic contaminants or specific material surfaces, especially sensitive to defects in certain coatings or encapsulation materials.

[0029] Red LED light source (wavelength approximately 620-680nm): It excels at penetrating certain semi-transparent materials or highlighting minor scratches, corrosion, and other defects on metal surfaces.

[0030] Near-infrared LED light sources (wavelength approximately 850-950nm): possess a certain penetrating power, capable of revealing certain defects within the chip or beneath the packaging material, such as bubbles or delamination. By sequentially or simultaneously activating light sources of different wavelengths, and employing a high-resolution camera for image acquisition, multiple images of the chip under different lighting conditions can be obtained. These images contain richer and more comprehensive information than those obtained with a single white light source.

[0031] High-resolution cameras, such as those equipped with CMOS sensors of 20 megapixels or higher, achieving micrometer-level optical resolution, are responsible for simultaneously capturing detailed images of the chip. To acquire information from multiple angles of the chip, multiple cameras can be configured, or a single camera can be used in conjunction with a turret for precise docking or continuous scanning. For example, multiple cameras can be set up to capture images from the top and sides to obtain three-dimensional information such as pin coplanarity. The acquired image data is then transmitted to an image processing unit for analysis.

[0032] Image processing and feature extraction algorithm steps: The acquired raw image data is transmitted to the image processing unit. This unit performs at least one of the following algorithm steps to extract the chip's feature parameters: 2.1. Preprocessing: The original image is subjected to grayscale conversion, noise reduction (such as Gaussian filtering and median filtering), and contrast enhancement (such as histogram equalization) to improve image quality and robustness to subsequent processing.

[0033] 2.2. Defect Region Segmentation and Area Calculation : Algorithm: The algorithm uses methods such as threshold segmentation, edge detection (e.g., Canny operator), region growing, or deep learning (e.g., U-Net model) to separate defective regions in an image from the background.

[0034] step: a. Set or obtain the grayscale / color threshold for defective pixels through training.

[0035] b. Mark the pixels in the image that meet the threshold condition as defective pixels.

[0036] c. Perform connected component analysis on the marked defective pixels to identify independent defective regions.

[0037] d. Calculate the number of pixels in each defect region and multiply it by the actual physical area of ​​a single pixel to obtain the defect area. .

[0038] e. Sum the areas of all independent defective regions, or take the area of ​​the largest defective region as the defective area index of the chip.

[0039] 2.3. Pin Coplanarity Calculation : Algorithm: Combining stereo vision technology with multi-angle images or laser triangulation, generate 3D point cloud data of the pin area, and then perform plane fitting and height difference calculation.

[0040] step: a. Identify and locate all pin areas of the chip from multi-angle images.

[0041] b. Use a stereo matching algorithm or a laser sensor to obtain the precise three-dimensional coordinates of the end of each pin, forming a pin point cloud.

[0042] c. Perform least-squares plane fitting on the point cloud data at the ends of all pins to obtain a reference plane.

[0043] d. Calculate the vertical distance from the end of each pin to the reference plane.

[0044] e. The maximum distance difference between all pins and the reference plane is defined as the pin coplanarity. .

[0045] 2.4. Packaging Integrity Assessment: Algorithm: Template matching, difference detection, edge contour analysis, or a defect classification model based on convolutional neural networks (CNN) are employed.

[0046] step: a. Obtain a template image or 3D model of a standard, defect-free chip.

[0047] b. Align and compare the image or 3D data of the chip to be tested with the template.

[0048] c. Identify and quantify structural defects such as edge chipping, cracks, missing corners, bulging or deformation of the package by pixel-level difference calculation or geometric shape comparison.

[0049] d. If a CNN model is used, the preprocessed chip image is input into the pre-trained model, and the model directly outputs the defect type and confidence level as the evaluation result of the packaging integrity.

[0050] Quality prediction level generation algorithm steps: The image processing unit performs the following logical steps to classify the quality prediction level based on the extracted feature parameters: 2.4.1. Define the discrimination rules: Preset a series of thresholds and logical rules, for example: if Packaging integrity score below It is then classified as Level D.

[0051] if or It is then classified as Level C.

[0052] if and It is then classified as Level B.

[0053] if and The package integrity score is higher than It is then classified as Level A.

[0054] in: It is the threshold for the defect area. It is the threshold of coplanarity. It is the scoring threshold for packaging integrity.

[0055] 2.4.2. Feature Parameter Input: Input the features extracted in step 2. , The results of the packaging integrity assessment are used as input.

[0056] 2.4.3. Level determination: According to the preset discrimination rules, the matching is performed step by step from the worst level (Level D) until the quality prediction level of the chip is determined.

[0057] 2.4.4. Machine Learning Model Ensemble (Optional): To improve accuracy and robustness, a multi-class machine learning model, such as a support vector machine, decision tree, or neural network, can be trained. This model uses... , The model uses numerical values ​​related to packaging integrity as input features to directly output the predicted quality level of the chip. It is trained and optimized by learning from a large amount of chip data with real-world quality labels.

[0058] 3. Data tracking and synchronization unit: The data tracking and synchronization unit assigns a unique ID to each chip entering the sorter throughout the sorting process. Once the vision pre-inspection module generates a chip's quality pre-judgment level, this unit immediately binds the chip's ID, its nozzle position information on the turret unit, and the corresponding quality pre-judgment level, and tracks it synchronously in real time via an internal bus or network interface. This ensures that the chip's "identity" and "pre-judgment level" information always precisely match the chip itself as it moves through subsequent workstations.

[0059] 4. Adaptive decision-making and command issuance algorithm steps of the central controller: The central controller has a pre-stored parameter configuration mapping table. This mapping table defines the parameter sets for the testing station and the marking station corresponding to different quality prediction levels.

[0060] Example of parameter configuration mapping (conceptual) Quality pre-judgment level Test voltage (V) Test current (mA) Test signal frequency (kHz) Test time (ms) Laser power (%) Marking speed (mm / s) Marking focal length (mm) Other instructions Level A Standard value Standard value Standard value Standard value Standard value Standard value Standard value No special Level B Standard value Standard value Standard value Shortened by 10% Standard value Standard value Standard value No special Level C Standard value Standard value Standard value Shortened by 40% Reduced by 10% Standard value Standard value No special Level D Skip Skip Skip Skip Reduced by 50% Accelerated by 20% Standard value Skip marking The table above is for illustrative purposes only; the actual parameters are described in text.

[0061] Real-time decision-making and instruction issuance algorithm steps: 1. Chip Status Query: When the data tracking and synchronization unit notifies a chip (by its ID and nozzle position) that it is about to enter the testing or marking station, the central controller will query its currently bound quality prediction level through the ID. .

[0062] 2. Parameter lookup: The central controller searches for the corresponding set of test station parameters in the pre-stored parameter configuration mapping table based on the queried quality prediction level. and / or marking station parameter set .

[0063] 3. Command generation and transmission: For the test station: the central controller according to Generate corresponding electrical test instructions, such as setting voltage, current, frequency, test time, or skipping the test, and send them to the test station controller via an industrial communication interface (such as EtherCAT or Profinet).

[0064] Special handling for Level D: If If it is Level D, a "Skip Test" instruction is generated, and the test station directly passes the chip to the next station.

[0065] For the marking station: the central controller according to Generate corresponding laser marking instructions, such as setting laser power, marking speed, focal length, or skipping marking, and send them to the marking station controller via the communication interface.

[0066] Special handling for Level D: If For Level D, depending on the specific strategy, it can generate instructions to "significantly reduce laser power" or "skip marking".

[0067] 5. Algorithm steps for the refined sorting strategy of the sorting and unloading unit: The sorting and unloading unit includes multiple categorized bins, such as premium product bins, qualified product bins, substandard product bins, and scrap product bins. After the chips have completed all tests and marking, the central controller executes the final comprehensive sorting decision.

[0068] Sorting Strategy Mapping Table (Conceptual) Quality pre-judgment level Electrical test result Final sorting bin Level A Pass Good product bin Level B Pass Good product bin Level C Pass Defective product bin Level D Pass / fail Waste product bin Any level (A, B, C) Fail Waste product bin Final sorting decision algorithm steps: 1. Obtaining the final result: The central controller obtains the chip's predicted quality level from the data tracking and synchronization unit. The final electrical test results fed back from the testing station .

[0069] 2. Sorting and querying: The central controller, based on... and These two dimensions are used to find the corresponding final sorting bins in the pre-stored sorting strategy mapping table.

[0070] 3. Unloading instruction: The central controller sends an instruction to the sorting and unloading unit, instructing it to place the chip into the target hopper found in the query.

[0071] Through this embodiment, the present invention achieves a comprehensive consideration of both the "appearance quality" and "internal quality" of the chip. By using forward-looking visual pre-inspection, adaptive process parameter adjustment, and multi-dimensional refined sorting, it significantly improves production efficiency, optimizes resource utilization, protects key equipment, and maximizes the market value of the product.

[0072] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. The scope of patent protection of the present invention shall be determined by the claims. Similarly, any equivalent structural changes made based on the content of the present invention's specification shall also be included within the scope of protection of the present invention.

Claims

1. A turret-type chip sorting system, comprising a frame, a loading unit, a turret unit, a testing station, a marking station, and a sorting and unloading unit mounted on the frame, wherein the turret unit is provided with multiple nozzles for carrying chips; characterized in that, The turret-type sorting chip system also includes: The visual pre-inspection module is positioned after the feeding unit and before the testing station, along the rotation direction of the turret unit. The visual pre-inspection module includes a multispectral light source, a high-resolution camera, and an image processing unit, used to acquire multi-angle images of the chip and extract at least one feature parameter from the chip's surface defect area, pin coplanarity, and package integrity, and then generate a chip quality pre-judgment level based on a preset threshold. The central controller is electrically connected to the visual pre-inspection module, the turret unit, the testing station, and the marking station; The data tracking and synchronization unit is used to assign a unique ID to each chip and bind and synchronize the chip's ID, the location information of its nozzle, and the quality prediction level. The central controller has a pre-stored parameter configuration mapping table, which defines the test station parameter set and marking station parameter set corresponding to different quality prediction levels. The central controller is configured to: based on the real-time information provided by the data tracking and synchronization unit, when the chip enters the testing station or the marking station, call the parameter set corresponding to the chip quality prediction level in the parameter configuration mapping table, and send instructions to the corresponding station to adjust its working parameters.

2. The turret-type chip sorting system according to claim 1, characterized in that, The testing station is a constant temperature testing station.

3. The turret-type chip sorting system according to claim 2, characterized in that, The adjustable parameters of the constant temperature testing station include at least one of the following: test voltage, test current, test signal frequency, and test time.

4. The turret-type chip sorting system according to claim 1, characterized in that, The marking station is a laser marking station.

5. A turret-type chip sorting system according to claim 4, characterized in that, The adjustable parameters of the laser marking station include at least one of laser power, marking speed, and marking focal length.

6. The turret-type chip sorting system according to claim 1, characterized in that, The sorting and feeding unit includes multiple sorting bins.

7. A turret-type chip sorting system according to claim 6, characterized in that, The central controller is also used to control the sorting and unloading unit to sort the chips into different classification bins based on the combination of the final electrical test results of the chips and their quality prediction level.

8. A turret-type chip sorting system according to claim 7, characterized in that, The sorting method of the turret-type sorting chip system includes the following steps: a. Loading and Carrying Steps: The chips to be sorted are picked up by the loading unit and carried by the nozzle of the turret unit; b. Visual pre-inspection step: Before the chip enters the test station, the visual pre-inspection module is used to illuminate the chip with multispectral light and acquire multi-angle images. At least one characteristic parameter among the chip's surface defect area, pin coplanarity, and package integrity is extracted from the images. Then, the chip's quality pre-judgment level is generated according to a preset threshold. c. Data binding and tracking steps: Assign a unique ID to each chip, and bind and track the chip's ID, its location information in the nozzle, and the quality prediction level in real time; d. Parameter calling and adjustment steps: When the tracked chip is about to enter the test station or marking station, the parameter set corresponding to the chip's quality prediction level is called from the parameter configuration mapping table pre-stored in the central controller; e. Workstation parameter adaptive adjustment steps: Based on the parameter set called, send instructions to the corresponding test station or marking station to dynamically adjust its working parameters; f. Sorting and unloading steps: After the chip completes the electrical test, the sorting and unloading unit is controlled to sort the chip into different classification bins by comprehensively considering the combination of the final electrical test results and the quality prediction level.

9. A turret-type chip sorting system according to claim 8, characterized in that, In the visual pre-inspection step, extracting the surface defect area includes the following sub-steps: performing grayscale conversion, noise reduction, contrast enhancement, defect segmentation, and connected component analysis on the acquired chip image.

10. A turret-type chip sorting system according to claim 8, characterized in that, In the visual pre-inspection step, extracting the pin coplanarity includes the following sub-steps: obtaining the pin coplanarity through three-dimensional point cloud or combining multi-angle two-dimensional projection with pin end plane fitting; The visual pre-inspection step, extracting the packaging integrity includes the following sub-steps: template matching and difference detection or specific defect pattern recognition.

Images