Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and the method comprises the steps: providing a substrate, the substrate comprises a semiconductor substrate and a gate structure, the gate structure is located on the semiconductor substrate, and the gate structure comprises a metal gate; forming a mask layer to cover the metal gate; forming an interlayer dielectric layer to cover the substrate and the mask layer; performing dry etching by using the mask layer as an etching stop layer to expose the mask layer; and performing wet etching, and further etching the mask layer to form a first contact hole exposing the metal gate. Therefore, the etching-resistant mask layer is arranged above the metal gate, so that the mask layer can be used as a stop layer for dry etching to prevent etching gas from contacting with the metal gate, and high-resistance byproducts such as aluminum fluoride complexes and the like generated in the etching process are reduced or avoided; the mask layer is further removed through wet etching to form the first contact hole exposing the metal gate, so that the contact resistance of the metal plug subsequently filled in the first contact hole can be reduced, and the connection stability is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] In the preparation process of a semiconductor device, a contact hole needs to be etched so that the current of the active region of the device can be connected to a metal layer through the contact hole as a bridge to ensure the reliability and stability of the electrical connection. With the reduction of nodes, the metal replacement gate process gradually becomes mainstream in logic technology. When the metal replacement gate process is used and the contact hole is etched, the etching gas is easy to react with the metal gate and produce high-resistance by-products, including aluminum fluoride complex AlFx which is difficult to remove, etc., resulting in an increase in the contact resistance of the metal plug filled in the contact hole subsequently, and low connection stability of the metal gate. SUMMARY

[0003] To solve the above technical problems, the present application provides a semiconductor device and a manufacturing method thereof.

[0004] To solve the above problems, the present application provides a technical scheme: providing a manufacturing method of a semiconductor device, comprising: providing a substrate, the substrate comprising a semiconductor substrate and a gate structure, the gate structure being located on the semiconductor substrate and comprising a metal gate; forming a mask layer covering the metal gate; forming an interlayer dielectric layer covering the substrate and covering the mask layer; using the mask layer as an etching stop layer to perform dry etching to expose the mask layer; performing wet etching to further etch the mask layer to form a first contact hole exposing the metal gate.

[0005] Optionally, the gate structure comprises a dummy gate and a sidewall located on both sides of the dummy gate, and the semiconductor substrate forms a source region and a drain region on both sides of the gate structure, respectively; the substrate further comprises a first dielectric layer covering the semiconductor substrate and located between adjacent two gate structures; the step of providing a substrate, the substrate comprising a semiconductor substrate and a gate structure, the gate structure being located on the semiconductor substrate and comprising a metal gate, comprises: providing the substrate, the substrate comprising the gate structure forming the dummy gate; removing the dummy gate in the gate structure to expose a groove formed by removing the dummy gate; forming the metal gate in the groove.

[0006] Optionally, the forming the metal gate in the recess comprises: depositing a metal gate material layer covering the semiconductor substrate; the forming the mask layer covering the metal gate comprises: depositing a mask material layer covering the metal gate material layer, and portions of the metal gate material layer and the mask material layer are filled in the recess respectively; removing portions of the metal gate material layer and the mask material layer, and portions of the metal gate material layer and the mask material layer in the recess are reserved as the metal gate and the mask layer respectively; wherein the thickness of the metal gate material layer is less than the height of the recess.

[0007] Optionally, after the step of depositing the metal gate material layer covering the semiconductor substrate, the manufacturing method further comprises: forming a metal gate material oxide layer on the surface of the metal gate material layer.

[0008] Optionally, the mask layer is made of a material resistant to the dry etching gas; and the etching selectivity ratio of the dry etching gas to the interlayer dielectric layer and the mask layer is greater than 5:1.

[0009] Optionally, the material of the mask layer comprises titanium nitride and / or tantalum nitride; and the thickness of the mask layer is between 50 Å and 400 Å.

[0010] Optionally, the sum of the thicknesses of the metal gate and the mask layer is between 200 Å and 500 Å.

[0011] Optionally, the etching rate of the selected material of the wet etching liquid to the mask layer and the metal gate is greater than the etching rate of the selected material of the wet etching liquid to the semiconductor material; and the selected material of the wet etching liquid comprises ammonia-peroxide mixture or hydrochloric acid-peroxide mixture.

[0012] To solve the above problems, the application provides another technical scheme: providing a semiconductor device, comprising a substrate, a mask layer, an interlayer dielectric layer and a first contact hole; the substrate comprises a semiconductor substrate and a metal gate, and the metal gate is located on the semiconductor substrate; the mask layer covers part of the metal gate; the interlayer dielectric layer covers the substrate and covers the mask layer; and the first contact hole is arranged in the interlayer dielectric layer and the mask layer to expose the metal gate.

[0013] Optionally, the width of the first contact hole exposing the metal gate is greater than the width of the first contact hole located in the interlayer dielectric layer.

[0014] This application provides a semiconductor device and a method for manufacturing the same. The method involves providing a substrate, including a semiconductor substrate and a gate structure, with the gate structure located on the semiconductor substrate and including a metal gate; forming a mask layer covering the metal gate; forming an interlayer dielectric layer covering the substrate and the mask layer; performing dry etching using the mask layer as an etch stop layer to expose the mask layer; and performing wet etching to further etch the mask layer to form a first contact hole exposing the metal gate. Therefore, by providing an etch-resistant mask layer above the metal gate, the mask layer can act as a stop layer for dry etching, preventing etching gas from contacting the metal gate and reducing or avoiding the generation of high-resistivity byproducts such as aluminum fluoride complexes during etching. Further removing the mask layer by wet etching to form a first contact hole exposing the metal gate reduces the contact resistance of the subsequently filled metal plug in the first contact hole and improves connection stability. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a schematic flowchart of an embodiment of the semiconductor device manufacturing method in this application; Figure 2 This is a schematic diagram of the structure of the semiconductor device exposing the mask layer in this application; Figure 3 This is a schematic diagram of the structure of the semiconductor device forming the first contact hole in this application; Figure 4 yes Figure 1 A flowchart illustrating the process of forming the metal gate; Figure 5 This is a schematic diagram of the structure of the semiconductor device forming a mask layer covering the metal gate in this application; Figure 6 yes Figure 1 A schematic diagram of the process for forming a mask layer covering a metal grid; Figure 7 This is a schematic diagram of the structure of the semiconductor device in this application, in which a mask material layer covers a metal gate material layer; Figure 8 This is a schematic diagram of the structure of the semiconductor device in this application.

[0016] 10, substrate; 11, semiconductor substrate; 12, metal gate; 13, metal gate material layer; 14, metal gate oxide layer; 20, interlayer dielectric layer; 31, mask layer; 32, mask material layer; 40, first contact hole; 50, first anti-reflective layer; 60, dielectric anti-reflective layer; 70, second dielectric layer; 80, second anti-reflective layer; 90, photoresist layer. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0018] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative positional relationship, movement condition, etc. between components in a certain posture (as shown in the drawings). If the certain posture changes, the directional indications also change accordingly.

[0019] In addition, if the embodiments of the present application involve descriptions such as "first", "second", etc., the descriptions of "first", "second", etc. are only for description purposes and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of each embodiment can be combined with each other, but it must be based on the fact that a person of ordinary skill in the art can realize it. When the combination of technical solutions contradicts each other or cannot be realized, it should be considered that the combination of technical solutions does not exist and is not within the scope of protection claimed by the present application.

[0020] In an embodiment, please refer to Figures 1-3 , Figure 1 is a flowchart of an embodiment of the manufacturing method of the semiconductor device in the present application, Figure 2 is a structural diagram of exposing the mask layer of the semiconductor device in the present application, Figure 3 is a structural diagram of forming the first contact hole of the semiconductor device in the present application. As Figure 1 shown, the present embodiment first proposes a manufacturing method of a semiconductor device, which is used to prepare a semiconductor device, and the semiconductor device includes but is not limited to at least one of an image sensor, a logic chip, a memory, a power semiconductor device, etc. The manufacturing method of the present embodiment includes the following steps: Step S10: Provide a substrate 10, which includes a semiconductor substrate 11 and a gate structure, the gate structure being located on the semiconductor substrate 11 and including a metal gate 12.

[0021] Specifically, the substrate 10 is provided with a semiconductor substrate 11 and a gate structure. The semiconductor substrate 11 includes at least a functional region, and the functional region of the semiconductor substrate 11 may, but is not limited to, be provided with a gate structure of a PMOS device and / or an NMOS device, the gate structure including a metal gate 12.

[0022] Step S20: Form a mask layer 31 to cover the metal grid 12.

[0023] Specifically, when replacing the dummy gate structure with the metal gate 12, the dummy gate structure on the semiconductor substrate 11 can be removed first to form a groove on the semiconductor substrate 11. The dummy gate structure is the gate structure that needs to be removed in subsequent processing. At least one functional layer is formed in the groove to form the metal gate 12. A mask layer 31 is then formed on the metal gate 12 to cover it.

[0024] Step S30: Form an interlayer dielectric layer 20 to cover the substrate 10 and cover it with a mask layer 31.

[0025] After covering the metal gate 12 with a mask layer, an interlayer dielectric layer 20 is formed, which covers the substrate 10 and the metal gate 12. The interlayer dielectric layer 20, the mask layer, and the metal gate 12 are stacked so that the mask layer can be used to protect the metal gate 12.

[0026] Step S40: Dry etching is performed using the mask layer 31 as an etch stop layer to expose the mask layer 31.

[0027] like Figure 2 As shown, after forming the interlayer dielectric layer 20, patterning is performed on the interlayer dielectric layer 20, and dry etching is performed on the interlayer dielectric layer 20 using etching gas. The mask layer 31 serves as an etch stop layer for dry etching, forming aperture shapes on the interlayer dielectric layer 20 and exposing the mask layer 31 through these aperture shapes. The etching gas used in dry etching causes low wear on the mask layer 31, and as an etch stop layer, the mask layer 31 isolates the etching gas from the metal gate 12, preventing the formation of high-resistivity byproducts when the etching gas contacts the metal gate 12.

[0028] Step S50: Perform wet etching to further etch the mask layer 31 to form the first contact hole 40 that exposes the metal gate 12.

[0029] like Figure 3As shown, after the mask layer 31 is exposed, wet etching is performed to further etch the mask layer 31 and expose the metal gate 12 to form the first contact hole 40. In this embodiment, the etching gas used in the dry etching has a high etching loss on the mask layer 31, and the etching liquid used in the wet etching has a low etching loss on the mask layer 31, so that the mask layer can be removed by the wet etching after the mask layer is prevented from contacting the etching gas and the metal gate 12. In a possible manner, the etching liquid used in the wet etching has a low etching loss on the gate material, so as to ensure the stability of the semiconductor substrate 11.

[0030] In the embodiment of the present application, the method includes the following steps. A substrate 10 is provided, the substrate 10 including a semiconductor substrate 11 and a gate structure on the semiconductor substrate 11, the gate structure including a metal gate 12. A mask layer 31 is formed to cover the metal gate 12. An interlayer dielectric layer 20 is formed to cover the substrate 10 and cover the mask layer 31. Dry etching is performed by using the mask layer 31 as an etching stop layer to expose the mask layer 31. Wet etching is performed to further etch the mask layer 31 to form a first contact hole 40 exposing the metal gate 12. Therefore, by providing the mask layer 31 above the metal gate 12, the mask layer 31 can be used as a stop layer of the dry etching to prevent the etching gas from contacting the metal gate 12, so as to reduce or avoid the generation of high-resistance by-products such as aluminum fluoride complex in the etching process. The mask layer 31 is further removed by the wet etching to form the first contact hole 40 exposing the metal gate 12, so as to reduce the contact resistance of the metal plug filled in the first contact hole 40 and improve the connection stability.

[0031] In an embodiment, the gate structure (not shown in the figure) is provided with a dummy gate before the metal gate 12 is formed. At this time, the gate structure includes the dummy gate and a sidewall on both sides of the dummy gate, and the semiconductor substrate 11 forms a source region and a drain region on both sides of the gate structure, respectively. The substrate 10 further includes a first dielectric layer (not shown in the figure) covering the semiconductor substrate 11 and located between two adjacent gate structures.

[0032] In the embodiment, please refer to Figure 4 and Figure 5 , Figure 4 is Figure 1 a flowchart of the step of forming the metal gate in Figure 5 is a structural schematic diagram of the semiconductor device in the present application, in which a mask layer covers a metal gate. As shown in Figure 4 , the step S10 further includes the following steps. Step S11: providing a substrate 10, the substrate 10 including a gate structure forming a dummy gate.

[0033] Specifically, before forming the metal gate 12, a dummy gate is formed within the sidewalls of the gate structure. A source region and a drain region are formed outside the sidewalls of the gate structure, with the dummy gate located between the source and drain regions. The aforementioned source and drain regions serve as channels for carriers to enter and exit the channel, forming the active region of the semiconductor device.

[0034] Step S12: Remove the dummy gate in the gate structure to expose the groove formed by removing the dummy gate.

[0035] The dummy gate in the gate structure is removed to expose a groove formed by removing the dummy gate on the semiconductor substrate 11. The shape and size of the groove correspond to the sidewalls, and their shape and size can be set according to the requirements of the gate structure, without being specifically limited here.

[0036] Step S13: Form a metal grid 12 in the groove.

[0037] like Figure 5 As shown, a metal gate 12 is formed in the groove. The metal gate 12 is formed of a metal gate material layer 13, which includes, but is not limited to, an interface oxide layer, a high-k gate dielectric layer, a work function adjustment layer, a metal filling layer, and a metal oxide layer. In a possible manner, a first dielectric layer is formed on the groove before the metal gate 12 is formed. The first dielectric layer may be, but is not limited to, a dielectric layer composed of a tungsten thin film or tungsten fluoride. The first dielectric layer can be used to isolate the metal gate 12 from the semiconductor substrate 11, improving the stability of the metal gate 12.

[0038] A metal gate 12 is formed in the groove, and further, a mask layer 31 covering the metal gate 12 is formed in the groove. After the metal gate 12 and the mask layer 31 are formed, the surface of the mask layer 31 is flush with the surface of the semiconductor substrate 11 on both sides of the groove to meet the planarization requirements of subsequent processing.

[0039] Optionally, please see Figure 6 and Figure 7 , Figure 6 yes Figure 1 A schematic diagram of the process for forming a mask layer covering the metal grid. Figure 7 This is a schematic diagram of an embodiment of forming a mask material layer covering a metal grid material layer in this application.

[0040] In the manufacturing method of this embodiment, step S13 further includes the following step: depositing a metal gate material layer 13 to cover the semiconductor substrate 11.

[0041] like Figure 6 As shown, step S20 further includes the following steps: Step S21: Deposit mask material layer 32 to cover metal grid material layer 13, and portions of metal grid material layer 13 and mask material layer 32 are respectively filled in the groove.

[0042] Specifically, as shown in FIG. 1C, after removing the dummy gate on the semiconductor substrate 11 and exposing the recess, a metal gate material layer 13 and a mask material layer 32 are sequentially deposited on the base 10, and the mask material layer 32 covers the metal gate material layer 13, so that the recess is filled with the metal gate material layer 13 and the mask material layer 32 respectively. Figure 7

[0043] Step S22: removing part of the metal gate material layer 13 and the mask material layer 32 to reserve the metal gate material layer 13 and the mask material layer 32 in the recess as the metal gate 12 and the mask layer 31 respectively. The thickness of the metal gate material layer 13 is less than the height of the recess.

[0044] As shown in FIG. 1C, after depositing the metal gate material layer 13 and the mask material layer 32, the metal gate material layer 13 and the mask material layer 32 outside the recess are removed to reserve part of the metal gate material layer 13 in the recess as the metal gate 12, and the mask material layer 32 covering the metal gate 12 in the recess as the mask layer 31. The material of the metal gate material layer 13 at least includes metal materials such as aluminum, tungsten, cobalt, etc. In possible manners, the material of the metal gate material layer 13 can also include silicon oxide and / or silicon oxynitride for forming an interface oxide layer, high-k gate dielectric, titanium nitride or tantalum nitride for forming a work function adjustment layer, and aluminum for forming a metal filling layer. Figure 5 The thickness of the metal gate material layer 13 is less than the height of the recess, so that part of the mask material layer 32 also remains in the recess to cover the metal gate material layer 13. The remaining mask material layer 32 forms the mask layer 31 covering the metal gate 12, so that the mask layer 31 can act as a dry etching stop layer to block the etching gas from contacting the metal gate 12, reducing or avoiding the generation of high-resistance by-products such as aluminum fluoride complex during the etching process. In the embodiment, the height of the surface of the mask layer 31 exposed by the recess is flush with the height of the recess.

[0045] Optionally, after the specific step of depositing the metal gate material layer 13 covering the semiconductor substrate 11 in step S13, the manufacturing method further includes: forming a metal gate oxide layer 14 on the surface of the metal gate material layer 13.

[0046]

[0047] ​​Specifically, the metal gate material layer 13 can be left to stand for a period of time so that the exposed surface of the metal gate material layer 13 is oxidized to form the metal gate oxide layer 14; or the metal gate material layer 13 can be reacted with an oxidizing chemical solution to form the metal gate oxide layer 14 on the surface of the metal gate material layer 13; or the metal gate material layer 13 can be used as an anode and a current is passed through to oxidize the metal gate material layer 13 by electrochemical reaction and obtain the metal gate oxide layer 14 covering the metal gate material layer 13. The formation of the metal gate oxide layer 14 can be selected according to the processing requirements of the semiconductor chip, and is not specifically limited here.

[0048] The metal gate oxide layer 14 is used to protect the metal gate material layer 13 by forming an oxide film to improve the stability of the metal gate 12. The metal gate oxide layer 14 includes metal oxide generated by oxidation of the metal gate material layer 13, for example, when the material of the metal gate 12 is aluminum, the metal gate oxide layer 14 includes aluminum oxide to protect the metal gate 12 by the dense oxide film of the metal gate oxide layer 14. After the metal gate oxide layer 14 is formed, step S20 or steps S21-S22 described above are further performed to cover the metal gate oxide layer 14 with the mask layer 31, and the metal gate oxide layer 14 is located between the metal gate material layer 13 and the mask layer 31.

[0049] In an embodiment, the mask layer 31 is made of a material resistant to dry etching gas. The etching selectivity ratio of the dry etching gas to the interlayer dielectric layer 20 and the mask layer 31 is greater than 5:1.

[0050] Specifically, the mask layer 31 is made of a material resistant to dry etching gas. When dry etching is performed using the mask layer 31 as an etching stop layer, the etching gas selected has an etching selectivity ratio to the interlayer dielectric layer 20 and the mask layer 31 greater than 5:1. The etching selectivity ratio is the ratio of the etching rate of the etching gas to the interlayer dielectric layer 20 to the etching rate of the etching gas to the mask layer 31, and the ratio is greater than 5:1. For example, the etching selectivity ratio of the etching gas to the interlayer dielectric layer 20 and the mask layer 31 can be 6:1, 8:1, 10:1, etc.

[0051] Therefore, by the above method, the loss of the mask layer 31 can be ensured to be low when the dry etching gas etches the interlayer dielectric layer 20, and the mask layer 31 can block the etching gas from contacting the metal gate 12 as a dry etching stop layer, reducing or avoiding the generation of aluminum fluoride complex and other high-resistance by-products during etching.

[0052] Optionally, the material of the mask layer 31 includes titanium nitride and / or tantalum nitride. The thickness of the mask layer 31 is between 50Å and 400Å.

[0053] Specifically, the material of the mask layer 31 includes a dry-etching-resistant material such as titanium nitride and / or tantalum nitride. The thickness of the mask layer 31 is between 50 A and 400 A, for example, the thickness of the mask layer 31 is 50 A, 100 A, 150 A, 200 A, 250 A, 300 A, 350 A, or 400 A. Therefore, the loss of the mask layer 31 caused by the etching gas during the dry etching process will not penetrate the mask layer 31, ensuring that the mask layer 31 can act as a dry etching stop layer to block the etching gas from contacting the metal gate 12, reducing or avoiding the generation of high-resistance by-products such as aluminum fluoride complexes during the etching process.

[0054] Optionally, the sum of the thicknesses of the metal gate 12 and the mask layer 31 is between 200 A and 500 A.

[0055] The sum of the thicknesses of the metal gate 12 and the mask layer 31 is between 200 A and 500 A, for example, the sum of the thicknesses of the metal gate 12 and the mask layer 31 is 200 A, 250 A, 300 A, 350 A, 400 A, 450 A, or 500 A. Therefore, the gate performance can be ensured and the aspect ratio of the contact hole formed and the subsequent connection process can be ensured.

[0056] In an embodiment, the etching rate of the selected material of the etching solution for wet etching on the mask layer 31 and the metal gate 12 is greater than the etching rate of the selected material of the etching solution on the metal silicide. The selected material of the etching solution includes an ammonia-peroxide mixture or a hydrochloric acid-peroxide mixture.

[0057] Specifically, the metal silicide is one of the materials constituting the active region of the device. Compared with the metal silicide, the selected material of the etching solution for wet etching has a higher selectivity ratio on the mask layer 31 and the metal gate 12. That is, the etching rate of the selected material of the etching solution on the mask layer 31 and the metal gate 12 is higher during wet etching, and the loss of the active region of the device caused by the etching solution when opening the mask layer 31 to form the first contact hole 40 is lower, reducing or avoiding the problem of increased contact resistance caused by damage to the active region of the device. The metal gate 12 includes but is not limited to a hierarchical structure formed by the metal gate material layer 13 and the metal gate oxide layer 14. The selected material of the etching solution includes an ammonia-peroxide mixture or a hydrochloric acid-peroxide mixture.

[0058] Exemplarily, the metal silicide is a compound formed by a metal element and a silicon element, including but not limited to titanium silicide, cobalt silicide, nickel silicide, etc. The metal silicide is used to reduce the contact resistance and series resistance on the active region of the device. The etching rate of the selected material of the etching solution of the wet etching of the embodiment on the mask layer 31 and the metal gate 12 is greater than the etching rate of the selected material of the etching solution on the metal silicide, or the etching rate of the selected material of the etching solution of the embodiment on the metal silicide is lower than a preset value, or the etching rate of the selected material of the etching solution of the embodiment on the metal silicide is 0. When the first contact hole 40 is formed by wet etching, the problem of the increase of the contact resistance and the series resistance caused by the loss of the metal silicide can be reduced or avoided.

[0059] In an embodiment, referring to Figure 8 , Figure 8 is a schematic structural diagram of patterning of a semiconductor device in the present application. As Figure 8 shown, before step S40, the manufacturing method further comprises: sequentially forming a first anti-reflective layer 50, a dielectric anti-reflective layer 60, a second dielectric layer 70, a second anti-reflective layer 80 and a photoresist layer 90 to cover the interlayer dielectric layer 20.

[0060] Specifically, the photoresist layer 90 is provided with at least one pattern window, and the photoresist layer 90 serves as a top layer mask to define the etching position of the underlying level material through the pattern window. The second anti-reflective layer 80 is used to eliminate the standing wave effect of the photoresist layer 90 and improve the exposure topography of the photoresist layer 90. The second dielectric layer 70 is used to block the migration of nitrogen atoms in the second anti-reflective layer 80 to the substrate 10, so as to improve the stability of the substrate 10. The first anti-reflective layer 50 can be used to suppress standing waves. The dielectric anti-reflective layer 60 can be used to optimize the standing wave effect and serve as a mask for dry etching.

[0061] The present application also provides a semiconductor device, which comprises a substrate 10, a mask layer 31, an interlayer dielectric layer 20 and a first contact hole 40.

[0062] The substrate 10 comprises a semiconductor substrate 11 and a metal gate 12, and the metal gate 12 is located on the semiconductor substrate 11. The mask layer 31 covers part of the metal gate 12. The interlayer dielectric layer 20 covers the substrate 10 and covers the mask layer 31. The first contact hole 40 is arranged in the interlayer dielectric layer 20 and the mask layer 31 to expose the metal gate 12.

[0063] Specifically, the semiconductor substrate 11 is provided with a groove, and the metal gate 12 is arranged in the groove of the semiconductor substrate 11. The mask layer 31 is arranged in the groove and covers part of the metal gate 12. The height of the surface of the groove exposed by the mask layer 31 is flush with the height of the groove. The interlayer dielectric layer 20 covers the substrate 10, and the interlayer dielectric layer 20 further covers the mask layer 31. The interlayer dielectric layer 20 and the mask layer are etched to form the first contact hole 40, so as to expose the metal gate 12 through the first contact hole 40, and the metal gate 12 can be connected to the outside through the first contact hole 40.

[0064] In an embodiment, the width of the first contact hole 40 exposing the metal gate 12 is greater than the width of the first contact hole 40 in the interlayer dielectric layer 20.

[0065] Specifically, the opening of the first contact hole 40 in the interlayer dielectric layer 20 is formed by dry etching, and the opening of the first contact hole 40 further exposing the metal gate 12 is formed by wet etching. Since the etching rate of the etching solution selected for the material of the mask layer 31 and the metal gate 12 is large, when the etching solution initially contacts the metal gate 12 through the opening in the interlayer dielectric layer 20, an etching space including a sidewall corresponding to the size of the opening is opened on the surface of the metal gate 12; as the etching proceeds, the etching solution further enters the etching space and etches the sidewall, so that the etching space gradually increases until the etching stops. Therefore, the opening width formed by wet etching the mask layer 31 and the metal gate 12 is greater than the width of the first contact hole 40 in the interlayer dielectric layer 20.

[0066] The opening width of the first contact hole 40 in the interlayer dielectric layer 20 in the embodiment is less than the opening width of the first contact hole 40 in the mask layer 31, so that the width of the first contact hole 40 exposing the metal gate 12 is greater than the width of the first contact hole 40 in the interlayer dielectric layer 20. Therefore, the metal plug subsequently filled in the first contact hole 40 can be connected to the metal gate 12 with a larger contact area, effectively improving the connection stability of the metal gate 12.

[0067] In an embodiment, the metal gate 12 includes a metal gate material layer 13 and a metal gate oxide layer 14, the mask layer 31 covers the metal gate oxide layer 14, and the metal gate oxide layer 14 is located between the mask layer 31 and the metal gate material layer 13.

[0068] Specifically, the metal gate oxide layer 14 is used to protect the metal gate material layer 13 by forming an oxide film, so as to improve the stability of the metal gate 12. The metal gate oxide layer 14 includes a metal oxide generated after the metal gate material layer 13 is oxidized with oxygen, for example, when the material of the metal gate 12 is aluminum, the metal gate oxide layer 14 includes aluminum oxide, so as to protect the metal gate 12 by the dense oxide film of the metal gate oxide layer 14.

[0069] The above merely provides the implementation of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation based on the content of the present application specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises the following steps: providing a substrate, the substrate comprising a semiconductor substrate and a gate structure, the gate structure being located on the semiconductor substrate and comprising a metal gate; forming a mask layer covering the metal gate; forming an interlayer dielectric layer covering the substrate and covering the mask layer; performing dry etching using the mask layer as an etching stop layer to expose the mask layer; performing wet etching to further etch the mask layer to form a first contact hole exposing the metal gate.

2. The method according to claim 1, wherein: the gate structure comprises a dummy gate and a sidewall located on both sides of the dummy gate, and the semiconductor substrate forms a source region and a drain region on both sides of the gate structure respectively; and the substrate further comprises a first dielectric layer covering the semiconductor substrate and located between two adjacent gate structures; the step of providing a substrate, the substrate comprising a semiconductor substrate and a gate structure, the gate structure being located on the semiconductor substrate and comprising a metal gate, comprises: providing the substrate, the substrate comprising the gate structure forming the dummy gate; removing the dummy gate in the gate structure to expose a recess formed by removing the dummy gate; forming the metal gate in the recess.

3. The production method according to claim 2, characterized by the step of forming the metal gate in the recess comprises: depositing a metal gate material layer covering the semiconductor substrate; the step of forming a mask layer covering the metal gate comprises: depositing a mask material layer covering the metal gate material layer, and parts of the metal gate material layer and the mask material layer are filled in the recess respectively; removing parts of the metal gate material layer and the mask material layer, and parts of the metal gate material layer and the mask material layer in the recess are reserved as the metal gate and the mask layer; wherein the thickness of the metal gate material layer is less than the height of the recess.

4. The method according to claim 3, wherein: after the step of depositing a metal gate material layer covering the semiconductor substrate, the method further comprises: forming a metal gate oxide layer on the surface of the metal gate material layer.

5. The method according to claim 1, wherein: the mask layer is made of a material resistant to etching gas of the dry etching; the etching selectivity ratio of the etching gas of the dry etching to the interlayer dielectric layer and the mask layer is greater than 5:

1.

6. The method according to claim 5, wherein: the material of the mask layer comprises titanium nitride and / or tantalum nitride; the thickness of the mask layer is between 50Å and 400Å.

7. The method according to claim 5, wherein: the sum of the thicknesses of the metal gate and the mask layer is between 200Å and 500Å.

8. The method according to claim 1, wherein: the etching rate of the selected material of the etching solution of the wet etching to the mask layer and the metal gate is greater than the etching rate of the selected material of the etching solution to semiconductor material; the selected material of the etching solution comprises ammonia-peroxide mixed solution or hydrochloric acid-peroxide mixed solution.

9. A semiconductor device, characterized by comprising: ​ a substrate comprising a semiconductor substrate and a metal gate on the semiconductor substrate; a mask layer covering a portion of the metal gate; an interlayer dielectric layer covering the substrate and covering the mask layer; and a first contact hole disposed in the interlayer dielectric layer and the mask layer to expose the metal gate. The first contact hole exposes a width of the metal gate that is greater than a width of the first contact hole in the interlayer dielectric layer.

10. The semiconductor device of claim 9, wherein, ​

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