Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method of the semiconductor device, and the semiconductor device comprises a substrate which comprises a first region and a second region, the first region is provided with a connection structure, the second region is provided with a heat dissipation structure, the heat dissipation structure comprises a plurality of heat dissipation layers, intervals and a heat conduction material filled in the intervals, the intervals are located between the adjacent heat dissipation layers. According to the invention, the connection structure is formed in the first region of the substrate, and the heat dissipation structure is formed in the second region of the substrate, so that the heat dissipation structure formed in the second region can be in contact with a subsequently formed chip, heat dissipation is carried out on the chip, the heat dissipation effect of the semiconductor device is improved, and the performance of the semiconductor device is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the semiconductor device. Background Technology

[0002] In the application of integrated circuits, the performance of various devices is affected by the manufacturing process, because in order to improve chip performance, bonding between chips is usually required during the manufacturing process.

[0003] In current semiconductor devices, bonding technology is typically used to bond different chips in order to improve chip performance and achieve efficient interconnection between different chips. However, as the interconnection density increases, heat dissipation becomes difficult, which affects the performance of semiconductor devices. Summary of the Invention

[0004] The main technical problem solved by this invention is to provide a semiconductor device and a method for manufacturing the semiconductor device, which can effectively improve the heat dissipation effect of the semiconductor device and thus improve the performance of the semiconductor device.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: to provide a semiconductor device, comprising: a substrate, the substrate including a first region and a second region, wherein the first region is formed with a connection structure, the second region is formed with a heat dissipation structure, the heat dissipation structure including a plurality of heat dissipation layers, a spacer, and a thermally conductive material filling the spacer, wherein the spacer is located between adjacent heat dissipation layers in a direction parallel to the surface of the substrate; and a first dielectric layer covering the heat dissipation layers.

[0006] In one embodiment of this application, the connection structure and the heat dissipation layer are formed by removing a portion of the conductive material from the same conductive material through a first patterning process and a second patterning process, and the interval is a first opening located between adjacent heat dissipation layers.

[0007] In one embodiment of this application, the first dielectric layer covers the thermally conductive material and the connection structure; or, the first dielectric layer exposes the thermally conductive material but covers the connection structure.

[0008] In one embodiment of this application, a plurality of heat dissipation layers surround the first region in a ring-like manner.

[0009] In one embodiment of this application, the substrate includes a substrate and a first interconnect structure formed in the substrate, the first interconnect structure being located in the first region and electrically connected to the connection structure.

[0010] In one embodiment of this application, it further includes: a first type chip connected to the substrate in the first region; and a second type chip connected to the substrate; wherein a portion of the first type chip and a portion of the second type chip are respectively electrically connected to the connection structure in the first region, and the orthographic projection of another portion of the second type chip on the substrate at least partially overlaps with the orthographic projection of the heat dissipation structure on the substrate.

[0011] In one embodiment of this application, it further includes: a packaging substrate, wherein the substrate having the first type chip and the second type chip is bonded to the packaging substrate.

[0012] To solve the above-mentioned technical problems, another technical solution adopted in this application is: providing a method for manufacturing a semiconductor device, comprising: providing a substrate, the substrate including a first region and a second region, forming a connection structure in the first region, forming a heat dissipation structure in the second region, the heat dissipation structure including a plurality of heat dissipation layers, a spacer, and a thermally conductive material filling the spacer, wherein the spacer is located between adjacent heat dissipation layers in a direction parallel to the surface of the substrate; forming a first dielectric layer, the first dielectric layer covering the heat dissipation layers.

[0013] In one embodiment of this application, forming a connection structure in the first region and a heat dissipation structure in the second region includes: forming a conductive material located in the first region and the second region of the substrate; performing a first patterning process in the first region and a second patterning process in the second region to remove a portion of the conductive material, thereby forming the connection structure in the first region and the heat dissipation layer in the second region, wherein the interval is a first opening located between adjacent heat dissipation layers.

[0014] In one embodiment of this application, after the thermally conductive material is filled into the interval, the first dielectric layer is formed, and the first dielectric layer also covers the thermally conductive material and the connection structure.

[0015] In one embodiment of this application, a first dielectric layer is formed, which covers the connection structure and the heat dissipation layer and fills the gap; a third patterning process is performed to remove the first dielectric layer in the area where the gap is located to form a second opening; the thermally conductive material is filled in the second opening, and the thermally conductive material is exposed in the first dielectric layer.

[0016] In one embodiment of this application, the method further includes: providing a first type chip connected to the substrate in the first region; providing a second type chip connected to the substrate, wherein a portion of the second type chip is located on the first region and another portion of the second type chip is located on the second region; wherein the first type chip and a portion of the second type chip are respectively electrically connected to the connection structure in the first region, and the other portion of the second type chip is located on the heat dissipation structure in the second region.

[0017] Unlike existing technologies, the semiconductor device provided in this application includes: a substrate comprising a first region and a second region; a connection structure formed in the first region; and a heat dissipation structure formed in the second region; the heat dissipation structure comprising multiple heat dissipation layers, spacers, and thermally conductive material filling the spacers; wherein the spacers are located between adjacent heat dissipation layers in a direction parallel to the substrate surface; and a first dielectric layer covering the heat dissipation layers. In other words, in this application, a connection structure is formed in the first region of the substrate, and a heat dissipation structure is formed in the second region of the substrate, thereby allowing the heat dissipation structure formed in the second region to contact the subsequently formed chip, thereby dissipating heat from the chip, improving the heat dissipation effect of the semiconductor device, and thus improving the performance of the semiconductor device. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a schematic diagram of the structure of the first embodiment of the semiconductor device in this application; Figure 2 This application Figure 1 A magnified structural diagram of region C in the middle; Figure 3 This is a top view of the structure of the second embodiment of the semiconductor device in this application; Figure 4 It is in this application Figure 3 A schematic diagram of the cross-section along AA; Figure 5 This is a schematic diagram of the structure of the third embodiment of the semiconductor device in this application; Figure 6 This is a schematic flowchart of an embodiment of the semiconductor device manufacturing method in this application; Figure 7 This is a schematic diagram of the structure of one embodiment of the substrate in this application; Figure 8This is a schematic diagram of an embodiment of the connection structure and heat dissipation layer in this application; Figure 9 This is a schematic diagram of a structure forming the first dielectric layer in this application; Figure 10 This is a schematic diagram of the structure of an embodiment forming the second opening in this application; Figure 11 This is a schematic diagram of an embodiment of filling the second opening with thermally conductive material in this application.

[0019] In the attached figures, there are semiconductor device 10, substrate 100, connection structure 110, heat dissipation structure 120, heat dissipation layer 121, gap 122, thermally conductive material 123, first opening 124, substrate 130, first interconnect structure 131, second dielectric layer 140, first sub-dielectric layer 141, second sub-dielectric layer 142, through hole 143, first dielectric layer 200, first type chip 300, second type chip 400, packaging substrate 500, first region A, and second region B. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0021] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0022] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0023] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0024] This application provides a semiconductor device that can effectively improve the heat dissipation effect of the semiconductor device, thereby improving the performance of the semiconductor device.

[0025] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the semiconductor device in this application.

[0026] like Figure 1 As shown, the semiconductor device 10 of this application includes: a substrate 100 and a first dielectric layer 200; the substrate 100 includes a first region A and a second region B, the first region A having a connection structure 110, and the second region B having a heat dissipation structure 120, the heat dissipation structure 120 including a plurality of heat dissipation layers 121, spacers 122, and thermally conductive material 123 filling the spacers, wherein, in a direction parallel to the surface of the substrate 100, the spacers 122 are located between adjacent heat dissipation layers 121. The first dielectric layer 200 covers the heat dissipation layers 121.

[0027] The substrate 100 refers to any suitable material known in the art, which can be a semiconductor material or a non-semiconductor material. For example, the substrate 100 can be a wafer or a chip. Further, in this context, the substrate 100 is an interposer. The substrate 100 includes multiple first regions A and multiple second regions B. The second regions B are located around and adjacent to the first regions A, and can surround the first regions A. The first regions A are used to form chip regions on the substrate 100, and the chip regions have connection structures for electrical connection to the chips. The second regions B are used to form overhangs on the substrate 100. The overhangs support the portion of the chip to be connected to the substrate 100 that extends beyond the chip region, and can also provide electrical connection to the portion of the chip to be connected to the substrate 100 that extends beyond the chip region. The overhangs expand the chip area, and compared to an interposer without overhangs, an interposer with overhangs can support more chips.

[0028] Further, the substrate 100 includes a substrate 130 and a first interconnect structure 131 formed in the substrate 130. The first interconnect structure 131 is located in a first region A and is electrically connected to the connection structure 110. In one embodiment, the first interconnect structure 131 is a through silicon via structure. The connection structure 110 includes, but is not limited to, a hybrid bonding structure, a microbump structure, a pad, and a metal wiring layer. Figure 1 The C region is where the heat dissipation structure is located.

[0029] In this embodiment, by forming a connection structure in the first region of the substrate and a heat dissipation structure in the second region of the substrate, heat dissipation can be effectively provided for the subsequently formed chip. In turn, heat dissipation is achieved through the heat dissipation structure, which effectively improves the heat dissipation effect of the semiconductor device and thus improves the performance of the semiconductor device.

[0030] Please see Figure 2 , Figure 2 This application Figure 1 A magnified structural diagram of region C in the middle.

[0031] like Figure 2 As shown, the heat dissipation structure 120 includes multiple spaced heat dissipation layers 121, gaps 122 between the heat dissipation layers 121, and thermally conductive material 123 filled in the gaps 122. The heat dissipation layers 121 may be metallic materials, including but not limited to copper, aluminum, and gold. The thermally conductive material 123 may be a fluid, such as liquid or gas, and carries away heat by flowing within the gaps 122. The thermally conductive material 123 may be thermal grease G-751; the thermally conductive material 123 may also be solid.

[0032] In some embodiments, the top surface of the thermally conductive material 123 may be lower than the top surface of the heat dissipation layer 121, that is, the thermally conductive material 123 only fills part of the space 122, and the space 122 may also have a partial cavity. The first dielectric layer 200 may further fill the cavity and cover the thermally conductive material 123, or the first dielectric layer 200 may not fill the cavity and may seal the cavity; or, the top surface of the thermally conductive material 123 may be at the same level as the top surface of the heat dissipation layer 121, that is, the thermally conductive material 123 completely fills the space 122, and the first dielectric layer 200 may further cover the thermally conductive material 123; or, the top surface of the thermally conductive material 123 may be higher than the top surface of the heat dissipation layer 121, that is, after the thermally conductive material 123 fills the space 122, it extends to the top surface of the first dielectric layer 200, that is, the first dielectric layer 200 is provided with an opening, so that the thermally conductive material 123 can be exposed in the first dielectric layer 200, that is, the first dielectric layer 200 exposes the thermally conductive material 123. Furthermore, the first dielectric layer 200 may also cover the connection structure 110.

[0033] In some embodiments, the first dielectric layer 200 includes, but is not limited to, silicon nitride.

[0034] In some embodiments, the connection structure 110 and the heat dissipation layer 121 are formed by removing part of the conductive material from the same conductive material through a first patterning process and a second patterning process, and the interval 122 is a first opening located between adjacent heat dissipation layers 121.

[0035] The first patterning process is different from the second patterning process. For example, the first patterning process is the process of forming the connection structure 110, and the second patterning process is the process of forming the heat dissipation layer 121.

[0036] In this embodiment, by forming a connection structure in the first region of the substrate and a heat dissipation structure in the second region of the substrate, heat dissipation can be effectively provided for the subsequently formed chip. In turn, heat dissipation is achieved through the heat dissipation structure, which effectively improves the heat dissipation effect of the semiconductor device and thus improves the performance of the semiconductor device.

[0037] Please see Figures 3 to 4 , Figures 3 to 4 This is a schematic diagram of the structure of the second embodiment of the semiconductor device in this application. Figure 3 This is a top view of the second embodiment of the semiconductor device in this application. Figure 4 It is in this application Figure 3 A schematic diagram of the cross section along AA.

[0038] Figures 3 to 4 The diagram shows a rectangular substrate 100, with a first region A located in the middle of the substrate 100 and a second region B located at the edge of the substrate 100, surrounding the first region A. It is understood that this application does not limit the specific shape of the substrate 100.

[0039] In this embodiment, multiple heat dissipation layers 121 surround the first region A in a ring-like manner.

[0040] Specifically, multiple heat dissipation layers 121 form annular heat dissipation layers in the second region B. For example, each heat dissipation layer 121 forms an annular heat dissipation layer, and multiple heat dissipation layers 121 correspond to multiple annular heat dissipation layers. Each annular heat dissipation layer surrounds the first region A, and there are annular intervals 122 between the annular heat dissipation layers. The annular intervals 122 are filled with thermally conductive material 123.

[0041] Figures 3 to 4The illustration also shows a first-type chip 300 and four second-type chips 400. The first-type chip 300 is connected to a substrate 100 in a first region A, and the second-type chips 400 are also connected to the substrate 100. A portion of each of the first-type chip 300 and second-type chips 400 is electrically connected to a connection structure 110 in the first region A. The orthographic projection of another portion of the second-type chip 400 onto the substrate 100 at least partially overlaps with the orthographic projection of the heat dissipation structure 120 onto the substrate 100. One first-type chip 300 is disposed in the middle of the first region A of the substrate 100, and four second-type chips 400 are disposed at the four corners of the first region A of the substrate 100, covering at least a portion of the second region B. It is understood that the first-type chip 300 may also extend into the second region B, specifically determined by the size of the first-type chip 300. The number and arrangement of the first-type chips 300 and second-type chips 400 in this application are not limited to this.

[0042] The first type of chip 300 or the second type of chip 400 includes logic dies (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), microcontroller, etc.), memory dies (e.g., dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, etc.), power management dies (e.g., power management integrated circuit (PMIC) dies), radio frequency (RF) dies, sensor dies, microelectromechanical systems (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), etc., or combinations thereof.

[0043] In this embodiment, a first type of chip and a second type of chip are formed in a first region of the substrate. A portion of the first type of chip and a portion of the second type of chip are electrically connected to the connection structure of the first region, and another portion of the second type of chip is located above the heat dissipation structure of the second region of the substrate. Heat dissipation is achieved through the heat dissipation structure, which effectively improves the heat dissipation effect of the semiconductor device and thus improves the performance of the semiconductor device.

[0044] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of the third embodiment of the semiconductor device in this application.

[0045] like Figure 5 As shown, in Figure 4Based on this, the semiconductor device 10 of this application further includes: a packaging substrate 500, wherein a substrate 100 having a first type chip 300 and a second type chip 400 is bonded to the packaging substrate 500, wherein the substrate 100 includes a substrate 130 and a second dielectric layer 140, a first interconnect structure 131 is formed in the substrate 130, and a connection structure 110 and a heat dissipation structure 120 are formed in the second dielectric layer 140, the connection structure 110 is located in a first region A, and the heat dissipation structure 120 is located in a second region B.

[0046] Wherein, the packaging substrate 500 refers to any suitable packaging substrate known in the art.

[0047] This application also provides a method for manufacturing a semiconductor device.

[0048] Please see Figure 6 , Figure 6 This is a schematic flowchart of an embodiment of the semiconductor device manufacturing method in this application.

[0049] S10. A substrate is provided, the substrate including a first region and a second region, a connection structure is formed in the first region, and a heat dissipation structure is formed in the second region. The heat dissipation structure includes a plurality of heat dissipation layers, a spacer, and a thermally conductive material filling the spacer. In a direction parallel to the surface of the substrate, the spacer is located between adjacent heat dissipation layers.

[0050] The substrate 100 is described above and will not be repeated here.

[0051] Specifically, a substrate 100 is provided, with a region in the substrate 100 where the connection structure 110 is formed being designated as a first region A, and other regions of the substrate 100 being designated as a second region B. A heat dissipation structure 120 is also formed in the substrate 100 in the second region B. The heat dissipation structure 120 is located close to a first surface of the substrate 100. The heat dissipation structure 120 includes a plurality of heat dissipation layers 121, spacers 122, and a thermally conductive material 123, wherein the thermally conductive material 123 fills the spacers 122. Furthermore, in a direction parallel to the surface of the substrate 100, the spacers 122 are located between adjacent heat dissipation layers 121.

[0052] S20. A first dielectric layer is formed, and the first dielectric layer covers the heat dissipation layer.

[0053] The first dielectric layer includes, but is not limited to, silicon nitride.

[0054] Specifically, after the substrate 100 is provided with the connection structure 110 and the heat dissipation structure 120, a first dielectric layer 200 is formed on the substrate 100, and the first dielectric layer 200 covers the heat dissipation layer 121.

[0055] In this embodiment, by forming a connection structure in the first region of the substrate and a heat dissipation structure in the second region of the substrate, heat dissipation can be effectively provided for the subsequently formed chip. In turn, heat dissipation is achieved through the heat dissipation structure, which effectively improves the heat dissipation effect of the semiconductor device and thus improves the performance of the semiconductor device.

[0056] The manufacturing process is described below with reference to the accompanying drawings.

[0057] Please see Figure 7 , Figure 7 This is a schematic diagram of the structure of one embodiment of the substrate in this application.

[0058] like Figure 7 As shown, a substrate 100 is provided, which includes a first region A and a second region B. In one embodiment, the first region A is located in the middle of the substrate 100, and the second region B is located at the edge of the substrate 100, surrounding the first region A.

[0059] Furthermore, the substrate 100 includes a substrate 130 and a first interconnect structure 131 formed in the substrate 130, the first interconnect structure 131 being located in a first region A.

[0060] In some embodiments, a first sub-dielectric layer 141 may be formed, which covers the substrate 130 and the first interconnect structure 131, and is provided with a via 143, through which the first interconnect structure 131 is exposed.

[0061] Please see Figures 8 to 11 , Figures 8 to 11 This is a schematic diagram of an embodiment of the connection structure and heat dissipation structure formed in this application; Figure 8 This is a schematic diagram of an embodiment of the connection structure and heat dissipation layer in this application. Figure 9 This is a schematic diagram of the structure of an embodiment of the first dielectric layer in this application; Figure 10 This is a schematic diagram of the structure of an embodiment forming the second opening in this application; Figure 11 This is a schematic diagram of a structure of an embodiment of the thermally conductive material formed in this application.

[0062] like Figure 8 As shown, in Figure 7 Based on this, a conductive material is formed, which is located in the first region A and the second region B of the substrate 100, covers the first sub-dielectric layer 141, and fills the through-holes 143, so that at least a portion of the conductive material is connected to the first interconnect structure 131.

[0063] Next, a first patterning process is performed in the first region A and a second patterning process is performed in the second region B to remove part of the conductive material, so as to form a connection structure 110 in the first region A and a heat dissipation layer 121 in the second region B, with a first opening 124 located between adjacent heat dissipation layers 121 at interval 122.

[0064] Continue reading Figure 8 A first patterning process is performed in the first region A to remove a portion of the conductive material in the first region A, with the remaining conductive material in the first region A serving as the connection structure 110; and a second patterning process is performed in the second region B to remove a portion of the conductive material in the second region B, with the remaining conductive material in the second region B serving as the heat dissipation layer 121.

[0065] There may be multiple heat dissipation layers 121, and there is a first opening 124 between adjacent heat dissipation layers 121, with the first opening 124 between adjacent heat dissipation layers 121 serving as a gap 122.

[0066] It is understandable that there is no restriction on the order of performing the first patterning process and the second patterning process; however, the pattern of the first patterning process is different from the pattern of the second patterning process; the patterning process refers to forming the target pattern by etching a portion of the material in the execution layer material through etching.

[0067] In one embodiment, such as Figure 9 As shown, in Figure 8 Based on this, thermally conductive material 123 is filled within the interval 122 to form a heat dissipation structure 120 in the second region B; that is, the heat dissipation layer 121, the interval 122 between the heat dissipation layers 121, and the thermally conductive material 123 filled in the interval 122 constitute the heat dissipation structure 120. A first dielectric layer 200 is then formed, covering the heat dissipation layer 121, the thermally conductive material 123, and the connecting structure 110. It is understood that when the thermally conductive material 123 is in a liquid or gaseous state, it can also be implanted after the formation of the first dielectric layer 200 via post-implantation onto the substrate 100.

[0068] Before forming the thermally conductive material 123, a second sub-dielectric layer 142 may be formed, which covers the first sub-dielectric layer 141. The second sub-dielectric layer 142 and the first sub-dielectric layer 141 constitute a second dielectric layer 140. The second sub-dielectric layer 142 is located between adjacent connecting structures 110 and between the connecting structure 110 and the heat dissipation layer 121. The second sub-dielectric layer 142 exposes a gap 122, and then the thermally conductive material 123 is filled in the gap 122.

[0069] In other embodiments, such as Figure 10 As shown, in Figure 8Based on this, a first dielectric layer 200 is formed, which covers the connecting structure 110 and the heat dissipation layer 121 and fills the gap 122; a third patterning process is performed to remove the first dielectric layer 200 in the area where the gap 122 is located to form a second opening (not shown); a thermally conductive material 123 is filled in the second opening, and the thermally conductive material 123 is exposed in the first dielectric layer 200.

[0070] It is understood that the second opening is part of the space 122, that is, the opening formed by part of the first dielectric layer in the area where the space is removed is the second opening, and the entire space into which the second opening extends is the space 122. That is, the first opening in the conductive material and the second opening in the first dielectric layer 200 together constitute the space 122.

[0071] Before forming the first dielectric layer 200, a second sub-dielectric layer 142 may be formed. The second sub-dielectric layer 142 covers the first sub-dielectric layer 141. The second sub-dielectric layer 142 and the first sub-dielectric layer 141 constitute the second dielectric layer 140, which also covers the connection structure 110 and the heat dissipation layer 121.

[0072] It is understood that if a second sub-dielectric layer 142 is formed above the first sub-dielectric layer 141, then at least a portion of the second sub-dielectric layer 142 needs to be removed so that the thermally conductive material 123 of the heat dissipation structure 120 is at least exposed.

[0073] Then, thermally conductive material 123 is filled into the spacer 122 through the second opening, exposing the thermally conductive material 123 in the first dielectric layer 200.

[0074] like Figure 11 As shown, in Figure 10 Based on this, thermally conductive material 123 is filled into the space 122 from the second opening, so that the thermally conductive material 123 can be exposed from the first dielectric layer 200.

[0075] Thus, the heat dissipation structure 120 is formed by the heat dissipation layer 121, the space 122, and the thermally conductive material 123 filled in the space 122.

[0076] Next, a first type chip 300 and a second type chip 400 are provided, and the first type chip 300 and the second type chip 400 are connected to the substrate 100.

[0077] like Figure 4 As shown, a first-type chip 300 and two second-type chips 400 are illustrated. Specifically, in Figure 10Based on this, a first type chip 300 is connected to the substrate 100 of the first region A, and a second type chip 400 is connected to the substrate 100. A portion of each of the first type chip 300 and the second type chip 400 is electrically connected to the connection structure 110 in the first region A. The orthographic projection of another portion of the second type chip 400 onto the substrate 100 at least partially overlaps with the orthographic projection of the heat dissipation structure 120 onto the substrate 100. One first type chip 300 is disposed in the middle of the first region A of the substrate 100, and two second type chips 400 are disposed on either side of the first region A of the substrate 100, covering at least a portion of the second region B. The number and arrangement of the first type chip 300 and the second type chip 400 in this application are not limited to this.

[0078] Additionally, the first type chip 300 is electrically connected to the connection structure 110 in the first region A of the substrate 100, a portion of the second type chip 400 is electrically connected to the connection structure 110 in the first region A, another portion of the second type chip 400 is located in the second region B of the substrate 100, and at least a portion of the second type chip 400 is located on the heat dissipation structure 120.

[0079] The first type of chip 300 or the second type of chip 400 includes logic dies (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), microcontroller, etc.), memory dies (e.g., dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, etc.), power management dies (e.g., power management integrated circuit (PMIC) dies), radio frequency (RF) dies, sensor dies, microelectromechanical systems (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), etc., or combinations thereof.

[0080] Specifically, a first type chip 300 and a second type chip 400 are provided. The first type chip 300 is formed on a first region A of the substrate 100 and electrically connected to a connection structure 110 in the first region A. The second type chip 400 is formed on the substrate 100, with a portion of the second type chip 400 located in the first region A and electrically connected to the connection structure 110 in the first region A, and another portion of the second type chip 400 located in a second region B and situated on a heat dissipation structure 120 in the second region B. For example, the second type chip 400 is in at least partial contact with the heat dissipation structure 120 in the second region B.

[0081] Furthermore, the substrate 100 can be thinned to expose the first interconnect structure 131 from the second side of the substrate 130; then, the first type chip 300 and the second type chip 400 are formed on the substrate 100; and then the first interconnect structure 131 in the substrate 100 is bonded to the packaging substrate 500. (See also...) Figure 5 .

[0082] In this embodiment, a first type of chip is formed in a first region of the substrate, which is electrically connected to the connection structure of the first region. A second type of chip is formed in a second region of the substrate, which is in contact with the heat dissipation structure of the second region. Heat is then dissipated through the heat dissipation structure, which effectively improves the heat dissipation effect of the semiconductor device and thus improves the performance of the semiconductor device.

[0083] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that, include: A substrate, the substrate including a first region and a second region, the first region having a connection structure, the second region having a heat dissipation structure, the heat dissipation structure including a plurality of heat dissipation layers, a spacer, and a thermally conductive material filling the spacer, wherein, in a direction parallel to the surface of the substrate, the spacer is located between adjacent heat dissipation layers; A first dielectric layer covers the heat dissipation layer.

2. The semiconductor device according to claim 1, characterized in that, The connection structure and the heat dissipation layer are formed by removing a portion of the conductive material through a first patterning process and a second patterning process, respectively, and the interval is a first opening located between adjacent heat dissipation layers.

3. The semiconductor device according to claim 1, characterized in that, The first dielectric layer covers the thermally conductive material and the connection structure; or, The first dielectric layer exposes the thermally conductive material but covers the connection structure.

4. The semiconductor device according to claim 1, characterized in that, The first region is surrounded by multiple heat dissipation layers arranged in a ring.

5. The semiconductor device according to claim 1, characterized in that, The substrate includes a substrate and a first interconnect structure formed in the substrate, the first interconnect structure being located in the first region and electrically connected to the connection structure.

6. The semiconductor device according to claim 1, characterized in that, It also includes, A first type of chip is connected to the substrate in the first region; A second type of chip is connected to the substrate; Wherein, a portion of the first type chip and a portion of the second type chip are electrically connected to the connection structure in the first region, and the orthographic projection of another portion of the second type chip on the substrate at least partially overlaps with the orthographic projection of the heat dissipation structure on the substrate.

7. The semiconductor device according to claim 6, characterized in that, Also includes: A packaging substrate, wherein the substrate having the first type of chip and the second type of chip is bonded to the packaging substrate.

8. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, the substrate including a first region and a second region, a connection structure is formed in the first region, and a heat dissipation structure is formed in the second region. The heat dissipation structure includes a plurality of heat dissipation layers, a spacer, and a thermally conductive material filling the spacer. In a direction parallel to the surface of the substrate, the spacer is located between adjacent heat dissipation layers. A first dielectric layer is formed, which covers the heat dissipation layer.

9. The manufacturing method according to claim 8, characterized in that, The step of forming a connection structure in the first region and a heat dissipation structure in the second region includes: A conductive material is formed, wherein the conductive material is located in the first region and the second region of the substrate; A first patterning process is performed in the first region and a second patterning process is performed in the second region to remove a portion of the conductive material, thereby forming the connection structure in the first region and the heat dissipation layer in the second region, wherein the spacing is a first opening located between adjacent heat dissipation layers.

10. The manufacturing method according to claim 9, characterized in that, After the thermally conductive material is filled into the interval, the first dielectric layer is formed, and the first dielectric layer also covers the thermally conductive material and the connection structure.

11. The manufacturing method according to claim 9, characterized in that, A first dielectric layer is formed, which covers the connection structure and the heat dissipation layer and fills the gap; A third patterning process is performed to remove the first dielectric layer in the region where the interval is located to form a second opening; The thermally conductive material is filled into the second opening, and the thermally conductive material is exposed in the first dielectric layer.

12. The manufacturing method according to claim 8, characterized in that, Also includes: A first type of chip is provided, the first type of chip being connected to the substrate in the first region; A second type of chip is provided, the second type of chip being connected to the substrate, and a portion of the second type of chip being located on the first region, and another portion of the second type of chip being located on the second region; The first type of chip and a portion of the second type of chip are electrically connected to the connection structure in the first region, and another portion of the second type of chip is located on the heat dissipation structure in the second region.

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