Ultra-thin multi-chip device

Abstract

The invention relates to the technical field of semiconductors, in particular to an ultra-thin multi-chip device, which comprises a chip comprising a silicon-based chip and a compound semiconductor chip which are sealed with each other; a frame base island structure, wherein all or part of the chip is arranged in the frame base island structure in a sinking manner; or, the frame base island structure is a structure of which the thickness is reduced through selective etching, and the chip is stacked on the frame base island structure. The compound semiconductor chip and the silicon-based chip can be highly integrated, the size of the whole device is controlled to be slightly larger than that of the silicon-based chip, the total chip packaging thickness can be effectively reduced, device miniaturization is achieved, and then multi-scene application can be achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a super-thin multi-chip device. BACKGROUND

[0002] Single compound semiconductor chips often have insufficient sensitivity and unstable performance in applications.

[0003] To achieve the high integration and miniaturization of compound semiconductor chips, related technologies usually use chip sealing methods such as flip chip and ball grid array (BGA). For example, a mother chip is first attached to a frame base island, and copper wires or other leads are used to connect the mother chip to the frame. Then, a child chip is attached to the mother chip, and copper wires or other leads are used to connect the child chip to the mother chip. If there are more child chips, they can be stacked in layers and connected by leads. Finally, the entire assembly is encapsulated and molded into a module.

[0004] The stacking method without any processing in related technologies results in low sensitivity, signal-to-noise ratio, reliability, and stability of compound semiconductor chips. Moreover, the stacking method without any processing in related technologies results in a large volume of the entire module, and the thickness often exceeds the expected value, limiting the application in more scenarios. SUMMARY

[0005] The present application provides a super-thin multi-chip device to at least solve the above problems in related technologies.

[0006] To solve the above technical problems, the technical solutions of the present application are as follows: In an optional embodiment, the super-thin multi-chip device includes: a chip including a silicon-based chip and a compound semiconductor chip that are sealed together; a frame base island structure, all or part of the chip is sunken inside the frame base island structure; or the frame base island structure is a structure that is thinned by selective etching, and the chip is stacked on the frame base island structure.

[0007] In an optional embodiment, when all or part of the chip is sunken inside the frame base island structure, the frame base island structure includes a bottom structure and a peripheral structure, the bottom structure and the peripheral structure form an internally hollow frame base island structure, the silicon-based chip is sunken inside the frame base island structure, and the compound semiconductor chip is stacked on the silicon-based chip. The thickness of the super-thin multi-chip device is less than 0.2 mm.

[0008] In an optional embodiment, when the frame base island structure is a structure with thickness reduction by selective etching, the silicon-based chip is disposed in the area of the frame base island structure with selective etching, and the compound semiconductor chip is stacked on the silicon-based chip; The thickness of the ultra-thin multi-chip device is less than 0.25 mm.

[0009] In an optional embodiment, a groove is formed on the silicon-based chip by photolithography and selective etching, and the compound semiconductor chip is stacked in the groove.

[0010] In an optional embodiment, when the silicon-based chip is disposed in the interior of the frame base island structure and the compound semiconductor chip is stacked in the groove, the thickness of the ultra-thin multi-chip device is less than 0.15 mm; In an optional embodiment, when the frame base island structure is a structure with thickness reduction by selective etching, the silicon-based chip is stacked on the frame base island structure, and the compound semiconductor chip is stacked in the groove, the thickness of the ultra-thin multi-chip device is less than 0.2 mm; In an optional embodiment, when the frame base island structure is a structure without thickness reduction by selective etching, the silicon-based chip is stacked on the frame base island structure, and the compound semiconductor chip is stacked in the groove, the thickness of the ultra-thin multi-chip device is less than 0.25 mm.

[0011] In an optional embodiment, the silicon-based chip and the frame base island structure are connected by lead wires; The silicon-based chip and the compound semiconductor chip are connected by lead wires or by flip-chip with solder balls.

[0012] In an optional embodiment, the silicon-based chip and the compound semiconductor chip are simultaneously disposed in the interior or on the upper surface of the frame base island structure, and the upper surface of the silicon-based chip and the upper surface of the compound semiconductor chip are at the same level.

[0013] In an optional embodiment, the frame base island structure comprises a bottom structure and a peripheral structure, the bottom structure and the peripheral structure form an internally hollow frame base island structure, the silicon-based chip and the compound semiconductor chip are simultaneously disposed in the interior of the frame base island structure, and the upper surface of the silicon-based chip and the upper surface of the compound semiconductor chip are at the same level. Alternatively, the frame base island structure is a structure that is thinned in thickness by selective etching, the silicon-based chip and the compound semiconductor chip are placed on the upper surface of the frame base island structure, and the upper surface of the silicon-based chip and the upper surface of the compound semiconductor chip are at the same level. Alternatively, the frame base island structure is a structure that is not thinned in thickness by selective etching, the silicon-based chip and the compound semiconductor chip are placed on the upper surface of the frame base island structure, and the upper surface of the silicon-based chip and the upper surface of the compound semiconductor chip are at the same level.

[0014] In an optional embodiment, the silicon-based chip and the compound semiconductor chip are connected by a lead, and the silicon-based chip and the frame base island structure are connected by a lead.

[0015] In an optional embodiment, the electronic device includes the ultra-thin multi-chip device of any of the above embodiments.

[0016] The technical scheme provided by the embodiments of the present application at least brings the following beneficial effects: The chip in the embodiments of the present application includes a silicon-based chip and a compound semiconductor chip that are hermetically sealed. Since the compound semiconductor chip is represented by gallium arsenide, indium arsenide and indium antimonide, its electron mobility is several times or even tens of times that of silicon, so the sensitivity of the compound semiconductor chip is significantly higher than that of the silicon-based Hall chip. Therefore, by hermetically sealing the compound semiconductor chip and the silicon-based chip, the sensitivity, sensor, reliability and stability of the device can be improved. In addition, by providing a frame base island structure, all or part of the chip can be sunk inside the frame base island structure, or the frame base island structure is set to a structure that is thinned in thickness by selective etching, and the chips are stacked on the frame base island structure. By different combinations of the frame base island structure, the silicon-based chip and the compound semiconductor chip, different hermetic sealing modes can be achieved, so that the compound semiconductor chip and the silicon-based chip can be highly integrated, the size of the whole device can be controlled to be slightly larger than the size of the silicon-based chip, the total thickness of the chip packaging can be effectively reduced, the device miniaturization can be realized, and multi-scene application can be realized. BRIEF DESCRIPTION OF DRAWINGS

[0017] The accompanying drawings, which are incorporated into and form part of the specification, illustrate an embodiment consistent with the present application and, together with the specification, serve to explain the principles of the present application and do not constitute an improper limitation of the present application.

[0018] Figure 1 is a structure diagram of an ultra-thin multi-chip device according to an exemplary embodiment Figure One .

[0019] Figure 2 is a structural diagram of a super-thin multi-chip device according to an exemplary embodiment Figure Two .

[0020] Figure 3 is a structural diagram of a super-thin multi-chip device according to an exemplary embodiment Figure Three .

[0021] Figure 4 is a structural diagram of a super-thin multi-chip device according to an exemplary embodiment Figure Four .

[0022] Figure 5 is a structural diagram of a super-thin multi-chip device according to an exemplary embodiment Figure Five .

[0023] Figure 6 is a structural diagram of a super-thin multi-chip device according to an exemplary embodiment Figure Six .

[0024] Figure 7 is a structural diagram of a super-thin multi-chip device according to an exemplary embodiment Figure Seven .

[0025] Figure 8 is a structural diagram of a super-thin multi-chip device according to an exemplary embodiment Figure Eight .

[0026] Figure 9 is a structural diagram of a super-thin multi-chip device according to an exemplary embodiment Figure Nine .

[0027] wherein the reference numerals in the figures correspond to: 1 - frame base island structure, 2 - silicon-based chip, 3 - compound semiconductor chip, 4 - lead. DETAILED DESCRIPTION

[0028] The following detailed description is presented in terms of a number of different embodiments or examples for implementing different features of the provided subject matter. The following detailed description describes certain examples of elements and / or configurations using the terminology "for example," "for instance," and "such as." These terms should not be construed so as to mean that the various embodiments are limited to the particular elements or configurations described. For example, the formation of one feature over or on another feature in the following description is intended to encompass embodiments where the one feature is formed directly on the other feature and embodiments where intervening features are formed between the one feature and the other feature such that the one feature and the other feature are not in direct contact. Further, the present application can make reference to certain examples in various places throughout the detailed description. These references are intended to serve as connections or relationships between the various embodiments and / or configurations, such that the applicant does not desire to receive equivalent structures only because they are not explicitly described in the examples.

[0029] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", "front", "back", "on", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures.

[0030] The embodiments of the present application provide a super-thin multi-chip device, which comprises: a chip, the chip comprising a silicon-based chip and a compound semiconductor chip which are mutually encapsulated; a frame base island structure, all or part of the chip being disposed inside the frame base island structure; or the frame base island structure being a structure which is thinned by selective etching, and the chip being stacked on the frame base island structure.

[0031] In some embodiments, the encapsulation manner between the mutually encapsulated silicon-based chip and compound semiconductor chip can be any one of the following: the compound semiconductor chip being stacked on the silicon-based chip, and the compound semiconductor chip and the silicon-based chip being on the same horizontal plane.

[0032] In some embodiments, all of the chip (i.e. the mutually encapsulated silicon-based chip and compound semiconductor chip) can be disposed inside the frame base island structure, or part of the chip (e.g. the silicon-based chip) can be disposed inside the frame base island structure. By the disposition, the size of the device, especially the thickness of the device, can be adjusted, and the total thickness of the chip package can be effectively reduced, so that the device can be miniaturized. It should be noted that, in the case that all of the chip is disposed inside the frame base island structure, the encapsulation manner between the silicon-based chip and the compound semiconductor chip can be that the compound semiconductor chip and the silicon-based chip are on the same horizontal plane. In the case that part of the chip is disposed inside the frame base island structure, the encapsulation manner between the silicon-based chip and the compound semiconductor chip can be that the silicon-based chip is disposed inside the frame base island structure, and the compound semiconductor chip is stacked on the silicon-based chip.

[0033] In other embodiments, in the case that the frame base island structure is a structure which is thinned by selective etching, the chip (i.e. the mutually encapsulated silicon-based chip and compound semiconductor chip) can be stacked on the frame base island structure. In this case, the encapsulation manner can be any one of the following: the compound semiconductor chip being stacked on the silicon-based chip, and the compound semiconductor chip and the silicon-based chip being on the same horizontal plane.

[0034] In other embodiments, where the framework island structure is a structure thinned by selective etching, the chip (i.e., the inter-encapsulated silicon-based chip and compound semiconductor chip) can also be stacked on the framework island structure. In this case, the encapsulation method can be any of the following: the compound semiconductor chip is stacked on the silicon-based chip, or the compound semiconductor chip and the silicon-based chip are on the same horizontal plane.

[0035] In some embodiments, the material of the silicon-based chip may include, but is not limited to, silicon (Si), germanium (Ge), etc.

[0036] In some embodiments, the compound semiconductor chip refers to a chip made of a semiconductor material formed by the combination of two or more elements. Optionally, the compound semiconductor chip is a group III-V compound semiconductor, the material of which is a combination of group III elements (such as gallium Ga, indium In) and group V elements (such as arsenic As, phosphorus P, nitrogen N) from the periodic table. Exemplarily, the material of the compound semiconductor chip is gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium gallium phosphide, etc. Because the electron mobility of compound semiconductor chips is several times or even tens of times that of silicon, the sensitivity of the device is significantly higher than that of silicon-based Hall chips.

[0037] In some embodiments, the frame island structure is a core component of the lead frame in a semiconductor package, referring to a metal platform used to fix and support the chip.

[0038] The chip in this embodiment includes a silicon-based chip and a compound semiconductor chip that are encapsulated together. Since compound semiconductor chips, represented by gallium arsenide, indium arsenide, and indium antimonide, have electron mobilities several times or even tens of times higher than silicon, their sensitivity is significantly higher than that of silicon-based Hall effect chips. Therefore, encapsulating the compound semiconductor chip with the silicon-based chip can improve the device's sensitivity, sensor performance, reliability, and stability. Furthermore, by setting a frame-island structure, all or part of the chip can be recessed into the frame-island structure. Alternatively, the frame-island structure can be selectively etched to reduce its thickness, and the chip can be stacked on top of the frame-island structure. Different encapsulation methods can be achieved through different combinations of the frame-island structure, silicon-based chip, and compound semiconductor chip, thereby enabling high integration of the compound semiconductor chip and the silicon-based chip. This keeps the overall device size slightly larger than the silicon-based chip and effectively reduces the total chip package thickness, achieving device miniaturization and enabling applications in multiple scenarios.

[0039] The following description uses the example of a frame-based island structure that has undergone selective etching to reduce its thickness to illustrate the above-mentioned ultra-thin multi-chip device.

[0040] Figure 1 This is a schematic diagram of the structure of an ultrathin multi-chip device according to an exemplary embodiment. Figure One , Figure 1 In this context, 'a' represents the top view. Figure 1 In this context, 'b' represents the front view, such as... Figure 1 As shown, a silicon-based chip 2 is directly stacked on a frame-based island structure 1, and a compound semiconductor chip 3 is also stacked on the silicon-based chip 2, thus achieving encapsulation. This solution does not require additional modifications to the frame-based island structure 1 or the silicon-based chip 2. Adhesive is directly applied at predetermined positions on the frame-based island structure 1, or a die-attach film (DAF) is used to place the silicon-based chip 2 on the frame-based island structure 1. Leads 4 connect the silicon-based chip 2 and the frame-based island structure 1. In this embodiment, the compound semiconductor chip 3 is connected to the silicon-based chip 2 using flip-chip soldering. Figure 1 As shown, the compound semiconductor chip 3 can be attached to the silicon-based chip 2 by flip-chip bonding, which can avoid the influence of the arc height of the bonding wire and further reduce the thickness.

[0041] As can be seen, by directly stacking the silicon-based chip 2 on the frame-island structure 1 and the compound semiconductor chip 3 on the silicon-based chip 2, no additional modifications are required to the frame-island structure 1 and the silicon-based chip 2, thus reducing the packaging cost. Furthermore, since the compound semiconductor chip 3 is represented by gallium arsenide, indium arsenide, and indium antimonide, its electron mobility is several times or even tens of times that of silicon, resulting in significantly higher device sensitivity than silicon-based Hall effect chips. Therefore, by packaging the compound semiconductor chip 3 with the silicon-based chip 2, the device's sensitivity, sensor signal-to-noise ratio, reliability, and stability can be improved. In addition, this configuration allows the overall device thickness to be less than 0.3 mm, effectively reducing the total chip package thickness, achieving device miniaturization, and enabling applications in multiple scenarios.

[0042] The following description uses the case where all or part of the chip is recessed inside the frame base island as an example to illustrate the ultra-thin multi-chip device.

[0043] In some embodiments, where all or part of the chip is recessed within the frame-based island structure, the frame-based island structure includes a bottom structure and a surrounding structure, the bottom structure and the surrounding structure forming an internally hollow frame-based island structure, the silicon-based chip is recessed within the frame-based island structure, and the compound semiconductor chip is stacked on the silicon-based chip; the thickness of the ultrathin multi-chip device is less than 0.2 mm.

[0044] Figure 2 This is a schematic diagram of the structure of an ultrathin multi-chip device according to an exemplary embodiment.Figure Two , Figure 2 a is a top view, Figure 2 b is a front view, as shown in Figure 2 The frame base island structure 1 includes a bottom structure and a peripheral structure, which form an internally hollow frame base island structure. When the frame base island structure 1 is manufactured, a high-temperature film is pasted to the bottom. When pasting, the chip bonding DAF film is used to place the silicon-based chip 2 on the high-temperature film, so as to realize the sinking arrangement of the silicon-based chip 2 in the interior of the frame base island structure 1. At the same time, the compound semiconductor chip 3 is stacked on the silicon-based chip 2.

[0045] It should be noted that, in order to further reduce the thickness of the ultra-thin multi-chip device, when the silicon-based chip 2 is sinkingly arranged in the interior of the frame base island structure 1, the upper surface of the silicon-based chip 2 can be flush with the top of the frame base island structure 1.

[0046] In some embodiments, the silicon-based chip 2 and the frame base island structure 1 can be connected through the lead wire 4, and the compound semiconductor chip 3 and the silicon-based chip 2 can also be connected through the lead wire 4. In other embodiments, the compound semiconductor chip 3 and the silicon-based chip 2 can also be connected through the solder ball flip chip mode. Figure 3 is a structural schematic diagram of an ultra-thin multi-chip device according to an exemplary embodiment Figure Three As shown in Figure 3 By means of the solder ball flip chip mode, the compound semiconductor chip 3 is pasted on the silicon-based chip 2, which can avoid the influence of the wire arc height of the solder wire, and further reduce the thickness.

[0047] It can be seen that, since the compound semiconductor chip 3 is represented by gallium arsenide, indium arsenide and indium antimonide, the electron mobility is several times or even tens of times of that of silicon, so the sensitivity of the device is obviously higher than that of the silicon-based Hall chip. Therefore, by means of the frame base island structure 1 which includes a bottom structure and a peripheral structure, the bottom structure and the peripheral structure form an internally hollow frame base island structure, the silicon-based chip 2 is sinkingly arranged in the interior of the frame base island structure 1, and the compound semiconductor chip 3 is stacked on the silicon-based chip 2, the sensitivity, sensor signal-to-noise ratio, reliability and stability of the device can be improved. In addition, this kind of sealing method can control the thickness of the device within a minimum range, for example, the thickness of the ultra-thin multi-chip device can be controlled within 0.2 mm, which effectively reduces the total thickness of the chip packaging and realizes the miniaturization of the device, thereby realizing multi-scene application.

[0048] Hereinafter, the ultra-thin multi-chip device is described by taking the case that the frame base island structure 1 is a structure subjected to selective etching and thickness reduction.

[0049] In some embodiments, when the frame base island structure 1 is a structure that is thinned in thickness by selective etching, the silicon-based chip 2 is disposed on the selectively etched region of the frame base island structure 1, and the compound semiconductor chip 3 is stacked on the silicon-based chip 2; the thickness of the ultra-thin multi-chip device is less than 0.25 mm.

[0050] Figure 4 is a structural schematic of an ultra-thin multi-chip device according to an exemplary embodiment Figure Four , Figure 4 a in FIG. is a top view, Figure 4 b in FIG. is a front view, Figure 4 c in FIG. is a side view, as shown in Figure 4 , the frame base island structure 1 can be selectively etched first, so that a selectively etched region is formed on the frame base island structure 1, and the silicon-based chip 2 is placed on the frame base island structure 1 by dispensing or using a chip bonding DAF film.

[0051] It should be noted that the specific process of selective etching is not limited in the embodiments of the present application, which can include the following steps: designing and typesetting the pattern to be processed, and making a fluorescent plate, then placing the fluorescent plate into an etching frame, after exposure, placing the fluorescent plate into a solution for etching, etching away the unnecessary copper foil to form the desired pattern, and obtaining the selectively etched region.

[0052] In some embodiments, the distance between the selectively etched region and the bottom of the frame base island mainly depends on the accuracy of the "selective etching". For example, the distance between the bottom of the selectively etched region and the bottom of the frame base island can be greater than or equal to tens of microns, and in order to further reduce the overall thickness of the device, the smaller the distance between the bottom of the selectively etched region and the bottom of the frame base island, the better.

[0053] In some embodiments, the silicon-based chip 2 and the frame base island structure 1 can be connected by the lead 4, and the compound semiconductor chip 3 and the silicon-based chip 2 can also be connected by the lead 4. In other embodiments, the compound semiconductor chip 3 and the silicon-based chip 2 can also be connected by solder ball flip. Figure 5 is a structural schematic of an ultra-thin multi-chip device according to an exemplary embodiment Figure Five As shown in Figure 5 , the compound semiconductor chip 3 is attached to the silicon-based chip 2 by solder ball flip, which can avoid the influence of the wire arc height of the solder wire, and further reduce the thickness.

[0054] In the embodiments of the present application, since the compound semiconductor chip 3 is represented by gallium arsenide, indium arsenide and indium antimonide, the electron mobility is several times or even tens of times that of silicon, and the sensitivity of the device is obviously higher than that of the silicon-based Hall chip. Therefore, by performing "selective etching" treatment on the frame base island, the silicon-based chip is arranged in the selectively etched area of the frame base island structure, and the compound semiconductor chip is stacked on the silicon-based chip in the sealing mode, so that the sensitivity, sensor signal-to-noise ratio, reliability and stability of the device can be improved. The thickness of the frame base island below the silicon-based chip 2 can be further reduced, so that the overall packaging thickness of the device is thinned, and the thickness of the device can be about 0.25 mm, so that the device is miniaturized, and multi-scene application is realized.

[0055] In some embodiments, a groove is formed on the silicon-based chip 2 by photolithography and selective etching, and the compound semiconductor chip 3 is stacked in the groove.

[0056] Optionally, after the compound semiconductor chip 3 is placed in the groove, the distance between the upper surface of the compound semiconductor chip 3 and the upper surface of the silicon-based chip 2 is greater than 0 and less than the thickness of the compound semiconductor chip 3 itself.

[0057] In the embodiments of the present application, by photolithography and selective etching, the silicon-based chip 2 is "half-etched", and a groove is formed at a specific position of the silicon-based chip 2, which can accommodate the compound semiconductor chip 3. Through the groove, the overall thickness of the device can be further reduced, and at the same time, since the compound semiconductor chip 3 is protected by the "groove", the packaging stress can be effectively reduced, and the reliability of the device can be improved.

[0058] In the following, several embodiments are described for forming a groove on the silicon-based chip 2 by photolithography and selective etching, and the compound semiconductor chip 3 is stacked in the groove.

[0059] In some embodiments, in the case where the frame base island structure 1 is a structure that has not been thinned by selective etching, the silicon-based chip 2 is stacked on the frame base island structure 1, and the compound semiconductor chip 3 is stacked in the groove, the thickness of the ultra-thin multi-chip device is less than 0.25 mm.

[0060] Figure 6 is a structure diagram of an ultra-thin multi-chip device according to an exemplary embodiment Figure Six , Figure 6 a in FIG. 1 is a top view, Figure 6 b in FIG. 1 is a front view, as Figure 6As shown, by means of photoetching and selective etching, a "half-etched" silicon-based chip 2 is obtained, and a recess is formed at a specific position of the silicon-based chip 2. The frame base island structure 1 is a structure that has not been subjected to selective etching for thickness reduction, and the "half-etched" silicon-based chip 2 is laminated on the frame base island structure 1 at a predetermined position of the frame base island structure 1 by means of dispensing or DAF, and the compound semiconductor chip 3 is laminated in the recess by means of dispensing or chip bonding DAF film.

[0061] In some embodiments, the silicon-based chip 2 and the frame base island structure 1 can be connected by means of a wire 4, and the compound semiconductor chip 3 and the silicon-based chip 2 can also be connected by means of a wire 4. In other embodiments, the compound semiconductor chip 3 and the silicon-based chip 2 can also be connected by means of flip-chip soldering. In addition, the compound semiconductor chip 3 is attached to the silicon-based chip 2 by means of flip-chip soldering, so that the wire loop height does not affect the thickness, and the thickness can be further reduced.

[0062] As can be seen, by laminating the silicon-based chip 2 directly on the frame base island structure 1 and laminating the compound semiconductor chip 3 on the silicon-based chip 2 for encapsulation, the encapsulation cost is reduced. Since the compound semiconductor chip 3 is represented by gallium arsenide, indium arsenide and indium antimonide, the electron mobility is several times or even tens of times that of silicon, and the sensitivity of the device is higher than that of the silicon-based Hall chip. Therefore, by encapsulating the compound semiconductor chip 3 and the silicon-based chip 2, the sensitivity, sensor signal-to-noise ratio, reliability and stability of the device can be improved. At the same time, by means of photoetching and selective etching, a "half-etched" silicon-based chip 2 is obtained, and a recess is formed at a specific position of the silicon-based chip 2. The recess can accommodate the compound semiconductor chip 3, and the overall thickness of the device can be further reduced by means of the recess, so that the overall device thickness is less than 0.25 mm, the total thickness of the chip package is effectively reduced, the device is miniaturized, and multi-scene application is achieved. In addition, since the compound semiconductor chip 3 is protected by the "recess", the packaging stress can be effectively reduced, and the reliability of the device can be improved.

[0063] In some embodiments, in the case where the silicon-based chip 2 is arranged inside the frame base island structure 1 and the compound semiconductor chip 3 is laminated in the recess, the thickness of the ultra-thin multi-chip device is less than 0.15 mm.

[0064] Figure 7 is a structure diagram of an ultra-thin multi-chip device according to an exemplary embodiment Figure Seven , Figure 7 a in FIG. 1 is a top view, Figure 7 b in FIG. 1 is a front view, as Figure 7As shown, by means of photoetching and selective etching, a "half-etched" silicon chip 2 is obtained, and a groove is formed at a specific position of the silicon chip 2. The frame base island structure 1 comprises a bottom structure and a peripheral structure, which form an internally hollow frame base island structure. When the frame base island structure 1 is manufactured, a high-temperature film is pasted to the bottom. When the frame base island structure 1 is pasted, the silicon chip 2 with the groove is placed on the high-temperature film by means of dispensing or chip bonding DAF film, so as to realize the sinking arrangement of the silicon chip 2 in the interior of the frame base island structure 1. At the same time, the compound semiconductor chip 3 is stacked in the groove of the silicon chip 2.

[0065] It should be noted that, in order to further reduce the thickness of the ultra-thin multi-chip device, when the silicon chip 2 is sinkingly arranged in the interior of the frame base island structure 1, the upper surface of the silicon chip 2 can be flush with the top of the frame base island structure 1.

[0066] In some embodiments, the silicon chip 2 and the frame base island structure 1 can be connected by means of the lead 4, and the compound semiconductor chip 3 and the silicon chip 2 can also be connected by means of the lead 4. In other embodiments, the compound semiconductor chip 3 and the silicon chip 2 can also be connected by means of solder ball flip. In addition, the compound semiconductor chip 3 is pasted on the silicon chip 2 by means of solder ball flip, so as to avoid the influence of the wire arc height of the solder wire, and the thickness can be further reduced.

[0067] It can be seen that, since the compound semiconductor chip 3 is represented by gallium arsenide, indium arsenide and indium antimonide, the electron mobility is several times or even tens of times of that of silicon, and the sensitivity of the device is higher than that of the silicon-based Hall chip. Therefore, by arranging the frame base island structure 1 to comprise a bottom structure and a peripheral structure, which form an internally hollow frame base island structure, sinkingly arranging the silicon chip 2 in the interior of the frame base island structure 1, and stacking the compound semiconductor chip 3 on the silicon chip 2, the sensitivity, sensor signal-to-noise ratio, reliability and stability of the device can be improved. At the same time, by means of photoetching and selective etching, a "half-etched" silicon chip 2 is obtained, and a groove is formed at a specific position of the silicon chip 2. The groove can accommodate the compound semiconductor chip 3, and the overall thickness of the device can be further reduced by means of the groove. The thickness of the ultra-thin multi-chip device is controlled to be less than or equal to 0.15 mm. In addition, since the compound semiconductor chip 3 is protected by the "groove", the packaging stress can be effectively reduced, and the reliability of the device can be improved.

[0068] Figure 8 is a structural schematic diagram of an ultra-thin multi-chip device according to an exemplary embodiment Figure Eight , Figure 8 a in FIG. 1 is a top view, Figure 8 b in FIG. 1 is a front view,Figure 8 The middle c is a side view, as shown, a "half-etching" silicon chip 2 can be achieved by lithography and selective etching to form a groove at a specific position of the silicon chip 2. At the same time, selective etching can also be performed on the frame base island structure 1 to form a selectively etched area on the frame base island structure 1. The silicon chip 2 with the groove is placed on the frame base island structure 1 by dispensing or using a chip bonding DAF film at the selectively etched area of the frame base island structure 1, and the compound semiconductor chip 3 is stacked in the groove of the frame base island structure 1. Figure 9

[0069] It should be noted that the specific process of selective etching is not limited in the embodiments of the present application.

[0070] In some embodiments, the distance between the bottom of the selectively etched area and the bottom of the frame base island mainly depends on the accuracy of "selective etching". For example, the distance between the bottom of the selectively etched area and the bottom of the frame base island can be greater than or equal to tens of microns, and the smaller the distance between the bottom of the selectively etched area and the bottom of the frame base island, the better for further reducing the overall thickness of the device.

[0071] It can be seen that since the compound semiconductor chip 3 is represented by gallium arsenide, indium arsenide and indium antimonide, the electron mobility is several times or even tens of times that of silicon, so the sensitivity of the device is higher than that of the silicon-based Hall chip. By performing "selective etching" treatment on the frame base island, the silicon-based chip is stacked on the frame base island structure, and the compound semiconductor chip is stacked in the groove, which can improve the sensitivity, sensor signal-to-noise ratio, reliability and stability of the device. At the same time, by lithography and selective etching, a "half-etching" silicon chip 2 is achieved to form a groove at a specific position of the silicon chip 2. The groove can accommodate the compound semiconductor chip 3, and through the groove, the overall thickness of the device can be further reduced, and the thickness of the ultra-thin multi-chip device is controlled to be within 0.2 mm. In addition, since the compound semiconductor chip 3 is protected by the "groove", the packaging stress can also be effectively reduced, and the reliability of the device can be improved.

[0072] In some embodiments, the silicon chip 2 and the compound semiconductor chip 3 can also be placed inside or on the upper surface of the frame base island structure 1, and the upper surfaces of the silicon chip 2 and the compound semiconductor chip 3 are at the same level.

[0073] ​In this embodiment, in addition to directly stacking the silicon-based chip 2 on the frame base island structure 1 and stacking the compound semiconductor chip 3 on the silicon-based chip 2 for encapsulation, the silicon-based chip 2 and the compound semiconductor chip 3 can also be placed on the upper surface of the frame base island structure 1 at the same time by using dispensing or chip bonding DAF film, and the upper surface of the silicon-based chip 2 and the upper surface of the compound semiconductor chip 3 are at the same level. Since the silicon-based chip 2 and the compound semiconductor chip 3 are placed on the upper surface of the frame base island structure 1 at the same time, the silicon-based chip 2 and the frame base island structure 1 can be connected by leads, and the compound semiconductor chip 3 and the silicon-based chip 2 can also be connected by leads, thereby effectively reducing the thickness of the device.

[0074] In some embodiments, when the frame base island structure 1 is not a structure that has been thinned by selective etching, the silicon-based chip 2 and the compound semiconductor chip 3 are placed on the upper surface of the frame base island structure 1, and the upper surface of the silicon-based chip 2 and the upper surface of the compound semiconductor chip 3 are at the same level.

[0075] Figure Nine is a structural diagram of an ultra-thin multi-chip device according to an exemplary embodiment Figure 9 , Figure 9 a in FIG. is a top view, Figure 9 b in FIG. is a front view, as shown in ​ the silicon-based chip 2 and the compound semiconductor chip 3 can be placed on the upper surface of the frame base island structure 1 at the same time by using dispensing or chip bonding DAF film, and a predetermined distance is left between the silicon-based chip 2 and the compound semiconductor chip 3, which can be set according to actual business needs, and is not specifically limited. The upper surface of the silicon-based chip 2 and the upper surface of the compound semiconductor chip 3 are at the same level.

[0076] In some embodiments, since the silicon-based chip 2 and the compound semiconductor chip 3 are placed on the upper surface of the frame base island structure 1 at the same time, the silicon-based chip 2 and the frame base island structure 1 can be connected by leads 4, and the compound semiconductor chip 3 and the silicon-based chip 2 can also be connected by leads, thereby further reducing the thickness.

[0077] Thus, by simultaneously accommodating the silicon-based chip 2 and the compound semiconductor chip 3 on the upper surface of a single frame base island structure 1, the device thickness can be effectively reduced, the overall thickness can be maintained within 0.25 mm, the device can be miniaturized, and multi-scene applications can be achieved.

[0078] In some embodiments, the frame base island structure 1 comprises a bottom structure and a peripheral structure, the bottom structure and the peripheral structure form an internally hollow frame base island structure 1, the silicon-based chip 2 and the compound semiconductor chip 3 are simultaneously arranged in the interior of the frame base island structure, and the upper surface of the silicon-based chip 2 and the upper surface of the compound semiconductor chip 3 are at the same level.

[0079] In this embodiment, the frame base island structure 1 comprises a bottom structure and a peripheral structure, the bottom structure and the peripheral structure form an internally hollow frame base island structure 1, and a high-temperature film is pasted on the bottom of the frame base island structure 1 when it is manufactured. The silicon-based chip 2 and the compound semiconductor chip 3 are simultaneously placed on the high-temperature film by using the chip bonding DAF film, so as to realize that the silicon-based chip 2 and the compound semiconductor chip 3 are simultaneously arranged in the interior of the frame base island structure 1, and the upper surface of the silicon-based chip 2 and the upper surface of the compound semiconductor chip 3 are at the same level.

[0080] It should be noted that, in order to further reduce the thickness of the ultra-thin multi-chip device, when the silicon-based chip 2 and the compound semiconductor chip 3 are arranged in the interior of the frame base island structure 1, the upper surface of the silicon-based chip 2 and the upper surface of the compound semiconductor chip 3 are at the same level.

[0081] In some embodiments, the silicon-based chip 2 and the frame base island structure 1 can be connected by leads, and the compound semiconductor chip 3 and the silicon-based chip 2 can also be connected by leads, so as to further reduce the thickness.

[0082] It can be seen that, since the compound semiconductor chip 3 is represented by gallium arsenide, indium arsenide and indium antimonide, the electron mobility thereof is several times or even tens of times of that of silicon, so the sensitivity of the device is higher than that of the silicon-based Hall chip. By arranging the frame base island structure 1 comprising a bottom structure and a peripheral structure, the bottom structure and the peripheral structure form an internally hollow frame base island structure 1, and the silicon-based chip 2 and the compound semiconductor chip 3 are simultaneously arranged in the interior of the frame base island structure 1, the sensitivity of the device, the signal-to-noise ratio of the sensor, the reliability and the stability can be improved. In addition, since the silicon-based chip 2 and the compound semiconductor chip 3 are simultaneously arranged in the interior of the frame base island structure 1, the total thickness of the chip packaging can be effectively reduced, the device can be miniaturized, and multi-scene application can be realized.

[0083] In some embodiments, the frame base island structure 1 is a structure which is not subjected to selective etching for thickness reduction, the silicon-based chip 2 and the compound semiconductor chip 3 are placed on the upper surface of the frame base island structure 1, and the upper surface of the silicon-based chip 2 and the upper surface of the compound semiconductor chip 3 are at the same level.

[0084] In this embodiment, the frame base island structure 1 can be selectively etched first, so that a selectively etched area is formed on the frame base island structure 1. The silicon-based chip 2 and the compound semiconductor chip 3 are placed on the upper surface of the frame base island structure 1 by dispensing or using a chip bonding DAF film, and the upper surface of the silicon-based chip 2 and the upper surface of the compound semiconductor chip 3 are at the same level.

[0085] It should be noted that the specific process of selective etching is not limited in the embodiments of the present application.

[0086] In some embodiments, the silicon-based chip 2 and the frame base island structure 1 can be connected by wires, and the compound semiconductor chip 3 and the silicon-based chip 2 can also be connected by wires, so as to further reduce the thickness.

[0087] In some embodiments, the distance between the selectively etched area and the bottom of the frame base island mainly depends on the accuracy of the selective etching. For example, the distance between the selectively etched area and the bottom of the frame base island can be greater than or equal to tens of microns. In order to further reduce the overall thickness of the device, the smaller the distance between the selectively etched area and the bottom of the frame base island is, the better.

[0088] As can be seen, since the compound semiconductor chip 3 is represented by gallium arsenide, indium arsenide and indium antimonide, the electron mobility is several times or even tens of times that of silicon, so the sensitivity of the device is higher than that of the silicon-based Hall chip. By placing the silicon-based chip 2 and the compound semiconductor chip 3 on the upper surface of the frame base island structure 1, the thickness of the frame base island below the silicon-based chip 2 can be further reduced, so as to thin the overall packaging thickness of the device, and the thickness of the device can be about 0.2 mm, realizing miniaturization of the device and achieving multi-scene application.

[0089] In an optional embodiment, the embodiments of the present application also provide an electronic device, which includes the ultra-thin multi-chip device in any of the above embodiments.

[0090] Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the present application cover any and all variations of the application that come within the scope of the claims and their equivalents. It is intended that the specification and examples be considered exemplary only, with the true scope and spirit of the application indicated by the following claims.

[0091] It is to be understood that the application is not limited to the precise construction already described above and shown in the drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the application. The scope of the application should only be limited by the claims appended hereto.

Claims

1. An ultra-thin multi-chip device, characterized by, The ultra-thin multi-chip device comprises: a chip, which comprises a silicon-based chip and a compound semiconductor chip that are mutually encapsulated; a frame base island structure, all or part of the chip is sunk inside the frame base island structure; or the frame base island structure is a structure that is thinned by selective etching, and the chip is stacked on the frame base island structure.

2. The ultra-thin multichip device of claim 1, wherein, In the case that all or part of the chip is sunk inside the frame base island structure, the frame base island structure comprises a bottom structure and a peripheral structure, which form an internally hollow frame base island structure, the silicon-based chip is sunk inside the frame base island structure, and the compound semiconductor chip is stacked on the silicon-based chip; The thickness of the ultra-thin multi-chip device is less than 0.2 mm.

3. The ultra-thin multichip device of claim 1, wherein, In the case that the frame base island structure is a structure that is thinned by selective etching, the silicon-based chip is arranged in the region of selective etching of the frame base island structure, and the compound semiconductor chip is stacked on the silicon-based chip; The thickness of the ultra-thin multi-chip device is less than 0.25 mm.

4. The ultra-thin multichip device of any of claims 1 to 3, wherein, A groove is formed on the silicon-based chip by photolithography and selective etching, and the compound semiconductor chip is stacked in the groove.

5. The ultra-thin multichip device of claim 4, wherein, In the case that the silicon-based chip is sunk inside the frame base island structure and the compound semiconductor chip is stacked in the groove, the thickness of the ultra-thin multi-chip device is less than 0.15 mm; In the case that the frame base island structure is a structure that is thinned by selective etching, the silicon-based chip is stacked on the frame base island structure, and the compound semiconductor chip is stacked in the groove, the thickness of the ultra-thin multi-chip device is less than 0.2 mm; In the case that the frame base island structure is a structure that is not thinned by selective etching, the silicon-based chip is stacked on the frame base island structure, and the compound semiconductor chip is stacked in the groove, the thickness of the ultra-thin multi-chip device is less than 0.25 mm.

6. The ultra-thin multichip device of any one of claims 1 to 3, wherein, The silicon-based chip and the frame base island structure are connected by leads; The silicon-based chip and the compound semiconductor chip are connected by leads or by flip-chip with solder balls.

7. The ultra-thin multichip device of claim 1, wherein, The silicon-based chip and the compound semiconductor chip are simultaneously placed inside or on the top surface of the frame base island structure, and the top surface of the silicon-based chip and the top surface of the compound semiconductor chip are at the same level.

8. The ultra-thin multichip device of claim 7, wherein, The frame base island structure comprises a bottom structure and a peripheral structure, which form an internally hollow frame base island structure, the silicon-based chip and the compound semiconductor chip are simultaneously sunk inside the frame base island structure, and the top surface of the silicon-based chip and the top surface of the compound semiconductor chip are at the same level; The frame base island structure comprises a bottom structure and a peripheral structure, which form an internally hollow frame base island structure, the silicon-based chip and the compound semiconductor chip are simultaneously sunk inside the frame base island structure, and the top surface of the silicon-based chip and the top surface of the compound semiconductor chip are at the same level; Or, the frame base island structure is a structure which is thinned by selective etching, the silicon-based chip and the compound semiconductor chip are placed on the upper surface of the frame base island structure at the same time, and the upper surface of the silicon-based chip and the upper surface of the compound semiconductor chip are at the same level. Or, the frame base island structure is a structure which is not thinned by selective etching, the silicon-based chip and the compound semiconductor chip are placed on the upper surface of the frame base island structure, and the upper surface of the silicon-based chip and the upper surface of the compound semiconductor chip are at the same level.

9. The ultra-thin multichip device of claim 8, wherein, The silicon-based chip and the compound semiconductor chip are connected by a lead, and the silicon-based chip and the frame base island structure are connected by a lead.

10. An electronic device, comprising: The electronic device comprises the ultra-thin multi-chip device as claimed in any one of claims 1-9.

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