Driving signal generation method, target board card and readable storage medium

Abstract

The embodiment of the invention provides a driving signal generation method, a target board card and a readable storage medium. According to the scheme, when an FPGA receives a task data packet sent by an upper computer for a target quantum computing task, trigger signals are sent to a DAC and a clock processing module based on waveform parameters in the task data packet; the clock processing module sends a clock signal to the DAC according to the received trigger signal; and the DAC generates a driving signal matched with the waveform parameter based on the received trigger signal and the clock signal. Through the technical scheme provided by the embodiment of the invention, the generation of the driving signal corresponding to the quantum computing task is realized, so that a guarantee is provided for the execution of the quantum computing task.

Description

Technical Field

[0001] This application relates to the field of quantum measurement and control technology, and in particular to a method for generating a driving signal, a target board, and a readable storage medium. Background Technology

[0002] Quantum computing is a computational paradigm that utilizes the fundamental properties of quantum mechanics to solve problems. By constructing precisely operable quantum physics hardware systems and running quantum computing software to implement quantum algorithms, computational problems can be solved, enabling the application of quantum computing in specific problems or fields.

[0003] As an important component of quantum computers, quantum computing measurement and control systems need to provide corresponding driving signals for the qubits participating in quantum computing during the quantum computing process. Summary of the Invention

[0004] The purpose of this application is to provide a method for generating driving signals, a target board, and a readable storage medium to generate driving signals corresponding to quantum computing tasks, thereby ensuring the execution of quantum computing tasks. The specific technical solution is as follows:

[0005] This application provides a driving signal generation method applied to a target board in a quantum computing measurement and control system. The target board includes a digital-to-analog converter (DAC), a clock processing module, and a field-programmable gate array (FPGA). The FPGA is communicatively connected to a host computer. The method includes:

[0006] When the FPGA receives the task data packet sent by the host computer for the target quantum computing task, it sends trigger signals to the DAC and the clock processing module respectively based on the waveform parameters in the task data packet.

[0007] The clock processing module sends a clock signal to the DAC based on the received trigger signal;

[0008] The DAC generates a drive signal that matches the waveform parameters based on the received trigger signal and clock signal.

[0009] This application embodiment also provides a target board, which is deployed in a quantum computing measurement and control system. The target board includes a DAC, a clock processing module, and an FPGA, and the FPGA is communicatively connected to a host computer.

[0010] The FPGA is used to send trigger signals to the DAC and the clock processing module respectively based on the waveform parameters in the task data packet when it receives the task data packet sent by the host computer for the target quantum computing task.

[0011] The clock processing module is used to send a clock signal to the DAC based on the received trigger signal;

[0012] The DAC is used to generate a drive signal that matches the waveform parameters based on the received trigger signal and clock signal.

[0013] This application embodiment also provides a target board, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus;

[0014] Memory, used to store computer programs;

[0015] When a processor executes a program stored in memory, it implements any of the drive signal generation method steps described above.

[0016] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements any of the drive signal generation method steps described above.

[0017] This application also provides a computer program product containing instructions that, when run on a computer, cause the computer to execute any of the drive signal generation methods described above.

[0018] Beneficial effects of the embodiments in this application:

[0019] The technical solution provided in this application embodiment can trigger the operation of the clock processing module and DAC in the target board after the FPGA receives the task data packet sent by the host computer for the target quantum computing task. This allows the FPGA to generate a drive signal that matches the waveform parameters in the task data packet based on the trigger signal sent by the FPGA and the clock signal provided by the clock processing module. This realizes the generation of the drive signal corresponding to the quantum computing task, thereby providing a guarantee for the execution of the quantum computing task.

[0020] Of course, implementing any product or method of this application does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of a first flowchart of a drive signal generation method provided in an embodiment of this application;

[0023] Figure 2 A schematic diagram of the structure of a quantum computer provided in an embodiment of this application;

[0024] Figure 3 This is a schematic diagram of a first structure of the target board provided in an embodiment of this application;

[0025] Figure 4 This is a second flowchart illustrating the driving signal generation method provided in an embodiment of this application;

[0026] Figure 5 This is a schematic diagram of a third process for the drive signal generation method provided in an embodiment of this application;

[0027] Figure 6 This is a schematic diagram of the fourth process of the drive signal generation method provided in the embodiments of this application;

[0028] Figure 7 A fifth flowchart illustrating the driving signal generation method provided in this application embodiment;

[0029] Figure 8 A sixth flowchart illustrating the driving signal generation method provided in this application embodiment;

[0030] Figure 9 This is a schematic diagram of a second structure of the target board provided in an embodiment of this application;

[0031] Figure 10 This is a schematic diagram of a third structure of the target board provided in an embodiment of this application. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0033] To address the problems in related technologies, embodiments of this application provide a method for generating driving signals. For example... Figure 1 As shown, Figure 1 This is a schematic flowchart of a first embodiment of the driving signal generation method provided in this application. This method can be applied to a target board in a quantum computing measurement and control system. The target board may include a DAC, a clock processing module, and an FPGA. The FPGA is communicatively connected to a host computer. Figure 1 The method shown includes the following steps.

[0034] In step S101, when the FPGA receives the task data packet sent by the host computer for the target quantum computing task, it sends trigger signals to the DAC and clock processing module respectively based on the waveform parameters in the task data packet.

[0035] In step S102, the clock processing module sends a clock signal to the DAC based on the received trigger signal.

[0036] In step S103, the DAC generates a drive signal that matches the waveform parameters based on the received trigger signal and clock signal.

[0037] In the embodiments of this application, such as Figure 2 As shown, Figure 2 This is a schematic diagram of a quantum computer provided in an embodiment of this application. The quantum computer includes a host computer and a quantum computing measurement and control system. The quantum computing measurement and control system can be a physical cabinet, and may include multiple chassis, such as... Figure 2 The diagram shows the central control board, routing boards, and bottom-level boards. For example, a known 72-qubit quantum computing measurement and control system may have one central control board, three routing boards, and each routing board may correspond to multiple bottom-level boards. Here, the specific number of each type of board in the aforementioned quantum computing measurement and control system is not limited.

[0038] The aforementioned target board can be a bottom-level board in the aforementioned quantum computing measurement and control system. When performing quantum computing tasks using qubits on a quantum chip, the bottom-level board in the quantum computing measurement and control system (i.e., the aforementioned target board) can provide the corresponding driving signals to the respective qubits.

[0039] like Figure 3 As shown, Figure 3 This is a schematic diagram of a first structure of a target board provided in an embodiment of this application. The target board may include multiple devices, such as... Figure 3 The diagram shows an FPGA, DAC, clock processing module, and fan-out clock buffer. The clock processing module may include a signal generator and a frequency multiplier. The FPGA on the target board communicates with a host computer; specifically, the host computer can communicate with the aforementioned... Figure 2The central control board or routing board in the quantum computing measurement and control system shown can be used for communication connection. The FPGA in the target board can communicate with the host computer through the routing board.

[0040] In an optional embodiment, the above Figure 3 The signal generator in the target board shown can be an HMC7044 chip, the frequency multiplier can be an ADF4355BCPZ chip, the fan-out clock buffer can be an LTC6955 chip, and the DAC can be an AD9164 chip. Furthermore, the target board can contain one or more DACs; the specific number of DACs included in the target board is not limited here.

[0041] pass Figure 1 The method shown allows the FPGA to trigger the clock processing module and DAC in the target board after receiving the task data packet sent by the host computer for the target quantum computing task. This enables the DAC to generate a drive signal that matches the waveform parameters in the task data packet based on the trigger signal sent by the FPGA and the clock signal provided by the clock processing module. This realizes the generation of the drive signal corresponding to the quantum computing task, thereby ensuring the execution of the quantum computing task.

[0042] The embodiments of this application will be described below through specific examples.

[0043] Regarding step S101 above, when the FPGA receives the task data packet sent by the host computer for the target quantum computing task, it sends trigger signals to the DAC and clock processing module respectively based on the waveform parameters in the task data packet.

[0044] In this embodiment, the user can trigger the execution of a target quantum computing task via a host computer. The host computer can then generate a task data packet corresponding to the target quantum computing task and send it to the aforementioned quantum computing measurement and control system. Upon receiving the task data packet, the central control board in the quantum computing measurement and control system can forward it to the target board via a routing board that is communicatively connected to the target board. The FPGA in the target board can then receive the task data packet.

[0045] The aforementioned task data packet contains waveform parameters of the driving signals required for the execution of the target quantum computing task, such as the output frequency corresponding to the driving signals.

[0046] Furthermore, when the target board includes multiple DACs, each DAC communicates with the FPGA through a different transmission channel. In this case, the task data packet may also include the channel number corresponding to the communication connection between the DAC and the FPGA. Here, no specific limitations are placed on the data carried in the task data packet.

[0047] After receiving the task data packet, the FPGA can parse it to obtain the data carried in the packet, such as the waveform parameters mentioned above. Based on the parsed data, the FPGA can generate a trigger signal corresponding to the DAC (denoted as the first trigger signal) and a trigger signal corresponding to the clock processing module (denoted as the second trigger signal). The first trigger signal may carry waveform parameters.

[0048] In an optional embodiment, when the target board includes multiple DACs, the waveform parameters carried in the first trigger signal corresponding to each DAC may be the same or different.

[0049] The FPGA can send the first trigger signal to the DAC and the second trigger signal to the clock processing module.

[0050] In an optional embodiment, when the target board includes only one DAC, the FPGA can directly send the first trigger signal to the DAC when sending the first trigger signal. When the target board includes multiple DACs, the FPGA can send the first trigger signal to the DAC that matches the channel number in the task data packet when sending the first trigger signal.

[0051] In this embodiment, the DAC includes a high-speed serial interface, through which the DAC can establish a link with the FPGA. For example, the high-speed serial interface can be a JESD204B interface. High-speed data transmission can be achieved between the DAC and the FPGA through this high-speed serial interface.

[0052] Regarding step S102 above, the clock processing module sends a clock signal to the DAC based on the received trigger signal.

[0053] In this step, upon receiving the trigger signal (i.e., the second trigger signal mentioned above) from the FPGA, the clock processing module determines that a clock signal needs to be provided to the DAC. At this time, the clock processing module can generate the clock signal required by the DAC and send the clock signal to the DAC.

[0054] In an optional embodiment, when the target board includes multiple DACs, the clock processing module is communicatively connected to each DAC. The clock processing module can send a clock signal to each DAC separately.

[0055] In the embodiments of this application, the clock processing module can provide clock signals to the FPGA in addition to providing clock signals to the DAC. For example, the clock processing module can output one 100MHz (megahertz) user logic clock and three 200MHz GT (Gigabit Transceiver) operating clock signals to the FPGA.

[0056] Regarding step S103 above, that is, the DAC generates a drive signal that matches the waveform parameters based on the received trigger signal and clock signal.

[0057] In this step, after receiving the trigger signal (i.e., the first trigger signal mentioned above) and the clock signal sent by the FPGA, the DAC can trigger the generation of the drive signal. That is, based on the waveform parameters carried in the first trigger signal, a drive signal matching the waveform parameters is generated.

[0058] In an optional embodiment, the aforementioned DAC can be an AD9164 chip. The data interface of the AD9164 chip consists of eight JESD204B serializers / deserializers (SERDES), i.e., eight lanes, providing interpolation modes of 2×, 3×, 4×, 6×, 8×, 12×, 16×, and 24×. Depending on the sampling rate requirements of the quantum computing task, in this embodiment, the AD9164 chip can select a 4LANE, 8x, or MIX_MODE (mixed mode) operating mode.

[0059] For ease of understanding, we will use a 5GHz (gigahertz) sine wave as an example. In the MIX_MODE operating mode, the AD9164 chip's DDS (Direct Digital Frequency Synthesis) can output a 4.8GHz signal, which is then mixed with a 200MHz sine wave configured by the host computer to obtain the drive signal. The generation method of this drive signal can be found in related technical documents and will not be detailed here.

[0060] During the aforementioned drive signal generation process, the host computer can provide a sinusoidal signal ranging from -250MHz to 250MHz.

[0061] In an optional embodiment, when the clock processing module includes a signal generator and a frequency multiplier, according to the above... Figure 1 The method shown in this application embodiment also provides a method for generating a driving signal. For example... Figure 4 As shown, Figure 4 This is a second flowchart illustrating a driving signal generation method provided in an embodiment of this application. The method includes the following steps.

[0062] In step S401, when the FPGA receives the task data packet sent by the host computer for the target quantum computing task, it sends trigger signals to the DAC and clock processing module respectively based on the waveform parameters in the task data packet.

[0063] The above step S401 is the same as the above step S101.

[0064] In step S402, when the signal generator receives the trigger signal, it generates a reference clock signal of the first frequency and a first working clock signal of the second frequency according to the external clock signal, and sends the reference clock signal to the DAC and the first working clock signal to the frequency multiplier respectively.

[0065] In this step, an external clock can provide a fourth frequency external clock signal to the signal generator. After receiving the second trigger signal mentioned above, the signal generator can generate the reference clock signal and the working clock signal (denoted as the first working clock signal) required by the ADC according to the external clock signal, and send the reference clock signal and the first working clock signal to the frequency multiplier and the DAC respectively.

[0066] For ease of understanding, we will use an example of a target board with eight DACs. An external clock can provide a 100MHz external clock signal. To ensure clock synchronization across all chassis in the quantum computing measurement and control system, the signal generator uses the 100MHz external clock signal to generate eight 12.5MHz reference clock signals and one 200MHz first operating clock signal. The signal generator can send the eight reference clock signals to each DAC and the first operating clock signal to the frequency multiplier.

[0067] In the hardware circuit design of the target board, the 100MHz external clock signal can be provided by the external clock, or it can be provided by the crystal oscillator inside the target board. Specifically, the selection of the 100MHz clock signal can be achieved by setting the default configuration file when the signal generator is powered on, that is, selecting the 100MHz clock signal generated by the crystal oscillator or the 100MHz clock signal generated by the external clock.

[0068] In an optional embodiment, the 100MHz clock signal generated by the crystal oscillator can be used to relock the signal generator when the 100MHz signal generated by the external clock is lost, causing the signal generator to lose lock. Since the signal frequency generated by the signal generator based on the 100MHz clock signal has a synchronization difference with other chassis at this time, the above-mentioned method of providing a 100MHz clock signal by the crystal oscillator is suitable for single chassis for quantum task testing or FPGA developers for simple logic function verification.

[0069] In one optional embodiment, the fourth frequency can be 100MHz, the first frequency can be 12.5MHz, and the second frequency can be 200MHz. The first, second, and fourth frequencies can be adjusted according to the different output frequencies corresponding to the driving signals required for the quantum computing task. Here, the first, second, and fourth frequencies are not specifically limited.

[0070] In step S403, the frequency multiplier performs frequency multiplication on the received first working clock signal to obtain a second working clock signal with a third frequency, and sends the second working clock signal to the DAC. The third frequency is greater than the second frequency.

[0071] In an optional embodiment, after receiving the first operating clock signal, the frequency multiplier can multiply the first operating clock signal to obtain a second operating clock signal. For example, after receiving the 200MHz first operating clock signal, the frequency multiplier can multiply the first operating clock signal to a 6.4GHz second operating clock signal. The frequency multiplier can then send the second operating clock signal to the DAC.

[0072] The aforementioned third frequency can be 6.4 GHz. No specific limitation is made regarding the third frequency. Furthermore, the aforementioned second operating clock signal and the aforementioned external clock signal are of the same origin and phase.

[0073] In another optional embodiment, when there are multiple DACs in the target board, the target board may also include a fan-out clock buffer.

[0074] The step S403 above, in which the second working clock signal is sent to the DAC, can be represented as follows: the frequency multiplier sends the second working clock signal to the fan-out clock buffer so that the fan-out clock buffer fans out the received second working clock signal into multiple second working clock signals, and sends one second working clock signal to each DAC respectively.

[0075] By using the aforementioned fan-out clock buffer, a single second working clock signal can be copied into multiple second working clock signals without altering the input and output signals. This ensures that each DAC can receive the same second working clock signal, thereby improving the flexibility of target board deployment and reducing the deployment cost of the target board while maintaining signal integrity and reliability.

[0076] Steps S402-S403 above are a refinement of step S102 above.

[0077] In step S404, the DAC generates a drive signal that matches the waveform parameters based on the received trigger signal, reference clock signal, and second operating clock signal.

[0078] In this embodiment, the DAC includes a DLL (Delay-Locked Loop) and a PLL (Phase-Locked Loop). The reference clock signal and the second operating clock signal are provided to the DLL and PLL, respectively.

[0079] Through steps S402-S404 above, the target board uses the signal generator and frequency multiplier to generate the clock signal required for the operation of the phase-locked loop in the DAC, thus ensuring the accuracy and stability of the DAC operation.

[0080] In an optional embodiment, according to the above... Figure 1 The method shown in this application embodiment also provides a method for generating a driving signal. For example... Figure 5 As shown, Figure 5 This is a schematic diagram of a third method for generating drive signals provided in an embodiment of this application. The method includes the following steps.

[0081] In step S501, when the FPGA receives the task data packet sent by the host computer for the target quantum computing task, it sends trigger signals to the DAC and clock processing module respectively based on the waveform parameters in the task data packet.

[0082] In step S502, the clock processing module sends a clock signal to the DAC based on the received trigger signal.

[0083] In step S503, the DAC generates a drive signal that matches the waveform parameters based on the received trigger signal and clock signal.

[0084] Steps S501-S503 are the same as steps S101-S103.

[0085] In step S504, when the FPGA is powered on or when it receives a configuration command from the host computer, it loads its own first configuration file and sends the corresponding first configuration file to other devices in the target board.

[0086] In this embodiment, the FPGA pre-stores a first configuration file corresponding to each device in the target board. The devices in the target board include the FPGA, DAC, signal generator, and frequency multiplier, etc. The first configuration file corresponding to each device is the file required for configuring the corresponding function of each component.

[0087] In an optional embodiment, the first configuration file described above can be stored as an ELF file in the FPGA's BD (Block Design) soft core. ELF is a file format used for binary files, executable files, object code, shared libraries, and core dump files.

[0088] In an optional embodiment, when the FPGA is powered on, or when the FPGA receives a configuration command sent by the host computer, the FPGA can trigger the function configuration process of itself and other devices in the target board, that is, load the corresponding first configuration file and send the corresponding first configuration file to each other device.

[0089] In this embodiment, if the FPGA triggers its own and other device's functional configuration process upon power-up, then step S504 is executed before step S501. If the FPGA triggers its own and other device's functional configuration process upon receiving a configuration command from the host computer, then step S504 can be executed at any time. Here, the execution time of step S504 is not specifically limited.

[0090] In step S505, other devices load the received first configuration file.

[0091] Through steps S504-S505 described above, the FPGA can trigger the functional configuration process for each device on the target board, effectively ensuring that each device on the target board can operate normally. Furthermore, compared to related technologies, the functional configuration of all devices on the target board can be achieved simply by issuing the above configuration commands, eliminating the need for restarting or reprogramming configuration files as in related technologies, thus shortening the time required for the functional configuration process.

[0092] In the above Figure 5 The method described herein uses only an example where the configuration command is used to configure the functions of all devices on the target board. However, the configuration command can also be used to configure the functions of one or more devices on the target board. No specific limitations are imposed on the configuration command described here.

[0093] In an optional embodiment, according to the above... Figure 5 The method shown in this application embodiment also provides a method for generating a driving signal. For example... Figure 6 As shown, Figure 6 This is a schematic diagram of the fourth process for the drive signal generation method provided in an embodiment of this application. Figure 6 The method shown has been augmented with the following step, namely step S506.

[0094] In step S506, when the FPGA receives the second configuration file sent by the host computer for the target device, it updates the pre-stored first configuration file corresponding to the target device to the second configuration file. The target device is any one or more devices in the target board.

[0095] In this embodiment, for each device in the target board, the user can modify or update the first configuration file corresponding to that device (denoted as the target device) to obtain a second configuration file. The host computer can then obtain the second configuration file and send it to the FPGA of the target board.

[0096] When the FPGA receives the second configuration file sent by the host computer for the target device, it can determine that the configuration file corresponding to the target device has changed. At this time, the FPGA can update the first configuration file corresponding to the target device that it stores to the second configuration file.

[0097] The target device mentioned above can be any one or more devices from the target board mentioned above. No specific limitations are imposed on the target device mentioned above.

[0098] In step S506 above, the host computer updates the configuration file corresponding to the target device stored in the FPGA by sending the second configuration file, avoiding problems such as device damage and long time consumption that may be caused by re-burning, and improving the convenience of updating the configuration file corresponding to the target device.

[0099] In an optional embodiment, after the host computer updates the configuration file corresponding to the target device to the second configuration file, it can send a configuration instruction for the target device to the FPGA, so that the FPGA can configure the function of the target device according to the configuration instruction, thus ensuring the functional accuracy of the target device.

[0100] In an optional embodiment, when the FPGA includes a detection unit, according to the above... Figure 1 The method shown in this application embodiment also provides a method for generating a driving signal. For example... Figure 7 As shown, Figure 7 This is a fifth flowchart illustrating a driving signal generation method provided in an embodiment of this application. The method includes the following steps.

[0101] In step S701, when the FPGA receives the task data packet sent by the host computer for the target quantum computing task, it sends trigger signals to the DAC and clock processing module respectively based on the waveform parameters in the task data packet.

[0102] In step S702, the clock processing module sends a clock signal to the DAC based on the received trigger signal.

[0103] In step S703, the DAC generates a drive signal that matches the waveform parameters based on the received trigger signal and clock signal.

[0104] The steps S701-S703 described above are the same as the steps S101-S103 described above.

[0105] In step S704, when the detection unit receives the detection task sent by the host computer, it acquires the abnormal indication signal corresponding to the high-speed serial interface within a preset time period, and determines whether there is an intermittent abnormality in the connection between the FPGA and the DAC based on the abnormal indication signal, and obtains the abnormal detection result.

[0106] In this embodiment, the user can trigger a detection of intermittent anomalies in the link between the FPGA and the DAC via the aforementioned host computer. In this case, the host computer can send a detection task to the FPGA, and the detection unit within the FPGA will receive the task.

[0107] When the detection unit receives the aforementioned detection task, it can acquire the abnormal indication signal corresponding to the high-speed serial interface on the DAC within a preset time period after the current moment. Based on this abnormal indication signal, it can determine whether there is an intermittent abnormality in the link between the FPGA and the DAC, thus obtaining an abnormality detection result. This abnormality detection result is used to indicate whether there is an intermittent abnormality in the link between the FPGA and the DAC, or to indicate whether there is no intermittent abnormality in the link between the FPGA and the DAC.

[0108] The duration of the preset time period can be set according to user needs, and is not specifically limited here.

[0109] In an optional embodiment, when the FPGA and DAC communicate via the 204B protocol, the detection unit can use the SYNC signal as an anomaly indication signal to obtain the SYNC signal within a preset time period. Since the SYNC signal is active low, when a high-level SYNC signal appears within the preset time period, the detection unit can determine that there is an intermittent anomaly in the connection between the FPGA and DAC; when all SYNC signals within the preset time period are low-level, the detection unit can determine that there is no intermittent anomaly in the connection between the FPGA and DAC.

[0110] In the embodiments of this application, the intermittent abnormality of the link between the FPGA and the DAC can be expressed as: the link between the FPGA and the DAC is intermittent, that is, the link between the FPGA and the DAC is normal during a certain period of time, and abnormal during a certain period of time, and so on.

[0111] Step S705: When the abnormal detection result indicates the presence of intermittent abnormalities, the detection unit sends an abnormal alarm to the host computer.

[0112] In an optional embodiment, when there are multiple DACs, the detection unit can acquire the anomaly detection result for each DAC separately. When the anomaly detection result for any DAC indicates an intermittent anomaly, the detection unit can send an anomaly alarm to the host computer. This anomaly alarm may carry information such as the DAC identifier or channel number.

[0113] In an optional embodiment, when the host computer receives the aforementioned abnormal alarm, it can send a configuration command to the FPGA. If the abnormal alarm carries information such as the DAC identifier or channel number, the configuration command can also carry such information. When the FPGA receives the configuration command, it can send a configuration file to the corresponding DAC according to the information carried in the configuration command.

[0114] In this embodiment, depending on the trigger time of the detection task, steps S704-S705 can be executed at any time. Therefore, no specific limitation is made on the execution time of steps S704-S705.

[0115] Through steps S704-S705 above, the detection unit can accurately determine whether there is an intermittent abnormality in the link between the FPGA and the DAC based on the above abnormality indication signal, and issue an abnormality alarm when an intermittent abnormality exists, thereby avoiding the impact of the intermittent abnormality and ensuring the accuracy of the generated drive signal.

[0116] In an optional embodiment, according to the above... Figure 1 The method shown in this application embodiment also provides a method for generating a driving signal. For example... Figure 8 As shown, Figure 8 This is a sixth flowchart illustrating a driving signal generation method provided in an embodiment of this application. The method includes the following steps.

[0117] In step S801, when the FPGA receives the task data packet sent by the host computer for the target quantum computing task, it sends trigger signals to the DAC and clock processing module respectively based on the waveform parameters in the task data packet.

[0118] In step S802, the clock processing module sends a clock signal to the DAC based on the received trigger signal.

[0119] In step S803, the DAC generates a drive signal that matches the waveform parameters based on the received trigger signal and clock signal.

[0120] The steps S801-S803 described above are the same as the steps S101-S103 described above.

[0121] In step S804, when the FPGA receives the version query command sent by the host computer, it obtains the version information corresponding to each device in the target board.

[0122] In this embodiment, the user can trigger a version query operation for each device on the target board via the aforementioned host computer. At this time, the host computer can send a version query command to the target board. The FPGA on the target board will receive this version query command. Based on this version query command, the FPGA can obtain the version information corresponding to each device on the target board. This version information includes, but is not limited to, the version number and the program development date.

[0123] In step S805, the FPGA sends version information to the host computer.

[0124] In one optional embodiment, after receiving the version information, the host computer can display the version information to the user, so that the user can check the displayed version information and ensure the accuracy of the version corresponding to each device in the target board.

[0125] Based on the same inventive concept, and according to the driving signal generation method provided in the above embodiments of this application, this application also provides a target board. For example... Figure 9 As shown, Figure 9 This is a second structural schematic diagram of the target board provided in an embodiment of this application. The target board is deployed in a quantum computing measurement and control system. The target board includes a DAC 901, a clock processing module 902, and an FPGA 903. The FPGA 903 is communicatively connected to a host computer.

[0126] The aforementioned FPGA 903 is used to send trigger signals to the DAC 901 and the clock processing module respectively based on the waveform parameters in the task data packet when it receives the task data packet sent by the host computer for the target quantum computing task.

[0127] The aforementioned clock processing module 902 is used to send a clock signal to the DAC 901 based on the received trigger signal;

[0128] The aforementioned DAC 901 is used to generate a drive signal that matches the waveform parameters based on the received trigger signal and clock signal.

[0129] Optionally, the clock processing module 902 may include a signal generator and a frequency multiplier;

[0130] The aforementioned signal generator is used to generate a reference clock signal of a first frequency and a first working clock signal of a second frequency according to an external clock signal when a trigger signal is received, and to send the reference clock signal to the DAC 901 and the first working clock signal to the frequency multiplier, respectively.

[0131] The aforementioned frequency multiplier is used to multiply the received first working clock signal to obtain a second working clock signal with a third frequency, and to send the second working clock signal to the DAC 901. The third frequency is greater than the second frequency.

[0132] Specifically, the aforementioned DAC 901 can be used to generate a drive signal that matches the waveform parameters based on the received trigger signal, reference clock signal, and second operating clock signal.

[0133] Optionally, when there are multiple DAC 901s, the target board may also include a fan-out clock buffer;

[0134] The aforementioned frequency multiplier is used to send a second working clock signal to the fan-out clock buffer, so that the fan-out clock buffer fans out the received second working clock signal into multiple second working clock signals, and sends one second working clock signal to each DAC 901 respectively.

[0135] Optionally, the FPGA 903 described above pre-stores a first configuration file corresponding to each device in the target board;

[0136] The aforementioned FPGA 903 can also be used to load its own first configuration file upon power-on or upon receiving a configuration command from a host computer, and send the corresponding first configuration file to other devices in the target board.

[0137] The other devices mentioned above are used to load the received first configuration file.

[0138] Optionally, the FPGA 903 described above can also be used to update the pre-stored first configuration file corresponding to the target device to the second configuration file when receiving the second configuration file sent by the host computer for the target device. The target device can be any one or more devices in the target board.

[0139] Optionally, the FPGA 903 may also include a detection unit, and the DAC 901 includes a high-speed serial interface for establishing a link with the FPGA 903.

[0140] The aforementioned detection unit is used to obtain the abnormal indication signal corresponding to the high-speed serial interface within a preset time period when it receives the detection task sent by the host computer, and to determine whether there is an intermittent abnormality in the link between FPGA 903 and DAC 901 based on the abnormal indication signal, thereby obtaining the abnormality detection result; when the abnormality detection result indicates that there is an intermittent abnormality, it sends an abnormality alarm to the host computer.

[0141] Optionally, the FPGA 903 described above can also obtain the version information corresponding to each device in the target board when it receives a version query command sent by the host computer; and send the version information to the host computer.

[0142] The apparatus provided in this application embodiment enables the FPGA to trigger the operation of the clock processing module and DAC in the target board after receiving the task data packet sent by the host computer for the target quantum computing task. This allows the DAC to generate a drive signal that matches the waveform parameters in the task data packet based on the trigger signal sent by the FPGA and the clock signal provided by the clock processing module, thereby realizing the generation of the drive signal corresponding to the quantum computing task and providing a guarantee for the execution of the quantum computing task.

[0143] Based on the same inventive concept, and according to the driving signal generation method provided in the above embodiments of this application, this application also provides a target board, such as... Figure 10 As shown, it includes a processor 1001, a communication interface 1002, a memory 1003, and a communication bus 1004, wherein the processor 1001, the communication interface 1002, and the memory 1003 communicate with each other through the communication bus 1004.

[0144] Memory 1003 is used to store computer programs;

[0145] When the processor 1001 executes the program stored in the memory 1003, it implements any of the steps of the drive signal generation method described above.

[0146] The communication bus mentioned in the above electronic devices can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0147] The communication interface is used for communication between the aforementioned electronic devices and other devices.

[0148] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0149] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0150] Based on the same inventive concept, and according to the driving signal generation method provided in the above embodiments of this application, this application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of any of the above driving signal generation methods.

[0151] Based on the same inventive concept, and according to the drive signal generation method provided in the above embodiments of this application, this application also provides a computer program product containing instructions, which, when run on a computer, causes the computer to execute any of the drive signal generation methods in the above embodiments.

[0152] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).

[0153] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0154] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, embodiments such as target boards, computer-readable storage media, and computer program products are basically similar to the method embodiments, so the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0155] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A method for generating a driving signal, characterized in that, A target board for use in a quantum computing measurement and control system, the target board including a digital-to-analog converter (DAC), a clock processing module, and a field-programmable gate array (FPGA), the FPGA being communicatively connected to a host computer, the method including: When the FPGA receives the task data packet sent by the host computer for the target quantum computing task, it sends trigger signals to the DAC and the clock processing module respectively based on the waveform parameters in the task data packet. The clock processing module sends a clock signal to the DAC based on the received trigger signal; The DAC generates a drive signal that matches the waveform parameters based on the received trigger signal and clock signal.

2. The method according to claim 1, characterized in that, The clock processing module includes a signal generator and a frequency multiplier; The step of the clock processing module sending a clock signal to the DAC based on the received trigger signal includes: When the signal generator receives the trigger signal, it generates a reference clock signal of a first frequency and a first working clock signal of a second frequency according to the external clock signal, and sends the reference clock signal to the DAC and the first working clock signal to the frequency multiplier respectively. The frequency multiplier performs frequency multiplication on the received first working clock signal to obtain a second working clock signal with a third frequency, and sends the second working clock signal to the DAC, wherein the third frequency is greater than the second frequency. The step of the DAC generating a drive signal matching the waveform parameters based on the received trigger signal and clock signal includes: The DAC generates a drive signal that matches the waveform parameters based on the received trigger signal, reference clock signal, and second operating clock signal.

3. The method according to claim 2, characterized in that, When there are multiple DACs, the target board also includes a fan-out clock buffer; The step of sending the second operating clock signal to the DAC includes: The frequency multiplier sends the second working clock signal to the fan-out clock buffer, so that the fan-out clock buffer fans out the received second working clock signal into multiple second working clock signals, and sends one second working clock signal to each DAC respectively.

4. The method according to claim 1, characterized in that, The FPGA pre-stores a first configuration file corresponding to each device in the target board; The method further includes: When the FPGA is powered on or when it receives a configuration command from the host computer, it loads its own first configuration file and sends the corresponding first configuration file to other devices in the target board. The other devices load the received first configuration file.

5. The method according to claim 4, characterized in that, The method further includes: When the FPGA receives the second configuration file sent by the host computer for the target device, it updates the pre-stored first configuration file corresponding to the target device to the second configuration file. The target device can be any one or more devices in the target board.

6. The method according to claim 1, characterized in that, The FPGA also includes a detection unit, and the DAC includes a high-speed serial interface for establishing a link with the FPGA. The method further includes: When the detection unit receives the detection task sent by the host computer, it acquires the abnormal indication signal corresponding to the high-speed serial interface within a preset time period, and determines whether there is an intermittent abnormality in the link between the FPGA and the DAC based on the abnormal indication signal, and obtains the abnormal detection result. When the abnormal detection result indicates the presence of intermittent abnormalities, the detection unit sends an abnormal alarm to the host computer.

7. The method according to claim 1, characterized in that, The method further includes: When the FPGA receives a version query command sent by the host computer, it obtains the version information corresponding to each device in the target board. The FPGA sends the version information to the host computer.

8. A target board, characterized in that, The target board is deployed in the quantum computing measurement and control system. The target board includes a digital-to-analog converter (DAC), a clock processing module, and a field-programmable gate array (FPGA). The FPGA is connected to the host computer. The FPGA is used to send trigger signals to the DAC and the clock processing module respectively based on the waveform parameters in the task data packet when it receives the task data packet sent by the host computer for the target quantum computing task. The clock processing module is used to send a clock signal to the DAC based on the received trigger signal; The DAC is used to generate a drive signal that matches the waveform parameters based on the received trigger signal and clock signal.

9. A target board, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, when executing a program stored in memory, implements the steps of the method described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method described in any one of claims 1-7.

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