Chip capable of being trimmed, auxiliary trimming chip and trimming circuit

Abstract

The embodiment of the invention provides a trimming chip, an auxiliary trimming chip and a trimming circuit. The chip capable of being trimmed comprises a first modulation and demodulation module and a trimming module which are coupled through a first power input end of the chip capable of being trimmed, and the first modulation and demodulation module is configured to demodulate a first instruction modulation signal modulated by a first instruction signal obtained by the first power input end. A second instruction signal is obtained after demodulation; and the trimming module comprises a trimming unit, and the trimming module is configured to execute trimming operation on the trimming unit according to the second instruction signal. The method has the advantages that batch trimming can be achieved, the trimming mass production efficiency is improved, the cost is saved, and the programming driving capacity is improved directly through power supply.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the field of integrated circuit technology, and more specifically to an adjustable chip, an auxiliary adjustable chip, and an adjustable circuit. Background Technology

[0002] For the design of high-precision analog integrated circuits such as references, operational amplifiers, and analog converters, the accuracy requirements of their circuit parameters are very high. Therefore, the chips are generally tuned after packaging, and the tuning results need to be read back after tuning. The conventional practice is to use the data pins on the chip to write and read the tuning data. Because tuning is done using the data pins, the data pins are connected to both the functional circuits and the tuning circuits in the chip, which can easily cause instability in the chip during use.

[0003] The prior art discloses a trimming circuit for multiplexing power input pins, but it cannot perform batch trimming operations and has low efficiency. In addition, the fuse burning process requires a large burning current to blow the fuse, which places a large demand on the driving capability of the first superimposed circuit. When the driving capability of the first superimposed circuit is insufficient, the trimming chip will not work properly and the trimming will fail. Summary of the Invention

[0004] The purpose of the embodiments of this disclosure is to provide a trimmable chip, an auxiliary trimmable chip, and a trimmable circuit. Through modulation and demodulation functions, the modulation signal obtained through the power line is demodulated into an instruction signal for controlling the trimmable operation. The trimmable chip can be batch-trimmed by a microprocessor, which improves the efficiency of trimmable mass production and saves costs. In addition, the driving capability of programming is improved by directly supplying power.

[0005] To achieve the above objectives, a first aspect of this disclosure provides an adjustable chip, comprising: a first modulation / demodulation module and an adjustment module coupled to a first power input terminal of the adjustable chip, wherein the first modulation / demodulation module is configured to demodulate a first command modulation signal obtained via the first power input terminal that modulates a first command signal, and obtain a second command signal after demodulation; the adjustment module includes an adjustment unit, and the adjustment module is configured to perform an adjustment operation on the adjustment unit according to the second command signal.

[0006] In some embodiments of this disclosure, the first instruction signal and the second instruction signal include adjustment operation information, or adjustment operation information and address information, wherein the address information is used to locate the adjustment unit, and the adjustment operation information includes write operation information or read operation information.

[0007] In some embodiments of this disclosure, the trimming module includes a trimming array, wherein the trimming array includes a plurality of trimming units, each trimming unit includes a plurality of trimming basic units, and the trimming array is configured to perform trimming operations on the trimming basic units in the trimming units according to the second instruction signal.

[0008] In some embodiments of this disclosure, the adjustable chip further includes a control module, wherein the control module is configured to convert the second instruction signal into an adjustment signal, locate the adjustment unit in the adjustment module through the adjustment signal, and perform an adjustment operation.

[0009] In some embodiments of this disclosure, when the trimming module includes a trimming array, the trimming signal includes a trimming operation signal, a first address parallel signal, and a second address parallel signal. The trimming array is configured to locate the trimming unit in the trimming array using the first address parallel signal, and to determine the trimming basic unit in the located trimming unit according to the second address parallel signal and perform the corresponding trimming operation according to the trimming operation signal.

[0010] In some embodiments of this disclosure, the first instruction signal and the second instruction signal are frame signals.

[0011] In some embodiments of this disclosure, when the adjustment operation performed by the adjustment module is a write operation, the control module is further configured to place the address information in the second instruction signal or at least one of the first address information and the second address information in the adjustment signal into a first return signal and return it to the first modulation and demodulation module; the first modulation and demodulation module is further configured to modulate the first return signal into a first return modulation signal, and after receiving confirmation information for the address information, send the confirmation information to the control module; the control module is further configured to control the adjustment module to perform the corresponding write operation according to the confirmation information.

[0012] In some embodiments of this disclosure, the adjustable chip further includes: a decoupling capacitor connected in series with a capacitor control switch between the ground terminal and the adjustment module; the control module is further configured to control the capacitor control switch to close to connect the decoupling capacitor to the ground terminal when the adjustment module performs an adjustment write operation or when the adjustment operation of the adjustable chip is completed; and to control the capacitor control switch to open to disconnect the decoupling capacitor from the ground terminal when the first power input terminal transmits a signal.

[0013] In some embodiments of this disclosure, the adjustable chip further includes: a first high-pass filter configured to filter out the DC signal and low-frequency noise signal input to the adjustable chip from the first power input terminal to obtain the first command modulation signal.

[0014] A second aspect of this disclosure provides an auxiliary tuning chip that works in conjunction with the tuneable chip provided in the first aspect of this disclosure. The auxiliary tuning chip includes a second modulation / demodulation module and a second high-pass filter. The second modulation / demodulation module is configured to convert a first instruction signal sent by a microprocessor into a first instruction modulation signal and send it to the tuneable chip via a first signal terminal. The second high-pass filter is configured to filter out the DC signal and low-frequency noise signal input to the auxiliary tuning chip from the first signal terminal, thereby obtaining a first feedback modulation signal returned by the tuneable chip.

[0015] A third aspect of this disclosure provides a tuning circuit, comprising: an auxiliary tuning chip provided in a second aspect of this disclosure, at least one tuneable chip provided in a first aspect of this disclosure, and a first inductor connected via a power line, wherein a first terminal of the first inductor is coupled to a power supply and a second power input terminal of the auxiliary tuning chip, and a second terminal of the first inductor is coupled to the first power input terminal of the tuneable chip and the first signal terminal of the auxiliary tuning chip.

[0016] Other features and advantages of the embodiments disclosed herein will be described in detail in the following detailed description section. Attached Figure Description

[0017] The accompanying drawings are provided to further illustrate embodiments of the present disclosure and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present disclosure, but do not constitute a limitation on the embodiments of the present disclosure. In the drawings:

[0018] Figure 1 This is a schematic diagram of a trimming circuit for a multiplexed power supply pin in the prior art;

[0019] Figure 2 This is a schematic block diagram of a trimming circuit provided in an embodiment of this disclosure;

[0020] Figure 3 This is a schematic block diagram of an adjustable chip provided in an embodiment of this disclosure;

[0021] Figure 4 This is a circuit diagram of a trimming module provided in an embodiment of this disclosure;

[0022] Figure 5This is a circuit diagram of another adjustment module provided in an embodiment of this disclosure;

[0023] Figure 6 The embodiments provided in this disclosure are related to Figure 5 Combined with a partial trimming circuit diagram for the trimming array;

[0024] Figure 7 This is a timing diagram of the write operation frame signal provided in an embodiment of this disclosure;

[0025] Figure 8 This is a timing diagram of the read operation frame signal provided in an embodiment of this disclosure;

[0026] Figure 9 This is a schematic diagram of the architecture of an adjustable chip provided in an embodiment of this disclosure.

[0027] The elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0029] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. Furthermore, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0030] As is well known to those skilled in the art, in the field of trimming, trimming circuits can be categorized into various trimming methods based on the number of times they can be repeatedly trimmed, such as MTP (Multiple-Time Programmable), FTP (Few-Time Programmable), and OTP (One-Time Programmable, which allows programming only once and whose data is permanently valid once programmed). Commonly used trimming techniques include: Digital Calibration, Trimming with Register Settings, Fuse Programming or Laser Trimming, Adaptive Calibration, Multiplexer and Resistor Array, Iterative Learning Algorithm, On-Chip Self-Calibration (OSCAL), and Multistage Calibration. This disclosure uses a fuse as a trimming unit for example, and fuse trimming itself is a specific implementation example of OTP trimming; the specific trimmable chip is also exemplified by a fuse trimming circuit.

[0031] Figure 1 This is a schematic diagram of a trimming circuit using multiplexed power pins in the prior art. In this circuit structure, the first superposition circuit 1 supplies power to the trimming chip 2 through the power input pin of the trimming chip 2. Therefore, the first superposition circuit 1 needs to have a strong driving capability, and the power consumption of the trimming chip 2 needs to be controlled as much as possible. A large writing current is required to blow the fuse during the writing process. Therefore, if the driving capability of the first superposition circuit 1 is insufficient during writing, the power supply of the trimming chip 2 will drop instantaneously. If the power supply drop of the trimming chip 2 is large, the trimming chip will not function properly, resulting in trimming failure. Furthermore, it cannot perform batch trimming operations and has low efficiency.

[0032] Therefore, in order to solve the above problems, when it is necessary to adjust the adjustable chip, an instruction signal related to the adjustment operation is provided, and a corresponding adjustment circuit, adjustable chip, and auxiliary adjustment chip are provided.

[0033] Figure 2A schematic block diagram of a trimming circuit according to an embodiment of the present disclosure is shown, comprising: an auxiliary trimming chip 14 connected via a power line, at least one trimmable chip 13, and a first inductor L1. The first terminal of the first inductor L1 is coupled to a power supply VDD and a second power input terminal of the auxiliary trimming chip 14, and the second terminal of the first inductor L1 is coupled to a first power input terminal of the trimmable chip 13 and a first signal terminal of the auxiliary trimming chip 14.

[0034] When the adjustment operation is a write or read operation, the microprocessor sends a first instruction signal to the second modulation / demodulation module 141 in the auxiliary adjustment chip 14. The second modulation / demodulation module 141 modulates the first instruction signal into a first instruction modulation signal and sends the first instruction modulation signal to the first power input terminal of the adjustable chip 13 via the power line through the first signal terminal. Since the first instruction modulation signal is a high-frequency signal at the MHz level, the first inductor L1 (which can pass DC and blocks AC, and is 100nH in this embodiment) prevents the loss of signal energy transmitted to the power supply VDD, thereby maximizing the transmission of the first instruction modulation signal to the adjustable chip 13. The first instruction modulation signal is transmitted to the first modulation / demodulation module 310 of the adjustable chip 13 via the first power input terminal of the adjustable chip 13. The first modulation / demodulation module 310 demodulates the first instruction modulation signal to obtain the second instruction signal. The adjustment module 320 in the adjustable chip 13 can perform adjustment operations on the adjustment units included in the adjustment module 320 according to the second instruction signal. When the adjustment operation is a read operation, the adjustment module 320 reads the state of the adjustment unit to obtain the readback data, generates a first return signal, modulates the first return signal through the first modulation and demodulation module 310 to obtain a first return modulation signal, and transmits it back to the auxiliary adjustment chip 14 through the power line. The auxiliary adjustment chip 14 demodulates the first return modulation signal to obtain a second return signal and transmits it to the microprocessor, so that the microprocessor obtains the readback data.

[0035] In this embodiment, since the adjustable chip and the auxiliary adjustable chip are directly powered by the same power line, instead of the adjustable chip being indirectly powered through the auxiliary adjustable chip, the driving capability of the auxiliary adjustable chip does not need to be considered. This enables one-to-many batch adjustment, improves mass production efficiency, and saves costs.

[0036] In this embodiment of the disclosure, for Figure 2The adjustable chip 13 in the illustrated adjustment circuit may include a first modulation / demodulation module 310 and an adjustment module 320 coupled to a first power input terminal of the adjustable chip 13. The first modulation / demodulation module 310 is configured to demodulate a first command modulation signal obtained by modulating a first command signal via a signal coupled to the first power input terminal, resulting in a second command signal. The adjustment module 320 includes an adjustment unit and is configured to perform an adjustment operation on the adjustment unit according to the second command signal. Optionally, after the adjustable chip 13 is packaged, its power input terminal may be coupled to a power input pin.

[0037] The number of adjustment units (fuse wires in this embodiment) included in the adjustment module 320 is not limited. When there is one adjustment unit, it can represent a single fuse or multiple fuses, such as fuses arranged in rows or columns. When there are multiple adjustment units, the fuses can be arranged in a matrix. For example, each row of fuses represents one adjustment unit, and one adjustment unit includes multiple adjustment basic units. Each adjustment basic unit corresponds to each fuse, that is, multiple adjustment basic units correspond one-to-one with multiple fuses in the row. Or each column of fuses represents one adjustment unit. Similarly, one adjustment unit includes multiple adjustment basic units, that is, multiple adjustment basic units correspond one-to-one with multiple fuses in the column.

[0038] Optionally, in embodiments of this disclosure, the first command signal and the second command signal may include modulation operation information, or modulation operation information and address information. The address information is used to locate the modulation unit, and the modulation operation information includes write operation information or read operation information. Those skilled in the art should understand that the second command signal is obtained by modulating and demodulating the first command signal. Therefore, when the modulation and demodulation communication transmission process is complete and error-free, the information contained in the first command signal and the second command signal should be completely identical. For situations where the information contained in the two signals may differ, corresponding solutions will be described in detail below. In this disclosure, the aforementioned information is contained in the signal in the form of data.

[0039] Specifically, when the adjustable chip 13 contains only one adjustment unit corresponding to a single fuse, i.e., when the adjustable chip has only a single fuse, the first instruction signal may not contain address information, but only adjustment operation information. This adjustment operation information may correspond to a single bit of adjustment operation data, used to indicate whether it is a write operation or a read operation. For example, when the adjustment operation information is a write operation, the data bit is set to "1" and the corresponding data bit signal is set to a first level, such as a high level; when the adjustment operation information is a read operation, the data bit is set to "0" and the corresponding data bit signal is set to a second level, such as a low level. In this case, since the first instruction signal may not contain address information, but only adjustment operation information, the second instruction signal obtained after modulation and demodulation of the first instruction signal may also only contain adjustment operation information. The second instruction signal can be transmitted to the adjustment module 320 to directly perform adjustment operations on the adjustment unit in the adjustment module 320. When the adjustment operation is a read operation, it also includes forming a first feedback signal from the data read back according to the status of the adjustment unit and directly transmitting it back to the first modulation and demodulation module 310 by the adjustment module 320. After being modulated by the first modulation and demodulation module 310 and demodulated by the auxiliary adjustment chip 14, it is transmitted to the microprocessor.

[0040] When the adjustable chip 13 contains only one adjustment unit corresponding to a single row or column of fuses, the second instruction signal may contain address information and adjustment operation information. The address information corresponds to one or more address data bits, used to determine the fuse to be adjusted. For example, an adjustment unit may contain eight fuses in a single row, fuses 1 to 8, which can be located using eight address data bits. If an adjustment operation is to be performed on fuse 1, its address data may be represented as "10000000", which corresponds to setting the data bit signal of fuse 1 to the first level (e.g., high level) and the remaining seven data bit signals to the second level (e.g., low level). The adjustment operation information can correspond to a single bit of adjustment operation data, indicating whether the adjustment operation is a write operation or a read operation. For example, when the adjustment operation information is a write operation, the data bit is set to "1" and the corresponding data bit signal is set to a first level, such as a high level; when the adjustment operation information is a read operation, the data bit is set to "0" and the corresponding data bit signal is set to a second level, such as a low level. When the adjustment operation is a read operation, it also includes forming a first feedback signal from the data read back according to the adjustment unit status and directly transmitting it back to the first modulation and demodulation module 310 by the adjustment module 320. After being modulated by the first modulation and demodulation module 310 and demodulated by the auxiliary adjustment chip 14, it is transmitted to the microprocessor.

[0041] When a trimmable chip contains multiple trimmable units, and each trimmable unit contains multiple trimmable basic units, i.e., when the trimmable chip contains a fuse array, the following can be used: Figure 3 A modifiable chip 13 is provided, which is compatible with... Figure 2The same structure in the function and Figure 2 To maintain consistency, I will not elaborate further. For example... Figure 3 As shown, the trimming module 320 further includes a trimming array 321. The trimming array 321 may include multiple trimming units, each trimming unit including multiple basic trimming units, and the trimming array 321 is configured to perform trimming operations on the basic trimming units in the trimming units according to the second instruction signal.

[0042] like Figure 3 As shown, the adjustable chip 13 further includes a control module 330. The control module 330 is configured to convert the second instruction signal into an adjustment signal, and use the adjustment signal to locate the adjustment unit and the basic adjustment unit in the adjustment module and perform adjustment operations.

[0043] When the trimming module includes a trimming array 321, the trimming signal includes trimming operation information, first address information, and second address information. The trimming operation information indicates whether it is a write operation or a read operation. The first address information is used to locate trimming units in the trimming array; for example, when each row of fuses in the trimming array represents a trimming unit, the first address information is used to select the trimming unit in the corresponding row. The second address information is used to determine the basic trimming unit in the located trimming unit. Specifically, the trimming array 321 is configured to locate trimming units in the trimming array using the first address information, and to determine the basic trimming unit in the located trimming unit based on the second address information and perform the corresponding trimming operation based on the trimming operation information. Those skilled in the art should understand that the trimming operation information, first address information, and second address information included in the trimming signal correspond to the trimming operation information and address information included in the aforementioned first instruction signal and second instruction signal. Therefore, the trimming operation information, first address information, and second address information in the trimming signal are contained and determined by signals sent by the microcontroller.

[0044] The adjustment operation information can be transmitted via the read / write signal r / w. The read / write signal r / w is generated by the control module 330 according to the second instruction signal and transmitted to the adjustment module (at this time, the read / write signal r / w is part of the adjustment signal). When the adjustment operation is a write operation, the read / write signal is write enabled, used to control the selected adjustment basic unit to enter the burning state. When the adjustment operation is a read operation, the read / write signal is read enabled, used to determine the operation of reading back the status data information of the selected adjustment basic unit. The read-back data information is generated by the control module 330 through the read-back data signal r_data and sent to the first modulation and demodulation module 310. After demodulation by the auxiliary adjustment chip 14, it is transmitted to the microprocessor. The specific working process is similar to the aforementioned process and will not be repeated here.

[0045] Preferably, the commands for programming multiple trimming units can be entered at once and controlled by the control module 330, so that multiple trimming units are not programmed at the same time, but rather one trimming unit is programmed sequentially. This avoids the problem of excessive power supply jitter causing circuit failure due to simultaneous programming of multiple trimming units, and also avoids the problem of repeatedly entering the programming command for a single trimming unit, making it easier to control and implement batch trimming.

[0046] Of course, in optional cases, when the fuses corresponding to the adjustment units included in the adjustable chip are in a single row, single column, or single wire, this method can also be used. Figure 3 The structure is adjusted. At this time, the adjustment signal generated by the control module 330 may include adjustment operation information and address information without distinguishing between the first address information and the second address information, or it may only include adjustment operation information, which may include write operation information or read operation information.

[0047] Figure 4 This is a circuit diagram of an adjustment module 320 provided in an embodiment of this disclosure. In one embodiment of this disclosure, when the adjustment unit adjusts a single fuse, the adjustment module 320 can perform the following... Figure 4As shown, it may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a fuse. The input signal to the control electrode Control of the first transistor M1 is determined by the adjustment operation information in the first / second instruction signals. For example, when a read / write signal r / w is present, this read / write signal r / w is input to the control electrode Control to control the first transistor M1. The first terminals of the first transistor M1, the second transistor M2, and the third transistor M3 are all coupled to the ground terminal GND. The second terminals of the first transistor M1, the second transistor M2, the control electrode of the third transistor M3, and the control electrode of the fourth transistor M4 are all coupled to the first end of the fuse. The control electrode of the second transistor M2 is coupled to the reference voltage terminal Vbias. The second terminals of the third transistor M3 and the fourth transistor M4 are coupled to the output terminal OUT of the adjustment module 320. The first terminal of the fourth transistor M4 is coupled to the power supply VDD, and the second end of the fuse is coupled to the power supply VDD. The basic working principle of this circuit is as follows: A bias voltage is provided to the second transistor M2 through the reference voltage terminal Vbias, causing the second transistor M2 to operate in the saturation region. At this time, the second transistor M2 and the fuse are connected in series to form a circuit. Since the second transistor M2 has a relatively large resistance relative to the fuse, it achieves weak conduction. The current through the fuse is relatively small and insufficient to blow it. At this time, the control terminals of the third transistor M3 and the fourth transistor M4 are at a high level, and the output terminal OUT is at a low level, indicating that the fuse has not blown. When the input terminal Control is at a low level, the first transistor M1 is turned off, which does not affect the operation of the above circuit. However, when the input terminal Control is high, i.e., the data bit signal corresponding to the trimming operation information is set to high, or the read / write signal is set to high, the first transistor M1 is turned on. At this time, the first transistor M1 and the fuse form a circuit in series. Since the resistance of the first transistor M1 is much smaller than that of the second transistor M2 in this embodiment, a large current will flow through the circuit formed by the first transistor M1 and the fuse, burning the fuse and completing the trimming write operation. At this time, the control terminals of the third transistor M3 and the fourth transistor M4 will become low, and the output terminal OUT will output a high level, indicating that the fuse has blown and the trimming write operation has been completed. Those skilled in the art should understand that... Figure 4 The circuit shown is just one implementation of the trimming module. It can be used as a trimming module containing only a single trimming unit corresponding to a single fuse, as a basic trimming unit module containing a trimming module containing a single trimming unit corresponding to a single row or column of fuses, or as a basic trimming unit module containing one trimming unit among multiple trimming units corresponding to array fuses.

[0048] Figure 5This is a circuit diagram of another trimming module 320 provided in this embodiment. In another embodiment of this disclosure, when trimming is performed on a single row of fuses corresponding to a trimming unit, the trimming module 320 can be as follows: Figure 5As shown, the device may include a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a single row of Y fuses. Each of the Y fuses has a corresponding selection switch transistor MS1 to MSY. The input signal to the control electrode Control of the fifth transistor M5 is determined by the adjustment operation information in the first / second instruction signals. For example, when a read / write signal r / w is present, this read / write signal r / w is input to the control electrode Control to control the first transistor M5. The first terminals of the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are all coupled to the ground terminal GND. The second terminals of the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are coupled to the first terminals of each of the selection switch transistors MS1 to MSY. The control terminal of the sixth transistor M6 is coupled to the reference voltage terminal Vbias. The second terminals of the seventh transistor M7 and the eighth transistor M8 are coupled to the output terminal OUT of the trimming module 320. The first terminal of the eighth transistor M8 is coupled to the power supply VDD. The control terminals of each of the selection switch transistors MS1 to MSY are coupled to the input terminals S1 to SY that determine the corresponding address information. The second terminal of each of the selection switch transistors MS1 to MSY is coupled to the first terminal of the corresponding fuse that needs to be trimmed. The second terminal of each fuse that needs to be trimmed is coupled to the power supply VDD. The basic working principle of this circuit is as follows: A bias voltage is provided to the sixth transistor M6 through the reference voltage terminal Vbias, causing the sixth transistor M6 to operate in the saturation region. At this time, the sixth transistor M6 forms a circuit with fuses 1 to Y in series. Since the sixth transistor M6 has a relatively large resistance relative to the fuses, it achieves weak conduction. The current through the fuses is relatively small and insufficient to blow them. At this time, the control terminals of the seventh transistor M7 and the eighth transistor M8 are at a high level, and the output terminal OUT is at a low level, indicating that the fuses have not blown. When the input terminal Control is at a low level, the fifth transistor M5 is turned off, which does not affect the operation of the above circuit. However, when the input terminal Control is high (i.e., the adjustment operation information data position is high, or the read / write signal is high), and when the address information selects fuse j (j is an integer, and 1≤j≤Y), the input terminal Sj corresponding to fuse j is set to high. At this time, the corresponding selection switch transistor MSj is turned on, and the fifth transistor M5 is turned on. The fifth transistor M5 and fuse j are connected in series to form a path. Since the resistance of the fifth transistor M5 is much smaller than that of the sixth transistor M6 in this embodiment, a large current will flow through the path formed by the fifth transistor M5 and fuse j, burning out fuse j and completing the adjustment / write operation. At this time, the control terminals of the seventh transistor M7 and the eighth transistor M8 will become low, and the output terminal OUT will output a high level, indicating that fuse j has blown and the adjustment / write operation of fuse j has been completed. Figure 5 The example circuit is also applicable to the adjustment of single-row fuses.

[0049] Figure 6 The embodiments provided in this disclosure are related to Figure 5 The combined schematic diagram shows the adjustment circuit for the adjustment array, where the adjustment array is an X×Y fuse array. Figure 5 This is a circuit example diagram for adjusting a single row of fuses corresponding to an adjustment unit. In the adjustment control circuit of an X×Y fuse array, X fuses can be set at this time. Figure 5 The circuit structure of the trimming unit is shown. When trimming is performed on the trimming array corresponding to multiple trimming units... Figure 5 The selector transistors MS1 to MSY and fuses 1 to Y can be used as one row in the trimming array, i.e., one of the trimming units among multiple trimming units. The fuses in this row correspond to the trimming basic units in that trimming unit. The control electrode of the selector transistor of each trimming basic unit is controlled by a corresponding 2-input AND gate, wherein the two input terminals of the AND gate are determined by the first address parallel signal addr1 and the second address parallel signal addr2 in the trimming signal, respectively. When a write or read operation needs to be performed on the trimming basic unit, only one of the X first address parallel signals addr1<1:X> can be set to a high level. Then, the X first address parallel signals addr1<1:X> and Y second address parallel signals addr2<1:Y> are ANDed with each other through the AND gate to obtain the control signal controlling the control electrode of the selector transistor corresponding to each trimming basic unit (i.e., each fuse in this embodiment). In one embodiment of this disclosure, taking a write operation and the target trimming basic unit fuse ij (i.e., the fuse ij in the i-th row and j-th column of the trimming array, where i and j are integers, and 1≤i≤X, 1≤j≤Y) as an example, there are X first address parallel signals addr1<1:X>, i.e., the first first address parallel signal addr1 <1> Up to the Xth parallel signal at the first address, addr1 <x>These correspond to the address information of X trimming units (i.e., the row information of the trimming array). There are a total of Y second address parallel signals addr2<1:Y>, which is the first second address parallel signal addr2. <1> Up to the Yth parallel signal at the second address, addr2 <y>These correspond to the address information (i.e., column information) of Y basic adjustment units. The adjustment units in the adjustment array can be determined through the first address parallel signal, for example, through the i-th first address parallel signal addr1. The trimming unit i in the trimming array can be determined, that is, the trimming basic unit in the i-th row, and then according to the j-th second address parallel signal addr2 <j>The basic adjustment unit ij in adjustment unit i can be determined, that is, the fuse ij in the i-th row and j-th column of the adjustment array. The i-th first address parallel signal addr1 in the first address parallel signal addr1<1:X> If the first address parallel signal is set to high and the remaining first address parallel signals are set to low, then the trimming unit i is selected (i.e., the fuse in the i-th row is selected), and the j-th second address parallel signal addr2 in the second address parallel signal addr2<1:Y> is... <j>If the first address parallel signal is set to high and the remaining second address parallel signals are set to low, then the i-th first address parallel signal addr1 will be used. parallel signal addr2 at the j-th second address <j>After performing an AND operation, if the control signal at the control electrode Sij of the corresponding selection switch transistor MSij is high, then the basic unit ij (i.e., the fuse ij in the i-th row and j-th column of the adjustment array) is programmed. If the control signals at the control electrodes of the other selection switch transistors (not simultaneously high, i.e., one is low) are all low after an AND operation, then the corresponding basic units (i.e., fuses) are not programmed. Additionally, during a write operation, the control input terminal Control is set high according to the adjustment operation information or read / write signal. Figure 5 The circuit example diagram shown follows the same principle and will not be repeated here. The above example only shows the settings of the first address parallel signal, the second address parallel signal, and the circuit when only one basic unit (such as a fuse) is selected for a write operation. Those skilled in the art can adjust the number of fuses for a single read or write operation according to the fuse's adjustment power capability, and control the generation of the first address parallel signal and the second address parallel signal according to the number of fuses that can perform adjustment operations. The row and column information contained in the first address parallel signal and the second address parallel signal can also be interchanged, or a single address signal can be used to represent the row and column information, and other appropriate circuits can be selected to perform the adjustment operation, etc. There are no restrictions here.

[0050] In one embodiment of this disclosure, when the adjustment module 320 performs a write operation, the control module 330 can place the address information (or at least one of the first and second address information in the adjustment signal) in the second instruction signal into a first return signal and return it to the first modem module 310. The first modem module 310 modulates the first return signal into a first return modulation signal and sends it to the auxiliary adjustment chip 14. The second modem module 141 demodulates the first return modulation signal to obtain a second return signal and returns the second return signal to the microprocessor, which confirms the address information in the second return signal. After confirming that it is correct, the microprocessor sends the confirmation information to the first modem module 310 in the adjustable chip 13 via the auxiliary adjustment chip 14. After receiving the confirmation information for the address information, the first modem module 310 sends the confirmation information to the control module 330. The control module 330 controls the adjustment module to perform the corresponding write operation according to the confirmation information. Conversely, when the microprocessor confirms the address information in the second feedback signal, if the address information is incorrect, it can send a denial message and the correct address information to the first modem module 310 in the modifiable chip 13 via the auxiliary tuning chip 14. After receiving the denial message and the correct address information, the first modem module 310 sends the denial message and the correct address information to the control module 330. The control module 330 controls the tuning module to perform the corresponding write operation based on the correct address information. This reconfirmation of the address information further enhances the accuracy of the tuning information, especially the address information, during the write operation, reducing the occurrence of incorrect tuning writes due to address information errors. Optionally, after the write operation is completed, the control module 330 returns the fuse array-related status information after the write operation to the microprocessor via the first modem module 310 and the auxiliary tuning chip 14.

[0051] In another embodiment of this disclosure, to ensure the accuracy of the first command signal and the second command signal, the first command signal and the second command signal may be frame signals. As mentioned above, those skilled in the art should know that the second command signal is the signal obtained by modulating and demodulating the first command signal. Under normal circumstances, the information contained in the first command signal and the second command signal should be exactly the same. Therefore, the second command signal is used as an example for explanation here.

[0052] Taking the trimming operation of an 8×8 fuse array for a 64-bit trimming array as an example, it can consist of 8 trimming units (corresponding to 8 rows of fuses), each trimming unit having 8 basic trimming units (corresponding to 8 columns of fuses). When the trimming operation performed by the trimming module 320 is a write operation, such as... Figure 7 The diagram shows the frame signal timing diagram during a write operation. The second instruction signal modifies the write operation frame, which includes a frame header "0", first address data "addr1", modifier operation data "w", second address data "addr2", and a checksum "pec". The first address data "addr1" (e.g., representing row information in the modifier array) can be binary address data, consisting of 3 bits. Specifically, this data can be one of "000", "001", "010", "011", "100", "101", "110", or "111" to represent each of the eight fuse row addresses. The modifier operation data "w" represents the write operation information and can be represented by 1 bit. The second address data "addr2" (e.g., representing column information in the modifier array), similar to the first address data "addr1", can also be binary address data, consisting of 3 bits. The settings for the frame format, frame header, first address data, second address data bits, address correspondence method, and adjustment operation data of the aforementioned second instruction signal adjustment write operation can all be set according to user needs and are not limited in this embodiment. When the adjustable chip contains only one adjustment unit and corresponds to a single row or column fuse, the frame signal may contain only one of the first address data addr1 and the second address data addr2. For example, the frame signal may not contain the first address data addr1, or one of the first address data addr1 and the second address data addr2 may be set to invalid data, for example, both of the first address data addr1 may be set to "0". When the adjustable chip contains only one adjustment unit and corresponds to a single fuse, the frame signal may not contain the first address data addr1 and the second address data addr2, or both of the aforementioned first address data addr1 and the second address data addr2 may be set to invalid data, for example, both may be set to "0".

[0053] The positioning of the basic unit can be achieved using the first and second address data in the frame signal. However, the adjustable chip 13 needs to have a control module inside to convert and process the frame signal, and then generate a series of signals to control the adjustment module. The control module 330 can both parse and process the received frame signal to generate other control signals, and process the received data to generate a frame signal of a specific format for transmission back, such as... Figure 3 As shown. Specifically, the control module 330 can... Figure 7 The second instruction signal modifies the write operation frame signal to generate a modifying signal. This modifying signal may include a first address parallel signal addr1 (containing first address information), a second address parallel signal addr2 (containing second address information), and a read / write signal w / r (containing modifying operation information), such as... Figure 9 As shown. The control module 330 modifies the first address data and second address data in the write operation frame according to the second instruction signal, generating corresponding first address parallel signals addr1 and second address parallel signals addr2. As mentioned earlier, in Figure 7 The first address data addr1 (or row information) and the second address data addr2 (or column information) can be 3 bits of binary data. However, the first address parallel signal addr1 and the second address parallel signal addr2 need to correspond to each specific switch control, therefore they must each be an 8-bit signal (where each bit represents a control signal with two states, "1" and "0"), distinguished by a first level (e.g., high level) and a second level (e.g., low level). Here, data "1" and "0" are chosen to represent the first and second levels, respectively. The binary address data "000", "001", and "010" in the aforementioned second instruction signal... For example, "011", "100", "101", "110", and "111" can be converted into the data "00000001", "00000010", "00000100", "00001000", "0001000", "0010000", "01000000", "10000000" in the first address parallel signal addr1. The "1" in the first address parallel signal addr1 indicates the selected trimming unit (corresponding to the fuse row), which can set the corresponding trimming unit to the first level. That is, the corresponding trimming unit can be found by the position set to the first level (e.g., high level). In the selected trimming unit, the column where the trimming basic unit is located can be further located through the second address parallel signal addr2 (or column information), where "1" indicates the column where the selected trimming basic unit is located (corresponding to the fuse column), which can set the corresponding trimming basic unit column to the first level. That is, the corresponding trimming basic unit in the trimming unit can be selected by the position set to the first level (e.g., high level). The control module 330 generates the corresponding read / write signal w / r according to the trimming operation data in the trimming write operation frame of the second instruction signal, for example... Figure 7 When the adjustment operation data is "w" indicating a write operation, the read / write signal w / r enables the write operation and is used to initiate the programming of the selected adjustment basic unit. The bit length and correspondence of the first address data, second address data, and address data in the adjustment write operation frame of the second instruction signal can be set according to user needs and are not limited in this embodiment.

[0054] Preferably, to enhance the accuracy of the trimming information, especially the address information, during write operations and reduce the occurrence of incorrect trimming writes due to address information errors, the control module 330 can place the address information (or at least one of the first and second address information in the trimming signal) in the second instruction signal into the first feedback signal and return it to the first modem module 310 and further back to the microcontroller. This embodiment takes the feedback of only the second address information in the trimming signal as an example. (Continue referring to...) Figure 7 A first frame interval is set between the second instruction signal modification write operation frame and the first return signal address return frame. This interval can be set by the user according to their needs, for example, 36 clock cycles, but is not limited in this embodiment. The shaded part is the first return signal generated and returned by the control module 330, which is also a frame signal, namely the first return signal address return frame, including a frame header "0", second address data addr2, and a check bit "pec". This first return signal is used to return the second address information addr2 to the microprocessor for address information confirmation. The returned address information can be set by the user according to their needs. For example, in this embodiment, it is the second address information addr2, but it can also be selected as the first address information addr1 or both the first address information addr1 and the second address information addr2 can be returned simultaneously. At the same time, the user can either select the address information corresponding to the second instruction signal received by the control module 330 for return, or select the address information corresponding to the first address information and the second address information in the modification signal (first / second address parallel signal) issued by the control module 330 for return, but is not limited in this embodiment. While waiting for confirmation, a second frame interval may exist. This interval can be set by the user according to their needs, for example, 30 clock cycles, but is not limited in this embodiment. After the second frame interval, the first modulation and demodulation module 310 receives confirmation information for the address information transmitted from the microprocessor via the auxiliary tuning chip 14, and sends it to the control module 330. The control module 330 sets the read / write signal r / w to write enable, thereby controlling the tuning module 320 to perform the corresponding tuning operation, i.e., the write operation.

[0055] Taking the adjustment operation of the aforementioned 64-bit adjustment array 8×8 fuse array as an example, when the adjustment module 320 performs a read operation, such as... Figure 8 The diagram shows the timing of the read operation frame signal. The second instruction signal modifies the read operation frame, including a frame header "0", first address data addr1 (e.g., representing row information in the modulating array), which, similar to the previous example, can be binary address data (3 bits), modulating operation data "r" representing read operation information (1 bit), and second address data addr2 (e.g., representing column information in the modulating array), which can also be 3 bits. It may also include a parity bit "pec". The format of the second instruction signal modifies the read operation frame, the number of bits for the first and second address data, etc., can be set according to user requirements and are not limited in this embodiment. Similarly, when the modifiable chip contains only one modulating unit corresponding to a single row or column fuse, the frame signal may contain only one of the first address data addr1 and the second address data addr2. For example, the frame signal may not contain the first address data addr1, or one of the first address data addr1 and the second address data addr2 may be set to invalid data, such as setting both first address data addr1 to "0". When the adjustable chip contains only one adjustment unit and corresponds to a single fuse, the frame signal may not contain the first address data addr1 and the second address data addr2, or both the first address data addr1 and the second address data addr2 may be set to invalid data, for example, both may be set to "0". The first feedback signal is also a frame signal when it is used to feedback readback data. It is generated by the control module 330 based on the readback data signal r_data and is the first feedback signal readback data frame, including the frame header "0", the readback data r_data, and the check bit "pec". The second instruction signal adjustment read operation frame and the first feedback signal readback data frame are separated by a third frame interval. This interval can be set by the user according to their needs, for example, 36 clock cycles, but is not limited in this embodiment. The adjustment module 320 sends the readback data to the control module 330 via the readback data signal r_data. The control module 330 places the received readback data into a frame signal, forming the readback data r_data in the frame signal, and thereby generates the first return signal, the readback data frame signal (as described above). Figure 8 The shaded area shows that the first backhaul signal readback data frame includes readback data (r_data). The control module 330 modulates the first backhaul modulation signal through the first modulation and demodulation module 310 and returns the first backhaul modulation signal so that the adjustment chip 14 can demodulate the first backhaul modulation signal of the frame signal into a second backhaul signal and return it to the microprocessor. The microprocessor reads the readback data from the second backhaul signal of the frame signal, thereby completing the adjustment read operation.

[0056] In another embodiment of this disclosure, the adjustable chip 13 may further include: a decoupling capacitor C0, which is connected to a capacitor control switch k. C0 It is connected in series between the ground terminal GND and the adjustment module 320. The decoupling capacitor C0 and the capacitor control switch k... C0 Either of them can be coupled to the ground terminal GND; this is not limited in the embodiments disclosed herein. Figure 3 As shown, switch k is controlled by a capacitor. C0 Taking the decoupling capacitor C0 connected to the ground terminal GND as an example, the first terminal of the decoupling capacitor C0 controls the switch k through the capacitor. C0 The second terminal of the decoupling capacitor C0 is coupled to the ground terminal GND and is coupled to the adjustment module 320. The control module 330 outputs the decoupling capacitor switch control signal ctrl_k. c0 Used to control capacitor control switch k C0 Whether the decoupling capacitor C0 is connected depends on whether it is closed. When the control module 330 outputs the decoupling capacitor switch control signal ctrl_k... c0 When the voltage level is the first level (e.g., high level), the control capacitor controls the switch k. C0 The circuit closes, thus connecting the decoupling capacitor C0; when the control module 330 outputs the decoupling capacitor switch control signal ctrl_k... c0 When the voltage level is the second level (e.g., low level), the control capacitor controls the switch k. C0 Disconnected; decoupling capacitor C0 is not connected. Specifically, when the adjustment module 320 performs a write operation, the control module 330 outputs the decoupling capacitor switch control signal ctrl_k. c0 The first level controls the capacitor control switch k. C0 The decoupling capacitor C0 is closed to connect to the ground terminal GND. Then, the control module 330 controls the trimming module 320 to perform a write operation, so as to effectively reduce the power supply jitter on the trimmable chip 13 caused by the large current change when the fuse blows during the write operation (i.e., fuse trimming). In addition, when the write operation is completely completed, the power line no longer needs to transmit signals, and the decoupling capacitor switch control signal ctrl_k output by the control module 330 is used. c0 The first level controls the capacitor control switch k. C0 Closing the decoupling capacitor C0 to connect it to the ground terminal GND can stabilize the power supply voltage. Additionally, when the first power input terminal of the adjustable chip 13 needs to transmit an AC signal, whether receiving a signal to transmit an AC signal internally or externally, the connection between the decoupling capacitor C0 and the ground terminal must be disconnected to prevent the AC signal from being filtered or weakened by the decoupling capacitor C0. For example, during the transmission of the first command modulation signal in a read or write operation, the signal is transmitted from the auxiliary adjustment chip 14 to the adjustable chip 13. To prevent the first command modulation signal on the power line from being weakened due to the connection of the decoupling capacitor C0, the control module 330 outputs the decoupling capacitor switch control signal ctrl_k. c0 The second level controls the capacitor control switch k. C0 Disconnect the decoupling capacitor C0 from the ground terminal GND. When performing a write operation to the trim module for address feedback confirmation or a read operation, it is also necessary to send back the first feedback modulation signal through the first power input terminal. In this case, it is also necessary to control the capacitor control switch k. C0 Disconnected; decoupling capacitor C0 is not connected. Furthermore, after a phased write operation (i.e., after fuse adjustment), if it is desired to continue transmitting modulation signals for adjustment, the control module 330 outputs the decoupling capacitor switch control signal ctrl_k. c0 Still at the second level, controlling the capacitor and controlling the switch k C0 Disconnected; decoupling capacitor C0 is not connected. In this embodiment, the setting of decoupling capacitor C0 is optional and can be set according to specific requirements.

[0057] In another embodiment of the present disclosure, such as Figure 3 As shown, the adjustable chip 13 may further include a first high-pass filter 340, which is configured to filter out the DC signal and low-frequency noise signal input to the adjustable chip 13 from the first power input terminal to obtain an AC signal, namely the first command modulation signal. Specifically, the first high-pass filter 340 may be an RC filter, and may include a first capacitor C1 and a first resistor R1. The first end of the first capacitor C1 is coupled to the first power input terminal of the adjustable chip 13, the second end of the first capacitor C1 is coupled to the first end of the first resistor R1 and the first modulation and demodulation module 310 through a fourth switch k4, and the second end of the first capacitor C1 is coupled to the first modulation and demodulation module 310 through a third switch k3. The second end of the first resistor R1 is coupled to the ground terminal GND. Figure 3 The arrows in the diagram indicate the direction of signal flow, such as... Figure 3 As shown, on the path of the fourth switch k4, the signal flows from the first capacitor C1 to the first modem module 310, corresponding to the signal flow when the microprocessor sends an instruction signal to the adjustable chip 13; on the path of the third switch k3, the signal flows from the first modem module 310 to the first capacitor C1, corresponding to the signal flow when the adjustable chip 13 sends a signal back to the microprocessor.

[0058] In this embodiment, the first modulation and demodulation module 310 can be implemented using OOK (On-Off Keying) or modulation and demodulation methods such as AM (Amplitude Modulation), FM (Frequency Modulation), PM (Phase Modulation), PF (Pulse Frequency Modulation), PSK (Phase Shift Keying), and FSK (Frequency Shift Keying). For example, in this embodiment, the first modulation and demodulation module 310 can be implemented using an OOK modulation module and an OOK demodulation module.

[0059] In another embodiment of this disclosure, the adjustable chip 13 may further include an oscillation module for providing a clock signal to the control module 330. The oscillation module may be an oscillator or a phase-locked loop. The oscillation module may be located within the adjustment module 320, the adjustment array 321, the control module 330, or inside the adjustable chip 13 (and outside the first modulation / demodulation module 310, the adjustment module 320, and the control module 330). Alternatively, in another embodiment of this disclosure, the oscillation module may be located outside the adjustable chip 13. The oscillation module can be configured to provide a clock signal to the control module 330; the method of configuring the oscillation module is not limited in this disclosure.

[0060] The adjustable chip in this embodiment demodulates the modulation signal obtained via the power line into a command signal for controlling the adjustment operation through the modulation and demodulation function, thereby improving the efficiency of mass production of adjustment and saving costs. In addition, it improves the driving capability of programming by directly supplying power.

[0061] To further describe the embodiments of this disclosure in detail, Figure 9 A schematic diagram of the architecture of an adjustable chip 13 provided in an embodiment of this disclosure is shown. Figure 9 As shown, taking the adjustment array as an example, when the microcontroller controls the adjustmentable chip 13 to perform adjustment operations, the microprocessor provides the adjustmentable chip with a first instruction signal containing adjustment operation information, address information, etc. The control module 330 generates a fourth switch enable signal to control the fourth switch k4. When the fourth switch enable signal is at a first level (e.g., high level), the fourth switch k4 controlled by the fourth switch enable signal is closed. Thus, the first modulation and demodulation module 310 receives the first instruction modulation signal from the microcontroller through the first power input terminal, demodulates it to obtain a second instruction signal and sends it to the control module 330. The control module 330 converts the second instruction signal (wherein, the first instruction signal and the second instruction signal can be frame signals) into an adjustment signal. The adjustment signals include a first address parallel signal addr1 (which contains first address information addr1<1:X>, used to select the adjustment unit in a specific address bit, i.e., the fuse row in the adjustment array, and select the adjustment unit to perform a write or read operation), a second address parallel signal addr2 (which contains second address information addr2<1:Y>, used to determine the basic adjustment unit in the selected adjustment unit, i.e., the fuse in the fuse row, and select the fuse to perform a write or read operation), and a read / write signal r / w (which contains adjustment operation information, used to indicate whether it is a read operation or a write operation; when it is a write enable signal, the adjustment module performs an adjustment write operation; when it is a read enable signal, the adjustment module performs an adjustment read operation), thereby realizing the microcontroller's control of the adjustment operation of the adjustable chip 13.

[0062] When the adjustable chip 13 sends a signal back to the microcontroller (for example, before the actual execution of the adjustment write operation, to confirm the address information parsed by the control module 330, or during the adjustment read operation, to send back the read information of the adjustment result of the adjustment module), the control module 330 of the adjustable chip provides a first feedback signal containing address information or read information to the first modulation and demodulation module 310. The control module 330 generates a third switch enable signal to control the third switch k3. When the third switch enable signal is at the first level (e.g., high level), the third switch k3 controlled by the third switch enable signal is closed, and the first modulation and demodulation module 310 can modulate the first feedback signal into a first feedback modulation signal and send it out.

[0063] Taking the programming operation of the basic unit ij (i.e., the fuse ij in the i-th row and j-th column of the tuning array) in the X×Y tuning array as an example, the i-th first address parallel signal addr1 If the first level is set (e.g., high level) and the remaining positions are set to the second level (e.g., low level), then the trimming unit i is selected (i.e., the fuse in the i-th row is selected), and the j-th parallel signal addr2 of the second address is activated. <j>Set it to the first level (e.g., high level), and the rest to the second level (e.g., low level), for example, in Figure 6 In the diagram, each of the outputs after performing a logical AND operation on the X×Y first address parallel signals addr1 and second address parallel signals addr2 corresponds to a basic tuning unit, which is the control electrode of the control selection switch transistor. That is, when the i-th first address parallel signal addr1... Set to the first level (e.g., high level), and the j-th parallel signal at the second address, addr2 <j>When set to the first level (e.g., high level), the output after the logical AND operation between the two is also the first level (e.g., high level). The control signal Sij for the control electrode of the corresponding selection switch transistor is also at the first level (e.g., high level), selecting fuse ij for control. The read / write signal r / w in the trimming signal is set to write enable, indicating that the process of writing the fuse begins, and controlling the trimming array to be in the writing state. For example, in Figure 5 In this circuit, the write enable signal is input to the Control terminal of the fifth transistor M5. Therefore, after the read / write signal r / w is set to write enable, the selected fuse ij enters the writing state, and the trimming write operation is completed after fuse ij blows.

[0064] Similarly, taking the above X×Y trimming array with the trimming basic unit ij (i.e., the fuse ij in the i-th row and j-th column of the trimming array) as an example for reading, when the i-th first address parallel signal addr1 Set to the first level (e.g., high level), and the j-th parallel signal at the second address, addr2 <j>is set to the first level (e.g. high level), and the read / write signal r / w in the trimming signal is set to read enable, the on-off state of the trimming basic unit ij is determined, the control signal Sij of the control electrode of the corresponding selection switch transistor is set to the first level (e.g. high level), the corresponding selection switch transistor is closed, and the selection switch transistor of other unselected trimming basic units is opened, so that the on-off state of the selected fuse is read. The read data signal r_data is generated and sent to the control module 330, which contains the read data returned in the read operation. For example, Figure 5 The read data signal r_data corresponding to the trimming basic unit ij is obtained at the output end OUT. The read data signal r_data is necessary for reading the trimming state, but if the read operation function is not required, the read data signal and the read data transmission can be omitted.

[0065] The clock signal required by the control module 330 is provided by the oscillation module 322 in the trimming module 320. Figure 9 The oscillation module 322 provides the clock signal CLK to the control module 330, but in actual application, the oscillation module can be arranged outside the trimming module 320, inside the trimming chip 13, inside the control module 330, or outside the trimming chip 13, etc. When the oscillation module is arranged inside the trimming chip 13, the advantage is that no external clock is required, reducing the use of chip pins, and the disadvantage is that the area is occupied. In addition, after the trimming is completed, the oscillation module is preferably turned off to save power consumption.

[0066] Figure 2 A schematic block diagram of an auxiliary trimming chip 14 is shown, which can work with the trimming chip 13 described in the above embodiments. As shown in Figure 2 The auxiliary trimming chip 14 can include a second modulation and demodulation module 141 and a second high-pass filter 142. The second modulation and demodulation module 141 is configured to convert the first instruction signal sent by the microprocessor into a first instruction modulation signal and send it to the trimming chip 13 through the first signal end. The second high-pass filter 142 is configured to filter out the direct current signal and low frequency noise signal input from the first signal end to the auxiliary trimming chip 14 to obtain the first return modulation signal returned by the trimming chip 13.

[0067] The second modulation and demodulation module 141 can refer to the first modulation and demodulation module 310 in the trimming chip 13, and can be implemented by OOK, AM, PM, PF, PSK or FSK modulation and demodulation mode.

[0068] The working principle of the second high-pass filter 142 is also the same as that of the first high-pass filter 340, and the main structure thereof can be composed of an RC filter of a second resistor R2 and a second capacitor C2, specifically to filter out direct current signals and low-frequency noise signals input by the first signal end to the auxiliary trimming chip 14, to obtain alternating current signals in a specified frequency range in the return signal of the trimmable chip 13, that is, the first return modulation signal.

[0069] The microprocessor can be an FPGA (Field Programmable Gate Array), a single-chip microcomputer, an ECU (Electronic Control Unit), a DSP (Digital Signal Processor), or the like.

[0070] As shown in Figure 2 The second modulation and demodulation module 141 receives a first switch enable signal for controlling the first switch k1 and a second switch enable signal for controlling the second switch k2 from the microprocessor. When the first switch enable signal is at a first level (for example, a high level), the first switch k1 is closed, and the second modulation and demodulation module 141 sends the first instruction modulation signal to the trimmable chip 13 via the first signal end. If the first switch enable signal is at a second level (for example, a low level), the first switch k1 is opened. When the second switch enable signal is at the first level (for example, a high level), the second switch k2 is closed, and the second modulation and demodulation module 141 receives the first return modulation signal sent by the trimmable chip 13 via the first signal end through the second high-pass filter 142. If the second switch enable signal is at the second level (for example, a low level), the second switch k2 is opened. Figure 2 The arrows in the figure indicate the flow direction of the signals, as shown in Figure 2 As shown in

[0071] In the embodiments of the present disclosure, the modulation signal obtained via the power line is demodulated into an instruction signal for controlling the trimming operation by the modulation and demodulation function. Since the trimmable chip and the auxiliary trimming chip are directly powered by the power line, it is not necessary to consider the driving problem of the auxiliary trimming chip, and one-to-many batch trimming can be realized, the efficiency of mass production is improved, and the cost is saved.

[0072] The singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a" or "the" element is

[0073] Further aspects and ranges of adaptation will become apparent from the description provided herein. It should be understood that the various aspects of the application can be practiced separately or in combination with one or more other aspects. It should also be understood that the description and specific examples herein are intended to be illustrative only and are not intended to limit the scope of the application.

[0074] The above detailed description of several embodiments of the disclosure has been presented for the purposes of illustration and description. It is not intended to be exhaustive or limiting to the precise form described. Many modifications and variations are possible in light of this disclosure. It is intended to cover all modifications and variations as long as they fall within the scope of the disclosure. The disclosure was chosen and disclosed in order to best explain the principles and the practical application of the disclosure to others skilled in the art.< / j> < / j> < / j> < / j> < / j> < / j> < / y> < / x>

Claims

1. A repairable chip, characterized in that, include: The first modulation / demodulation module and the adjustment module are coupled to the first power input terminal of the adjustable chip. The first modulation and demodulation module is configured to demodulate the first command modulation signal that modulates the first command signal obtained through the first power input terminal, and obtain the second command signal after demodulation. The adjustment module includes an adjustment unit, and the adjustment module is configured to perform an adjustment operation on the adjustment unit according to the second instruction signal.

2. The adjustable chip according to claim 1, characterized in that, The first instruction signal and the second instruction signal include adjustment operation information, or adjustment operation information and address information. The address information is used to locate the adjustment unit, and the adjustment operation information includes write operation information or read operation information.

3. The adjustable chip according to claim 1, characterized in that, The adjustment module includes: an adjustment array. The trimming array includes multiple trimming units, each trimming unit includes multiple trimming basic units, and the trimming array is configured to perform trimming operations on the trimming basic units in the trimming units according to the second instruction signal.

4. The adjustable chip according to any one of claims 1-3, characterized in that, The adjustable chip also includes a control module. The control module is configured to convert the second command signal into a trimming signal, and use the trimming signal to locate the trimming unit in the trimming module and perform the trimming operation.

5. The adjustable chip according to claim 4, characterized in that, When the trimming module includes a trimming array, the trimming signal includes a trimming operation signal, a first address parallel signal, and a second address parallel signal. The trimming array is configured to locate trimming units in the trimming array using the first address parallel signal, and to determine the basic trimming units in the located trimming units according to the second address parallel signal and to perform corresponding trimming operations according to the trimming operation signal.

6. The adjustable chip according to claim 5, characterized in that, When the adjustment module performs a write operation, The control module is further configured to place the address information in the second instruction signal or at least one of the first address information and the second address information in the trimming signal into the first feedback signal and return it to the first modulation and demodulation module. The first modulation and demodulation module is further configured to modulate the first return signal into a first return modulation signal, and after receiving confirmation information for the address information, send the confirmation information to the control module. The control module is also configured to control the trimming module to perform a corresponding write operation based on the confirmation information.

7. The adjustable chip according to claim 4, characterized in that, The adjustable chip further includes a decoupling capacitor, which is connected in series with the capacitor control switch between the ground terminal and the adjustment module; The control module is further configured to close the capacitor control switch to connect the decoupling capacitor to the ground terminal when the adjustment module performs an adjustment write operation or when the adjustment operation of the adjustable chip is completed; and to open the capacitor control switch to disconnect the decoupling capacitor from the ground terminal when the first power input terminal transmits a signal.

8. The adjustable chip according to claim 1, characterized in that, The adjustable chip further includes a first high-pass filter, which is configured to filter out the DC signal and low-frequency noise signal input to the adjustable chip from the first power input terminal to obtain the first command modulation signal.

9. An auxiliary adjustment chip, characterized in that, In conjunction with the adjustable chip according to any one of claims 1-8, the auxiliary adjustment chip includes: a second modulation / demodulation module and a second high-pass filter. The second modulation and demodulation module is configured to convert the first instruction signal sent by the microprocessor into a first instruction modulation signal and send it to the adjustable chip through the first signal terminal; The second high-pass filter is configured to filter out the DC signal and low-frequency noise signal input to the auxiliary tuning chip from the first signal terminal, so as to obtain the first feedback modulation signal returned by the tuned chip.

10. A tuning circuit, characterized in that, include: The auxiliary adjustment chip according to claim 9, at least one adjustable chip according to any one of claims 1-8, and a first inductor are connected via a power line, wherein a first end of the first inductor is coupled to a power supply and a second power input terminal of the auxiliary adjustment chip, and a second end of the first inductor is coupled to the first power input terminal of the adjustable chip and the first signal terminal of the auxiliary adjustment chip.

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