A data synchronization system based on event instructions
By using an event-based data synchronization system, which combines synchronization event commands and identification information, the problem of low synchronization efficiency caused by data packet dependencies is solved, and efficient parallel data synchronization is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-13
- Publication Date
- 2026-03-27
Smart Images
Figure CN121501521B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of integrated circuit design, in particular to a data synchronization system based on event instructions. BACKGROUND
[0002] In a chip application scenario, the data amount of a data packet corresponding to a program is usually large, and the data packet needs to be split into multiple sub-packets, and each sub-packet is allocated to a different computing module for parallel computing, so as to improve the efficiency of program execution.
[0003] Since the speed of sub-packet splitting is faster than the processing speed of the computing module on the sub-packet, a corresponding memory is usually set for the computing module to store multiple sub-packets allocated to the corresponding computing module, so that sub-packet splitting and sub-packet processing can be performed simultaneously, thereby improving the overall processing efficiency.
[0004] However, since there may be a dependency relationship between data packets, that is, the processing of a data packet needs to depend on the results of other data packets that have been processed, the data packet that depends on the processing results of other data packets needs to wait until the data packet it depends on is processed before it can be taken and split.
[0005] To solve the above problems, the prior art proposes to send read instructions to the addresses where the processing status of each dependent data packet is stored in sequence by event instructions to access, and when the results returned by the read instructions are all processing completed status, the data packet to be processed can be taken and split. However, the sequential reading of addresses may cause the result returned by a read instruction to be in an unprocessed completed state for a long time, thereby consuming a long time for reading the address, resulting in low overall data synchronization efficiency.
[0006] Therefore, how to improve the data synchronization efficiency has become a problem to be solved. SUMMARY
[0007] To solve the above technical problems, the technical solution adopted by the present application is:
[0008] A data synchronization system based on event instructions, the system comprising: a storage module, a packet taking module, a data packet distribution module, a firmware, M memories and M computing modules, wherein the memory and the computing module are one-to-one corresponding, and M is a positive integer.
[0009] The packet taking module is configured to read an initial data packet corresponding to a packet taking instruction from the storage module after receiving the packet taking instruction.
[0010] The data packet distribution module is configured to receive the initial data packet sent by the packet taking module, split a target data packet from the initial data packet, and send the target data packet to the arbitrated memory.
[0011] The memory is configured to receive target data packets and send the received target data packets to corresponding calculation modules.
[0012] The calculation modules are configured to perform calculation processing on the received target data packets.
[0013] The firmware is configured to update the record values of the data packet processing record addresses of the initial data packets to which the target data packets belong in the storage module after the calculation processing of any target data packet is completed.
[0014] The system simultaneously sends read instructions to the data packet processing record addresses corresponding to the N initial data packets in the storage module after receiving a synchronization event instruction for the N initial data packets, and the read instructions include identification information, wherein N is a positive integer.
[0015] For any read instruction, the record value read back by the read instruction is written into a register corresponding to the identification information included in the read instruction.
[0016] If the record values in the registers corresponding to the initial data packet identification information of the N initial data packets satisfy a preset condition, data synchronization is completed, and a new packet taking instruction is generated and sent to the packet taking module.
[0017] Compared with the prior art, the data synchronization system based on event instructions provided by the present application has obvious beneficial effects, and can achieve considerable technical progress and practicality, and has wide industrial utilization value. The present application has at least the following beneficial effects:
[0018] The present application simultaneously sends read instructions to multiple data packet processing record addresses, avoids mutual waiting of read operations between different data packet processing record addresses, improves data synchronization efficiency, and further includes identification information in the read instructions, different identification information corresponds to different registers, and the record values read back by the read instructions are stored in the corresponding registers, which avoids the disorder of the read record values due to different return times of the read instructions in the case of simultaneously sending read instructions, thereby ensuring the feasibility of parallel reading of the record values of multiple data packet processing record addresses. BRIEF DESCRIPTION OF DRAWINGS
[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0020] Figure 1A structure schematic view of a data synchronization system based on event instruction provided by the embodiment one of the present application is provided.
[0021] Figure 2 A structure schematic view of an identification generation system based on FIFO provided by the embodiment two of the present application is provided. DETAILED DESCRIPTION
[0022] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person skilled in the art without creative work fall within the protection scope of the present application.
[0023] The embodiment one provides a data synchronization system based on event instruction, referring to Figure 1 A structure schematic view of a data synchronization system based on event instruction provided by the embodiment one of the present application is provided, and the system comprises a storage module, a packet taking module, a data packet distribution module, a firmware, M storage memories and M computing modules, wherein, the storage memory and the computing module are one-to-one corresponding, M is a positive integer;
[0024] The packet taking module is used for reading the initial data packet corresponding to the packet taking instruction from the storage module after receiving the packet taking instruction;
[0025] The data packet distribution module is used for receiving the initial data packet sent by the packet taking module, splitting the target data packet from the initial data packet, and sending the target data packet to the arbitrated storage memory;
[0026] The storage memory is used for receiving the target data packet, and sending the received target data packet to the corresponding computing module;
[0027] The computing module is used for performing computing processing on the received target data packet;
[0028] The firmware is used for updating the record value of the data packet processing record address of the initial data packet to which any target data packet belongs in the storage module after the computing processing of the target data packet is completed;
[0029] The system simultaneously sends a read instruction to the data packet processing record address corresponding to N initial data packets in the storage module after receiving the synchronization event instruction of the N initial data packets, and the read instruction comprises identification information, and N is a positive integer;
[0030] For any read instruction, the record value read back by the read instruction is written into the register corresponding to the identification information contained in the read instruction;
[0031] If the record values in the registers corresponding to the initial data packet identification information of the N initial data packets satisfy a preset condition, data synchronization is completed, and a new packet taking instruction is generated and sent to the packet taking module.
[0032] The storage module can be a memory of a chip, and access to the storage module needs to be performed through an interface provided by the storage module. In this embodiment, reading the initial data packet and reading the record value need to be performed through the interface of the storage module.
[0033] The memory can be a first input first output (FIFO) memory, that is, a sub data packet that enters the memory first will be sent to the computing unit first.
[0034] The firmware can be an RSICV firmware, which is used to perform a specific function. In this embodiment, the firmware is used to update the corresponding record value according to the processing condition of the target data packet.
[0035] The packet taking instruction can contain a packet taking address in the storage module, and the packet taking module reads the initial data packet corresponding to the packet taking instruction from the storage module according to the packet taking address.
[0036] The arbitration mode of the memory can be configured by an implementer through software. The arbitration mode can include a round robin arbitration mode, a disorder arbitration mode, a weight arbitration mode, and the like.
[0037] In a specific implementation, after the computing and processing of any target data packet are completed, the record value of the data packet processing record address corresponding to the initial data packet to which the target data packet belongs in the storage module is updated, including:
[0038] After the computing and processing of any target data packet are completed, the record value of the data packet processing record address corresponding to the initial data packet to which the target data packet belongs in the storage module is reduced by one, and the update of the record value is completed.
[0039] The initial data packet to which the target data packet belongs can be the split source of the target data packet.
[0040] In a specific implementation, for any initial data packet, the record value corresponding to the initial data packet is initially the number of target data packets split from the initial data packet.
[0041] Since the data amount of the initial data packet is known, the data amount of the target data packet can be set by an implementer, and then the number of target data packets split from the initial data packet can be determined according to the data amount of the initial data packet and the data amount of the target data packet.
[0042] In an embodiment, the updating manner of the record value can also be that, after the processing of any target data packet is completed, the record value of the corresponding data packet processing record address of the initial data packet to which the target data packet belongs in the storage module is increased by one. Correspondingly, for any initial data packet, the record value corresponding to the initial data packet is initially 0, and the record values in the registers corresponding to the initial data packet identification information of the N initial data packets can satisfy the preset condition, which can mean that the record values in the registers corresponding to the initial data packet identification information of the N initial data packets are respectively consistent with the number of target data packets corresponding to the N initial data packets.
[0043] In a specific embodiment, the identification information includes initial data packet identification.
[0044] In the embodiment, the identification information includes initial data packet identification, and each initial data packet corresponds to a register.
[0045] In a specific embodiment, the identification information further includes pipeline identification.
[0046] In the embodiment, one pipeline can include the processing of multiple initial data packets, multiple pipelines can be executed in parallel, and when the identification information includes initial data packet identification and pipeline identification, each initial data packet of each pipeline corresponds to a register.
[0047] In an embodiment, the identification information can further include queue identification, one queue can include multiple pipelines, and multiple queues can use the computing resources in a time slice allocation manner.
[0048] In a specific embodiment, the addresses of the registers corresponding to the initial data packet identification information of the N initial data packets form an address interval, the address interval corresponds to a read pointer, and the read pointer initially points to the start address of the address interval.
[0049] When the record value in the register pointed to by the read pointer is 0, the read pointer is increased by 1.
[0050] When the value of the read pointer is greater than the end address of the address interval, it is determined that the record values in the registers corresponding to the initial data packet identification information of the N initial data packets satisfy the preset condition.
[0051] In order to facilitate processing, the addresses of the registers corresponding to the initial data packet identification information of the N initial data packets are set to be consecutive in the embodiment, and the addresses of the registers corresponding to the initial data packet identification information of the N initial data packets can form an address interval.
[0052] Specifically, when the value of the read pointer is greater than the end address of the address interval, it indicates that the record values in the registers corresponding to the initial data packet identification information of the N initial data packets are all 0, at this time, it can be indicated that the N initial data packets are all processed, and the preset condition can be met.
[0053] In a specific embodiment, for any read instruction, if the record value read back by the read instruction is not 0, a read instruction is sent to the data packet processing record address corresponding to the read instruction again.
[0054] In a specific embodiment, for any read instruction, if the record value read back by the read instruction is not 0, a read instruction is sent to the data packet processing record address corresponding to the read instruction again.
[0055] Specifically, since different registers are set for different initial data packets in the embodiment, the above-mentioned way of re-sending the read instruction will not cause the record values read back to be in disorder, and the efficiency of data synchronization is improved.
[0056] In a specific embodiment, when the required initial data packet to be read has a dependency relationship with the N initial data packets that have been read, a synchronization event instruction of the N initial data packets is generated and sent to the system.
[0057] Correspondingly, if the record values in the registers corresponding to the initial data packet identification information of the N initial data packets meet the preset condition, the data synchronization is completed, a new packet taking instruction is generated and sent to the packet taking module, including:
[0058] If the record values in the registers corresponding to the initial data packet identification information of the N initial data packets meet the preset condition, the data synchronization is completed, and a new packet taking instruction corresponding to the required initial data packet to be read is generated and sent to the packet taking module.
[0059] If the processing of the required initial data packet to be read needs the processing results of the N initial data packets that have been read, it indicates that the required initial data packet to be read has a dependency relationship with the N initial data packets that have been read.
[0060] In the first embodiment, read instructions are sent to multiple data packet processing record addresses at the same time, which avoids the mutual waiting of read operations between different data packet processing record addresses, improves the data synchronization efficiency, and in addition, the identification information is included in the read instruction, different identification information corresponds to different registers, and the record values read back by the read instruction are stored in the corresponding registers, which avoids the disorder of the record values read back due to different return times of the read instructions in the case of sending read instructions at the same time, thereby ensuring the feasibility of parallel reading of record values of multiple data packet processing record addresses.
[0061] The embodiment two provides a FIFO-based identification generation system, referring to Figure 2 , a FIFO-based identification generation system structure diagram provided by the embodiment two of the application, the system comprises a client, a storage module, a cache module, an identification FIFO memory, wherein the storage module contains N initial data packet corresponding data packet processing record addresses respectively, the data packet processing record address corresponds to a record value, the identification FIFO memory contains K identification information, the cache module includes K cache addresses corresponding to the identification information respectively, N and K are positive integers;
[0062] After the system receives the synchronization event instruction of the N initial data packets, the read instruction is sent to the data packet processing record address corresponding to the N initial data packets in the storage module respectively;
[0063] The identification FIFO memory is used to provide identification information for the read instruction;
[0064] The cache module is used to temporarily store the record value read back by the read instruction in the cache address corresponding to the identification information of the read instruction, so that the client reads;
[0065] After any cache address is read by the client, the identification information corresponding to the cache address is input into the identification FIFO memory.
[0066] Wherein, the record value can represent the processing of the corresponding initial data packet, in order to facilitate processing, the K identification information contained in the identification FIFO memory can be continuous, for example, 1 to K.
[0067] The identification FIFO memory can be a FIFO memory carrying an initial value, and the K identification information is stored in the identification FIFO memory in ascending order. Since the FIFO memory is first-in first-out, the order of the identification information output by the identification FIFO memory is also from small to large.
[0068] It should be noted that this embodiment only takes the reading of the record value as an example, and the implementer can apply this embodiment in the scene where multiple read instructions need to be read and ordered according to the actual situation.
[0069] In a specific implementation, for any read instruction, before the read instruction is sent to the storage module, an identification information output by the identification FIFO memory is used to form a target read instruction corresponding to the read instruction, and the target read instruction corresponding to the read instruction is sent to the storage module.
[0070] Wherein, the identification information output by the identification FIFO memory can be spliced with the read instruction to form the target read instruction corresponding to the read instruction.
[0071] Specifically, after the identification FIFO memory outputs an identification information, the identification information adjacent to the identification information and greater than the identification information is output as the next output of the identification FIFO memory.
[0072] In a specific embodiment, when any target read instruction reads back a record value, according to the identification information corresponding to the target read instruction, the record value read back by the target read instruction is stored in the cache module at the cache address corresponding to the identification information.
[0073] In a specific embodiment, when multiple target read instructions are issued, the return times of the target read instructions can be different, and by using the identification information of the target read instruction, the record value read back by the target read instruction is stored in the cache module at the cache address corresponding to the identification information, so that the return results of the target read instructions can be ordered.
[0074] In a specific embodiment, the cache module corresponds to a read pointer, and the read pointer starts at the same position as the smallest identification information in the identification FIFO memory.
[0075] In a specific embodiment, the read pointer starts at the same position as the smallest identification information in the identification FIFO memory, which means that the read pointer starts at the cache address corresponding to the smallest identification information in the identification FIFO memory.
[0076] In a specific embodiment, when the record value in the cache address pointed to by the read pointer is read by the client, the read pointer is increased by one.
[0077] In a specific embodiment, when the record value in the cache address pointed to by the read pointer is read by the client, the read pointer is increased by one.
[0078] In a specific embodiment, when the read pointer is greater than the largest identification information, the read pointer is set to the smallest identification information.
[0079] In a specific embodiment, when the read pointer is greater than the largest identification information, it means that all identification information has been used for one round, and at this time the read pointer is set to the smallest identification information.
[0080] In a specific embodiment, when any identification information is less than the read pointer, the identification information is input into the identification FIFO memory.
[0081] In a specific embodiment, when any identification information is less than the read pointer, it means that the record value corresponding to the identification information has been read by the client, and the identification information can be reused. The identification information is input into the identification FIFO memory, and the identification information will be assigned to a new read instruction in the future.
[0082] In a specific embodiment, when the N initial data packets read by the client each correspond to a preset value, it is determined that the synchronization event instruction is executed.
[0083] The preset value can be 0, and when the synchronization event instruction is executed, a packet taking instruction can be generated to instruct to continue reading the initial data packets from the storage module for splitting and processing.
[0084] It should be noted that the identification generation system provided in Embodiment Two can be applied to Embodiment One to provide identification information for the read instruction in Embodiment One.
[0085] In Embodiment Two, the identification FIFO memory provides identification information for the read instruction, which can achieve the order preservation of the read results of multiple read instructions in a multiple read instruction concurrent scenario, and the identification information can be reused, so there is no need to set several bits in each read instruction as the identification information corresponding to the read instruction, which improves the convenience of generating the identification information of the read instruction and further improves the efficiency of data reading.
[0086] Although some specific embodiments of the present application have been described in detail by examples, those skilled in the art should understand that the above examples are only for illustration, not for limiting the scope of the present application. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present application. The scope of the present application is defined by the appended claims.
Claims
1. A data synchronization system based on event commands, characterized in that, The system includes: a storage module, a packet retrieval module, a data packet distribution module, firmware, M memory units, and M computing modules, wherein each memory unit corresponds to a computing module, and M is a positive integer; The packet retrieval module is used to read the initial data packet corresponding to the packet retrieval instruction from the storage module after receiving the packet retrieval instruction; The data packet distribution module is used to receive the initial data packet sent by the packet retrieval module, extract the target data packet from the initial data packet, and send the target data packet to the arbitrated memory; The memory is used to receive target data packets and send the received target data packets to the corresponding computing module; The calculation module is used to perform calculations on the received target data packets; The firmware is used to update the record value of the corresponding data packet processing record address in the storage module after the calculation and processing of any target data packet is completed; After receiving a synchronization event instruction for N initial data packets, the system simultaneously sends a read instruction to the corresponding data packet processing record address in the storage module for each of the N initial data packets. The read instruction includes identification information, where N is a positive integer. For any read instruction, the record value read back by the read instruction is written into the register corresponding to the identification information contained in the read instruction; If the record values in the registers corresponding to the initial data packet identifier information of the N initial data packets meet the preset conditions, then data synchronization is completed, and a new packet retrieval instruction is generated and sent to the packet retrieval module.
2. The data synchronization system based on event commands according to claim 1, characterized in that, The step of updating the record value of the corresponding data packet processing record address in the storage module after the calculation and processing of any target data packet is completed includes: After any target data packet has been processed, the record value of the corresponding data packet processing record address of the initial data packet to which the target data packet belongs in the storage module is decremented by one, thus completing the update of the record value.
3. The data synchronization system based on event commands according to claim 2, characterized in that, For any initial data packet, the record value corresponding to that initial data packet is initially the number of target data packets split from that initial data packet.
4. The data synchronization system based on event commands according to claim 1, characterized in that, The identification information includes the initial data packet identifier.
5. The data synchronization system based on event commands according to claim 4, characterized in that, The identification information also includes assembly line identification.
6. The data synchronization system based on event commands according to claim 1, characterized in that, The addresses of the registers corresponding to the initial data packet identifiers of the N initial data packets form an address range, and the address range corresponds to the read pointer, which initially points to the starting address of the address range; When the value of the record in the register pointed to by the read pointer is 0, the read pointer increments by 1; When the value of the read pointer is greater than the end address of the address range, the record values in the registers corresponding to the initial data packet identifier information of the N initial data packets are determined to satisfy the preset conditions.
7. The data synchronization system based on event commands according to claim 1, characterized in that, For any read command, if the record value read back by the read command is not 0, then a read command is sent again to the data packet processing record address corresponding to the read command.
8. The data synchronization system based on event commands according to claim 1, characterized in that, When the initial data packet to be read has a dependency relationship with the N initial data packets that have already been read, a synchronization event instruction to generate N initial data packets is sent to the system; Accordingly, if the record values in the registers corresponding to the initial data packet identifier information of the N initial data packets respectively meet the preset conditions, then data synchronization is completed, and a new packet retrieval instruction is generated and sent to the packet retrieval module, including: If the record values in the registers corresponding to the initial data packet identifier information of the N initial data packets meet the preset conditions, then data synchronization is completed, and a new packet retrieval instruction corresponding to the initial data packet to be read is generated and sent to the packet retrieval module.
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