Data transmission method and system, chip, electronic equipment and storage medium
By employing segmented transmission and hardware verification mechanisms in data transmission between graphics processors, the problems of transmission latency and consistency are solved, achieving efficient data transmission and interconnect bandwidth utilization, which is suitable for high-performance computing and deep learning scenarios.
Patent Information
- Application Number
- CN202511675969.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-13
- Publication Date
- 2026-02-10
AI Technical Summary
In high-performance computing and deep learning applications, high-speed interconnect technologies between graphics processors suffer from increased transmission latency and data consistency issues, leading to a sharp increase in logical resource overhead and becoming a bottleneck for improving interconnect bandwidth.
By receiving write request data and immediately returning a response without carrying a last refresh flag, the system verifies that all write request data has been correctly written to the target device's memory, ensuring data consistency. It employs a hardware mechanism to implement active reading and error correction functions, and a segmented transmission scheme reduces resource requirements.
It significantly improves the utilization of interconnect bandwidth and the reliability of data transmission, avoids data errors and system crashes, and enhances computing performance.
Smart Images
Figure CN121501533A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic communication technology, and in particular to a data transmission method, system, chip, electronic device and storage medium. Background Technology
[0002] In current high-performance computing (HPC) and deep learning applications, high-speed interconnect technology between graphics processing units (GPUs) has become crucial for improving computational efficiency. However, as scale increases, inter-device transmission latency continues to rise, especially during write operations. To ensure data consistency, a response cannot be returned until the write request has fully arrived at the target device's memory. This mechanism places extremely high demands on the outstanding transaction capacity of the initiating device, leading to a sharp increase in logical resource overhead and becoming a major bottleneck for further improving interconnect bandwidth.
[0003] In existing technologies, split transaction protocols (such as those used in USB 2.0) aim to alleviate bandwidth consumption issues between buses of different speeds by relaying takeover requests and releasing the bus early. However, the additional completion messages they introduce can actually reduce effective bandwidth in interconnects of devices with the same speed. On the other hand, the posted transmission mechanism of the Peripheral Component Interconnect Express (PCIe) can release upstream resources immediately after a write request is forwarded by the bridging device. While this helps improve effective bandwidth, it may cause data consistency issues because it does not guarantee that the data will actually be stored, making it unsuitable for GPU interconnect scenarios with strict consistency requirements. Summary of the Invention
[0004] In view of this, embodiments of this application provide a power supply circuit, power supply method, electronic device, and storage medium that can improve the utilization of interconnect bandwidth and ensure data consistency.
[0005] In a first aspect, embodiments of this application provide a data transmission method, comprising: receiving multiple write request data sent by a source device, and sending current write request data to a target device; in response to the current write request data not carrying a last refresh flag, returning a transmission response of the current write request data to the source device; in response to the write request data carrying a last refresh flag, verifying whether all sent write request data has been correctly written to the memory of the target device, and if all sent write request data has been correctly written to the memory of the target device, returning a transmission response of the current write request data carrying a last refresh flag to the source device.
[0006] According to a specific implementation of an embodiment of this application, verifying whether all sent pen-write request data has been correctly written to the memory of the target device includes: initiating a read operation request to the memory of the target device based on a pre-configured memory access address of the target device; if a valid response is received from all sent read operation requests, it is determined that all sent pen-write request data has been correctly written to the memory of the target device; wherein, the valid response is used to indicate that the previously written data has been successfully read from the memory of the target device; if at least one read operation request does not return a valid response, it is determined that the sent write request data has not been correctly written to the memory of the target device.
[0007] According to one specific implementation of the embodiments of this application, the pre-configured memory access address of the target device at least covers all memory channels of the target device.
[0008] According to a specific implementation of this application, after at least one read operation request fails to return a valid response, the step of verifying whether all written request data sent has been correctly written to the memory of the target device further includes: recording read operation exception information and sending the read operation exception information to the source device to trigger the source device to generate an error interrupt signal.
[0009] According to a specific implementation of an embodiment of this application, after returning a transmission response of the current pen-writing request data to the source device, the method further includes: releasing the transmission resources occupied by the current pen-writing request data via the source device based on the transmission response, and receiving another pen-writing request data transmitted by the source device.
[0010] Secondly, embodiments of this application provide a data transmission system, including: a receiving unit, configured to receive multiple write request data sent by a source device and send the current write request data to a target device; a first response unit, configured to return a transmission response of the current write request data to the source device in response to the current write request data not carrying a last refresh flag; and a second response unit, configured to verify whether all sent write request data has been correctly written to the memory of the target device in response to the write request data carrying a last refresh flag, and if all sent write request data has been correctly written to the memory of the target device, return a transmission response of the current write request data carrying a last refresh flag to the source device.
[0011] According to a specific implementation of an embodiment of this application, the second response unit includes: a request initiation module, configured to initiate a read operation request to the memory of the target device based on a pre-configured memory access address of the target device; a first determination module, configured to determine that all written request data has been correctly written to the memory of the target device if valid responses are received from all sent read operation requests; wherein the valid responses are used to indicate that previously written data has been successfully read from the memory of the target device; and a second determination module, configured to determine that written request data has not been correctly written to the memory of the target device if at least one read operation request has not returned a valid response.
[0012] According to one specific implementation of the embodiments of this application, the pre-configured memory access address of the target device at least covers all memory channels of the target device.
[0013] According to a specific implementation of an embodiment of this application, the second determining module is specifically used to: record read operation exception information and send the read operation exception information to the source device to trigger the source device to generate an error interrupt signal.
[0014] According to a specific implementation of an embodiment of this application, the first response unit is specifically used to: release the transmission resources occupied by the current pen-write request data via the source end according to the transmission response, and receive another pen-write request data transmitted by the source end device.
[0015] Thirdly, embodiments of this application provide a chip, the chip comprising: a source device configured to send multiple write request data to a switching device; a switching device configured to receive the multiple write request data sent by the source device and send the current write request data to a target device; in response to the current write request data not carrying a last refresh flag, returning a transmission response of the current write request data to the source device; in response to the write request data carrying a last refresh flag, verifying whether all sent write request data has been correctly written to the memory of the target device, and if all sent write request data has been correctly written to the memory of the target device, returning a transmission response of the current write request data carrying a last refresh flag to the source device; and a target device configured to receive the multiple write request data sent by the switching device, store the data content corresponding to the write request data in a write cache; receive a read request from the switching device, and return a read response to the switching device in response to the read request, wherein the read request points to one or more pre-configured memory access addresses.
[0016] Fourthly, embodiments of this application provide an electronic device, which includes: a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed inside the space enclosed by the housing, and the processor and the memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the data transmission method provided in any embodiment of this application.
[0017] Fifthly, embodiments of this application provide a computer-readable storage medium storing one or more computer programs, which, when executed by one or more processors, implement the data transmission method described in any of the first aspects. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 A flowchart illustrating the data transmission method provided in an embodiment of this application; Figure 2 This is a schematic diagram of data transmission provided in an embodiment of this application; Figure 3 This is a schematic diagram of the address bus and data bus during data transmission provided in an embodiment of this application; Figure 4 This is a schematic diagram of the operation flow of the refresh control module provided in an embodiment of this application; Figure 5 Another schematic diagram illustrating data transmission provided in an embodiment of this application; Figure 6 A schematic diagram of the structure of a data transmission system provided in an embodiment of this application; Figure 7 This is a schematic diagram of an electronic device provided in an embodiment of this application. Detailed Implementation
[0020] The embodiments of this application will now be described in detail with reference to the accompanying drawings.
[0021] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.
[0022] Firstly, embodiments of this application provide a data transmission method that can improve the utilization of interconnect bandwidth and ensure data consistency.
[0023] like Figure 1 As shown, an embodiment of this application provides a data transmission method, including: S11. Receive multiple write request data sent by the source device, and send the current write request data to the target device; In modern data centers, high-performance computing, and artificial intelligence accelerators, different hardware devices need to be interconnected at high speeds to transmit massive amounts of data.
[0024] Figure 2 This is a schematic diagram of data transmission provided in an embodiment of this application. See also: Figure 2 During data transmission, the core process of receiving and identifying write request data is collaboratively completed by the on-chip network (XBAR) located at the center of the switch and the control logic of its various ports. When a transmission task is initiated, it is broken down into multiple data bus-level transmissions. During system initialization, the addresses in each port of the switch need to be pre-configured. In some examples, the corresponding memory access addresses are set according to the memory characteristics of the devices connected to each port. After configuring the corresponding memory access addresses, the master device inside the source device (Device A) initiates multiple write requests, sequentially writing the split data from address A0 to An. Figure 3 This is a schematic diagram of the address bus and data bus during data transmission, such as... Figure 3 The last transmission contains two data sets, Dn0 and Dn1. When sending data between D00 and Dn0, the source device does not perform a Last Flush on these data sets, treating them as normal transmission requests. Next, the data first enters the ingress port of the source device connected to the switching equipment via the physical link. The physical layer (PHY) chip within the port receives the bit stream, performs clock recovery and serial-to-parallel conversion, forming digital data packets. Subsequently, the link layer logic performs error checking and sequence checks to ensure data integrity.
[0025] Then, the data packet is passed to the transaction layer of the port, where key information is parsed. This key information includes the destination address, transaction type, and last refresh flag. After parsing, the data packet is sent to the central on-chip network via the internal interface of the switching device according to the destination address. The on-chip network then sends the data packet to the output port of the target device according to the address information. In some examples, just before the data packet is sent from the output port, the built-in refresh control module of the output port is activated to check the data packet and obtain all necessary information, including the flag status of the last refresh flag. Figure 4 This is a schematic diagram of the operation flow of the refresh control module provided in an embodiment of this application. See also: Figure 4 After a write request arrives at the refresh control module, the combinational logic circuit or state machine inside the refresh control module directly detects the last refresh flag bit in the data packet header and makes a real-time judgment on the currently processed data packet in each clock cycle, and determines the subsequent processing flow based on the status of the flag bit.
[0026] S12. In response to the fact that the current pen writing request data does not carry the last refresh mark, return the transmission response of the current pen writing request data to the source device; When the refresh control module detects that the current pen writing request data does not carry the last refresh marker, such as Figure 4 First, the data transmission operation is executed. Specifically, the refresh control module's control logic does not intercept or specially process data packets. Instead, based on the destination address of the data packet, it accurately forwards the packet to the final target device through the on-chip network within the switching chip, ensuring rapid data delivery. Then, simultaneously with data transmission, the refresh control module, in conjunction with the internal response generation unit, immediately simulates and generates a write response signal indicating successful transmission. This signal is then returned along the original path to the master control device of the source device. The write response signal does not originate from the target device but is a pre-acknowledgment mechanism generated locally within the switching chip, designed to significantly reduce response latency. By returning a response in advance for the current write request, the sending capacity of the source device is greatly released, enabling high-concurrency transmission and significantly improving the utilization of interconnect bandwidth.
[0027] S13. In response to the write request data carrying the last refresh flag, verify whether all the pen write request data sent has been correctly written to the memory of the target device. If all the pen write request data sent has been correctly written to the memory of the target device, return a transmission response carrying the last refresh flag of the current pen write request data to the source device.
[0028] When the refresh control module detects that the write request data carries the last refresh flag, see [link / reference]. Figure 4First, the final write data is sent to the target device to ensure that all data from this transmission task has reached the target device's memory subsystem. Then, the cached data is flushed into memory. Specifically, the flush control module does not immediately return a response; instead, it automatically initiates a series of read requests based on internally pre-configured flush address units. In some cases, by reading specific addresses, it forces the target device's memory controller to completely flush all previously cached and queued write operations into the memory chips, thus ensuring that the data is immediately visible for subsequent accesses. Flushing the cached data into memory ensures strong data consistency, allowing upper-layer software to safely rely on the data state upon task completion.
[0029] After automatically initiating a series of read requests, the refresh control module waits for read responses. Each read response represents the completion of all previous write operations in the corresponding memory channel. Only when all read responses return successfully does the refresh control module finally determine that all sent data has been correctly written to memory and that data consistency has been guaranteed. At this point, if... Figure 4 As shown, the refresh control module generates a transmission success response for the last write request and returns it to the master control device of the source device. The master control device of the source device confirms that the entire batch transmission task has been completed and the data is consistent and reliable based on the transmission success response for the last write request. It then terminates the task, releases resources, and notifies the upper-layer software that the data is ready. The entire data transmission process is implemented in hardware, with no software overhead. Consistency assurance is achieved in parallel by a dedicated module, resulting in lower latency and higher efficiency compared to software refresh methods, significantly improving overall system performance.
[0030] By breaking down the challenge of balancing bandwidth and consistency into two stages and marking only the last piece of data, it achieves both high bandwidth and high reliability at minimal cost. This makes it ideal for scenarios with extremely high requirements for data transmission performance and data consistency, such as high-speed interconnect fields like AI accelerator cards, high-performance computing (HPC) chips, and smart network cards.
[0031] This application provides a data transmission method that receives multiple write request data from a source device and sends the current write request data to a target device. In response to the current write request data not carrying a last refresh flag, a transmission response for the current write request data is returned to the source device. By returning a response immediately after transmission, rather than waiting for the data to be actually written to the target device's memory, the response time for each write request is significantly shortened. This allows the source device to issue more requests in the same amount of time without waiting for preceding requests to complete, thereby improving the utilization of interconnect bandwidth. In response to the write request data carrying a last refresh flag, the method verifies whether all sent write request data has been correctly written to the target device's memory. This ensures that all sent write request data is persistently stored by the target device before notifying the source device of the completion of the entire data transmission. This prevents upper-layer software from reading data that has not yet been written to disk upon receiving a completion signal, thus avoiding data errors and system crashes, and ensuring the correctness and reliability of calculations. If all the pen write request data sent has been correctly written to the memory of the target device, a transmission response carrying the last refresh mark of the current pen write request data is returned to the source device. In this way, for requests carrying special marks, a verification process is triggered to ensure that all data has been correctly written to disk before returning the final response, thereby strictly ensuring data consistency and avoiding data errors that may be caused by premature release of resources.
[0032] In some embodiments, verifying whether all sent pen-write request data has been correctly written to the memory of the target device includes: initiating a read operation request to the memory of the target device based on a pre-configured memory access address of the target device; if a valid response is received from all sent read operation requests, it is determined that all sent pen-write request data has been correctly written to the memory of the target device; wherein the valid response is used to indicate that the previously written data has been successfully read from the memory of the target device; if at least one read operation request does not return a valid response, it is determined that the sent write request data has not been correctly written to the memory of the target device.
[0033] This application embodiment verifies whether all previous write operations have been completed by actively reading the target device's memory. Specifically, the refresh control module automatically initiates a series of read operation requests to the target device's memory based on the address list configured during initialization. The response of the read requests is used to determine whether all write data has been correctly written to memory. If all read requests return valid responses, then based on the strictly ordered nature of memory access, it is determined that all write data has been correctly written to memory. The strictly ordered nature of memory access means that the memory controller must complete all previous write operations on the same address range before processing a new read request. Conversely, if any read request does not return a valid response, such as timeout, error, or no response, it indicates that there is a consistency defect or transmission failure in the corresponding memory channel or region, and it can be determined that some write data has not been correctly written.
[0034] It implements proactive verification and forced sorting through hardware mechanisms, and efficiently detects the write completion status through read operations, which not only ensures global data consistency, but also has error correction capabilities, thereby providing eventual consistency guarantee for large-scale data migration.
[0035] In some embodiments, the pre-configured memory access addresses of the target device cover at least all memory channels of the target device.
[0036] During data transmission, the memory access addresses pre-configured for the refresh control module must evenly cover all memory channels of the target device. This is the core mechanism to ensure comprehensive and reliable data consistency verification. Modern high-performance devices typically employ a multi-channel memory architecture, with each channel having an independent memory controller, I / O interface, and write cache, enabling parallel data processing. Data transmitted from the source device is automatically distributed across channels for writing to improve bandwidth; however, data may be temporarily stored in channel caches without being persisted. If the memory access addresses do not fully cover all channels, verification can only confirm that data from some channels has been written to disk. Unrefreshed data in the caches of other channels will cause errors when read by the software.
[0037] Therefore, during initialization, the driver or firmware needs to configure a set of addresses mapped to all channels for the refresh control module based on the target device's memory topology. For example, a 32-channel High Bandwidth Memory (HBM) requires 32 addresses belonging to different channels. During verification, the refresh control module initiates read requests to these addresses, which is equivalent to issuing commands to all channel controllers, requesting them to complete temporary write operations and return data. This achieves synchronous flushing and status confirmation for each channel, ensuring the comprehensiveness of verification, the global consistency of data, and the overall reliability of the mechanism. This allows performance optimization to be built on a strict consistency foundation and serves as a key bridge in transforming abstract consistency semantics into a hardware-implementable solution.
[0038] In some embodiments, after at least one read operation request fails to return a valid response, verifying whether all written request data sent has been correctly written to the memory of the target device further includes: recording read operation exception information and sending the read operation exception information to the source device to trigger the source device to generate an error interrupt signal.
[0039] When the refresh control module detects that at least one read operation request has not returned a valid response during the consistency verification process, in addition to determining that the data has not been written correctly, it also needs to execute a complete error handling process.
[0040] First, the refresh control module records the exception information, including the error type, faulty memory address, timestamp, and related transaction ID, and temporarily stores it in a dedicated register or storage area. In some cases, the error type includes timeout, checksum error, or device error response. Then, the refresh control module encapsulates this exception information into an exception response for the last write request and sends it back to the source device.
[0041] After receiving an abnormal response, the master control device of the source device parses the error content and generates a hardware error interrupt signal. The hardware error interrupt signal triggers the central processing unit (CPU) to execute a preset interrupt service routine. By reading detailed error information, it then performs operations such as system log recording, terminating the current task, reporting application layer transmission failure, or starting a recovery mechanism.
[0042] By constructing a complete error path from hardware detection to software response, the risk of silent data corruption is avoided. Furthermore, by providing accurate fault information, the system's diagnosability is greatly enhanced, ensuring reliable collaboration between hardware and software. This enables the entire high-performance transmission solution to improve efficiency while possessing comprehensive error detection and processing capabilities.
[0043] In some embodiments, after returning a transmission response of the current pen-writing request data to the source device, the method further includes: releasing the transmission resources occupied by the current pen-writing request data via the source device according to the transmission response, and receiving another pen-writing request data transmitted by the source device.
[0044] After the refresh control module returns the transmission response of the current pen writing request data to the source device, the source device will immediately perform subsequent critical operations to maintain high-throughput data transmission.
[0045] Specifically, first, the various transmission resources occupied by the current request are released, including buffers for storing data and metadata, credits used for flow control, and slots in the packet queue, providing the necessary resource space for subsequent requests. Then, the next write request data is retrieved from its pending queue and immediately sent out through the interconnect link. This continuous operation allows the data stream to be seamlessly connected, continuously injecting into the transmission pipeline, thus forming a continuous high-speed data stream on a macroscopic level, rather than an isolated single request.
[0046] By rapidly releasing resources and immediately sending new requests in a local loop, a large number of requests are kept in transit simultaneously. While this does not reduce the transmission latency of a single request, it significantly increases the number of requests completed per unit time, effectively hiding transmission latency. This constitutes a pipeline mechanism that achieves high concurrency and high bandwidth utilization. Overall, it establishes a continuous loop of releasing resources and sending new requests for the high-speed data transmission engine, ensuring uninterrupted data flow and fully utilizing the available bandwidth of the interconnect links.
[0047] In some cases, the switching device can be responsible for the rapid response of the vast majority of data to maximize performance, while the master device of the source device is responsible for ensuring the consistency of the last piece of data, thereby reducing the implementation complexity of the switching device.
[0048] Figure 5 See another schematic diagram of data transmission provided in the embodiments of this application. Figure 5 For ordinary data, a segmented transmission model is adopted. After the Master at the source device sends a write request to the switching device, the switching device immediately returns a response upon receiving the routing request, rather than waiting for the data to be completely written to the target device's memory. The response prompts the Master to quickly release resources such as buffers, credits, and queue slots, thereby continuously initiating subsequent requests, ensuring efficient filling of the transmission pipeline and maximizing the utilization of interconnect bandwidth. Then, the last piece of data is processed. After issuing the last write request, the Master autonomously initiates a read request to the target device's memory that covers the entire memory channel. By forcibly reading, the cached data in the target device's memory controller is flushed. Only after all read requests have been successfully responded to is the entire transmission task confirmed as truly complete, and the upper-layer software is notified.
[0049] pass Figure 5The data transmission process shown simplifies the design of switching equipment. It only requires the switching equipment to implement request forwarding and fast response functions, eliminating the need to integrate complex consistency verification logic. A flush initiation and collaborative waiting mechanism is added to the Master side. This achieves a balance between the complexity of the switching chip and the intelligence of the endpoint devices, making it suitable for application scenarios that prioritize a simple switching equipment structure and where the endpoint control devices have a certain degree of functional expansion capabilities.
[0050] Secondly, embodiments of this application provide a data transmission system that can improve the utilization of interconnect bandwidth and ensure data consistency.
[0051] like Figure 6 As shown, embodiments of this application also provide a data transmission system, including: a receiving unit 31, a first response unit 32, and a second response unit 33.
[0052] The receiving unit 31 is used to receive multiple write request data sent by the source device and send the current write request data to the target device. The first response unit 32 is used to return a transmission response of the current pen writing request data to the source device in response to the fact that the current pen writing request data does not carry the last refresh mark. The second response unit 33 is used to respond to the write request data carrying the last refresh mark, verify whether all the pen write request data that has been sent has been correctly written into the memory of the target device, and if it is verified that all the pen write request data that has been sent has been correctly written into the memory of the target device, then return a transmission response carrying the last refresh mark of the current pen write request data to the source device.
[0053] This application provides a data transmission system that receives multiple write request data from a source device and sends the current write request data to a target device. In response to the current write request data not carrying a last refresh flag, the system returns a transmission response to the source device. By returning a response immediately after transmission, rather than waiting for the data to be actually written to the target device's memory, the response time for each write request is significantly shortened. This allows the source device to issue more requests within the same timeframe without waiting for preceding requests to complete, thereby improving the utilization of interconnect bandwidth. In response to the write request data carrying a last refresh flag, the system verifies whether all sent write request data has been correctly written to the target device's memory. This ensures that all sent write request data is persistently stored by the target device before notifying the source device of the entire data transmission completion. This prevents upper-layer software from reading data that has not yet been written to disk upon receiving a completion signal, thus avoiding data errors and system crashes, and ensuring the correctness and reliability of calculations. If all the pen write request data sent has been correctly written to the memory of the target device, a transmission response carrying the last refresh mark of the current pen write request data is returned to the source device. In this way, for requests carrying special marks, a verification process is triggered to ensure that all data has been correctly written to disk before returning the final response, thereby strictly ensuring data consistency and avoiding data errors that may be caused by premature release of resources.
[0054] In some embodiments, the second response unit includes: a request initiation module, configured to initiate a read operation request to the memory of the target device based on a pre-configured memory access address of the target device; a first determination module, configured to determine that all written request data has been correctly written to the memory of the target device if a valid response is received from all sent read operation requests; wherein the valid response is used to indicate that previously written data has been successfully read from the memory of the target device; and a second determination module, configured to determine that written request data has not been correctly written to the memory of the target device if at least one read operation request has not returned a valid response.
[0055] In some embodiments, the pre-configured memory access addresses of the target device cover at least all memory channels of the target device.
[0056] In some embodiments, the second determining module is specifically used to: record read operation exception information and send the read operation exception information to the source device to trigger the source device to generate an error interrupt signal.
[0057] In some embodiments, the first response unit is specifically configured to: release the transmission resources occupied by the current pen write request data via the source end according to the transmission response, and receive another pen write request data transmitted by the source end device.
[0058] Thirdly, embodiments of this application also provide a chip that can improve the utilization of interconnect bandwidth and ensure data consistency.
[0059] The chip provided in the embodiments of this application includes: a source device configured to send multiple write request data to a switching device; a switching device configured to receive the multiple write request data sent by the source device and send the current write request data to a target device; in response to the current write request data not carrying a last refresh flag, returning a transmission response of the current write request data to the source device; in response to the write request data carrying a last refresh flag, verifying whether all sent write request data has been correctly written to the memory of the target device, and if all sent write request data has been correctly written to the memory of the target device, returning a transmission response of the current write request data carrying a last refresh flag to the source device; and a target device configured to receive the multiple write request data sent by the switching device, store the data content corresponding to the write request data in a write cache; receive a read request from the switching device, and return a read response to the switching device in response to the read request, wherein the read request points to one or more pre-configured memory access addresses.
[0060] Fourthly, embodiments of this application also provide an electronic device that can improve the utilization of interconnect bandwidth and ensure data consistency.
[0061] like Figure 7 As shown, the electronic device provided in the embodiments of this application may include: a housing 51, a processor 52, a memory 53, a circuit board 54, and a power supply circuit 55, wherein the circuit board 54 is disposed inside the space enclosed by the housing 51, and the processor 52 and the memory 53 are disposed on the circuit board 54; the power supply circuit 55 is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory 53 is used to store executable program code; the processor 52 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 53, for executing the data transmission method provided in any of the foregoing embodiments.
[0062] For details on the specific execution process of the above steps by the processor 52 and the steps further executed by the processor 52 by running executable program code, please refer to the description of the foregoing embodiments, which will not be repeated here.
[0063] Fifthly, embodiments of this application also provide a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement any of the data transmission methods provided in the foregoing embodiments, thus achieving the corresponding technical effects. This has been described in detail above and will not be repeated here.
[0064] This application's solution employs a segmented transmission scheme at the end of the interconnection link, splitting end-to-end transmission into two segments: device-to-switching chip and switching chip-to-target device. This significantly reduces the resource requirements of the source device for outstanding capabilities, thereby effectively increasing the actual available bandwidth of the interconnection between devices. Secondly, it introduces a LastFlush mechanism for the last write operation, with the underlying hardware autonomously ensuring data consistency, avoiding the introduction of complex software co-design and improving the overall efficiency of hardware and software. It also has strong compatibility with different devices, eliminating the need to reserve specific memory address space, simplifying memory management and avoiding the system complexity caused by memory management.
[0065] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0066] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.
[0067] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.
[0068] For ease of description, the above apparatus is described by dividing it into various functional units / modules. Of course, in implementing this application, the functions of each unit / module can be implemented in one or more software and / or hardware.
[0069] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.
[0070] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A data transmission method, characterized in that, include: Receive multiple write request data sent by the source device, and send the current write request data to the target device; In response to the fact that the current pen writing request data does not carry a last refresh marker, a transmission response for the current pen writing request data is returned to the source device; In response to the write request data carrying a last refresh flag, verify whether all sent pen write request data has been correctly written to the memory of the target device. If all sent pen write request data has been correctly written to the memory of the target device, return a transmission response carrying the last refresh flag of the current pen write request data to the source device.
2. The data transmission method according to claim 1, characterized in that, The verification of whether all sent pen write request data has been correctly written to the target device's memory includes: Based on the pre-configured memory access address of the target device, a read operation request is initiated on the memory of the target device. If a valid response is received from all sent read operation requests, it is determined that all sent pen write request data has been correctly written to the memory of the target device; wherein, the valid response is used to indicate that the previously written data has been successfully read from the memory of the target device; If at least one read operation request does not return a valid response, it is determined that the data sent for the write request was not correctly written to the memory of the target device.
3. The data transmission method according to claim 2, characterized in that, The pre-configured memory access addresses of the target device at least cover all memory channels of the target device.
4. The data transmission method according to claim 2, characterized in that, If at least one read operation request fails to return a valid response, the verification of whether all written request data sent has been correctly written to the memory of the target device further includes: recording read operation exception information and sending the read operation exception information to the source device to trigger the source device to generate an error interrupt signal.
5. The data transmission method according to claim 1, characterized in that, After returning a transmission response of the current pen-writing request data to the source device, the method further includes: releasing the transmission resources occupied by the current pen-writing request data via the source device according to the transmission response, and receiving another pen-writing request data transmitted by the source device.
6. A data transmission system, characterized in that, include: The receiving unit is used to receive multiple write request data sent by the source device and send the current write request data to the target device. The first response unit is used to return a transmission response of the current pen writing request data to the source device in response to the fact that the current pen writing request data does not carry the last refresh mark. The second response unit is used to respond to the write request data carrying the last refresh flag, verify whether all the pen write request data that has been sent has been correctly written to the memory of the target device, and if all the pen write request data that has been sent has been correctly written to the memory of the target device, then return a transmission response carrying the last refresh flag of the current pen write request data to the source device.
7. The data transmission system according to claim 6, characterized in that, The second response unit includes: The request initiation module is used to initiate a read operation request to the memory of the target device based on the pre-configured memory access address of the target device. The first determining module is configured to determine, if a valid response is received from all sent read operation requests, that all sent pen write request data has been correctly written to the memory of the target device; wherein, the valid response is used to indicate that the previously written data has been successfully read from the memory of the target device; The second determining module is used to determine that the sent write request data has not been correctly written to the memory of the target device if at least one read operation request has not returned a valid response.
8. The data transmission system according to claim 7, characterized in that, The pre-configured memory access addresses of the target device at least cover all memory channels of the target device.
9. The data transmission system according to claim 7, characterized in that, The second determining module is specifically used to: record read operation exception information and send the read operation exception information to the source device to trigger the source device to generate an error interrupt signal.
10. The data transmission system according to claim 6, characterized in that, The first response unit is specifically used to: release the transmission resources occupied by the current pen write request data via the source end according to the transmission response, and receive another pen write request data transmitted by the source end device.
11. A chip, characterized in that, include: The source device is configured to send multiple write request data to the switching device; A switching device is configured to receive multiple write request data sent by a source device and send the current write request data to a target device; in response to the current write request data not carrying a last refresh flag, it returns a transmission response of the current write request data to the source device; in response to the write request data carrying a last refresh flag, it verifies whether all the written request data sent has been correctly written to the memory of the target device, and if all the written request data sent has been correctly written to the memory of the target device, it returns a transmission response of the current write request data carrying a last refresh flag to the source device. The target device is configured to receive multiple write request data sent by the switching device and store the data content corresponding to the write request data into the write cache. The system receives a read request from the switching device and, in response to the read request, returns a read response to the switching device. The read request points to one or more pre-configured memory access addresses.
12. An electronic device, characterized in that, The electronic device includes: a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed inside the space enclosed by the housing, and the processor and the memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the data transmission method of any one of claims 1 to 5.
13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the data transmission method of any one of claims 1 to 5.