Board card test system, test method and computing device

Abstract

The embodiment of the invention provides a board card test system, a test method and computing equipment. Comprising a to-be-tested board card which comprises a first programmable logic controller, and the first programmable logic controller is provided with a first pin; the first programmable logic controller comprises a plurality of second pins, and after the first programmable logic controller enters a test state, the plurality of second pins are used for sending a test code stream; the test code stream is used for determining a to-be-tested signal path after entering a test state; the test card is connected with the to-be-tested board card and comprises a second programmable logic controller, and the second programmable logic controller is used for receiving the test code stream, determining a to-be-tested signal channel based on the test code stream, executing test operation on the to-be-tested signal channel, collecting signal level changes on the to-be-tested signal channel and sending the signal level changes to the to-be-tested board card. Therefore, whether the to-be-detected signal channel is normal is determined. In the unified test state, the to-be-tested signal path is detected, so that the test efficiency can be effectively improved.

Description

Technical Field

[0001] This application relates to the field of circuit board testing, and more particularly to a circuit board testing system, testing method, and computing device. Background Technology

[0002] Computing devices typically consist of various functional boards, such as motherboards and hard drive backplanes. These boards usually integrate numerous components, including control units, complex programmable logic devices (CPLDs), and connectors. Communication and interaction with external components are achieved through multiple connectors. In computing devices, the control units on the boards act as auxiliary control centers, controlling power timing, forwarding key signals, and other functions. To achieve these functions, the pins of the control units must be routed through a printed circuit board (PCB) to establish a one-to-one electrical connection with specific pins on the connectors, forming a physical signal path from the connector to the control unit.

[0003] During the manufacturing process of computer motherboards, the large number of connector pins and the multiple processes involved in assembly, such as dense layout, reflow soldering, manual component insertion, and final assembly, make them highly susceptible to process defects, such as short circuits. Therefore, it is necessary to test the connectivity of the entire path from "control unit pins → traces → connector pins" to ensure the board functions properly.

[0004] Existing solutions configure corresponding test strategies based on the predefined functions of different connector pins, and then perform corresponding tests according to the test strategies. The above method requires analyzing each connector pin and control unit pin one by one to generate a test strategy. Since the test strategies for different pins are independent of each other, the test configuration process is cumbersome and labor-intensive, resulting in low test efficiency. Summary of the Invention

[0005] This application provides a test method, test system, and computing device for circuit boards. By setting control points on the circuit board and constructing a unified test state to test the path of the signal to be tested, the test efficiency can be effectively improved.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] In a first aspect, embodiments of this application provide a board testing system, comprising: a board to be tested, including a first programmable logic controller (PLC), the first PLC having a first pin for receiving an enable signal, the enable signal being used to control the first PLC to enter a test state; the first PLC including a plurality of second pins, the plurality of second pins being used to emit a test code stream after entering the test state; the test code stream being used to determine a signal path to be tested after entering the test state; and a test card connected to the board to be tested, the test card including a second PLC, the second PLC being used to receive the test code stream, determine the signal path to be tested based on the test code stream, apply test operations to the signal path to be tested, and collect signal level changes on the signal path to be tested to determine whether the signal path to be tested is normal.

[0008] Based on this solution, the board testing system provided in this application, when the first programmable logic controller (PLC) is in test mode, achieves test stream generation and parsing through the coordinated operation of the first and second PLCs, thereby accurately locating signal paths and accurately acquiring the level changes of each node. This eliminates the need to design differentiated test procedures for different types of pins; all signal paths can be tested under a unified test state, effectively simplifying the test logic, reducing test complexity, improving test efficiency, and ensuring complete coverage of all signal paths, thus enhancing the comprehensiveness of the test.

[0009] In one possible implementation, the system further includes: a test fixture; the test fixture includes a test probe and a test station; one end of the test probe is electrically connected to the board under test, and the other end of the test probe is fixed to the test fixture and grounded; the board under test and the test card are detachably installed in the test station; the test probe is used to drive the signal level of the first pin to a first preset level when the board under test is installed in place, so as to provide an enable signal to the first pin; and a first programmable logic controller is used to determine that the test card has entered the test state when the signal level of the first pin is detected to be the first preset level.

[0010] Based on this solution, by setting up a test fixture, the test probe automatically drives the level of the first pin of the board under test to a first preset level when it is installed at the test station, thereby providing the enable signal required for the first programmable logic controller (PLC) to enter the test state. In this way, the test start condition is automatically triggered without the need for additional external control signals or manual operation. When the first PLC detects that the level of the first pin has reached the first preset level, it automatically switches to the test state, simplifying the testing process and improving operational convenience.

[0011] In one possible implementation, the board under test further includes a first bias resistor and a control point; the control point is electrically connected to a first pin; a first end of the first bias resistor is electrically connected to the control point; a second end of the first bias resistor is connected to a power supply voltage; the first bias resistor drives the level of the control point to a first preset level when the control point is electrically connected to the test probe, thereby triggering the first programmable logic controller to enter the test state; when the control point is not electrically connected to the test probe, it establishes a second preset level for the control point, thereby enabling the first programmable logic controller to operate.

[0012] Based on this solution, reliable switching between test and normal operating states is achieved by setting a first bias resistor and a control point on the board under test. Specifically, when the board under test is installed in the test fixture, the control point is connected to the power supply voltage through the test probe. The first bias resistor pulls the control point level up to a first preset level, triggering the first programmable logic controller (PLC) to enter the test state. When not under test, the control point is left floating, and the first bias resistor maintains it at a second preset level, ensuring normal operation of the controller. In this way, automatic switching between test and operating states is achieved using a simple bias resistor, eliminating the need for additional control signals and avoiding malfunctions caused by floating pins, thus ensuring system reliability.

[0013] In one possible implementation, the board under test (DUT) further includes an external connector, which includes multiple first pins. Multiple second pins of a first programmable logic controller (PLC) are connected via traces to form multiple signal paths with their corresponding first pins on the external connector. In test mode, the first PLC outputs a test code stream through these signal paths. The test code stream includes a synchronization signal and target pin information. The synchronization signal indicates the start position of the test code stream, and the target pin information is transmitted following the synchronization signal. A second PLC parses the synchronization signal, performs timing synchronization between the DUT and the test card, and parses the target pin information to determine the signal path under test from the multiple signal paths.

[0014] Based on this scheme, in the test state, the first programmable logic controller (PLC) outputs a test code stream containing synchronization signals and target pin information via a signal path, achieving self-synchronization and path identification during the test process. The second PLC parses this information to accurately identify the signal path under test, and then performs targeted level acquisition and path verification. In this way, no external configuration or prior knowledge of the path sequence is required; the test information is embedded in the code stream, improving the automation and reliability of the test.

[0015] In one possible implementation, a first programmable logic controller (PLC) is used to send a synchronization signal to a second PLC; encode the pin information of a target pin based on a preset data frame format to obtain target pin information; and send the target pin information to the second PLC; wherein the target pin information is an encoded signal of a logic identifier; the second PLC is specifically used to determine the timing synchronization between the test card and the board under test based on the synchronization signal; after determining the timing synchronization, parse the encoded signal to determine the signal path under test; apply a test operation to the signal path under test, and collect the signal level changes on the signal path under test to determine whether the signal path under test is normal.

[0016] Based on this scheme, the first programmable logic controller encodes the data according to a preset data frame format, and sends the encoded logic identifier signal as the target pin information along with the synchronization signal to the test card. The second programmable logic controller aligns with the timing of the board under test based on the synchronization signal, then parses the encoded signal, identifies the target pin and the signal path under test, and judges whether its connectivity and electrical performance are normal by collecting level changes. In this way, through standardized data frame format and encoded transmission, reliable transmission and accurate parsing of test information are achieved without manual intervention or fixed test order, which can improve the reliability of information in the communication transmission process.

[0017] In one possible implementation, a first programmable logic controller (PLC) is used to send a synchronization signal to a second PLC; acquire the time-domain waveform corresponding to the target pin; determine the target pin information based on the time-domain waveform and a preset time-domain waveform; and send the target pin information to the second PLC. The target pin information is a physical waveform signal. The second PLC is specifically used to determine the timing synchronization between the test card and the board under test based on the synchronization signal; after determining the timing synchronization, parse the physical waveform signal to determine the signal path under test; apply a test operation to the signal path under test and collect the signal level changes on the signal path under test to determine whether the signal path under test is normal.

[0018] Based on this scheme, the first programmable logic controller (PLC) sends a synchronization signal to achieve timing alignment, and generates a physical waveform signal as pin information based on the time-domain waveform of the target pin and a preset waveform, and sends it. The second PLC, after synchronization, analyzes this physical waveform, identifies the path of the signal under test, and determines its connectivity and electrical performance by acquiring level changes. In this way, the physical waveform carries the pin information without the need for additional data encoding protocols, ensuring reliable transmission and accurate analysis of test information. It also eliminates the need for manual intervention or fixed test sequences, improving the reliability of information during communication transmission.

[0019] In one possible implementation, the second programmable logic controller is specifically configured to: determine the target pin of the external connector based on the target pin information and a preset connector pin mapping table; acquire the signal path under test between the target pin and the target pin; apply a test operation to the signal path under test and collect the signal level changes on the signal path under test to determine whether the signal path under test is normal; wherein, the test operation includes at least one of pull-up operation, pull-down operation, and no pull-up or pull-down operation.

[0020] Based on this scheme, the second programmable logic controller (PLC) determines the target pin according to the target pin information and a preset mapping table, obtains the corresponding signal path to be tested, and excites the path through pull-up, pull-down, or no pull-up / pull-down operation, and collects level changes to determine whether its connectivity and electrical performance are normal. In this way, the mapping table enables precise positioning of pin information to physical paths, supports various electrical condition tests, improves the accuracy and coverage of the test, and can effectively detect typical faults such as open circuits, short circuits, and impedance abnormalities.

[0021] Secondly, embodiments of this application also provide a testing method for a circuit board, applied to a circuit board under test, the circuit board under test including a first programmable logic controller (PLC). The method includes: detecting the operating state of the first PLC on the circuit board under test; when the operating state of the first PLC is a test state, sending a synchronization signal to a test card; sending target pin information to the test card so that the test card determines the signal path under test corresponding to the target pin information; applying a test operation to the signal path under test, and judging whether the signal path under test on the circuit board under test is normal based on the test results.

[0022] Based on this solution, by detecting the operating status of the first programmable logic controller on the board under test, the test process is initiated only when it enters the test state, ensuring the accuracy and safety of the test timing. In this way, a unified test state can be used to test the signal paths corresponding to different target pins without distinguishing between target pin types, thus improving test efficiency and ensuring the completeness of test coverage.

[0023] Thirdly, embodiments of this application also provide a testing method for a circuit board, applied to a test card, the test card including a second programmable logic controller (PLC). The method includes: receiving a synchronization signal sent by a first PLC on the circuit board under test, and determining the timing synchronization between the test card and the circuit board under test based on the synchronization signal; receiving target pin information sent by the first PLC, and determining the test signal path corresponding to the target pin information; performing a preset level operation on the test signal path to obtain the test result of the test signal path; and determining whether the test signal path of the circuit board under test is in a normal state based on the test result.

[0024] Based on this solution, the test card receives a synchronization signal through a second programmable logic controller (PLC) to achieve timing synchronization with the board under test (BUT). It receives target pin information, determines the signal path under test, applies preset level operations such as pull-up and pull-down, and collects response levels to determine if the path is normal. This allows for testing of different target pin-corresponding signal paths using a unified test state, eliminating the need to distinguish between target pin types. This improves testing efficiency and ensures complete test coverage.

[0025] Fourthly, embodiments of this application also provide a computing device, including: a processor and a memory; the processor and the memory are coupled; the memory is used to store program instructions; the processor is used to execute the program instructions to perform the method as described in any one of the second and third aspects above.

[0026] Fifthly, embodiments of this application provide a chip for performing the methods described in any one of the second and third aspects above.

[0027] In a sixth aspect, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a computer, implement the method as described in any one of the second and third aspects.

[0028] In a seventh aspect, embodiments of this application provide a program product including a computer program that, when executed by a processor, implements the method as described in any one of the second and third aspects. Attached Figure Description

[0029] Figure 1 This is a hardware schematic diagram of a computing device provided in an embodiment of this application;

[0030] Figure 2 This is a first structural schematic diagram of a board testing system provided in an embodiment of this application;

[0031] Figure 3 This is a three-dimensional structural schematic diagram of a board testing system provided in an embodiment of this application;

[0032] Figure 4 This is a second structural schematic diagram of a board testing system provided in an embodiment of this application;

[0033] Figure 5 This is a first flowchart illustrating a board testing method improved in an embodiment of this application;

[0034] Figure 6 This is a timing diagram of a board testing method provided in an embodiment of this application;

[0035] Figure 7This is a first flowchart illustrating a method for obtaining target pin information provided in an embodiment of this application;

[0036] Figure 8 This is a second flowchart illustrating a method for obtaining target pin information provided in an embodiment of this application;

[0037] Figure 9 This is a schematic diagram of a time-domain waveform provided in an embodiment of this application;

[0038] Figure 10 This is a schematic flowchart of a process for determining a signal path to be tested, provided in an embodiment of this application.

[0039] Figure 11 This is a second flowchart illustrating a testing method for a circuit board provided in an embodiment of this application;

[0040] Figure 12 This is a third flowchart illustrating a testing method for a circuit board provided in this application embodiment;

[0041] Figure 13 This is a fourth flowchart illustrating a testing method for a circuit board provided in this application embodiment;

[0042] Figure 14 This is a schematic diagram of a computing device provided in an embodiment of this application. Detailed Implementation

[0043] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. To facilitate a clear description of the technical solutions of the embodiments of this application, the use of terms such as "first," "second," etc., in the embodiments of this application is for illustrative purposes and to distinguish the objects being described. There is no particular order between them, nor does it indicate a specific limitation on the number of devices in the embodiments of this application, and they do not constitute any limitation on the embodiments of this application.

[0044] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of this application.

[0045] It should be noted that many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Therefore, the scope of protection of this application is not limited to the specific embodiments disclosed below.

[0046] The following explanations of the technical terms mentioned in the embodiments of this application are provided to facilitate understanding by those skilled in the art.

[0047] A circuit board, also known as a programmable logic board, is a specialized circuit board that uses a printed circuit board (PCB) as its basic carrier and a complex programmable logic device (CPLD) as its core controller. Examples include circuit boards that integrate a complex programmable logic device (CPLD) or a field-programmable gate array (FPGA).

[0048] A complex programmable logic device (CPLD) is a high-density programmable logic device, typically integrated as a separate chip on a circuit board, capable of implementing complex combinational and sequential logic functions within a single chip. A CPLD has multiple pins for signal interaction and data transmission with external chips or peripheral devices (such as connectors, sensors, and memory). In this embodiment, the CPLD is integrated on a board, and its input / output signals are led out through connectors on the board to achieve data communication with external devices.

[0049] A connector, also known as an external connector, is a device in a computing device used to connect two or more subsystems, circuit boards, wires, or other electronic components. They ensure reliable transmission of electrical signals and data while allowing for quick installation and removal of components, facilitating maintenance and upgrades. A connector includes multiple pins that mate with corresponding slots or pins to form a stable electrical connection. In the embodiments of this application, the connector is integrated onto a circuit board, and its input / output signals are led out through the connector on the board to achieve data communication with external devices.

[0050] Pins, also known as traces, are conductive metal terminals on electronic components (such as integrated circuits, chips, connectors, etc.) used to achieve electrical connections. They typically extend outward from the device body, inserting into pad holes on a circuit board, or mating with sockets, connectors, etc., to transmit electrical signals.

[0051] The embodiments of this application will now be described with reference to the accompanying drawings.

[0052] Figure 1 This is a hardware schematic diagram of a computing device provided in an embodiment of this application.

[0053] like Figure 1As shown, computing devices typically include multiple functional boards 1 such as a motherboard and a hard disk backplane. Board 1 usually integrates a large number of components, such as complex programmable logic devices 11 and connectors 12, which enable communication and interaction with external components. During the manufacturing process of board 10 of computing device 1, multiple connectors 12 can be installed on board 10, each connector having multiple pins. Due to the high pin density and large number of connectors 12, multiple processes are involved in the assembly process, such as high-density layout, making it highly susceptible to process defects, such as failure to properly connect the components. Figure 1 As shown, any two pins of connector 12 can be connected to form a short circuit, etc.

[0054] Continue to combine Figure 1 As shown, the complex programmable logic device 11, as the logic control core on the board, also has multiple pins. These pins are connected one-to-one with the pins of the connector 12 through the wiring on the board, forming a signal path of "pin → wiring → pin".

[0055] To ensure the board functions properly, the connectivity of the entire path from "pin → trace → pin" needs to be tested to ensure reliable signal transmission.

[0056] Figure 2 This is the first structural schematic diagram of a board testing system provided in the embodiments of this application.

[0057] like Figure 2 As shown, the board testing system includes the board under test 21 and the test card 22.

[0058] In some examples, the board under test 21 can be a PCB circuit board of various computing devices, used to implement the core functions of computing, storage and communication of the computing device, such as server motherboard, embedded control board or communication module board. Among them, the board under test 21 includes a first programmable logic controller 210, which can be a chip with configurable logic functions such as CPLD or field-programmable gate array (FPGA).

[0059] The first programmable logic controller 210 has a first pin 211, which is used to receive an enable signal. The enable signal is a preset level transition signal, such as a pulse signal that transitions from a low level to a high level. The enable signal is used to control the first programmable logic controller 210 to enter the test state. That is, when the first pin 211 detects the enable signal, the first programmable logic controller 210 is triggered and enters the preset test state, thereby starting the automatic test process of the board under test 21.

[0060] It should be noted that before entering the testing state, the board under test 21 can be in normal working state or power-on standby state, without running an operating system or loading firmware.

[0061] Furthermore, the first programmable logic controller 210 may also include multiple second pins 212. The multiple second pins 212 may be distributed in different functional areas of the first programmable logic controller 210, corresponding to different signal paths under test. The signal path under test refers to the physical signal path that needs to be verified for connectivity and evaluated for electrical performance, such as power supply lines, clock signal lines, data buses, differential communication links (such as PCIe, USB) or GPIO interface lines, etc.

[0062] When the board under test 21 enters the test state, the first programmable logic controller 210 controls multiple second pins 212 to output test code streams. The test code stream is a set of digital signal sequences with specific timing and level characteristics, such as periodic square wave signals (e.g., 1kHz TTL level signals), pseudo-random binary sequences (PRBS), or address / data encoded sequences.

[0063] In some examples, test card 22 is connected to board under test 21. Test card 22 includes a second programmable logic controller 220, which receives a test code stream sent by a first programmable logic controller 210, determines the currently active signal path under test based on the test code stream, and performs test operations on that path.

[0064] Specifically, the testing operations include:

[0065] The signal level changes on the signal path under test are collected, for example, to detect whether the signal correctly transitions from a low level (0V~0.8V) to a high level (2.0V~3.3V), and whether there are any level drifts, ringing, abnormal rise / fall times, or signal loss. If the second programmable logic controller 220 receives a complete test code stream that meets the expected timing and level standards within a preset time, the signal path under test is determined to be normal, that is, the signal path under test is connected normally and its electrical performance meets the specifications; if no signal is received, the signal level does not invert (e.g., it is always high or always low), the waveform is distorted, or the timing is disordered, the signal path under test is determined to be abnormal, that is, the signal path under test has defects such as open circuit, short circuit, cold solder joint, impedance mismatch, or crosstalk.

[0066] In this embodiment, by setting a first programmable logic controller that can respond to an enable signal in the board under test and using it to drive the test code stream output, combined with the test card's analysis of the level and waveform of the received signal, the automation of the board's signal path is realized, which can effectively improve test efficiency.

[0067] The following describes the specific structure of the board testing system.

[0068] The following is combined with Figure 3 and Figure 4 The operating status of the board 21 under test is illustrated by example.

[0069] Figure 3 This is a three-dimensional structural schematic diagram of a board testing system provided in an embodiment of this application.

[0070] Figure 4 This is a second structural schematic diagram of a board testing system provided in an embodiment of this application.

[0071] In some examples, such as Figure 3 and Figure 4 As shown, the board testing system includes a test tool 31, which is a mechanical-electrical integrated test fixture used to fix the board under test 21 and the test card 22, and to realize the physical positioning and electrical connection between the two, so as to ensure the stability of signal transmission during the test.

[0072] In one example, the test tool 31 includes a test station 310 and a test probe 311. The test station 310 is disposed inside the test tool 31 and is used to detachably mount the board under test 21 and the test card 22. The board under test 21 and the test card 22 are inserted or pressed into the test station according to a preset direction and position to ensure that the pins of each pair are accurately aligned and to avoid misalignment or poor contact. The test probe 311 is a flexible conductive pin structure. One end of it is electrically connected to the first pin 211 on the board under test 21 through a flexible contact, and the other end is fixed to the substrate of the test tool 31 and connected to the power supply voltage to provide a first preset level.

[0073] For example, the power supply voltage can provide a first preset level to the test probe 311, such as a DC low-level signal of 0V.

[0074] In this embodiment, whether the board under test 21 is installed correctly directly determines the voltage level of the first pin 211, thereby affecting the operating state of the first programmable logic controller 210. This process is achieved through the following two states:

[0075] In one example, when the board under test 21 is not installed or not fully installed, the test probe 311 is in a floating or uncompressed state and has no effective contact with the first pin 211. The first pin 211 can be in a high level by default. In order to prevent the first pin 211 from having an uncertain state when it is not connected, the board under test 21 is also configured with a first bias resistor 214 and a control point 215.

[0076] Control point 215 is an electrical node specifically designed to connect the first pin 211 to other circuit components. Control point 215 is directly electrically connected to the first pin 211 and undergoes further level stabilization via a first bias resistor 214. The first end of the first bias resistor 214 is connected to control point 215, and the second end is connected to the power supply voltage. Because the first bias resistor 214 is connected to the power supply voltage, it acts as a pull-up resistor, pulling the level of control point 215 high to a value close to the power supply voltage (e.g., VCC = 3.3V) when no external signal is applied, thereby ensuring that the first pin 211 remains in a stable high-level state.

[0077] For example, when the first bias resistor 214 is connected to the power supply voltage, the control point 215 will be kept at a stable high level, i.e., the second preset level, when there is no external input signal, so that the first programmable logic controller 210 can remain in normal working state.

[0078] In another example, when the board under test 21 is correctly installed in the test station and fully in place, the test probe 311 is compressed, and its tip forms a stable electrical connection with the first pin 211 of the board under test 21, applying a first preset level (such as 0V low level) to the first pin 211. In practical applications, the test probe 311 should be designed to pull the first pin 211 down to a low level (GND), thereby forming a high-to-low level transition as an enable signal to trigger the test process.

[0079] For example, the first programmable logic controller 210 monitors the signal level of the first pin 211 in real time. When it detects that the level of the first pin 211 drops from a high level (e.g., 3.3V) to a low level (0V), it determines that a valid enable signal has been received, and then controls the board under test 21 to enter the test state and start the automatic test process, that is, enter the test state.

[0080] In summary, the test process is automatically triggered by the physical installation of the board under test, without the need for additional external control signals or manual operation. When the first programmable logic controller detects a specific change in the level of the first pin (e.g., from high to low), it automatically switches to the test state, improving test efficiency.

[0081] Continue to combine Figure 4 As shown, in one example, the board under test 21 includes an external connector 216, which is used to realize electrical connection and signal transmission between the board under test 21 and other external devices (such as test card 22, system backplane or functional module).

[0082] The external connector 216 includes multiple first pins 217, which can be arranged in a preset layout to support various types of connections, such as power signals and differential signals. Multiple second pins of the first programmable logic controller 210 are electrically connected to the corresponding first pins 217 in the external connector 216 via traces on the PCB board, forming multiple signal paths. Each signal path corresponds to a signal path under test, used for transmitting data, clock, control signals, etc.

[0083] After the board under test 21 enters the test state, the first programmable logic controller 210 outputs a predefined test code stream through multiple signal paths. The test code stream is used to activate and identify each signal path under test so that the test card 22 can receive and analyze it.

[0084] Specifically, the test stream can include two types of signals: a synchronization signal and target pin information. The synchronization signal is a fixed code pattern with specific timing characteristics, used to indicate the start position of each frame of the test stream, facilitating frame synchronization at the receiving end (test card). The target pin information is transmitted following the synchronization signal, meaning it is transmitted after the signal is synchronized. It is used to identify the second pin number corresponding to the currently output test signal or the target pin position on the external connector.

[0085] The second programmable logic controller 220 receives and parses the test code stream sent by the first programmable logic controller 210, and, in conjunction with a pre-stored preset connector pin mapping table, determines the specific location of each target pin on the board under test 21 in the external connector 216. The pin mapping table records the physical and logical correspondence between each second pin on the board under test and its corresponding first pin on the external connector.

[0086] Furthermore, the second programmable logic controller 220 obtains the signal path under test between the target pin and the first pin based on the target pin information, and performs a test operation on the signal path under test.

[0087] In one example, the test operation includes, but is not limited to, one or more of the following patterns.

[0088] Pull-up operation: The signal path under test is pulled up to a high level using an internal or external pull-up resistor to check if it can reach the high level normally. This is used to verify open circuit or weak drive problems. For example, a 200k ohm pull-up resistor is connected to the power supply voltage to pull up the signal path under test. For example, the pull-up threshold can be set to 1.

[0089] Pull-down operation: A signal line is pulled down to a low level using a pull-down resistor, and its ability to stably maintain a low level is detected to identify short circuit or leakage risks. For example, a 200k ohm pull-down resistor connected to ground is used to pull down the signal path under test; for instance, the pull-down threshold can be set to 0.

[0090] No pull-up / pull-down operation: Monitor signal level changes under high impedance conditions to assess signal integrity and crosstalk.

[0091] During the test operation, the second programmable logic controller 220 collects signal level changes on the signal path under test through test probes, including whether level transitions occur, whether rise / fall times meet expectations, and whether there are glitches or abnormal delays. If the collected results are consistent with the expected behavior, the signal path under test is determined to be normally connected and have good electrical performance; if signal loss, abnormal level, timing deviation, or logic error occurs, the path is determined to have defects, such as open circuit, short circuit, poor soldering, or impedance mismatch.

[0092] In summary, there is no need to design differentiated test procedures for different types of pins. All signal paths can be tested under a unified test state, which effectively simplifies the test logic, reduces test complexity, and improves test efficiency. At the same time, it ensures that all types of signal paths are fully covered, enhancing the comprehensiveness of the test.

[0093] Corresponding to the above embodiments, this application also provides a test method for a circuit board. The test method for the circuit board described above will be specifically described below with reference to the accompanying drawings.

[0094] Figure 5 This is the first flowchart of a board testing method improved in the embodiments of this application.

[0095] like Figure 5 As shown, the board testing method includes the following steps:

[0096] S1: Detect the operating status of the first programmable logic controller on the board under test.

[0097] In one implementation, the board under test detects the operating state of the first programmable logic controller on the board under test based on the connection relationship between the test probe and the control point.

[0098] Specifically, the control point of the board under test (DUT) is electrically connected to the test probes (not shown in the diagram) on the test fixture, while the test card is connected to the DUT via a connector. In this test scheme, if the control point is not in contact with the test probe, it remains at a high level by default; this represents the system being in a "default state." Once the control point establishes physical contact with the test probe, a pull-down operation is performed on the control point, causing its level to change from high to low. At this time, this level change is detected, and the system's operating status is determined accordingly. Specifically, if a high level is detected for the corresponding test point, it indicates that the system is currently in the default state, meaning no actual test operation has been performed. Conversely, if a low level is detected, it means that the test probe has successfully made contact with the control point, and the system enters the "test state," allowing further functional verification or fault diagnosis.

[0099] It should be noted that the above "default state" refers to the normal working state of the board under test without specific testing or external intervention.

[0100] In one implementation, the first programmable logic controller (PLC) can detect its operating state by monitoring changes in the voltage level on a pin connected to a control point. For example, the control point is connected to a power supply (such as VCC) via a first bias resistor, so its corresponding pin remains high by default when not in contact with a test probe. When a probe of the test fixture contacts a control point, the probe is typically grounded (GND), pulling the control point low and causing its corresponding input pin of the first PLC to go low. At this point, the first PLC can detect its operating state by monitoring changes in the voltage level on the pin connected to the control point.

[0101] The first programmable logic controller can be a complex programmable logic device or other devices, without specific limitations.

[0102] S2: When the first programmable logic controller is in test mode, the board under test sends a synchronization signal to the test card.

[0103] To ensure reliable communication between the board under test (DUT) and the test card, synchronization between them is necessary before data exchange. This synchronization typically refers to time synchronization, using synchronization signals to ensure correct data transmission and reception.

[0104] In one implementation, by defining different timing characteristics, such as the duration of level states, multiple types of control or status information can be encoded on the same physical signal line, thereby enabling the identification of the current signal type based on timing differences. Specifically, synchronization signals can be transmitted using timing encoding. Unique level change patterns, such as specific combinations of high and low level durations, are used to characterize unique signal types. The receiving end detects and parses these timing characteristics, accurately determining the specific type and meaning of the current signal based on the duration and order of the high / low levels.

[0105] Figure 6 This is a timing diagram of a board testing method provided in an embodiment of this application.

[0106] like Figure 6 As shown, when the first programmable logic controller is in test mode, synchronization between the board under test (DUT) and the test card is achieved through a specific timing sequence. Specifically, a timing sequence consisting of "200 microseconds high level + 1500 microseconds low level + 300 microseconds high level" can be used as the synchronization signal. This sequence has unique high and low level characteristics, making it easy for the receiving end to accurately identify.

[0107] For example, continue as follows Figure 6 As shown, the entire synchronization signal transmission process is as follows: the time axis starts from 0 milliseconds, and the total duration of the entire synchronization signal is approximately 2 milliseconds. That is, the timing sequence of the synchronization signal can be "first output a high level for 200 microseconds; then output a low level for 1500 microseconds, and finally output a high level for 300 microseconds".

[0108] In addition, continue as Figure 6 As shown, the level changes are also marked, visually demonstrating the high-low level transition process in the synchronization signal.

[0109] S3: The test card receives the synchronization signal sent by the second programmable logic controller on the board under test, and determines the timing synchronization between the test card and the board under test based on the synchronization signal.

[0110] After receiving the synchronization signal from the control unit on the board under test, the test card analyzes the timing characteristics of the signal (such as the duration and order of high and low levels) to identify the signal type, i.e., the specific synchronization signal that serves as a synchronization marker. Based on this identification result, the test card can determine the relative time reference between itself and the board under test, thereby establishing and confirming timing synchronization between the two.

[0111] This ensures that the test card can start sampling or responding to subsequent data at the correct time, providing time alignment for subsequent test data interaction and improving the reliability and accuracy of communication.

[0112] S4: The board under test sends the target pin information corresponding to the target pin to the test card.

[0113] In this article, "pin" can also be called "pin" or "pin terminal". Without specific definition, it refers to the electrical connection endpoint on the connector or chip.

[0114] Figure 7 This is a first flowchart illustrating a method for obtaining target pin information provided in an embodiment of this application.

[0115] Figure 8 This is a second flowchart illustrating a method for obtaining target pin information provided in an embodiment of this application.

[0116] In one implementation, such as Figure 7 and Figure 8 As shown, step S4 includes step S41.

[0117] S41: Obtain pin information for at least one target pin.

[0118] The target pin refers to a specific physical pin in a hardware circuit, which has specific functions and electrical characteristics.

[0119] For example, the first programmable logic controller on the board under test acquires these target pins. Target pins typically include critical information such as location, purpose (input, output, power supply, etc.), operating voltage, and current requirements. For clarity, the pin information of the target pins will be used in the subsequent explanation.

[0120] For example, the first programmable logic controller can identify and extract three such target pins, such as pin information A, pin information B, and pin information C. Each pin's pin information may carry different signals or functions.

[0121] However, this form of definition is not suitable for direct communication transmission, so it is necessary to convert this critical information into a data format suitable for transmission.

[0122] The following will continue to combine Figure 7 As shown, step S4 also includes step S42.

[0123] S42: Based on the pin information of the target pin, determine the target pin information that is compatible with the data format for communication transmission.

[0124] To enable efficient transmission of raw pin information between different devices, it needs to be converted into a standardized data format, namely, target pin information. There are various ways to determine the target pin information, such as transmitting it in the form of data frames or time-domain waveforms.

[0125] The following will continue to combine Figure 7 The various methods for obtaining the target pin are explained in detail.

[0126] In one example, step S42 includes step S421.

[0127] S421: Based on the preset data frame format, the pin information of the target pin is encoded to obtain the target pin information.

[0128] The target pin information is a data representation generated by formatting and encoding the pin information of the target pins according to a predetermined data structure and communication protocol requirements. This target pin information is adapted to the data format for communication transmission and can be reliably transmitted between the board under test and the test card.

[0129] Continue to combine Figure 7 As shown, step S421 includes steps S4211-S4213.

[0130] S4211: Based on a preset data frame format, convert the pin information of the target pin to obtain the target data frame.

[0131] The target data frame is displayed as a string. Each standard data frame is 20 characters long. The format of the data frame begins with "PIN" as a prefix to identify that it is a pin name transmission, followed by the actual pin name. After adding the prefix and pin name, the remaining part is padded with spaces or other specified characters to ensure that the entire string is 20 characters long, thus forming a standardized data frame.

[0132] For example, based on a preset data frame format, the pin information A of the target pin is converted to obtain target data frame A': "PIN_A"; based on the preset data frame format, the pin information B of the target pin is converted to obtain target data frame B': "PIN_B"; based on the preset data frame format, the pin information C of the target pin is converted to obtain target data frame C': "PIN_C".

[0133] S4212: Encode at least one character in a target data frame to obtain at least one corresponding American Standard Information Interchange Code value.

[0134] The American Standard Code for Information Interchange (ASCII) is a character encoding standard based on the Latin alphabet, widely used in electronic communications. It converts text characters (such as English letters, numbers, punctuation marks, and control characters) into computer-recognizable binary values, thereby achieving unified data representation and reliable transmission. In this embodiment, ASCII is used to convert each character of the formatted target data frame into its corresponding numerical code, so that it can be transmitted bit by bit in the form of level signals through a serial communication interface.

[0135] For example, let's take target data frame A' as an example. The ASCII code values ​​of target data frame A' are: "P" code value is 80, "I" code value is 73, "N" code value is 78, "_" code value is 95, "A" code value is 65, and "" (space) code value is 32 (repeated 15 times).

[0136] S4213: Convert at least one American Standard Information Interchange Code value to determine at least one target pin information.

[0137] ASCII code values ​​are further decomposed into binary bit sequences, where each ASCII code is an integer from 0 to 255, corresponding to an 8-bit binary number (1 byte). For example, ASCII code 80 corresponds to "01010000". If the target data frame contains 20 characters, the entire 20-character data frame requires 160 bits. After being decomposed into binary bit sequences, level patterns are encoded to form a series of signals that can be transmitted over physical lines.

[0138] For example, a timing sequence consisting of "level mode corresponding to bit value 0, high level for 200μs; level mode corresponding to bit value 1, low level for 600μs + high level for 200μs" can be used as the signal type corresponding to the target pin information.

[0139] In another example, the combination continues. Figure 8 As shown, step S42 includes steps S422-S423.

[0140] S422: The time-domain waveform corresponding to the pin information of the target pin on the board under test.

[0141] Optionally, the time-domain waveform corresponding to the pin information of the target pin can be obtained on the board under test based on a clock counter.

[0142] The clock counter, which can be built into the first programmable logic controller, is a component used to provide a precise time reference. It increments at a fixed frequency, allowing it to measure time intervals. For example, if the clock frequency is 10MHz, the counter increments once every 0.1 microseconds.

[0143] For example, by recording the pin information state of the target pin at each moment and combining it with the precise time points provided by the clock counter, a graph showing the change of the pin state over time can be plotted on the time axis, i.e., a time-domain waveform. The pin information of each target pin can be a time-domain waveform, consisting of a high level (logic 1) and a low level (logic 0).

[0144] Figure 9 This is a schematic diagram of a time-domain waveform provided in an embodiment of this application.

[0145] Combination Figure 9 As shown, let's continue with the example of target pin information A, target pin information B, and target pin information C. Here, we assume that the time-domain waveform corresponding to B0 represents target pin information A, the time-domain waveform corresponding to B1 represents target pin information B, and the time-domain waveform corresponding to B2 represents target pin information C.

[0146] To reduce memory usage, instead of directly storing complete time-domain waveform data, feature extraction is performed first, and only feature parameters related to target pin identification are saved.

[0147] The following is an illustrative example in conjunction with step S423.

[0148] S423: Determine the target pin information corresponding to the target pin based on the time-domain waveform and the preset time-domain waveform.

[0149] The preset time-domain waveform can be a general time-domain waveform or a time-domain waveform defined in a real-time scenario.

[0150] In one implementation, continue to combine Figure 7 As shown, step S423 includes step S4231.

[0151] S4231: Calculate the AND value between the time-domain waveform and the preset time-domain waveform to obtain the target pin information corresponding to the target pin.

[0152] The target pin information is adapted to the data format of communication transmission. "AND value" refers to performing a logical AND operation on two binary signals point-by-point along the time axis. A logical AND operation means that the output is high only when both input signals are simultaneously high; otherwise, the output is low. For time-domain waveforms, this means that the resulting waveform will only display a high level at that time point if both waveforms are high at the same time.

[0153] For example, continue to combine Figure 8 As shown, for ease of explanation, taking the preset time-domain waveform B1 as an example, the AND value of at least two time-domain waveforms is calculated. For example, the AND value of time-domain waveforms B0 and B1 is calculated, i.e., "B0&B1", to obtain the target pin information A-1; the AND value of time-domain waveforms B1 and B2 is calculated, i.e., "B1&B2", to obtain the target pin information B-1; the AND value of time-domain waveforms B1 and B3 is calculated, i.e., "B1&B3", to obtain the target pin information C-1.

[0154] S5: Receive the target pin information of the target pin sent by the first programmable logic controller, and determine the signal path to be tested corresponding to the target pin information.

[0155] In one implementation, Figure 10 This is a schematic diagram of a process for determining a signal path to be tested, provided in an embodiment of this application.

[0156] like Figure 10 As shown, step S5 includes steps S51-S52.

[0157] S51: The board under test sends at least one target pin information to the test card.

[0158] It should be noted that when the board under test sends at least one target pin information to the test card, the sending order can be determined by priority or preset rules. The time interval for sending each target pin information can be set to two seconds or three seconds; no specific limitation is made here.

[0159] Following the example above, the board under test sends three target pin information to the test card.

[0160] S52: The test card receives the target pin information sent by the first programmable logic controller, decodes the target pin information based on the target pin information, and obtains the target pin information.

[0161] In one example, step S52 includes steps S521-S523.

[0162] S521: The test card converts at least one target pin information into at least one American Standard Information Exchange Code (USSIC) value.

[0163] Step S521 can be referred to as the reverse process of step S4213 above, and will not be repeated here.

[0164] S522: The test card decodes at least one corresponding US Standard Information Exchange Code value to obtain at least one target data frame.

[0165] Continuing with the example above, “8073739565323232323232323232323232323232” is converted into target data frame A': A“PIN_A”.

[0166] S523: The test card converts at least one target data frame to obtain the pin information of the target pin.

[0167] Continuing with the example above, "PIN_A" is converted to pin information A for the target pin.

[0168] In another implementation, the combination continues. Figure 8 As shown, step S52 includes step S524.

[0169] S524: The test card receives the target pin information sent by the first programmable logic controller, processes the target pin information based on the target pin information, and obtains the pin information of the target pin.

[0170] In one example, step S524 includes steps S5241-S5242.

[0171] S5241: Based on a heuristic algorithm, obtain the time-domain waveform pairs corresponding to the target pin information.

[0172] After knowing the time-domain waveform corresponding to the target pin, a heuristic search strategy is used to infer one or more pairs of original pin time-domain waveforms that are most likely to generate the target waveform. For example, time-domain waveform pairs: B0 and B1.

[0173] S5242: Determines the pin information of the target pin based on the clock counter and time-domain waveform pair on the board under test.

[0174] By combining the precise timing points provided by the clock counter, the waveform pairs are time-aligned and matched with physical pins to determine the pin information of the corresponding target pin. For example, the pin information A of the target pin is determined.

[0175] S53: The test card determines the target pin of the external connector based on the target pin information and the preset connector pin mapping table, and determines the signal path to be tested between the target pin and the target pin.

[0176] Continuing with the example above, the pin information A, pin information B, and pin information C of the target pin correspond to different pins on the external connector. The system independently performs identification and mapping for each piece of information, determining each target pin and its signal path under test, namely signal path under test A-2, signal path under test B-2, and signal path under test C-2.

[0177] S6: The test card performs a preset level operation on the signal path under test and obtains the test results of the signal path under test.

[0178] In one embodiment, the second programmable logic controller of the test card performs a preset level operation on the signal path under test to obtain the test result of the signal path under test.

[0179] The preset level operation includes at least one of pull-up operation, pull-down operation, and no pull-up / pull-down operation. Pull-up operation refers to pulling the signal line level to a high level by using a pull-up bias resistor; pull-down operation refers to pulling the signal line level to a low level by using a pull-down bias resistor; no pull-up / pull-down operation refers to the signal line being in a high-impedance state without applying an external bias resistor.

[0180] In one example, taking the above-mentioned signal path A-2 as an example, after the second programmable logic controller of the test card applies a preset pull-up operation to the signal path A-2, it reads the state of the signal path A-2 and records it as a binary value (0 or 1) to evaluate the functional integrity of the signal path.

[0181] S7: Based on the test results, the test card determines whether the signal path under test of the board under test is in a normal state.

[0182] When the test card applies a pull-up operation, if the signal is not effectively pulled high, i.e. "not pulled", it indicates that there may be an abnormality such as an open circuit or overload in the signal path under test, and the corresponding test result is 0; if the signal is successfully pulled high, i.e. "pulled", it indicates that the signal path under test is normal, and the test result is 1.

[0183] When a pull-down operation is applied, if the signal is effectively pulled low (i.e., "pulled"), it indicates that the signal path under test is conducting well, and the corresponding test result is 0. If the pull-down operation fails to pull the signal low (i.e., "not pulled"), it may be due to shorting to the power supply or excessive pull-up strength, and the corresponding test result is 1.

[0184] Optionally, when the test card is not pulled up or down, the test card does not actively change the signal state, but passively detects the current real level of the signal line, and then determines whether the signal path of the board under test is in a normal state.

[0185] It should be noted that after the detection of the signal path under test is completed, the board under test will automatically enter the test waiting phase. In this state, the board maintains its current configuration and status, preparing for possible subsequent test tasks, thereby improving the flexibility and efficiency of the testing process.

[0186] In summary, by using a unified test state to test the signal paths corresponding to different target pins, there is no need to distinguish between target pin types, which improves test efficiency and ensures the integrity of test coverage.

[0187] To more intuitively understand the testing methods for the aforementioned boards, the following example uses a single side of the board under test to illustrate the testing methods. The following section combines... Figure 11 Specific examples will be provided.

[0188] Figure 11 This is a second flowchart illustrating a testing method for a circuit board provided in this application embodiment.

[0189] like Figure 11 As shown, the testing method for the board includes the following steps:

[0190] S1101: The test board detects the operating status of the first programmable logic controller on the test board based on the connection relationship between the test probe and the control point.

[0191] Step S1101 can refer to the specific content of step S1 above, and will not be repeated here.

[0192] S1102: When the board under test is in test mode, it sends a synchronization signal to the test card.

[0193] Step S1102 can be referred to the specific content of step S2 above, and will not be repeated here.

[0194] S1103: Send the target pin information corresponding to the target pin to the test card so that the test card can determine the signal path to be tested corresponding to the target pin information; perform test operations on the signal path to be tested, and determine whether the signal path to be tested on the board under test is normal based on the test results.

[0195] Among them, the signal path to be tested is used to characterize the communication path between the target pin and the target terminal.

[0196] Step S1103 can be referred to the specific content of steps S3-S7 above, and will not be repeated here.

[0197] In summary, by using a unified test state to test the signal paths corresponding to different target pins, there is no need to distinguish between target pin types, which improves test efficiency and ensures the integrity of test coverage.

[0198] The following example, using a single side of the test card, illustrates the testing method for the circuit board. The following section combines... Figure 12 Specific examples will be provided.

[0199] Figure 12 This is the third flowchart of a testing method for a circuit board provided in this application embodiment.

[0200] like Figure 12 As shown, the testing method for the board includes the following steps:

[0201] S1201: The test card receives the synchronization signal sent by the first programmable logic controller on the board under test, and determines the timing synchronization between the test card and the board under test based on the synchronization signal.

[0202] Step S1201 can refer to the specific content of step S3 above, and will not be repeated here.

[0203] S1202: The test card receives the target pin information of the target pin sent by the first programmable logic controller and determines the signal path to be tested corresponding to the target pin information.

[0204] Among them, the signal path to be tested is used to characterize the communication path between the target pin and the target terminal.

[0205] Step S1202 can refer to the specific content of steps S4-S5 above, and will not be repeated here.

[0206] S1203: The test card performs a preset level operation on the signal path under test and obtains the test results of the signal path under test.

[0207] Step S11203 can be referred to the specific content of step S6 above, and will not be repeated here.

[0208] S11204: Based on the test results, the test card determines whether the signal path under test of the board under test is in a normal state.

[0209] Step S1204 can be referred to the specific content of step S7 above, and will not be repeated here.

[0210] In summary, by using a unified test state to test the signal paths corresponding to different target pins, there is no need to distinguish between target pin types, which improves test efficiency and ensures the integrity of test coverage.

[0211] Figure 13 This is the fourth flowchart of a testing method for a circuit board provided in this application embodiment.

[0212] like Figure 13The testing method for the circuit board includes the following steps:

[0213] S131: The first programmable logic controller of the board under test detects whether it has entered the test state.

[0214] Step S131 can refer to the specific content of step S1 above, and will not be repeated here.

[0215] S132: When the first programmable logic controller enters the test state, the board under test sends a synchronization signal to the test card.

[0216] Step S132 can be referred to the specific content of step S2 above, and will not be repeated here.

[0217] S133: The test card determines whether the board under test and the test card are synchronized based on the synchronization signal.

[0218] Step S133 can be referred to the specific content of step S3 above, and will not be repeated here.

[0219] S134: Determine the target pin information of the board under test.

[0220] Step S134 can refer to the specific content of step S4 above, and will not be repeated here.

[0221] S135: The board under test sends target pin information to the test card.

[0222] Step S135 can be referred to the specific content of step S5 above, and will not be repeated here.

[0223] It should be noted that the order of steps S133 and steps S134-S135 is not specifically limited.

[0224] S136: When the board under test and the test card are synchronized, the test card receives at least one target pin information sent by the first programmable logic controller and determines the signal path under test corresponding to the target pin information.

[0225] Step S136 can be referred to the specific content of step S6 above, and will not be repeated here.

[0226] S137: The test card applies a preset level operation to the signal path under test and detects the test result of the signal path under test.

[0227] Step S137 can be referred to the specific content of step S7 above, and will not be repeated here.

[0228] S138: Based on the test results, determine whether the signal path under test of the board under test is in a normal state.

[0229] Step S138 can be referred to the specific content of step S8 above, and will not be repeated here.

[0230] S139: After the detection of the signal path to be tested corresponding to the target pin information is completed, the test card re-executes step S133.

[0231] S140: After the detection of the signal path to be tested corresponding to the target pin information is completed, the board under test enters the test waiting stage.

[0232] In summary, by using a unified test state to test the signal paths corresponding to different target pins, there is no need to distinguish between target pin types, which improves test efficiency and ensures the integrity of test coverage.

[0233] Figure 14 This is a schematic diagram of a computing device provided in an embodiment of this application.

[0234] like Figure 14 As shown, the computing device 1400 includes: a processor 1401, a memory 1402, a first programmable logic controller 1403, and a second programmable logic controller 1404.

[0235] For example, the computing device 1400 may also include a communications interface 1405 and a communications bus 1406.

[0236] The processor 1401, memory 1402, and communication interface 1405 communicate with each other via communication bus 1406. The communication interface 1405 may include a transmitter and receiver for communicating with other devices or communication networks, and may be a wired interface (port), such as a fiber distributed data interface (FDDI) or a gigabit Ethernet interface (GE).

[0237] The first programmable logic controller 1403 and the second programmable logic controller 1404 can be complex programmable logic devices or other devices, without specific limitations. Through their internal programmable logic arrays, the first programmable logic controller 1403 and the second programmable logic controller 1404 support various input / output configurations and complex timing control, thereby providing high flexibility and configurability.

[0238] In some embodiments, the processor 1401 is used to execute program 1407, specifically performing the relevant steps in the above-described board test execution method embodiments. Specifically, program 1407 may include program code, which includes computer-executable instructions.

[0239] For example, processor 1401 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement some embodiments of this application. Computing device 1400 may include one or more processors, which may be processors of the same type, such as one or more CPUs; or they may be processors of different types, such as one or more CPUs and one or more ASICs. The CPU may be a single-core CPU or a multi-core CPU.

[0240] In some embodiments, memory 1402 is used to store program 1407. Memory 1402 may include high-speed random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device.

[0241] Specifically, program 1407 can be called by processor 1401 to cause computing device 1400 to execute the board's test execution method operation.

[0242] Some embodiments of this application provide a computer-readable storage medium storing at least one executable instruction that, when executed on a computing device 1400, causes the computing device 1400 to perform the board testing method described in the above embodiments.

[0243] For example, the computer-readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, a floppy disk, and an optical data storage device.

[0244] Some embodiments of this application provide a chip system applied to a server. The chip system includes one or more interface circuits and one or more processors. The interface circuits and processors are interconnected via lines. The interface circuits are used to receive signals from the server's memory and send signals to the processors, the signals including computer instructions stored in the memory. When the server processor executes the computer instructions, the server performs various steps in the board test execution method shown in the above-described method embodiments.

[0245] The beneficial effects that the readable storage medium provided in some embodiments of this application can achieve can be referred to the beneficial effects in the corresponding inference task execution method provided above, and will not be repeated here.

[0246] It should be noted that, in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0247] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0248] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus or device (such as a computer-based system, a processor-included system or other system that can fetch and execute instructions from, an instruction execution system, apparatus or device).

[0249] For the purposes of this specification, "computer-readable medium" can mean any means that can contain, store, communicate, propagate, or transmit programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0250] More specific examples (a non-exhaustive list) of computer-readable media include the following: electrical connections having one or more wires (electronic devices), portable computer disks (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM).

[0251] Furthermore, the computer-readable medium can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory. It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof.

[0252] In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc. The embodiments described above are merely specific embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made based on the technical solutions of this application should be included within the scope of protection of this application.

Claims

1. A board testing system, characterized in that, include: The board to be tested includes a first programmable logic controller (PLC). The first PLC has a first pin, which is used to receive an enable signal. The enable signal is used to control the first PLC to enter a test state. The first programmable logic controller includes a plurality of second pins, which are used to send out test code streams after entering the test state; The test stream is used to determine the path of the signal to be tested after entering the test state; A test card is connected to the board under test. The test card includes a second programmable logic controller (PLC). The second PLC is used to receive the test code stream, determine the signal path under test based on the test code stream, apply test operations to the signal path under test, and collect the signal level changes on the signal path under test to determine whether the signal path under test is normal.

2. The board testing system according to claim 1, characterized in that, Also includes: Test fixture; The test fixture includes a test probe and a test station; one end of the test probe is electrically connected to the board under test, and the other end of the test probe is fixed to the test fixture and grounded; the board under test and the test card are detachably installed in the test station; The test probe is used to drive the signal level of the first pin to a first preset level when the board under test is installed in place, so as to provide the enable signal to the first pin; The first programmable logic controller is configured to determine that the test card enters the test state when the signal level of the first pin is detected to be a first preset level.

3. The board testing system according to claim 2, characterized in that, The board under test further includes a first bias resistor and a control point; the control point is electrically connected to the first pin; the first end of the first bias resistor is electrically connected to the control point; the second end of the first bias resistor is connected to the power supply voltage. When the control point is electrically connected to the test probe, the first bias resistor drives the level of the control point to the first preset level, thereby triggering the first programmable logic controller to enter the test state. When the control point is not electrically connected to the test probe, a second preset level is established for the control point to enable the first programmable logic controller to operate.

4. The board testing system according to claim 2 or 3, characterized in that, The board under test also includes an external connector, which includes multiple first pins; multiple second pins of the first programmable logic controller form multiple signal paths with the corresponding first pins of the external connector through wiring. In the test state, the first programmable logic controller is used to output the test code stream through the signal path; the test code stream includes a synchronization signal and target pin information, the synchronization signal is used to indicate the starting position of the test code stream; the target pin information is transmitted following the synchronization signal. The second programmable logic controller is used to parse the synchronization signal, perform timing synchronization of the board under test and the test card, parse the target pin information, and determine the signal path under test from the multiple signal paths.

5. The board testing system according to claim 4, characterized in that, The first programmable logic controller is used to send the synchronization signal to the second programmable logic controller; and to encode the pin information of the target pin based on a preset data frame format to obtain the target pin information. The target pin information is sent to the second programmable logic controller; wherein the target pin information is an encoded signal of a logic identifier; The second programmable logic controller is specifically used to determine the timing synchronization between the test card and the board under test based on the synchronization signal; after determining the timing synchronization, it parses the encoded signal to determine the signal path under test; applies a test operation to the signal path under test and collects the signal level changes on the signal path under test to determine whether the signal path under test is normal.

6. The board testing system according to claim 4, characterized in that, The first programmable logic controller (PLC) is configured to send a synchronization signal to the second PLC; acquire the time-domain waveform corresponding to the target pin; determine the target pin information based on the time-domain waveform and a preset time-domain waveform; and send the target pin information to the second PLC; wherein the target pin information is a physical waveform signal. The second programmable logic controller is specifically used to determine the timing synchronization between the test card and the board under test based on the synchronization signal; after determining the timing synchronization, it analyzes the physical waveform signal to determine the signal path under test; applies a test operation to the signal path under test and collects the signal level changes on the signal path under test to determine whether the signal path under test is normal.

7. The board testing system according to claim 5 or 6, characterized in that, The second programmable logic controller is specifically used to determine the target pin of the external connector based on the target pin information and a preset connector pin mapping table; and to obtain the signal path to be tested between the target pin and the target pin. A test operation is applied to the signal path under test, and the signal level change on the signal path under test is collected to determine whether the signal path under test is normal; wherein, the test operation includes at least one of pull-up operation, pull-down operation, and no pull-up or pull-down operation.

8. A testing method for a circuit board, characterized in that, Applied to a board under test, the board under test including a first programmable logic controller, the method includes: Detect the operating status of the first programmable logic controller on the board under test; When the first programmable logic controller is in test mode, a synchronization signal is sent to the test card; The test card sends target pin information to the test card so that the test card can determine the signal path to be tested corresponding to the target pin information; a test operation is applied to the signal path to be tested, and the test results are used to determine whether the signal path to be tested on the board under test is normal.

9. A testing method for a circuit board, characterized in that, Applied to a test card, the test card including a second programmable logic controller, the method includes: The test card receives a synchronization signal sent by the first programmable logic controller on the board under test, and determines the timing synchronization between the test card and the board under test based on the synchronization signal. Receive the target pin information sent by the first programmable logic controller, and determine the signal path to be tested corresponding to the target pin information; Perform a preset level operation on the signal path under test, and obtain the test result of the signal path under test; Based on the test results, it is determined whether the signal path under test of the board under test is in a normal state.

10. A computing device, characterized in that, The computing device includes a memory and a processor; the memory and the processor are coupled; the memory is used to store computer program code, the computer program code including computer instructions, which, when executed by the processor, cause the computing device to perform the board testing system as described in any one of claims 1 or 7 and the board testing method as described in claim 8 or 9.

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