Universal DDR delay model verification method
By dynamically managing signal direction using status flags and inserting configurable delays, the simulation challenge of bidirectional signal delays in DDR interface verification is solved, improving the flexibility and efficiency of verification, simplifying module integration, and ensuring the correctness of the simulation model.
Patent Information
- Application Number
- CN202511676596.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-14
- Publication Date
- 2026-02-10
AI Technical Summary
Existing technologies struggle to effectively simulate bidirectional signal delays, especially DQ/DQS signals, in DDR interface verification. Furthermore, modifying the PAD or memory model can lead to maintenance difficulties and fail to meet multi-rank calibration requirements.
By dynamically managing signal direction through status flags and inserting configurable delays, combinational logic loops are avoided, and bidirectional signal delays are achieved. Delayed signals are generated and output using status flag storage units, direction control logic units, and delay logic units, independent of the PHY or memory model.
It improves the flexibility and efficiency of DDR interface verification, especially the verification of calibration functions, simplifies module integration, and ensures the correctness of the simulation model and its consistency with the real circuit.
Smart Images
Figure CN121501631A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of chip model verification technology, and particularly relates to a general DDR delay model verification method, a bidirectional signal delay device for digital circuit simulation, and a DDR interface verification system. Background Technology
[0002] With the upgrade of DDR standards (such as DDR5-6400), the valid window for data has shrunk to the 30–50 ps range, resulting in extremely low tolerance for signal skew and jitter. Issues such as PCB trace length differences, impedance mismatch, and crosstalk can lead to signal skew and distortion. DDR PHY controller calibration requires dynamically adjusting timing parameters to compensate for signal transmission delay differences, ensuring accurate data capture within the picosecond window. This includes, but is not limited to, Read DQSGate, Write Leveling, and Vref Calibration. During pre-simulation of the chip controller, these PCB trace delays and process variations can be abstracted as signal delays. Currently, the common approach is to add input and output delays to the chip's PAD model or the DDR memory model to coordinate with the DDR PHY controller for timing calibration.
[0003] Specifically, by modifying the PAD model and adding a one-way signal delay function, and by modifying the memory model, a one-way signal delay function is added. The PHY controller, in conjunction with the PAD or memory model, verifies that all calibration processes are correct under different delay conditions. By adding a one-way delay module to the SOC PAD and memory model, all delay variations are reflected in this mode.
[0004] However, the above methods have the following drawbacks: PAD models provided by manufacturers may not have delay modification capabilities. Generally, PAD models are not modified at the SOC level. Directly modifying the PAD model to add delay functionality will lead to significant maintenance difficulties later in the project. Changing delay functionality only on the PAD test panel cannot solve the DDR multi-rank calibration problem. Adding delay functionality to the model test panel can solve the multi-rank calibration problem, but many models are encrypted files from memory manufacturers and cannot be directly modified. Even if some memory models are not encrypted, directly adding delay functionality to the model will still lead to significant maintenance difficulties later in the project. Most delays within PAD models, even if present, are implemented using System Verilog parameter syntax, but this functionality cannot be dynamically changed during simulation. The dynamic calibration function of the DDRPHY controller cannot be verified, i.e., modifying the delay values multiple times in a single simulation to simulate the changes in the chip's internal delay chain due to temperature in a real-world environment.
[0005] Because different chip companies may use different manufacturing processes, and different projects may employ different process libraries or fab vendors, PAD models vary widely. Even the same DDR PAD may connect to different memory chips, resulting in different latency models. Even with the same DDR PAD model and a common memory model, dual-rank access can occur, causing the signal lines from the same DDR PAD to the corresponding signal lines in the two ranks to have different latency states due to different PCB layouts and routing. Adding unidirectional delay modules to the SOC PAD and memory model can solve some variations in unidirectional delay signals, such as the CA signal in DDR, but it cannot effectively simulate bidirectional delay signals like DQ and DQS. Summary of the Invention
[0006] To address the aforementioned issues, the present invention aims to provide a general DDR delay model verification method, a bidirectional signal delay device for digital circuit simulation, and a DDR interface verification system. By dynamically managing signal direction through status flags, it enables the independent insertion of configurable delays without any modifications to the PHY or memory model, greatly improving the flexibility and efficiency of DDR interface verification, especially calibration function verification.
[0007] The technical solution provided by this invention is: a general DDR latency model verification method, comprising the following steps: Set the first input status flag INA, the second input status flag INB, the first delay status flag INA_Delayed, and the second delay status flag INB_Delayed to an invalid state; By monitoring the signal status of the first bidirectional port A and the second bidirectional port B, the first input status flag INA and the second input status flag INB are dynamically set to determine the currently valid signal transmission direction and avoid forming combinational logic loops. Based on the first input status flag INA and the preset delay requirement, a delayed signal A2B is generated from the first bidirectional port A to the second bidirectional port B; and based on the second input status flag INB and the preset delay requirement, a delayed signal B2A is generated from the second bidirectional port B to the first bidirectional port A. Based on the first delay status flag INA_Delayed and the second delay status flag INB_Delayed, the delayed signal A2B and the delayed signal B2A are output to the corresponding bidirectional ports.
[0008] Preferably, monitoring the signal states of the first bidirectional port A and the second bidirectional port B further includes: In response to detecting a change in the signal state of the first bidirectional port A, determine whether it is in a high-impedance state; If the first bidirectional port A is in a high-impedance state, then the first input status flag INA is set to invalid. If the first bidirectional port A is not in a high-impedance state, check whether the second input status flag INB and the second delay status flag INB_Delayed are both invalid; If both the second input status flag INB and the second delay status flag INB_Delayed are invalid, then the first input status flag INA is set to valid; A symmetrical detection and judgment process is performed on the second bidirectional port B to set the second input status flag INB.
[0009] Preferably, outputting the delayed signal A2B and the delayed signal B2A to the corresponding bidirectional port according to the first delay status flag INA_Delayed and the second delay status flag INB_Delayed further includes: When the second delay status flag INB_Delayed is valid, the delay signal B2A is driven to the first bidirectional port A; otherwise, the first bidirectional port A is set to a high impedance state. When the first delay status flag INA_Delayed is valid, the delayed signal A2B is driven to the second bidirectional port B; otherwise, the second bidirectional port B is set to a high impedance state.
[0010] Preferably, the method operates at the delta-cycle accuracy of the simulator without relying on internal or external clock signals.
[0011] Preferably, a state machine is implemented within the module, wherein the state machine is driven by an internal clock signal, and its state transitions are based on the current signal states of the first bidirectional port A and the second bidirectional port B.
[0012] Based on the same inventive concept, the present invention also provides a bidirectional signal delay device for digital circuit simulation, the device being used to implement the method, the device comprising: A status flag storage unit is used to store the first input status flag INA, the second input status flag INB, the first delayed status flag INA_Delayed, and the second delayed status flag INB_Delayed; The direction control logic unit, coupled to the status flag storage unit, is configured to perform the direction detection and loop interruption steps; A delay logic unit, coupled to the direction control logic unit and the status flag storage unit, is configured to perform the delay signal generation step; An output driving unit, coupled to the delay logic unit and the status flag storage unit, is configured to perform the signal output step.
[0013] Based on the same inventive concept, the present invention also provides a DDR interface verification system for verifying the calibration function of the physical layer interface PHY, the system comprising: At least one of the bidirectional signal delay devices described above; The bidirectional signal delay device is connected in series on the bidirectional data signal line DQ and / or the data strobe signal line DQS between the PHY and memory model of the system-on-a-chip (SOC). Specifically, by configuring the delay parameters of the bidirectional signal delay device, the signal delay caused by PCB trace delay and PVT variation can be simulated without modifying the PHY's PAD model or memory model.
[0014] Preferred, including: The system is configured for multi-rank memory verification scenarios; Among them, the same set of bidirectional data signal lines DQn of the system-on-a-chip (SOC) is connected to multiple memory chip models through multiple bidirectional signal delay devices; Each of the bidirectional signal delay devices is independently configured with different delay parameters to simulate the independent delay characteristics of different memory chips.
[0015] Based on the same concept, the present invention also provides an electronic device, comprising: a memory for storing a processing program; and a processor that, when executing the processing program, implements the general DDR latency model verification method described in any one of the above embodiments.
[0016] Based on the same concept, the present invention also provides a readable storage medium storing a processing program, which, when executed by a processor, implements the general DDR latency model verification method described in any one of the above.
[0017] Because the present invention adopts the above technical solution, it has the following advantages and positive effects compared with the prior art: This invention provides a universal, reconfigurable method for verifying bidirectional signal delays, fundamentally solving the technical problem of easily forming combinational logic loops when adding delays to bidirectional signals (such as DQ / DQS) in digital simulations. By dynamically managing signal direction through status flags, it enables the independent insertion of configurable delays without any modifications to the PHY or memory model, greatly improving the flexibility and efficiency of DDR interface verification, especially calibration function verification. Attached Figure Description
[0018] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, wherein: Figure 1 This is a diagram of the device architecture used for existing technology verification. Figure 2 A device architecture diagram for verifying another existing technology; Figure 3 This is a schematic diagram of the verification method for the general DDR latency model of the present invention. Detailed Implementation
[0019] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0020] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.
[0021] like Figure 1As shown, to verify the calibration function of a PHY, it is usually necessary to simulate the delays of different signal lines on the PCB and the pin signal delay variations of the SOC or memory under different PVT conditions by using different signal delays. While implementing the delay of a unidirectional port of a CA signal is very easy in Verilog or System Verilog, implementing the delay function of a simple bidirectional port like DQ / DQS is difficult due to syntax limitations and can easily lead to combinational loops. If bidirectional delays like DQ / DQS cannot be implemented, the same effect can only be achieved by adding the input and output delays of the PAD model in the PHY separately. Alternatively, the same effect can be achieved by adding the input and output delays of the memory model separately.
[0022] See Figure 2 For scenarios requiring verification of multiple ranks, the same DQn signal of the SOC needs to be connected to the DQn signals of different memory chips simultaneously. If a bidirectional port delay module cannot be implemented, the PHY calibration function can only be verified by modifying the input and output delays of the memory during simulation. In this case, even modifying the input and output delays of the PHY's PAD model cannot achieve delay control for different memory chips.
[0023] Example See Figure 3 This embodiment provides a general DDR latency model verification method, including the following steps: Set the first input status flag INA, the second input status flag INB, the first delay status flag INA_Delayed, and the second delay status flag INB_Delayed to an invalid state; By monitoring the signal status of the first bidirectional port A and the second bidirectional port B, the first input status flag INA and the second input status flag INB are dynamically set to determine the currently valid signal transmission direction and avoid forming combinational logic loops. Based on the first input status flag INA and the preset delay requirement, a delayed signal A2B is generated from the first bidirectional port A to the second bidirectional port B; and based on the second input status flag INB and the preset delay requirement, a delayed signal B2A is generated from the second bidirectional port B to the first bidirectional port A. Based on the first delay status flag INA_Delayed and the second delay status flag INB_Delayed, the delayed signal A2B and the delayed signal B2A are output to the corresponding bidirectional ports.
[0024] This embodiment provides a general, reconfigurable method for verifying bidirectional signal delays, fundamentally solving the technical challenge of easily forming combinational logic loops when adding delays to bidirectional signals (such as DQ / DQS) in digital simulations. By dynamically managing signal direction through status flags, configurable delays can be independently inserted without any modifications to the PHY or memory model, greatly improving the flexibility and efficiency of DDR interface verification, especially calibration function verification.
[0025] Once the DQ / DQS model is programmed using the method described in this patent, verification at the SOC level only requires instantiating different latency modules according to different verification requirements. No modification to the PHY model or memory model is necessary. In fact, some memory models cannot be directly modified due to vendor encryption.
[0026] For the delay module of a bidirectional port, data transmitted from port A is sent to port B, but if data is generated at port B, the same data is transmitted back to port A via port B. This creates a logical data loop. The technical solution uses the first input status flag INA, the second input status flag INB, the first delay status flag INA_delayed, and the second delay status flag INB_delayed to record the actual transmission direction of the current signal, thus breaking this logical data loop. At the first moment of bidirectional signal transmission, when there is no high impedance, the validity of ports A and B is recorded to determine the direction of the transmitted signal. After fulfilling the signal delay transmission requirement, the process returns to the signal transmission detection stage, repeating this process.
[0027] Preferably, monitoring the signal states of the first bidirectional port A and the second bidirectional port B further includes: In response to detecting a change in the signal state of the first bidirectional port A, determine whether it is in a high-impedance state; If the first bidirectional port A is in a high-impedance state, then the first input status flag INA is set to invalid. If the first bidirectional port A is not in a high-impedance state, check whether the second input status flag INB and the second delay status flag INB_Delayed are both invalid; If both the second input status flag INB and the second delay status flag INB_Delayed are invalid, then the first input status flag INA is set to valid; A symmetrical detection and judgment process is performed on the second bidirectional port B to set the second input status flag INB.
[0028] This embodiment provides a specific, reliable, and unambiguous signal direction detection and loop interruption mechanism. By checking the status flags of the peer port, the data transmission direction is precisely arbitrated, ensuring that only one direction of drive is valid at any given time. This stably and reliably avoids logic races and loop problems in simulation.
[0029] Preferably, outputting the delayed signal A2B and the delayed signal B2A to the corresponding bidirectional port according to the first delay status flag INA_Delayed and the second delay status flag INB_Delayed further includes: When the second delay status flag INB_Delayed is valid, the delay signal B2A is driven to the first bidirectional port A; otherwise, the first bidirectional port A is set to a high impedance state. When the first delay status flag INA_Delayed is valid, the delayed signal A2B is driven to the second bidirectional port B; otherwise, the second bidirectional port B is set to a high impedance state.
[0030] This embodiment provides a deterministic and secure signal output scheme based on directional arbitration results. It ensures that the delayed signal is driven to the port only in the correct transmission direction, while the port is set to a high-impedance state during non-driving moments. This perfectly simulates the behavior of real bidirectional I / O, guaranteeing the correctness of the simulation model and its consistency with the real circuit.
[0031] Preferably, the method operates at the delta-cycle accuracy of the simulator without relying on internal or external clock signals.
[0032] This embodiment achieves the highest precision delay control and simplifies module integration. Utilizing the simulator kernel's delta-cycle mechanism, it provides finer timing control than any fixed clock cycle. Simultaneously, it eliminates the need for clock generation and configuration, reducing the complexity of module usage and the workload of integration and verification engineers.
[0033] Preferably, a state machine is implemented within the module, wherein the state machine is driven by an internal clock signal, and its state transitions are based on the current signal states of the first bidirectional port A and the second bidirectional port B.
[0034] In implementing the bidirectional delay module, this embodiment serves as an alternative solution. It achieves the delay in both signal transmission directions by implementing a state machine within the module. Since a state machine is required, a clock needs to be generated within the module. This clock generation raises the question of its frequency. Furthermore, the SOC integration verification personnel may need to configure the clock with different precisions based on the specific project requirements.
[0035] Based on the same inventive concept, the present invention also provides a bidirectional signal delay device for digital circuit simulation, the device being used to implement the method, the device comprising: A status flag storage unit is used to store the first input status flag INA, the second input status flag INB, the first delayed status flag INA_Delayed, and the second delayed status flag INB_Delayed; The direction control logic unit, coupled to the status flag storage unit, is configured to perform the direction detection and loop interruption steps; A delay logic unit, coupled to the direction control logic unit and the status flag storage unit, is configured to perform the delay signal generation step; An output driving unit, coupled to the delay logic unit and the status flag storage unit, is configured to perform the signal output step.
[0036] The complex bidirectional delay processing logic is encapsulated into an independent device with clearly defined interfaces (port A, port B) and internal functional units (storage, control, delay, and drive). Verification engineers do not need to understand the complex internal direction arbitration algorithm; they only need to instantiate this device on the bidirectional signal lines between the SOC and the memory model and set the delay parameters. This avoids writing error-prone delay code in a scattered and repetitive manner in existing verification platforms, greatly simplifying system integration and improving the efficiency and quality of verification platform construction. Through clear internal unit division (storage, control, delay, and drive), the functions of signal direction determination, delay calculation, and signal driving are decoupled.
[0037] Based on the same inventive concept, the present invention also provides a DDR interface verification system for verifying the calibration function of the physical layer interface PHY, the system comprising: At least one of the bidirectional signal delay devices described above; The bidirectional signal delay device is connected in series on the bidirectional data signal line DQ and / or the data strobe signal line DQS between the PHY and memory model of the system-on-a-chip (SOC). Specifically, by configuring the delay parameters of the bidirectional signal delay device, the signal delay caused by PCB trace delay and PVT variation can be simulated without modifying the PHY's PAD model or memory model.
[0038] By "cascading" the latency device between the SOC PHY and the memory model, complete decoupling of latency control logic from the existing design model is achieved. No modification is needed to the PHY's PAD model (typically provided by the IP vendor and may be encrypted or black-box) or the memory model (such as an encrypted model from the memory vendor). This is the most practical advantage, making verification feasible in commercialization and real-world engineering. It avoids errors that might be introduced by directly modifying the model and ensures that the model's behavior itself is consistent with the official definition; all latency effects are explicitly attributed to the externally inserted device.
[0039] Preferred, including: The system is configured for multi-rank memory verification scenarios; Among them, the same set of bidirectional data signal lines DQn of the system-on-a-chip (SOC) is connected to multiple memory chip models through multiple bidirectional signal delay devices; Each of the bidirectional signal delay devices is independently configured with different delay parameters to simulate the independent delay characteristics of different memory chips.
[0040] This embodiment addresses a long-standing and most challenging issue in the verification of multi-rank (multi-select) DDR systems—how to simulate independent and parallel timing environments for different memory chips (ranks) sharing the same physical channel within the same simulation, in order to comprehensively verify the effectiveness of the PHY calibration algorithm under real-world multi-load scenarios. Physically, the same set of DQ / DQS signal lines of the SOC are connected to multiple memory ranks in the form of a "bus." Traditional methods cannot apply different delays to different "branches" on this shared bus. By independently instantiating a delay device for each rank, the real physical connection is accurately reproduced at the simulation level—that is, the path length (delay) from each rank to the SOC is essentially independent. This allows the SOC to see signals from different ranks with different timings.
[0041] Based on the same concept, the present invention also provides an electronic device, comprising: a memory for storing a processing program; and a processor that, when executing the processing program, implements the general DDR latency model verification method described in any one of the above embodiments.
[0042] Based on the same concept, the present invention also provides a readable storage medium storing a processing program, which, when executed by a processor, implements the general DDR latency model verification method described in any one of the above.
[0043] If the general DDR latency model verification method is implemented as program instructions and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this embodiment, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in software. This computer software is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0044] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific identification content executed by the system and device described above can be referred to the corresponding process in the foregoing method embodiments.
[0045] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, if these changes fall within the scope of the claims of the present invention and their equivalents, they shall still fall within the protection scope of the present invention.
Claims
1. A general DDR latency model verification method, characterized in that, Includes the following steps: Set the first input status flag INA, the second input status flag INB, the first delay status flag INA_Delayed, and the second delay status flag INB_Delayed to an invalid state; By monitoring the signal status of the first bidirectional port A and the second bidirectional port B, the first input status flag INA and the second input status flag INB are dynamically set to determine the currently valid signal transmission direction and avoid forming combinational logic loops. Based on the first input status flag INA and the preset delay requirement, a delayed signal A2B is generated from the first bidirectional port A to the second bidirectional port B; and based on the second input status flag INB and the preset delay requirement, a delayed signal B2A is generated from the second bidirectional port B to the first bidirectional port A. Based on the first delay status flag INA_Delayed and the second delay status flag INB_Delayed, the delayed signal A2B and the delayed signal B2A are output to the corresponding bidirectional ports.
2. The universal DDR latency model verification method according to claim 1, characterized in that, Monitoring the signal status of the first bidirectional port A and the second bidirectional port B further includes: In response to detecting a change in the signal state of the first bidirectional port A, determine whether it is in a high-impedance state; If the first bidirectional port A is in a high-impedance state, then the first input status flag INA is set to invalid. If the first bidirectional port A is not in a high-impedance state, check whether the second input status flag INB and the second delay status flag INB_Delayed are both invalid; If both the second input status flag INB and the second delay status flag INB_Delayed are invalid, then the first input status flag INA is set to valid; A symmetrical detection and judgment process is performed on the second bidirectional port B to set the second input status flag INB.
3. The universal DDR latency model verification method according to claim 1, characterized in that, Outputting the delayed signal A2B and the delayed signal B2A to the corresponding bidirectional port based on the first delay status flag INA_Delayed and the second delay status flag INB_Delayed further includes: When the second delay status flag INB_Delayed is valid, the delay signal B2A is driven to the first bidirectional port A; otherwise, the first bidirectional port A is set to a high impedance state. When the first delay status flag INA_Delayed is valid, the delayed signal A2B is driven to the second bidirectional port B; otherwise, the second bidirectional port B is set to a high impedance state.
4. The universal DDR latency model verification method according to claim 1, characterized in that, The method operates at delta-cycle accuracy in the simulator and does not rely on internal or external clock signals.
5. The universal DDR latency model verification method according to claim 1, characterized in that, A state machine is implemented within the module, which is driven by an internal clock signal, and its state transitions are based on the current signal states of the first bidirectional port A and the second bidirectional port B.
6. A bidirectional signal delay device for digital circuit simulation, the device being used to implement the method as described in any one of claims 1 to 5, characterized in that, The device includes: A status flag storage unit is used to store the first input status flag INA, the second input status flag INB, the first delayed status flag INA_Delayed, and the second delayed status flag INB_Delayed; The direction control logic unit, coupled to the status flag storage unit, is configured to perform the direction detection and loop interruption steps; A delay logic unit, coupled to the direction control logic unit and the status flag storage unit, is configured to perform the delay signal generation step; An output driving unit, coupled to the delay logic unit and the status flag storage unit, is configured to perform the signal output step.
7. A DDR interface verification system for verifying the calibration function of the physical layer interface PHY, characterized in that, The system includes: At least one bidirectional signal delay device as described in claim 6; The bidirectional signal delay device is connected in series on the bidirectional data signal line DQ and / or the data strobe signal line DQS between the PHY and memory model of the system-on-a-chip (SOC). Specifically, by configuring the delay parameters of the bidirectional signal delay device, the signal delay caused by PCB trace delay and PVT variation can be simulated without modifying the PHY's PAD model or memory model.
8. The DDR interface verification system according to claim 7, characterized in that, include: The system is configured for multi-rank memory verification scenarios; Among them, the same set of bidirectional data signal lines DQn of the system-on-a-chip (SOC) is connected to multiple memory chip models through multiple bidirectional signal delay devices; Each of the bidirectional signal delay devices is independently configured with different delay parameters to simulate the independent delay characteristics of different memory chips.
9. An electronic device, characterized in that, include: The memory is used to store the processing program; A processor that, when executing the processing program, implements the general DDR latency model verification method as described in any one of claims 1 to 7.
10. A readable storage medium, characterized in that, The readable storage medium stores a processing program, which, when executed by a processor, implements the general DDR latency model verification method as described in any one of claims 1 to 7.