Transmission operation completion notification method, electronic equipment, storage medium and product

Abstract

The invention discloses a transmission operation completion notification method, electronic equipment, a storage medium and a product, and relates to the technical field of data transmission, and the method comprises the following steps: when it is detected that a count value recorded by a target counter in slave equipment is non-zero and the state of an identification information queue of the slave equipment is a non-null state, sending a notification message to the slave equipment; a state of the write response valid signal may be set to a valid state. And when detecting that the states of the write response receiving preparation signal and the write response effective signal are both effective states, transmitting the first received target write address identification information read from the identification information queue to the master device. And finally, after receiving the target write address identification information and the write response effective signal in the effective state, the main device can determine that the target transmission operation of the target emergency is completed. According to the design, the slave device can correctly complete the notification operation of the completion of the transmission operation of the emergencies.

Description

Technical Field

[0001] This application relates to the field of data transmission technology, and in particular to methods, electronic devices, storage media, and products for notifying the completion of transmission operations. Background Technology

[0002] In the field of data transmission technology, the Advanced eXtensible Interface (AXI) protocol defines five independent transaction channels based on burst events: read address channel, read data channel, write address channel, write data channel, and write response channel. On the slave device side of the AXI protocol, the write address typically arrives before the write data, or they arrive simultaneously. Accordingly, once the slave device has received all the write data from the burst event, it will notify the master device that the transmission operation for that burst event is complete.

[0003] However, when the number of register levels in the write address channel is greater than that in the write data channel, data may arrive before the address. If the current design is followed, the write address may not be received when the last write data is received, leading to the slave device incorrectly notifying the master device that the transmission operation is complete. Summary of the Invention

[0004] This application provides a method, apparatus, electronic device, storage medium, and program product for notifying the master device of the completion of a transmission operation, in order to solve the problem of a slave device incorrectly notifying the master device of the completion of a transmission operation.

[0005] This application provides a method for notifying the completion of a transmission operation, including: When it is detected that the count value recorded in the target counter included in the slave device is non-zero and the status of the identification information queue in the slave device is non-empty, the status of the write response valid signal of the write response channel between the master device and the slave device is set to valid. The identification information queue is used to store the write address identification information of at least one burst event, and the target counter is used to record the number of burst events that have completed the write data transmission operation. When the write response receive preparation signal and the write response valid signal in the write response channel are both detected to be in a valid state, the target write address identifier information that was received first is read from at least one write address identifier information stored in the identifier information queue. The target write address identification information is transmitted to the master device through the write response channel. The write response valid signal and the target write address identification information in the valid state are used to jointly notify the master device that the target transmission operation corresponding to the target burst event corresponding to the target write address identification information has been completed. The target transmission operation includes write data transmission operation and write address transmission operation.

[0006] This application also provides a notification device for the completion of a transmission operation, comprising: The setting module is used to set the status of the write response valid signal of the write response channel between the master device and the slave device to valid when the count value recorded in the target counter included in the slave device is non-zero and the status of the identification information queue in the slave device is non-empty. The identification information queue is used to store the write address identification information of at least one burst event, and the target counter is used to record the number of burst events that have completed the write data transmission operation. The reading module is used to read the first received target write address identifier from at least one write address identifier stored in the identifier information queue when the write response receive preparation signal and the write response valid signal in the write response channel are both in a valid state. The transmission module is used to transmit the target write address identification information to the master device through the write response channel. The write response valid signal and the target write address identification information in the valid state are used to jointly notify the master device that the target transmission operation corresponding to the target burst event corresponding to the target write address identification information has been completed. The target transmission operation includes write data transmission operation and write address transmission operation.

[0007] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of the notification method for the completion of any of the above-described transmission operations.

[0008] This application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of the notification method for the completion of any of the above-described transmission operations.

[0009] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the notification method for the completion of any of the above-described transmission operations.

[0010] This application demonstrates that when the target counter in the slave device records a non-zero count and the slave device's identification information queue is not empty, it indicates the presence of a burst event where complete write data and write address have been received. This allows for notification of transmission operation completion. Accordingly, the write response valid signal can be set to a valid state, enabling transmission to the master device. When both the write response receive ready signal and the write response valid signal are valid, the write response channel handshake is complete. Furthermore, the slave device can transmit the first received target write address identification information read from its identification information queue to the master device. Finally, upon receiving the target write address identification information and the valid write response signal, the master device can determine that the target transmission operation for the burst event has been completed. This design supports writing data ahead of writing address for multiple cycles, meaning the slave device can correctly complete the notification of burst event transmission operation completion without needing to consider the order of write data and write address. Attached Figure Description

[0011] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This application provides a schematic diagram of the architecture of a data transmission system according to an embodiment of the present application. Figure 2 This is a schematic diagram of the architecture of another data transmission system provided in an embodiment of this application; Figure 3 This is a schematic diagram illustrating the dependencies between signals provided in the embodiments of this application; Figure 4 A flowchart illustrating a method for notifying the completion of a transmission operation, as provided in an embodiment of this application; Figure 5 A schematic diagram of the signal logic relationship of a write response channel provided in an embodiment of this application; Figure 6 A schematic diagram of the signal logic relationship of a write data channel provided in an embodiment of this application; Figure 7 A schematic diagram of the signal logic relationship of a write address channel provided in an embodiment of this application; Figure 8 A complete signal logic relationship diagram is provided for an embodiment of this application; Figure 9 A flowchart illustrating a notification device for the completion of a transmission operation, provided in an embodiment of this application; Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0013] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0014] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0015] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0016] The method for notifying the completion of the transmission operation provided in this application can be implemented by a data transmission system, such as... Figure 1 As shown, a data transmission system can include a master device and slave devices, with the master device connecting to the slave devices. Under the Advanced eXtensible Interface (AXI) protocol, five independent transaction channels can be set up between the master and slave devices: a read address channel, a read data channel, a write address channel, a write data channel, and a write response channel. The read address channel is used to transmit the address of the data being transmitted, or other control information. The read data channel can be used to transmit data read from the slave device to the master device. The write address channel can be used to transmit write commands and write address identifier (AWID) information. The write command can include the write address and other control information, such as burst length and burst size. The write data channel can be used to transfer write data from the master device to the slave device. The write response channel can be used by the slave device to notify the master device that the transmission operation is complete.

[0017] Each of the aforementioned transaction channels has its own valid and ready signals for handshaking. The valid signal generated by the source indicates when the transmitted signal is available. The ready signal generated by the destination indicates that it is ready to receive the transmitted signal. The transmission operation will only be performed when both the valid and ready signals are valid.

[0018] In the direction of writing data from the master device to the slave device, there are three independent channels: the write address channel, the write data channel, and the write response channel. (See reference) Figure 2 This describes the dependencies between three sets of handshake signals. The valid signals for the write address channel can be called the write address valid signal (AWVALID) and the write address receive ready signal (AWREADY). The valid signals for the write data channel can be called the write data valid signal (WVALID) and the write data receive ready signal (WREADY). The valid signals for the write response channel can be called the write response valid signal (BVALID) and the write response receive ready signal (BREADY).

[0019] In addition to the handshake signals mentioned above, other signals also need to be transmitted on each transaction channel.

[0020] Table 1 shows the main transmission signals of the write data channel, including the write data signal, the last write data flag signal, the write data valid signal, and the write data ready signal. Taking the slave device as the reference, the write data signal, the last write data flag signal, and the write data valid signal are all input signals of the slave device, while the write data ready signal is the output signal of the slave device.

[0021] Table 1

[0022] In the AXI protocol, a sudden event generally refers to a continuous transmission of multiple write data.

[0023] Table 2 shows the main transmission signals of the write address channel, including write address identification information, write address, burst length, burst size, write address valid signal, and write address receive ready signal. Taking the slave device as the reference, write address identification information, write address, burst length, burst size, and write address valid signal are all input signals of the slave device, while write address receive ready signal is the output signal of the slave device.

[0024] Table 2

[0025] Table 3 shows the main transmission signals of the write response channel, including the write address identification information signal, the write response signal, the write response valid signal, and the write response ready to receive signal. Taking the slave device as the reference, the write address identification information signal, the write response signal, and the write response valid signal are all input signals of the slave device, while the write response ready to receive signal is the output signal of the slave device.

[0026] Table 3

[0027] Continue to refer to Figure 2 In this context, a single arrow indicates a signal that is valid before or after the preceding signal (the signal at the start of the arrow), while a double arrow indicates a signal that is valid only after the preceding signal is valid. Correspondingly, the AXI protocol stipulates that the write response signal must be sent after the last write data of the transaction. However, the AXI protocol does not specify a dependency between the write address and the write data; that is, the write data can appear before the corresponding write address or appear in the same period as the write address. Furthermore, when the number of register levels in the write address channel exceeds the number of register levels in the write data channel, the write data may appear before the corresponding write address, meaning the write response signal may appear before the write address, causing the slave device to incorrectly notify the master device that the transmission operation is complete.

[0028] like Figure 3 As shown, in streaming image processing, image data is streamed out under the acquisition of image sensors, but the write address needs to be calculated for a period of time to obtain. In order to improve data transmission efficiency, the write data will be sent before the write address. That is, on the slave device side, the write data will appear before the write address, causing the slave device to send an incorrect write response signal to the master device.

[0029] Embodiments of this application provide a method for notifying the completion of a transmission operation, which can be executed by the aforementioned slave device, such as... Figure 4 As shown, the specific processing steps of the notification method for the completion of the transmission operation may include: Step S401: When it is detected that the count value recorded in the target counter included in the slave device is non-zero and the status of the identification information queue in the slave device is non-empty, the status of the write response valid signal of the write response channel between the master device and the slave device is set to valid.

[0030] The identification information queue can be used to store the write address identification information of at least one burst event, and the target counter is used to record the number of burst events that have completed write data transmission operations.

[0031] Specifically, a dedicated counter (i.e., a target counter) can be set in the device to record the number of burst events in which complete write data has been received. For example, burst event 1 corresponds to 10 write data entries. When 10 write data entries are received, the complete write data for the burst event is received, meaning the write data transmission operation corresponding to burst event 1 is complete. Furthermore, an identification information queue can typically be used to store the write address identification information corresponding to each burst event. Each write address identification information entry indicates that a write address corresponding to a burst event has been received.

[0032] Based on this, when the slave device detects that the count value recorded in the target counter is non-zero and the status of the identification information queue is not empty, the slave device can determine that there is a burst event in which both write data transmission and write address transmission operations have been completed, and that this burst event has not transmitted a write response signal. Therefore, the slave device can set the status of the write response valid signal of the write response channel to a valid state, for example, to a high level. In this way, the master device can receive the write response valid signal transmitted by the slave device in a valid state, and then determine whether to set the status of the write response receive preparation signal to a valid state according to its own data processing rules. For example, if it is ready to receive, it can set the status of the write response receive preparation signal to a valid state.

[0033] Step S402: When it is detected that both the write response receive preparation signal and the write response valid signal in the write response channel are in a valid state, the target write address identifier information that was received first is read from at least one write address identifier information stored in the identifier information queue.

[0034] Specifically, when both the write response receive ready signal and the write response valid signal are detected as valid, it indicates that the master device and the slave device have completed their handshake and can proceed with signal transmission. Accordingly, the slave device can read the first received target write address identifier from at least one write address identifier included in the identifier information queue. For example, when the identifier information queue is a First-In-First-Out (FIFO) queue, the write address identifier can be directly extracted from the tail of the identifier information queue as the target write address identifier, meaning the first received target write address identifier has been read.

[0035] refer to Figure 5The write response receive ready signal and the write response valid signal can be connected to a first AND gate. The first AND gate controls the state of the first read enable signal based on the result of the AND operation on these two signals. In other words, the first read enable signal controls whether a read operation is performed on the identification information queue. For example, when both the write response receive ready signal and the write response valid signal are valid, the slave device can use the first AND gate to set the state of the first read enable signal to valid. That is, when the slave device detects that both the write response receive ready signal and the write response valid signal are valid, it can read the write address identification information at the tail of the identification information queue and transmit it to the master device.

[0036] Step S403: Transmit the target write address identification information to the master device through the write response channel.

[0037] Among them, the write response valid signal and the target write address identification information in the valid state are used to jointly notify the master device that the transmission operation corresponding to the target burst event corresponding to the target write address identification information has been completed.

[0038] Specifically, after completing the extraction of the target write address identifier information, the slave device can send the target write address identifier information to the master device through the write response channel. In this way, the master device can receive the write response signal (including the write response validity signal in the valid state and the target write address identifier information), and match the received target write address identifier information as the received write response signal to determine that the target transmission operation with the target burst event has been completed.

[0039] Additionally, after the device detects that the write response reception preparation signal is valid, the write response valid signal for the next clock cycle can be pulled low to restore it to an invalid state (which can be a low level), so that the transmission operation of the write response signal for the next burst event can be restarted.

[0040] The transmission operation completion notification method of this application, when detecting that the count value recorded by the target counter in the slave device is non-zero and the state of the slave device's identification information queue is not empty, indicates that a burst event has occurred in which complete write data and write address have been received, and a transmission operation completion notification can be made. Accordingly, the state of the write response valid signal can be set to valid, allowing the valid write response signal in the valid state to be transmitted to the master device. When both the write response receive ready signal and the write response valid signal are detected to be valid, it indicates that the write response channel has completed its handshake. Additionally, the slave device can transmit the target write address identification information read first from the identification information queue to the master device. Finally, after receiving the target write address identification information and the valid write response signal in the valid state, the master device can determine that the target transmission operation of the target burst event has been completed. With this design, it is possible to support write data preceding write address by multiple cycles; that is, without needing to consider the order of write data and write address, the slave device can correctly complete the transmission operation completion notification operation for the burst event.

[0041] In some alternative implementations, since the target burst event requires the transmission of at least one write data, to ensure that the slave device can correctly process the write data, the slave device writes the received write data into the slave device's data queue whenever it receives a write data corresponding to the target burst event from the master device. For example, this data queue can be a FIFO queue.

[0042] refer to Figure 6 The slave device can connect the write data valid signal and the write data receive ready signal to a second AND gate. The second AND gate performs a bitwise AND operation on the write data valid signal and the write data receive ready signal. Based on the result of the bitwise AND operation, the slave device can control the state of the first write enable signal, thereby controlling whether to perform a write operation on the identification information queue. For example, when both the write data valid signal and the write data receive ready signal are detected to be valid, the slave device can use the second AND gate to set the state of the first write enable signal to be valid. In other words, the slave device will only write the received write data to the data queue when both the write data valid signal and the write data receive ready signal are detected to be valid.

[0043] In some optional implementations, the slave device can update the number of burst events recorded in the target counter based on the burst event transmission completion indication information. The update can be an increase or a decrease. The transmission completion indication information can be used to indicate whether all write data corresponding to the burst event has been received, or it can be used to indicate whether a read operation of the write address identifier information corresponding to the burst event is in progress. Accordingly, it can include the following two cases: In scenario one, when it is determined that all write data corresponding to at least one write data item for the target burst event has been received, the count value recorded in the target counter is increased by a first preset value.

[0044] Specifically, taking a target emergency as an example, when the device receives the last write data corresponding to the target emergency, it means that the device has received all the write data corresponding to the target emergency, that is, the write data transmission operation of one emergency has been completed. At this time, the count value recorded by the target counter can be increased by a first preset value. For example, the first preset value can be 1.

[0045] In scenario two, when a read operation on the identification information queue is detected, the count value recorded in the target counter is reduced by a first preset value.

[0046] Specifically, when a device detects that it is currently reading from the identification information queue, it indicates that the device is transmitting a write response signal corresponding to a sudden event. Accordingly, the device can reduce the count value recorded in the target counter by a first preset value to indicate the completion of the transmission operation of a write response signal for a sudden event.

[0047] In this way, only a target counter is needed, and the count value of the target counter is updated by simple logic settings based on the completion status of write data transmission operations and write address transmission operations of sudden events. This indicates whether to perform a write response signal transmission operation. The operation is simple and occupies less hardware resources.

[0048] refer to Figure 5 When the device detects that the first read enable signal is in a valid state, it can be determined that a read operation on the identification information queue has been detected. At this time, the count value recorded in the counter can be decremented by 1.

[0049] In some optional implementations, in the first scenario described above, the slave device can specifically determine whether it has received the last write data of the target burst event based on the status of the write data related signals transmitted through the write data channel. The write data related signals may include the write data valid signal, the write data receive ready signal, and the last write data signal. Accordingly, when the slave device detects that the status of the write data valid signal, the write data receive ready signal, and the last write data signal in the write data channel between the master device and the slave device are all valid, it determines that it has received all the write data in at least one write data corresponding to the target burst event.

[0050] Specifically, the write data valid signal in the valid state is used to indicate that the master device is ready to write data, the write data receive ready signal in the valid state is used to indicate that the slave device is ready to receive write data, and the last write data signal in the valid state is used to indicate the last write data in at least one write data corresponding to the current burst event being transmitted. When all three of these states are valid, it can be determined that the slave device has received the last write data, that is, it has received all the write data corresponding to the target burst event.

[0051] In this way, by monitoring various signals transmitted through the write data channel and making simple logical judgments, it can be determined whether all write data corresponding to a sudden event has been received. The logic is simple, and most of the original transmission link resources can be reused, resulting in low cost.

[0052] refer to Figure 5 The write data valid signal, write data ready signal, and last write data signal can be connected to the counter. Accordingly, when the states of the write data valid signal, write data ready signal, and last write data signal are all detected to be valid, the slave device can increment the count value recorded in the counter by 1.

[0053] In some optional implementations, the write data receive preparation signal is an output signal of the slave device, controlled by the slave device. Accordingly, the slave device can set the state of the write data receive preparation signal according to the remaining space of the data queue, specifically including the following two cases: In scenario one, when the first write operation to the data queue is detected and it is determined that the remaining space in the data queue is equal to the second preset value, the state of the write data receive preparation signal is set to invalid state to notify the master device that the slave device is not ready to receive the next write data after the current write data corresponding to the first write operation.

[0054] Specifically, when the slave device detects that it is currently writing received write data into the data queue (i.e., the first write operation), and the remaining space in the data queue is a second preset value (e.g., 1), it indicates that the data queue is full after the slave device completes the first write operation and cannot store new write data. At this time, the slave device can set the status of the write data receive preparation signal for the next cycle to an invalid state. In this way, the master device can detect the write data receive preparation signal in an invalid state, determine that the slave device is not ready to receive the next write data, and stop the write data transmission operation.

[0055] In scenario two, when the remaining space in the data queue is detected to be greater than or equal to the second preset value, the write data receive preparation signal is set to an active state to notify the master device that the slave device is ready to receive the next write data.

[0056] Specifically, after the slave device detects that the remaining space in the data queue is greater than or equal to the second preset value, it indicates that the data queue is not full. That is, in all cases except case one, as long as the data queue is not full, the slave device can set the write data receive preparation signal for the next cycle to an active state. In this way, the master device can detect the write data receive preparation signal in an active state, determine that the slave device is ready to receive the next write data, and can continue to transmit the next write data.

[0057] In this way, while ensuring that the notification operation for the completion of the transmission operation can be executed accurately, the slave device only needs to monitor the remaining space in the data queue and perform write operations to determine whether to receive the next write data, which is relatively simple.

[0058] refer to Figure 6 The remaining space in the data queue and the state of the write enable signal can be used together to set the state of the write data receive ready signal. Furthermore, the slave device can determine whether a first write operation is currently being performed on the data queue based on the state of the first write enable signal. For example, when the first write enable signal is detected as valid, it is determined that a first write operation on the data queue has been detected. Additionally, the data queue can also receive read data signals and read enable signals, allowing subsequent modules after the slave device to perform data read operations. Furthermore, subsequent modules can also obtain the remaining space in the data queue, for example, to obtain the readable space of the data queue.

[0059] In some optional implementations, to ensure data processing accuracy, the master device can transmit commands including address and structure information related to the write data to the slave device. This information can also be transmitted via the write address channel. Correspondingly, when a target write command corresponding to a target burst event is received from the master device via the write address channel between the master and slave devices, the target write command is written to the slave device's command queue. For example, the command queue can be a FIFO queue.

[0060] In this way, by temporarily storing the write command, it can be ensured that subsequent candidate modules can read the correct write data based on this write command.

[0061] refer to Figure 7The slave device can connect the write address valid signal and the write address receive ready signal to a third AND gate for a bitwise AND operation. Based on the result of the AND operation, the slave device can control the state of the second write enable signal, thus controlling whether to perform a write operation on the command queue. For example, when both the write address valid signal and the write address receive ready signal are detected as valid, the slave device can use the third AND gate to set the second write enable signal to be valid. In other words, the slave device will only write the received write command to the command queue when both the write address valid signal and the write address receive ready signal are detected as valid.

[0062] In some optional implementations, the write address receive ready signal is an output signal of the slave device, controlled by the slave device. Accordingly, the slave device can set the state of the write address receive ready signal according to the size of the remaining space in the command queue, specifically including the following two cases: In scenario one, when a second write operation to the command queue is detected, and the remaining space in the command queue or the remaining space in the identification information queue is a third preset value, the write address receive preparation signal is set to an invalid state to notify the master device that the slave device is not ready to receive the next write address after the current write address corresponding to the second write operation.

[0063] Specifically, when the slave device detects that a write command is being written to the command queue (i.e., the second write operation), and the remaining space in the command queue or the remaining space in the identification information queue is a third preset value (e.g., 1), it indicates that the command queue is full after the current write command is written, and no new write command can be stored. Furthermore, since there is a one-to-one correspondence between the messages stored in the command queue and the identification information queue, the slave device can also determine whether the remaining space in the identification information queue is the third preset value. If it is, it indicates that the identification information queue is full, indirectly indicating that the command queue is full and no new command can be stored. At this time, the slave device can set the write address receive preparation signal to an invalid state. In this way, the master device can detect an invalid write address receive preparation signal and will not transmit the next write address to the slave device.

[0064] In scenario two, when the remaining space in the command queue and the identification information queue is detected to be greater than or equal to the third preset value, the write address receive preparation signal is set to an active state to notify the master device that the slave device is ready to receive the next write address.

[0065] Specifically, in all cases except Case 1, the write address receive preparation signal is only set to a valid state when both the command queue and the identification information queue are detected to be in a non-full state (i.e., the remaining space in the command queue and the identification information queue is greater than or equal to the third preset threshold). In this way, the master device can detect a valid write address receive preparation signal and transmit the next write address to the slave device.

[0066] In this way, while ensuring that the notification operation for the completion of the transmission operation can be executed correctly, it is only necessary to monitor the remaining space of the command queue and the write operation and make simple logical judgments to accurately determine whether to receive the next write address.

[0067] refer to Figure 7 The remaining space in the command queue and the state of the second write enable signal can be used together to set the state of the write address receive ready signal. Furthermore, the slave device can determine whether a second write operation is currently being performed on the command queue based on the state of the second write enable signal; for example, if the second write enable signal is detected as valid, it indicates that a second write operation has been detected on the command queue. Additionally, the command queue can also receive read data and read enable signals to enable command reading operations by other modules following the slave device. Subsequent modules can also obtain the remaining space in the command queue, for example, the readable space. Subsequent modules can then read relevant content from the data queue based on information such as the write address, burst length, and burst size included in the command.

[0068] refer to Figure 5 The second write enable signal can also be used to control write operations to the identification information queue. For example, when the state of the second write enable signal is detected to be valid, the received write address identification information can be written into the identification information queue.

[0069] In some optional implementations, the write data channel can also be used to transmit a write strobe signal, which indicates the position of a valid byte in the write data. The transmission periods of the write strobe signal and the write data can be the same, that is, the slave device can simultaneously receive valid write data and the corresponding write strobe signal. Then, the slave device can concatenate the write strobe signal and the write data signal and store them in the data queue. If a subsequent module needs this information, the subsequent module can read the write data from the data queue and determine the valid byte in the write data based on the write strobe signal.

[0070] In this way, any type of data transmitted through the write data channel can be processed in a similar manner, making it highly versatile. Processing the write strobe signal in a similar way ensures that subsequent modules can accurately read the valid bytes in the write data, thereby performing the correct data processing operations.

[0071] Based on the above embodiments, Figure 5 , Figure 6 , Figure 7 After concatenation, the complete architecture consisting of the write data channel, write address channel, and write response channel can be as follows: Figure 8 As shown in the diagram. Under this architecture, the slave device can utilize its internal cache resources to establish a data queue, a command queue, and an identification information queue, respectively for caching write data, write commands, and write address identification information. Furthermore, through the logical relationships between various internal AND gates and signals, read and write operations on the data queue, command queue, and identification information queue are controlled. Combined with a counter, this forms a controller for responding to write response-related signals in the write response channel. This results in simple control logic, supports any order of data and address channels, converts AXI protocol signals into FIFO signals, and has good versatility. Moreover, it consumes fewer hardware resources; compared to general transmission operations, it only requires adding counters and some cache resources, and slightly modifying the connection relationships of various signals, making it relatively convenient. In addition, this solution adds read interfaces to the data queue and command queue respectively to transmit read enable signals and read command signals to subsequent modules, facilitating data reading operations by subsequent modules.

[0072] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0073] Embodiments of this application also provide a notification device for the completion of a transmission operation, such as... Figure 9 As shown, it includes: Setting module 910 is used to set the state of the write response valid signal of the write response channel between master device and slave device to valid state when the count value recorded in the target counter included in slave device is non-zero and the state of the identification information queue in slave device is non-empty. The identification information queue is used to store the write address identification information of at least one burst event, and the target counter is used to record the number of burst events that have completed the write data transmission operation. The reading module 920 is used to read the first received target write address identifier from at least one write address identifier stored in the identifier information queue when the states of the write response receive preparation signal and the write response valid signal in the write response channel are both valid. The transmission module 930 is used to transmit the target write address identification information to the master device through the write response channel. The write response valid signal in the valid state and the target write address identification information are used to jointly notify the master device that the target transmission operation corresponding to the target burst event corresponding to the target write address identification information has been completed. The target transmission operation includes write data transmission operation and write address transmission operation.

[0074] In some alternative embodiments, the device further includes a write module 940 for: Whenever a write data corresponding to a target burst event is received from the master device, the received write data is written to the slave device's data queue.

[0075] In some alternative implementations, the setting module 910 is further configured to: When it is determined that all write data corresponding to at least one write data corresponding to the target burst event has been received, the count value recorded in the target counter is increased by a first preset value; or, When a read operation on the identification information queue is detected, the count value recorded in the target counter is reduced by a first preset value.

[0076] In some alternative implementations, the setting module 910 is specifically used for: When the write data valid signal, write data receive ready signal, and last write data signal in the write data channel between the master device and the slave device are all in a valid state, it is determined that all write data in at least one write data corresponding to the target burst event has been received.

[0077] In some alternative implementations, the setting module 910 is further configured to: When the first write operation to the data queue is detected and it is determined that the remaining space of the data queue is equal to the second preset value, the state of the write data receive preparation signal is set to invalid state to notify the master device that the slave device is not ready to receive the next write data after the current write data corresponding to the first write operation. Alternatively, when the remaining space in the data queue is detected to be greater than or equal to a second preset value, the write data receive preparation signal is set to an active state to notify the master device that the slave device is ready to receive the next write data.

[0078] In some alternative implementations, the write module 940 is also used for: When a target write command corresponding to a target burst event is received from the master device through the write address channel between the master and slave devices, the target write command is written to the command queue of the slave device.

[0079] In some alternative implementations, the setting module 910 is further configured to: When a second write operation to the command queue is detected, and the remaining space of the command queue or the remaining space of the identification information queue is a third preset value, the state of the write address receive preparation signal is set to invalid state to notify the master device that the slave device is not ready to receive the next write address after the current write address corresponding to the second write operation. Alternatively, when the remaining space in the command queue and the identification information queue is detected to be greater than or equal to a third preset value, the write address receive preparation signal is set to an active state to notify the master device that the slave device is ready to receive the next write address.

[0080] For a description of the features of the notification device for completion of transmission operation in the corresponding embodiment, please refer to the relevant description of the notification method for completion of transmission operation in the corresponding embodiment, which will not be repeated here.

[0081] Embodiments of this application also provide an electronic device, such as... Figure 10 As shown, it includes a memory 10 and a processor 20. The memory 10 stores a computer program, and the processor 20 is configured to run the computer program to perform the steps in the notification method embodiment for the completion of any of the above-described transmission operations.

[0082] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in the above-described embodiments of the notification method for completion of any of the transmission operations.

[0083] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0084] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in the above-described method for notifying the completion of any of the transmission operations.

[0085] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in the above-described method embodiment for notifying the completion of any of the transmission operations.

[0086] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0087] The foregoing has provided a detailed description of a method, apparatus, electronic device, storage medium, and program product for notifying the completion of a transmission operation. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A method for notifying the completion of a transmission operation, characterized in that, include: When it is detected that the count value recorded in the target counter included in the slave device is non-zero, and the status of the identification information queue in the slave device is non-empty, the status of the write response valid signal of the write response channel between the master device and the slave device is set to valid. The identification information queue is used to store the write address identification information of at least one burst event, and the target counter is used to record the number of burst events that have completed the write data transmission operation. When it is detected that the write response receive preparation signal and the write response valid signal in the write response channel are both in the valid state, the target write address identifier information that was received first is read from at least one of the write address identifier information stored in the identifier information queue. The target write address identifier information is transmitted to the master device through the write response channel. The write response valid signal and the target write address identifier information in the valid state are used to jointly notify the master device that the target transmission operation corresponding to the target burst event corresponding to the target write command write address identifier information has been completed. The target transmission operation includes the write data transmission operation and the write address transmission operation.

2. The method for notifying the completion of a transmission operation according to claim 1, characterized in that, The method further includes: Whenever a write data corresponding to the target burst event is received from the master device, the received write data is written to the data queue of the slave device.

3. The method for notifying the completion of a transmission operation according to claim 1 or 2, characterized in that, The method further includes: When it is determined that all write data corresponding to at least one write data corresponding to the target burst event has been received, the count value recorded in the target counter is increased by a first preset value; or, When a read operation on the identification information queue is detected, the count value recorded in the target counter is reduced by the first preset value.

4. The method for notifying the completion of a transmission operation according to claim 3, characterized in that, Determine all write data received in at least one write data corresponding to the target burst event, including: When the write data valid signal, write data receive ready signal, and last write data signal in the write data channel between the master device and the slave device are all in the valid state, it is determined that all write data received in at least one write data corresponding to the target burst event are received.

5. The method for notifying the completion of a transmission operation according to claim 2, characterized in that, The method further includes: When a first write operation to the data queue is detected, and it is determined that the remaining space of the data queue is equal to a second preset value, the state of the write data receiving preparation signal is set to an invalid state to notify the master device that the slave device is not ready to receive the next write data after the current write data corresponding to the first write operation. Alternatively, when the remaining space in the data queue is detected to be greater than or equal to the second preset value, the state of the write data receiving preparation signal is set to the valid state to notify the master device that the slave device is ready to receive the next write data.

6. The method for notifying the completion of a transmission operation according to claim 1, characterized in that, The method further includes: When a target write command corresponding to the target burst event is received from the master device through the write address channel between the master device and the slave device, the target write command is written into the command queue of the slave device.

7. The method for notifying the completion of a transmission operation according to claim 6, characterized in that, The method further includes: When a second write operation to the command queue is detected, and the remaining space of the command queue or the remaining space of the identification information queue is a third preset value, the state of the write address receive preparation signal is set to an invalid state to notify the master device that the slave device is not ready to receive the next write address after the current write address corresponding to the second write operation. Alternatively, when the remaining space of the command queue and the identification information queue is detected to be greater than or equal to the third preset value, the state of the write address receive preparation signal is set to the valid state to notify the master device that the slave device is ready to receive the next write address.

8. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the notification method for completion of a transmission operation as described in any one of claims 1 to 7 when executing the computer program.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the notification method for completion of the transmission operation as described in any one of claims 1 to 7.

10. A computer program product, characterized in that, The computer program product includes a computer program, wherein, when executed by a processor, the computer program implements the steps of the notification method for completion of the transmission operation as described in any one of claims 1 to 7.

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