Time service module compatible with OTII standard and common PCIe slot

Abstract

The invention discloses a time service module compatible with an OTII standard and a common PCIe slot, the time service module comprises a GNSS module, a DPLL module, a CPLD module and an NIC module, the GNSS module is electrically connected with the DPLL module and the CPLD module, the DPLL module and the CPLD module are both electrically connected with the NIC module, the NIC module is electrically connected with a PCIe interface end, the DPLL module and the CPLD module are electrically connected with the PCIe interface end, and the PCIe interface end is electrically connected with the GNSS module. The pins, connected with the DPLL module and the CPLD module, of the PCIe interface end are reserved pins in the PCIe standard. The time service module has the advantages that TOD-IIC protocol conversion is carried out through the CPLD module, a TOD interface is converted into an IIC interface, reserved pins on a PCIe interface are reused, the technical specification of an OTII server is followed, the compatibility problem of the time service module to an OTII case and a common case is solved, and meanwhile high-precision time synchronization is achieved.

Description

Technical Field

[0001] This invention relates to the field of timing module technology, and more particularly to a timing module compatible with OTII specifications and common PCIe slots. Background Technology

[0002] OTII Specification: OTII, or Open IT Infrastructure for Telecommunications, is an open server standard for 5G and edge computing, requiring devices to have high compatibility and modular design. Traditional Standard CEM Card: CEM is a form of PCIe expansion card widely used in servers, but traditional CEM cards lack time synchronization functionality. Current technologies have the following problems: Compatibility issues: Time synchronization cards compliant with OTII server specifications cannot be used in ordinary chassis; Missing functionality: Standard PCIe CEM cards do not have time synchronization functionality, requiring additional customized hardware; Insufficient accuracy: Traditional time synchronization modules rely on crystal oscillators, resulting in poor long-term stability and insufficient time synchronization accuracy for high-precision scenarios.

[0003] Therefore, existing technologies have shortcomings and need to be improved. Summary of the Invention

[0004] The purpose of this invention is to overcome at least some of the shortcomings of the prior art and provide a timing module that is compatible with the OTII specification and ordinary PCIe slots.

[0005] The technical solution of the present invention is as follows: The present invention provides a timing module compatible with OTII specification and ordinary PCIe slot, including: GNSS module, DPLL module, CPLD module, and NIC module. The GNSS module is electrically connected to the DPLL module and CPLD module respectively. The DPLL module and CPLD module are both electrically connected to the NIC module. The NIC module is electrically connected to the PCIe interface terminal. The DPLL module and CPLD module are electrically connected to the PCIe interface terminal. The pins of the PCIe interface terminal connected to the DPLL module and CPLD module are reserved pins in the PCIe specification. When installed on a standard chassis, the time synchronization function is achieved through steps 1, 2, and 3; when installed on an OTII chassis, the time synchronization function is achieved through steps 1 and 4. Step 1: After the GNSS module locks onto the satellite signal, it continuously outputs stable PPS pulses and corresponding TOD data, and ensures that each PPS pulse has an accurate time stamp. Step 2: The DPLL module receives the PPS signal as a reference clock source, compares the phase of the PPS signal with the internal system clock, detects the phase difference between the two, filters the phase difference signal to remove noise interference, and dynamically adjusts the frequency and phase of the internal system clock according to the filtered phase difference to gradually synchronize the system clock with the PPS signal. The system clock synchronized with the PPS signal is then output and transmitted to the NIC module via the I2C protocol. Step 3: The CPLD module receives the raw TOD signal output by the GNSS module, converts the TOD signal format and interface to I2C through internally programmed logic circuits, and then sends the data to the NIC module. After receiving the information sent by the DPLL module and the CPLD module, the NIC transmits the time information to the system clock management module through the internal bus to complete the system time update. Step 4: The GNSS module sends the PPS signal and TOD signal to the PCIe interface through the DPLL module and CPLD module respectively.

[0006] Furthermore, the DPLL module is electrically connected to pins A19, A32, and A50 of the PCIe terminal, and the CPLD module is connected to pins B30, B12, and B82 of the PCIe terminal.

[0007] The advantages of this invention using the above solution are as follows: By converting the TOD-IIC protocol through the CPLD module, the TOD interface is transformed into an IIC interface, and reserved pins on the PCIe interface are reused. It adheres to the OTII server technical specifications, resolving the compatibility issue between the timing module and OTII chassis and ordinary chassis, while simultaneously achieving high-precision time synchronization. Compared to existing technologies, it offers lower deployment costs, greater flexibility, and wider applicability, making it suitable for high-precision time synchronization scenarios such as 5G base stations, edge computing, and industrial automation. Attached Figure Description

[0008] Figure 1 This is a structural block diagram of a timing module according to an embodiment of the present invention.

[0009] Figure 2A and Figure 2B This is a circuit diagram of a GNSS module according to an embodiment of the present invention.

[0010] Figures 3A to 3D This is a circuit diagram of a DPLL module according to an embodiment of the present invention.

[0011] Figure 4 This is a circuit diagram of a CPLD module according to an embodiment of the present invention.

[0012] Figure 5A and Figure 5B This is a circuit diagram of a NIC module according to an embodiment of the present invention.

[0013] Figure 6 is a circuit diagram of the PCIe terminal connected to the DPLL module and CPLD module according to an embodiment of the present invention. Detailed Implementation

[0014] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0015] In this solution, the OTII (Open Telecom IT Infrastructure) specification is defined as follows: OTII, or Open Telecom IT Infrastructure Project, belongs to the Open Data Center Committee (ODCC), China's largest open-source hardware organization. It is an open server standard for 5G and edge computing, requiring devices to have high compatibility and modular design. Traditional standard CEM (CardEdge Module) cards: CEM is a form of PCIe (Peripheral Component Interconnect Express) expansion card, widely used in servers, but traditional CEM cards lack time synchronization functionality. Time synchronization requirements: 5G base stations, edge computing, and other scenarios place higher demands on nanosecond-level time synchronization, requiring compatibility with multiple protocols such as IEEE 1588 PTP (Precision Timing Protocol), Sync-E (Synchronous Ethernet), and 1PPS+TOD (Pulse Per Second + Date and Time).

[0016] Please combine and adopt Figures 1 to 6 In this embodiment, the present invention provides a timing module compatible with OTII specifications and ordinary PCIe slots, including: a GNSS (Global Positioning System) module, a DPLL (Digital Phase-Locked Loop) module, a CPLD (Complex Programmable Logic Device) module, and a NIC (Ethernet Controller) module.

[0017] Specifically, the GNSS module is electrically connected to the DPLL module and the CPLD module respectively. The GNSS module, DPLL module, and CPLD module are all electrically connected to the NIC module via the I2C protocol. The NIC module is electrically connected to the PCIe interface. The DPLL module and CPLD module are electrically connected to the PCIe interface. The pins of the PCIe interface that connect to the DPLL module and CPLD module are reserved pins of the PCIe CEM4.0 specification.

[0018] More specifically, in this embodiment, the DPLL module is electrically connected to pins A19, A32, and A50 of the PCIe terminal, and the CPLD module is connected to pins B30, B12, and B82 of the PCIe terminal. The pin-to-name correspondence is as follows:

[0019] Please continue to refer to the following: Figures 1 to 4 In this solution, if the time synchronization module is installed on a standard chassis, the time synchronization function is achieved through the following steps 1, 2, and 3: Step 1: The GNSS module (such as GPS, BeiDou, etc.) receives signals from multiple satellites via its antenna. Its internal processor calculates precise time and location information, continuously outputting stable PPS pulses and corresponding TOD data, ensuring each PPS pulse has an accurate time stamp. The PPS signal is a precise 1Hz pulse signal, with each pulse's rising (or falling) edge precisely aligned with the second mark of UTC time. The pulse width is typically 10-100ms. This signal achieves nanosecond-level time accuracy, providing the system with a precise time reference. The TOD signal contains complete date and time information (year, month, day, hour, minute, second, etc.), usually output serially (e.g., RS-232 / 485), providing an absolute time reference.

[0020] Step 2: The DPLL module receives the PPS signal output from the GNSS module as a reference clock source. It compares the phase of the PPS signal with the system's internal clock (such as a clock generated by a crystal oscillator), detects the phase difference, filters the phase difference signal to remove noise interference, and dynamically adjusts the frequency and phase of the system's internal clock based on the filtered phase difference. This gradually synchronizes the system clock with the PPS signal, ultimately outputting a system clock synchronized with the PPS signal, ensuring that the entire system's time base remains consistent with GNSS time. The DPLL (Digital Phase-Locked Loop) module is a phase-locked system implemented using digital circuitry.

[0021] Step 3: The CPLD receives the raw TOD signal (UART format in this embodiment) output from the GNSS module. Through its internally programmed logic circuitry, it converts the TOD signal format and interface into I2C (Inter-Integrated Circuit) bus format and sends it to the NIC module. The NIC module reads the converted time information from the CPLD module via the I2C interface and obtains the system clock synchronized with the PPS signal from the DPLL module. It then transmits the time to the system clock management module via an internal bus (such as PCIe) to update the system time. Here, the CPLD module acts as both a signal converter and an interface adapter.

[0022] Additionally, it is worth noting that there is no fixed order between the two actions in step 2, where the DPLL module processes the PPS signal and outputs it to the NIC module, and in step 3, where the CPLD processes the TOD signal and outputs it to the NIC module; they can be performed simultaneously.

[0023] By converting the TOD signal to a universal I2C interface, this time synchronization solution can be adapted to ordinary chassis that do not have a dedicated GNSS interface.

[0024] If the time synchronization module is installed on a standard chassis, the time synchronization function is achieved through steps 1 and 4: Step 1: The GNSS module receives signals from multiple satellites through its antenna, calculates accurate time and location information through its internal processor, and continuously outputs stable PPS pulses and corresponding TOD data to ensure that each PPS pulse has an accurate time tag.

[0025] Step 4: The GNSS module sends the PPS signal and TOD signal to the PCIe interface through the DPLL module and CPLD module respectively. At this time, the DPLL module and CPLD module do not process the PPS signal and TOD signal, and the GNSS module is equivalent to being directly connected to the PCIe interface.

[0026] When designing the hardware, the PPS and TOD signals of the GNSS module are connected to these reserved pins. The PPS / TOD signals are then transmitted from the GNSS module to the system's time processing unit via PCIe physical layer wiring. This design does not require modification of the standard PCIe functionality, while meeting the precise time synchronization requirements of OTII servers and achieving hardware compatibility. It offers the following advantages: utilizing the existing PCIe interface physical layer avoids additional wiring, simplifies hardware design, and ensures the quality of time signal transmission.

[0027] By adopting the above-described solution, this solution has the following advantages: It achieves compatibility between OTII chassis and ordinary chassis; this design does not require modification of the standard PCIe functions, while meeting the precise time synchronization requirements of OTII servers, thus achieving hardware compatibility; The materials are simple, resulting in lower overall costs; this design uses a solution compatible with both OTII and standard chassis, eliminating the need for additional custom hardware. High timing accuracy. This design uses a high-precision clock, achieving nanosecond-level accuracy. The measured timing accuracy does not exceed 12 nanoseconds, meeting the requirements of applications such as 5G base stations and edge computing.

[0028] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A timing module compatible with OTII standard and ordinary PCIe slot, characterized in that, include: The system includes a GNSS module, a DPLL module, a CPLD module, and a NIC module. The GNSS module is electrically connected to the DPLL module and the CPLD module, respectively. The DPLL module and the CPLD module are both electrically connected to the NIC module. The NIC module is electrically connected to the PCIe interface. The DPLL module and the CPLD module are electrically connected to the PCIe interface, and the pins connecting the PCIe interface to the DPLL module and the CPLD module are reserved pins in the PCIe specification. When installed in a standard chassis, the time synchronization function is achieved through steps 1, 2, and 3. When installed in an OTII chassis, the time synchronization function is achieved through steps 1 and 4. Step 1: After locking onto the satellite signal, the GNSS module continuously outputs stable PPS pulses and corresponding TOD data, ensuring that each PPS pulse has an accurate time stamp. Step 2: The DPLL module receives the PPS signal as a reference clock source and sets the PPS... The signal is compared with the internal clock of the system to detect the phase difference between the two. The phase difference signal is filtered to remove noise interference. Based on the filtered phase difference, the frequency and phase of the internal clock of the system are dynamically adjusted so that the system clock is gradually synchronized with the PPS signal. The system clock synchronized with the PPS signal is output and transmitted to the NIC module via the I2C protocol. Step 3: The CPLD module receives the raw TOD signal output by the GNSS module. Through its internally programmed logic circuit, it converts the TOD signal format and interface to I2C and sends the data to the NIC module. After receiving the information sent by the DPLL module and the CPLD module, the NIC transmits the time information to the system clock management module through the internal bus to complete the system time update. Step 4: The GNSS module sends the PPS signal and TOD signal to the PCIe interface through the DPLL module and the CPLD module respectively.

2. The timing module compatible with OTII standard and ordinary PCIe slot as described in claim 1, characterized in that, The DPLL module is electrically connected to pins A19, A32, and A50 of the PCIe terminal, while the CPLD module is connected to pins B30, B12, and B82 of the PCIe terminal.

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