Artificial intelligence chip, artificial intelligence processor core and electronic device

Abstract

Embodiments of the present disclosure provide an artificial intelligence chip, an artificial intelligence processor core, and an electronic device. The artificial intelligence chip includes a plurality of artificial intelligence processor cores and at least one communication chain, each artificial intelligence processor core includes an arithmetic logic unit, and the at least one communication chain includes a first communication chain, the first communication chain being communicatively connected to the plurality of artificial intelligence processor cores; the arithmetic logic unit corresponding to each artificial intelligence processor core is communicatively connected to the first communication chain, so that the corresponding arithmetic logic unit directly transmits or receives data through the first communication chain; and each artificial intelligence processor core is configured to execute a first accumulation instruction by the corresponding arithmetic logic unit and directly transmit at least one intermediate calculation result corresponding to the first accumulation instruction through the first communication chain. The artificial intelligence chip can significantly improve the overall performance and energy efficiency ratio of the AI computing chip when processing cross-artificial intelligence processor core operations, such as reduction operations.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the field of computer technology, specifically to an artificial intelligence chip, an artificial intelligence processor core, and an electronic device. Background Technology

[0002] With the development of multi-core architecture in AI chips, data must be repeatedly written to and read from shared memory when transferred between multiple AI processor cores, causing communication link bandwidth to become a performance bottleneck. Furthermore, each cross-AI processor core accumulation requires independent instruction control, and instruction overhead increases linearly with the number of cores, severely limiting computational efficiency and system throughput. Summary of the Invention

[0003] This disclosure provides at least one embodiment of an artificial intelligence chip, the artificial intelligence chip including a plurality of artificial intelligence processor cores and at least one communication chain, each of the artificial intelligence processor cores including an arithmetic logic unit (ALU), wherein the at least one communication chain includes a first communication chain, the first communication chain being communicatively connected to the plurality of artificial intelligence processor cores, and the arithmetic logic unit (ALU) corresponding to each artificial intelligence processor core establishing a communication connection with the first communication chain, so that the corresponding arithmetic logic unit (ALU) directly sends or receives data through the first communication chain; each artificial intelligence processor core is configured to have its corresponding arithmetic logic unit execute a first accumulation instruction and directly transmit at least one intermediate calculation result corresponding to the first accumulation instruction through the first communication chain.

[0004] In the artificial intelligence chip provided in at least one embodiment of this disclosure, for each of the artificial intelligence processor cores, the arithmetic logic unit is connected to the first communication chain via a first path to directly receive data, and is connected to the first communication chain via a second path to directly send data.

[0005] In the artificial intelligence chip provided in at least one embodiment of this disclosure, each of the artificial intelligence processor cores further includes a first computing unit and a first multiplexer. The arithmetic logic unit and the first computing unit are both connected to the first communication chain via the first multiplexer through a second path. The first multiplexer is configured to select one of the first computing unit and the arithmetic logic unit to be connected to the first communication chain via the second path according to a selection signal.

[0006] In the artificial intelligence chip provided in at least one embodiment of this disclosure, each of the artificial intelligence processor cores further includes shared memory, and the arithmetic logic unit is communicatively connected to or integrated into the shared memory.

[0007] In an artificial intelligence chip provided in at least one embodiment of this disclosure, the plurality of artificial intelligence processor cores include a first artificial intelligence processor core, the first artificial intelligence processor core includes a first shared memory, and the arithmetic logic unit of the first artificial intelligence processor core is a first arithmetic logic unit; in response to the first artificial intelligence processor core initiating a first accumulation instruction, the first artificial intelligence processor core is configured to read first target data from the first shared memory according to the first accumulation instruction, execute the first accumulation instruction on the first target data by the first arithmetic logic unit to obtain first accumulated data, and send a first intermediate calculation result through the first communication link; wherein, the first intermediate calculation result includes a data address, the first accumulated data, and a processor core mask, the processor core mask is used to indicate the target artificial intelligence processor core among the plurality of artificial intelligence processor cores that executes the first accumulation instruction; the first intermediate calculation result serves as the upstream intermediate calculation result of the next processor core that executes the first accumulation instruction.

[0008] In an artificial intelligence chip provided in at least one embodiment of this disclosure, the plurality of artificial intelligence processor cores include a second artificial intelligence processor core, the second artificial intelligence processor core includes a second shared memory, and the arithmetic logic unit of the second artificial intelligence processor core is a second arithmetic logic unit; in response to the second artificial intelligence processor core receiving the first accumulation instruction and not being the last processor core to execute the first accumulation instruction, the second artificial intelligence processor core is configured to have the second arithmetic logic unit receive upstream intermediate calculation results through the first communication link, read second target data from the second shared memory according to the first accumulation instruction and the data address, execute the first accumulation instruction on the second target data and the accumulated data included in the upstream intermediate calculation result to obtain second accumulated data, and send the second intermediate calculation result through the first communication link; wherein, the second intermediate calculation result includes the data address, the second accumulated data, and the processor core mask, and the second intermediate calculation result serves as the upstream intermediate calculation result of the next processor core to execute the first accumulation instruction.

[0009] In an artificial intelligence chip provided in at least one embodiment of this disclosure, the plurality of artificial intelligence processor cores include a third artificial intelligence processor core, the third artificial intelligence processor core includes a third shared memory, and the arithmetic logic unit of the third artificial intelligence processor core is a third arithmetic logic unit; in response to the third artificial intelligence processor core receiving the first accumulation instruction and being the last processor core to execute the first accumulation instruction, the third artificial intelligence processor core is configured to have the third arithmetic logic unit receive upstream intermediate calculation results through the first communication link, read third target data from the third shared memory according to the first accumulation instruction and the data address, execute the first accumulation instruction on the third target data and the accumulation data included in the upstream intermediate calculation results to obtain final accumulation data, and write the final accumulation data into the third shared memory.

[0010] In the artificial intelligence chip provided in at least one embodiment of this disclosure, each of the artificial intelligence processor cores is configured to, in response to receiving an upstream intermediate calculation result, determine whether it is a processor core executing the first accumulation instruction based on the processor core mask in the upstream intermediate calculation result.

[0011] At least one embodiment of this disclosure provides an artificial intelligence processor core, which includes an arithmetic logic unit (ALU); the ALU is configured to, when connected to an artificial intelligence chip including multiple artificial intelligence processor cores, communicate with a first communication chain that communicates with the multiple artificial intelligence processor cores, and directly send or receive data through the first communication chain; the artificial intelligence processor core is configured to execute a first accumulation instruction by the ALU and directly transmit at least one intermediate calculation result through the first communication chain.

[0012] At least one embodiment of this disclosure provides an electronic device, which includes an artificial intelligence chip or an artificial intelligence processor core provided in any embodiment of this disclosure.

[0013] In at least one embodiment of this disclosure, by constructing a direct hardware path between the arithmetic logic unit and the communication chain, the problem of redundant data transfer between the computing unit and shared memory during the collaborative accumulation process of multiple AI processor cores is solved. For example, intermediate calculation results enter the transmission channel after being generated, and are consumed by the computing unit of the target AI processor core after arriving at it, forming a smooth computing transmission pipeline. At least one embodiment of this disclosure not only greatly reduces the latency and bandwidth contention pressure caused by multiple accesses to shared memory, but also compresses multiple independent accumulation operations that originally required multiple instructions into an automated continuous process triggered by a single instruction. At least one embodiment of this disclosure significantly improves the overall performance and energy efficiency of AI computing chips when processing reduction operations across AI processor cores, solving the performance bottleneck problem in scenarios with limited communication bandwidth. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure, and are not intended to limit this disclosure.

[0015] Figure 1 A schematic block diagram of an artificial intelligence chip is shown.

[0016] Figure 2 A schematic block diagram of an artificial intelligence chip provided in at least one embodiment of the present disclosure is shown.

[0017] Figure 3 A schematic block diagram of another artificial intelligence chip provided in at least one embodiment of the present disclosure is shown.

[0018] Figure 4 A schematic block diagram of an artificial intelligence processor core provided in at least one embodiment of the present disclosure is shown.

[0019] Figure 5 A schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure is shown.

[0020] Figure 6 A schematic block diagram of another electronic device provided in at least one embodiment of the present disclosure is shown. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0022] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0023] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numerals in each drawing.

[0024] In AI chip architecture, to improve the parallel processing capability of large-scale matrix operations, computational tasks can be decomposed and mapped to a computing cluster composed of multiple AI processor cores. Each AI processor core is responsible for processing a portion of the data, and then the final computation result is obtained through data interaction within the cluster. A commonly adopted collaborative computing model is as follows: each AI processor core writes its partial computation result to a shared memory area accessible by the cluster. Then, through a dedicated data chain (usually called a "data chain" or "communication chain") connecting the AI ​​processor cores, this intermediate data is transmitted between the cores for subsequent computation (e.g., summation). For example, the core initiating the computation needs to read data from its local storage or shared storage and send it to the target core through the data chain; after receiving the data, the target core usually needs to first store it in its own shared storage or local storage, and then its arithmetic logic unit reads it and performs operations with the local data. If the result needs to be further transmitted, the above process of storing, reading, transmitting, storing, and computing is repeated.

[0025] Figure 1 A schematic block diagram of an artificial intelligence chip is shown.

[0026] like Figure 1 As shown, the artificial intelligence chip includes a computing cluster architecture composed of multiple artificial intelligence processor cores. Figure 1 Taking four AI processor cores as an example, this AI chip is described in an exemplary manner. Each core is equipped with four independent computing units, A, B, C, and D. The four cores communicate with each other through segmented communication links to achieve cross-core data interaction. The direction of data transmission is clearly indicated by the arrows in the figure.

[0027] For example, data is transmitted from unit A1 of core 2 to unit A2 of core 3, and from unit B1 of core 2 to unit B2 of core 3. Reverse transmission also exists (such as transmission from unit C2 of core 3 to unit C1 of core 2, and transmission from unit B3 of core 4 to unit B2 of core 3). Data transmission between core 2 and core 1, and between core 3 and core 4, is also completed through similar links.

[0028] exist Figure 1 In the architecture shown, each single communication link in each direction needs to carry the transmission of 3 data units, and each core arithmetic logic unit needs to perform operations on these 3 data units; however, under this design, the communication link needs to carry a large amount of data transmission. If the bandwidth of the communication link itself is insufficient, excessive data transmission will become a bottleneck restricting the performance of the entire computing cluster.

[0029] The inventors of this disclosure have noted that the above-mentioned technical solutions have obvious performance bottlenecks and efficiency defects.

[0030] For example, data transmission paths are lengthy and bandwidth-intensive. Because each data transfer between cores involves writing to shared storage and reading from shared storage, a large amount of unnecessary data movement occurs. The physical bandwidth of the data links connecting the cores is often limited by chip area and power consumption, making significant improvements difficult. Frequent and redundant data travel between storage and the links can easily make the data chain a performance bottleneck in the entire computing process, limiting the overall computing throughput of the cluster.

[0031] For example, instruction overhead is high. In the step-by-step transfer and computation model described above, each time data is transferred from one core to the next and an accumulation operation is performed, a separate instruction is typically required. When continuous accumulation is required across multiple cores (such as vector summation across multiple cores), the number of instructions required is proportional to the number of cores involved in the computation. This not only consumes valuable instruction issue bandwidth but also increases the burden of instruction scheduling and decoding, reducing the processor's instruction efficiency.

[0032] The inventors of this disclosure have noted that multi-core chained accumulation schemes based on shared memory and multi-instruction control struggle to achieve efficient, low-latency continuous collaborative computing within limited data link bandwidth and instruction bandwidth. Reducing data redundancy in inter-core communication and lowering control overhead have become pressing technical challenges for improving the multi-core computing performance of AI chips.

[0033] Based on at least one of the aforementioned technical problems, at least one embodiment of this disclosure provides an artificial intelligence (AI) chip, an AI processor core, and an electronic device. The AI ​​chip includes multiple AI processor cores and at least one communication chain. Each AI processor core includes an arithmetic logic unit (ALU). The at least one communication chain includes a first communication chain, which communicatively connects the multiple AI processor cores. Each AI processor core's corresponding ALU establishes a communication connection with the first communication chain, enabling the corresponding ALU to directly send or receive data through the first communication chain. Each AI processor core is configured to execute a first accumulation instruction by its corresponding ALU and directly transmit at least one intermediate calculation result corresponding to the first accumulation instruction through the first communication chain. This AI chip can significantly improve the overall performance and energy efficiency of AI computing chips when handling reduction operations across AI processor cores.

[0034] Figure 2 A schematic block diagram of an artificial intelligence chip provided in at least one embodiment of the present disclosure is shown.

[0035] like Figure 2As shown, the artificial intelligence chip 2000 includes multiple artificial intelligence processor cores (AI Cores) and at least one communication chain. Each AI processor core includes an arithmetic logic unit, and the at least one communication chain includes a first communication chain that connects multiple AI processor cores. The arithmetic logic unit corresponding to each AI processor core establishes a communication connection with the first communication chain, so that the corresponding arithmetic logic unit can directly send or receive data through the first communication chain.

[0036] For example, each AI processor core is configured to execute a first accumulation instruction by the corresponding arithmetic logic unit and directly transmit at least one intermediate calculation result corresponding to the first accumulation instruction through a first communication link.

[0037] For example, such as Figure 2 As shown, multiple AI processor cores are represented by the first AI processor core Core 0, the second AI processor core Core 1, ..., the Nth AI processor core Core N-1, where N is a positive integer greater than 2.

[0038] For example, in some embodiments of this disclosure, the artificial intelligence processor core may include a general-purpose graphics processing unit (GPGPU) core, a tensor processor (TPU) core, etc., and the embodiments of this disclosure do not limit this; for example, each artificial intelligence processor core may include an array of computing units that perform artificial intelligence computing tasks such as arithmetic logic operations, vector operations, and nonlinear function activation, and may also include global memory, shared memory, etc.; the embodiments of this disclosure do not limit the implementation method of the artificial intelligence processor core.

[0039] For example, multiple AI processor cores can work together to form a computing cluster to collaboratively execute large-scale parallel computing tasks, such as reducing and accumulating large matrices or tensors during deep learning training or inference.

[0040] For example, each AI processor core may include at least one Arithmetic Logic Unit (ALU) for performing arithmetic logic operations.

[0041] For example, each AI processor core can also include basic units for performing AI computing tasks such as matrix multiplication and addition (MAC), vector operations, and nonlinear function activation.

[0042] For example, each AI processor core may also include control logic, global memory, shared memory, local cache (such as L0 / L1 buffer), etc.

[0043] For example, multiple AI processor cores can be homogeneous, all possessing the same computing power; or they can be heterogeneous, for example, in mixed-precision computing, some cores are dedicated to FP16 computing, while others are dedicated to INT8 computing, etc. The embodiments disclosed herein do not impose any limitations on this.

[0044] For example, multiple AI processor cores can be arranged in a linear chain or connected end-to-end to form a loop chain to increase path flexibility.

[0045] For example, the physical medium of the first communication link can be a dedicated on-chip interconnect network (NoC) link.

[0046] For example, at least one communication chain (e.g., the first communication chain) can physically or logically connect multiple AI processor cores (e.g., the first AI processor core Core 0, the second AI processor core Core 1, ..., the Nth AI processor core Core N-1) in series to form a dedicated channel for transmitting intermediate computing data.

[0047] For example, the first communication chain can be a one-way or two-way chain that supports sequential data transmission, such as data flowing from the first AI processor core Core 0 to the second AI processor core Core 1, then to the third AI processor core Core 2, and so on.

[0048] For example, the arithmetic logic units included in each AI processor core (e.g., the first AI processor core Core 0, the second AI processor core Core 1, etc.) have established direct, point-to-point communication connections with the first communication chain.

[0049] For example, each AI processor core's arithmetic logic unit has an output port that connects directly to the input node of the first communication chain via the data path inside the AI ​​processor core (e.g., through a multiplexer). This allows the generated computation results to be directly driven onto the first communication chain without needing to be stored in the shared memory inside the AI ​​processor core.

[0050] For example, the output data from the first communication chain at each AI processor core can be directly transmitted to an input port of the arithmetic logic unit (ALU) of that AI processor core. This allows data from upstream AI processor cores to directly enter the ALU of this AI processor core for computation.

[0051] For example, the "direct connection" architecture of arithmetic logic units of multiple AI processor cores can be represented in hardware as dedicated data paths and control signals to achieve tight coupling between computation flow and data flow.

[0052] For example, each AI processor core can be configured to recognize and execute a specific first accumulation instruction.

[0053] For example, the first accumulate instruction can encode a chained accumulate operation that spans multiple cores.

[0054] For example, when an AI processor core in a computing cluster (e.g., the first AI processor core Core 0 as the initiator) executes the first accumulation instruction, its corresponding arithmetic logic unit can perform the corresponding computation (e.g., read data from local memory and perform initialization or local accumulation). At least one intermediate computation result (e.g., a partial sum vector) is not written back to shared memory via the traditional path, but is directly input into the first communication chain through the transmission path directly connected to the aforementioned arithmetic logic unit.

[0055] For example, the arithmetic logic unit corresponding to each AI processor core can directly send or receive data through the first communication chain. Data can enter the first communication chain from the end of the arithmetic logic unit's computation pipeline after a very short internal delay. For example, the transmitted data unit may include a data packet, which may include a payload (i.e., intermediate calculation results) and corresponding routing or control information (such as core mask, target address, etc., which are not limited in the embodiments of this disclosure), so that the data can be correctly identified and transmitted on the first communication chain.

[0056] For example, each AI processor core may include a link port control unit.

[0057] For example, the link port control unit can be configured to pack and unpack data. For example, at the sending end, the raw data output by the arithmetic logic unit, the target address (or core mask) carried by the instruction, and other information can be encapsulated into a fixed-format data packet suitable for on-chain transmission. For example, at the receiving end, the data packet can be parsed to extract the payload (computation data) or control information, etc.

[0058] For example, the link port control unit can also be configured to parse the processor core mask in the data packet to determine whether the AI ​​processor core is the "target core" of the current data. If so, the data is sent to the aforementioned receiving path for use by the arithmetic logic unit; otherwise, the "pass-through" logic is activated to forward the input data packet to the downstream output port.

[0059] For example, an AI chip can be deployed with multiple communication chains, such as a "right-hand chain" and a "left-hand chain," to support data accumulation and propagation in different directions, thereby supporting more complex computational graphs.

[0060] For example, the connection between the arithmetic logic unit corresponding to each AI processor core and different communication chains can be configurable. For instance, a single arithmetic logic unit can be allowed to select to access different communication chains by using a switch, thereby enhancing flexibility.

[0061] It should be noted that in the embodiments of this disclosure, "left" and "right" are used to refer to two fixed and opposite logical data transmission directions on the corresponding communication chain. Their specific physical mapping relationship (corresponding to the actual orientation of the chip, such as east / west, up / down) or logical mapping relationship (corresponding to the increase / decrease of the core address) can be determined according to the specific chip layout or addressing scheme, but they are all within the scope of the core idea claimed in this disclosure, namely, to realize the dynamic selection of the transmission direction on the same physical link.

[0062] It should be noted that the artificial intelligence chip provided in at least one embodiment of this disclosure is not only applicable to the addition operation, but also supports other reduction operations that satisfy the associative law, such as finding the maximum value (Max), minimum value (Min), bitwise AND / OR, etc. The embodiments of this disclosure do not limit this.

[0063] In at least one embodiment of this disclosure, by constructing a direct hardware path between the arithmetic logic unit and the communication chain, the problem of redundant data transfer between the computing unit and shared memory during the collaborative accumulation process of multiple AI processor cores is solved. Intermediate calculation results enter the transmission channel after generation and are consumed by the computing unit of the target AI processor core after arriving at it, forming a smooth computational transmission pipeline. This embodiment of the disclosure not only significantly reduces the latency and bandwidth contention caused by multiple accesses to shared memory, but also compresses multiple independent accumulation operations that originally required multiple instructions into an automated, continuous process triggered by a single instruction. Furthermore, this embodiment of the disclosure significantly improves the overall performance and energy efficiency of the AI ​​computing chip when processing reduction operations across AI processor cores, solving the performance bottleneck problem in scenarios with limited communication bandwidth.

[0064] In some embodiments of this disclosure, for each artificial intelligence processor core, the arithmetic logic unit is connected to the first communication chain via a first path to directly receive data, and connected to the first communication chain via a second path to directly send data.

[0065] For example, for each AI processor core in an AI chip, its corresponding arithmetic logic unit (ALU) can be directly connected to the first communication chain through two independent hardware paths.

[0066] For example, the first path can be configured as the receiving path, and the second path can be configured as the sending path.

[0067] For example, directly receiving data means that the arithmetic logic unit (ALU) can obtain data packets provided by the upstream artificial intelligence processor core from the communication chain through a dedicated hardware connection established by the first path and the first communication chain.

[0068] For example, direct data transmission refers to the arithmetic logic unit (ALU) establishing a dedicated hardware connection with the first communication chain through a second path, which enables the intermediate calculation results generated after executing instructions to be directly output to the first communication chain for transmission.

[0069] For example, the first path can be configured to transmit data from the first communication chain directly and unidirectionally to the input port of the arithmetic logic unit corresponding to the core of this artificial intelligence processor.

[0070] For example, the second path can be configured to directly and unidirectionally drive the calculation results of the arithmetic logic unit corresponding to the core of this artificial intelligence processor to the first communication chain, so as to realize the instant external broadcast of the calculation results and eliminate storage delay.

[0071] In at least one embodiment of this disclosure, the receiving and transmitting paths of the arithmetic logic unit are physically separated, resolving the issues of contention and complex arbitration logic that may arise from a single bidirectional bus. This reduces the latency of computational communication across AI processor cores. For example, when the communication chain itself supports pipelined transmission, the arithmetic logic unit corresponding to an AI processor core can receive and perform calculations on the Nth data packet via a first path, while simultaneously sending the calculation result of the (N-1)th data packet via a second path. This achieves pipelined operations of receiving, calculating, and transmitting, significantly improving the overall data throughput of the cluster.

[0072] Figure 3 A schematic block diagram of another artificial intelligence chip provided in at least one embodiment of the present disclosure is shown.

[0073] like Figure 3 As shown, in some embodiments of this disclosure, each artificial intelligence processor core further includes a first computing unit and a first multiplexer, and both the arithmetic logic unit and the first computing unit are connected to the first communication link via the first multiplexer through a second path.

[0074] The first multiplexer is configured to select, based on a selection signal, one of a first computing unit and an arithmetic logic unit to be connected to the first communication link via a second path.

[0075] For example, the first computing unit can be a functional unit with independent data processing capabilities.

[0076] For example, the first computing unit 4100 may include a vector processing unit (VPU), a tensor processing unit (TPU), or a multiply-accumulate (MAC) unit array, which can be used for specific intensive computing (such as matrix multiplication, dot product operation), and the embodiments of this disclosure do not limit this.

[0077] For example, the first multiplexer can be configured as a data selection switch, such as a "source controller" for a transmission path (e.g., a second path).

[0078] For example, a first multiplexer may include multiple data inputs and one output.

[0079] For example, two of the inputs of the first multiplexer can be connected to the output register of the arithmetic logic unit (ALU) and the output interface of the first computation unit, respectively.

[0080] For example, when the selection signal indicates that an arithmetic logic unit is selected, the intermediate accumulation result calculated by the arithmetic logic unit (e.g., a scalar part and / or an accumulated vector) can be selected by the first multiplexer and enter the transmission path.

[0081] For example, when the selection signal indicates that the first computing unit is selected, the result calculated by the first computing unit (e.g., a data block after preliminary reduction by the tensor core) is selected and output.

[0082] For example, the selection signal can be generated by the instruction decoder or a dedicated configuration register of the AI ​​processor core.

[0083] For example, the selection signal can be encoded in a specific field of the first accumulation instruction or its accompanying instruction to achieve instruction-level control.

[0084] In at least one embodiment of this disclosure, a first multiplexer and support for multiple computing units as transmission sources enable intelligent, on-demand coupling of heterogeneous computing resources and efficient communication links within the AI ​​processor core. The AI ​​chip can instructively select whether to generate and transmit intermediate results from an arithmetic logic unit or a high-performance computing unit, based on the needs of specific computational stages. This not only maximizes the advantages of various computing hardware within the AI ​​processor core but also optimizes the overall task pipeline. By allowing computing units to "pass through" their results to the communication chain, unnecessary internal copying and format conversion of data between different computing units are reduced. This improves the efficiency of individual computational steps while further reducing end-to-end latency and energy consumption in the entire chained processing flow, enhancing the AI ​​processor's agility and overall performance in handling complex, heterogeneous computation graphs.

[0085] In some embodiments of this disclosure, each AI processor core also includes shared memory, and the arithmetic logic unit is communicatively connected to or integrated into the shared memory.

[0086] For example, shared memory refers to a storage area inside the core of an artificial intelligence processor that can be accessed by multiple or all other artificial intelligence processor cores within the same computing cluster through communication links or other interconnection methods, and is used to store source data or final results to be processed collaboratively.

[0087] In one alternative implementation, the arithmetic logic unit (ALU) is communicatively connected to the shared memory. For example, the ALU and the shared memory can be two physically independent modules that are tightly interconnected via a dedicated high-speed interface.

[0088] For example, the arithmetic logic unit (ALU) and shared memory can be connected via one or more dedicated, wide-bandwidth, low-latency data buses and corresponding address and control buses. For instance, the ALU can use this dedicated bus to directly read and write data at specific addresses in shared memory with extremely high bandwidth and extremely low latency.

[0089] For example, this connection method between the arithmetic logic unit (ALU) and shared memory allows the ALU to efficiently exchange data with shared memory when needed (e.g., when reading local source data or writing the final result in a chained accumulation instruction), reducing the access overhead caused by complex multi-level caches or global interconnect networks.

[0090] In one alternative implementation, the arithmetic logic unit is integrated into shared memory. The arithmetic logic unit serves as an embedded logic component of the shared memory, or resides on the same physical module or substrate as it, forming a "memory-to-memory" or "near-memory computing" unit.

[0091] For example, shared memory can be a multi-bank SRAM array, and arithmetic logic units (ALUs) can be physically arranged around the perimeter of the memory array or between the banks. For instance, operands required for computation can be read directly from adjacent memory rows or columns into the ALUs, and computation results can be written directly back to a nearby location.

[0092] This integrated architecture, where arithmetic logic units are integrated into shared memory, can greatly reduce data movement. Data can be processed without leaving the memory chip or module, achieving physical proximity between computation and storage, thereby minimizing data access latency and power consumption. It is suitable for reduction operations such as chained accumulation, which have extremely high bandwidth and energy efficiency requirements.

[0093] In some embodiments of this disclosure, the plurality of artificial intelligence processor cores include a first artificial intelligence processor core Core 0, the first artificial intelligence processor core Core 0 includes a first shared memory, and the arithmetic logic unit of the first artificial intelligence processor core Core 0 is a first arithmetic logic unit.

[0094] In response to the first AI processor core Core 0 initiating a first accumulation instruction, the first AI processor core Core 0 is configured to read first target data from the first shared memory according to the first accumulation instruction, execute the first accumulation instruction on the first target data by the first arithmetic logic unit to obtain the first accumulated data, and send the first intermediate calculation result through the first communication link.

[0095] For example, the first intermediate calculation result includes the data address, the first accumulated data, and the processor core mask.

[0096] For example, a processor core mask can be used to indicate the target AI processor core among multiple AI processor cores that executes the first accumulation instruction.

[0097] For example, the first intermediate calculation result can be used as the upstream intermediate calculation result of the next processor core that executes the first accumulation instruction.

[0098] For example, take the first AI processor core, Core 0, as the initiator of the chained accumulation operation in the computing cluster.

[0099] For example, when the first AI processor core, Core 0, needs to initiate a chained accumulation operation across multiple cores, the controller of the first AI processor core, Core 0, can obtain and decode the first accumulation instruction. For example, this first accumulation instruction encodes the type of this chained operation (such as cross-core summation), the logical address of the source / target data in shared memory, and the processor core mask that identifies the participating cores.

[0100] For example, based on the data address field carried in the first accumulation instruction, the access logic of the first AI processor core Core0 reads the first target data from the corresponding location in the first shared memory. For example, this data is the local data portion (e.g., a vector or matrix block) contributed by the first AI processor core Core0 in this global accumulation operation.

[0101] For example, the first target data read can be fed into the first arithmetic logic unit. For instance, the specific operation of the first accumulation instruction within the first AI processor core Core 0 could be to perform an initialization process on the first target data (e.g., adding it to a zero value or a specific initial value), or in some implementations, directly treat it as the first accumulated data. The first arithmetic logic unit performs this operation, outputting the first accumulated data.

[0102] For example, the first AI processor core, Core 0, can immediately send out the accumulated data instead of writing it back to shared memory to await transmission. For instance, the transmission control logic packages the corresponding information into a data packet containing the first intermediate computation result.

[0103] For example, the data packet containing the first intermediate calculation result may include:

[0104] (a) Data address: Inherited from the first accumulation instruction, it is used to instruct all subsequent participating AI processor cores which same logical address in their respective shared memory they need to read local data from for accumulation;

[0105] (b) First accumulated data: that is, the result calculated by the first arithmetic logic unit, which serves as the current value of the accumulated sum;

[0106] (c) Processor core mask: This indicates which AI processor cores are the target cores that need to participate in the computation during this chained operation. The masking mechanism can flexibly select the topology of the participating cores; for example, it can be all cores or only a subset of cores on a linear chain.

[0107] For example, the data packet of the first intermediate calculation result can be input into the first communication chain through the direct transmission path between the ALU inside the first artificial intelligence processor core Core 0 and the communication chain.

[0108] In at least one embodiment of this disclosure, once the first intermediate calculation result is sent, it becomes the upstream intermediate calculation result of the next core (such as the second artificial intelligence processor core Core 1) that executes the accumulation instruction, thereby achieving efficient computation and communication.

[0109] In some embodiments of this disclosure, the plurality of artificial intelligence processor cores include a second artificial intelligence processor core Core 1, the second artificial intelligence processor core Core 1 includes a second shared memory, and the arithmetic logic unit of the second artificial intelligence processor core Core 1 is a second arithmetic logic unit.

[0110] In response to the second AI processor core Core 1 receiving the first accumulation instruction and not being the last processor core to execute the first accumulation instruction, the second AI processor core Core 1 is configured to receive upstream intermediate calculation results through the second arithmetic logic unit via the first communication link, read second target data from the second shared memory according to the first accumulation instruction and data address, execute the first accumulation instruction on the second target data and the accumulation data included in the upstream intermediate calculation results to obtain second accumulation data, and send the second intermediate calculation results through the first communication link.

[0111] For example, the second intermediate calculation result includes the data address, the second accumulated data, and the processor core mask.

[0112] For example, the second intermediate calculation result serves as the upstream intermediate calculation result for the next processor core to execute the first accumulation instruction.

[0113] For example, take the second artificial intelligence processor core Core 1 as an intermediate participating node in the chained accumulation operation of the computing cluster.

[0114] For example, when the second AI processor core Core 1 is identified by the processor core mask as needing to participate in the accumulation and is not the last core, the second AI processor core Core 2 can obtain upstream intermediate calculation result data packets (e.g. from the first AI processor core Core 0) through the direct receiving path between its second arithmetic logic unit and the first communication chain.

[0115] For example, the intermediate calculation result data packet may include:

[0116] (a) Data address: Indicates the unified logical address of the local data to be accumulated in all cores;

[0117] (b) Upstream accumulated data: the partial sum accumulated by all upstream cores (such as the first AI processor core Core 0 or other upstream AI processor cores);

[0118] (c) Processor core mask: Identifies all target AI processor cores involved in this chain operation.

[0119] For example, the second AI processor core 1 can read the second target data (i.e., the local data part contributed by the second AI processor core 1 in this global accumulation) from the corresponding location of the second shared memory based on the data address included in the intermediate calculation result data packet.

[0120] For example, the second arithmetic logic unit can receive upstream accumulated data transmitted via a direct path, as well as second target data read from the second shared memory.

[0121] For example, the second arithmetic logic unit can execute the core operation (such as addition) defined by the first accumulation instruction, adding the two together to obtain the second accumulated data. This second accumulated data represents the cumulative sum up to the second AI processor core, Core 1.

[0122] For example, the second AI processor core, Core 1, can package the updated information into a second intermediate computation result data packet.

[0123] For example, the second intermediate calculation result data packet can inherit and maintain the data address and processor core mask in the upstream data packet, and only update the accumulated data to the second accumulated data that has just been calculated.

[0124] For example, the second intermediate computation result data packet can be sent to the next target core (such as the third artificial intelligence processor core 2) on the link via the direct sending path of the second artificial intelligence processor core Core 1 and through the first communication link. The second intermediate computation result data packet then becomes the upstream intermediate computation result of the downstream core (such as the third artificial intelligence processor core Core 2).

[0125] In at least one embodiment of this disclosure, the operating mode of the second AI processor core Core 1 is consistent with that of the initiating core (e.g., the first AI processor core Core 0) and subsequent intermediate cores, enabling the entire chain operation to form a stable computing and communication pipeline. While one AI processor core is performing computation, its upstream AI processor core may be sending data, and its downstream AI processor core may be receiving data, achieving a high degree of operational overlap and maximizing the utilization of hardware resources and communication bandwidth. The intermediate AI processor cores do not need to execute additional instructions or perform explicit synchronization for this collaborative operation; all their operations are triggered and controlled by the received data packets, realizing data flow-driven computation, greatly saving instruction bandwidth, and reducing the software overhead and latency of synchronization between AI processor cores. Furthermore, when forwarding data packets, the intermediate AI processor cores can update only the accumulated data field while keeping the address and mask unchanged, ensuring the consistency of control information propagation throughout the link, simplifying the processing logic of the AI ​​processor cores, and making the data flow deterministic.

[0126] In some embodiments of this disclosure, the plurality of artificial intelligence processor cores include a third artificial intelligence processor core Core 2, the third artificial intelligence processor core Core 2 includes a third shared memory, and the arithmetic logic unit of the third artificial intelligence processor core Core 2 is a third arithmetic logic unit.

[0127] In response to the third AI processor core Core 2 receiving the first accumulation instruction and being the last processor core to execute the first accumulation instruction, the third AI processor core Core 2 is configured to receive the upstream intermediate calculation result through the third arithmetic logic unit via the first communication link, read the third target data from the third shared memory according to the first accumulation instruction and the data address, execute the first accumulation instruction on the third target data and the accumulation data included in the upstream intermediate calculation result to obtain the final accumulation data, and write the final accumulation data into the third shared memory.

[0128] For example, taking the third AI processor core Core 2 as the termination node of the chained accumulation operation in the computing cluster, the third AI processor core Core 2 is configured to process the data stream from the upstream core, complete the final accumulation calculation, and store the global result, thereby terminating the chained operation.

[0129] For example, when the third AI processor core Core 2 is identified by the processor core mask as needing to participate in the accumulation and is determined to be the last core, the third AI processor core Core 2 can obtain upstream intermediate calculation result data packets (such as the second intermediate calculation result from the second AI processor core Core 1) through the direct receiving path between its third arithmetic logic unit and the first communication chain.

[0130] For example, the intermediate calculation result data packet may include:

[0131] (a) Data address: Indicates the unified logical address of the local data to be accumulated in all cores;

[0132] (b) Upstream accumulated data: for example, second accumulated data from the second AI processor core Core 1, such as the accumulated sum up to the second AI processor core Core 1;

[0133] (c) Processor core mask: Identifies all target AI processor cores involved in this chain operation.

[0134] For example, the third AI processor core Core 2 can read the third target data (i.e., the local data contributed by the third AI processor core Core 2 in this global accumulation) from the corresponding location in the third shared memory based on the data address in the intermediate calculation result data packet.

[0135] For example, the third arithmetic logic unit can receive upstream accumulated data transmitted via a direct path, as well as third target data read from the third shared memory.

[0136] For example, the third arithmetic logic unit can execute the core operation (such as addition) defined by the first accumulation instruction, adding the two together to obtain the final accumulated data. This data represents the sum of the local data of all participating cores (e.g., the first AI processor core Core 0, the second AI processor core Core 1, and the third AI processor core Core 2).

[0137] For example, as the endpoint of the chained operation, the third AI processor core, Core 2, does not need to package the computation result and continue sending it to the communication chain. This interrupts the continued transmission of data packets, marking the completion of the chained accumulation operation.

[0138] For example, the third AI processor core, Core 2, can write the final accumulated data to the result address specified by the instruction or system in the third shared memory via an efficient path between itself and the shared memory, thus archiving the global calculation results. At this point, the final result can be read by subsequent instructions or accessed by other AI processor cores in the cluster.

[0139] In at least one embodiment of this disclosure, the operating mode of the third AI processor core, Core 2, differs from that of the intermediate nodes, allowing the chained data flow to terminate naturally and deterministically after all computational tasks are completed, without the need for additional "stop" or "end" instructions, thus simplifying global control. The final AI processor core provides a definite and accessible storage location for the global computation results by writing the final accumulated data to its local shared memory.

[0140] In some embodiments of this disclosure, each AI processor core may be configured to determine whether it is a processor core executing the first accumulation instruction based on the processor core mask in the upstream intermediate computation result in response to receiving the upstream intermediate computation result.

[0141] For example, when an upstream intermediate computation result data packet (e.g., from the first AI processor core Core 0) arrives at the link input interface of the second AI processor core Core 1 through the first communication chain, the processor core mask field it includes can be extracted and sent to a dedicated mask decoding and matching logic unit.

[0142] For example, the logic unit can compare the received mask with the unique identifier (such as Core ID) of the core of this artificial intelligence processor.

[0143] For example, a processor core mask can be a bitmap, where each bit corresponds to an AI processor core in the cluster.

[0144] For example, the processor core mask 0b0111 (binary) can be used to indicate that the first AI processor core Core 0, the second AI processor core Core 1, and the third AI processor core Core 2 are involved in this operation.

[0145] For example, the matching logic of this logic unit can check whether the mask bit corresponding to the core ID of this artificial intelligence processor is set (e.g., "1").

[0146] In at least one embodiment of this disclosure, the processor core mask significantly simplifies the control complexity of the artificial intelligence chip and improves decision-making speed. The significantly reduced overhead of irrelevant artificial intelligence processor cores improves the resource utilization efficiency and overall throughput of the entire cluster.

[0147] Figure 4 A schematic block diagram of an artificial intelligence processor core provided in at least one embodiment of the present disclosure is shown.

[0148] At least one embodiment of this disclosure also provides an artificial intelligence processor core, such as Figure 4 As shown, the core 300 of this artificial intelligence processor includes an arithmetic logic unit 0 (ALU 0).

[0149] The arithmetic logic unit 0 is configured to communicate with a first communication chain that connects the multiple AI processor cores when it is connected to an AI chip that includes multiple AI processor cores, and to send or receive data directly through the first communication chain.

[0150] The core 300 of the artificial intelligence processor is configured to execute a first accumulation instruction by arithmetic logic unit 0 and directly transmit at least one intermediate calculation result through a first communication link.

[0151] For example, the Core 300 AI processor can be a basic processing unit for performing AI computing tasks.

[0152] For example, the Core 300 AI processor can be used to perform specific computational operations such as matrix multiplication and addition, vector operations, and nonlinear activation involved in deep learning and high-performance computing.

[0153] For example, the AI ​​processor core Core 300 can be a basic unit constituting an AI chip as provided in any of the foregoing embodiments.

[0154] For example, when the AI ​​processor core 300 is connected to an AI chip that includes multiple AI processor cores, its hardware interface can be designed to physically interface with the first communication chain in the AI ​​chip that connects all the AI ​​processor cores.

[0155] For example, the arithmetic logic unit 0 can establish a communication connection with this external first communication link through a dedicated path within the artificial intelligence processor core 300 (e.g., through a multiplexer or a direct connection).

[0156] For example, arithmetic logic unit 0 may include a direct transmit port that allows arithmetic logic unit 0 to directly drive its output data onto the first communication chain.

[0157] For example, arithmetic logic unit 0 may also include a direct receive port that allows arithmetic logic unit 0 to directly obtain input data from the first communication link.

[0158] For example, the AI ​​processor core 300 can be configured to recognize and execute a specific first accumulation instruction.

[0159] For example, the specific functions and beneficial technical effects of the artificial intelligence processor core 300 and the arithmetic logic unit 0 can be found in the descriptions of the artificial intelligence processor core and the arithmetic logic unit in the foregoing embodiments, which will not be repeated here.

[0160] In at least one embodiment of this disclosure, when multiple artificial intelligence processor cores similar to artificial intelligence processor core 300 are integrated into an artificial intelligence chip, no additional complex adaptation is required. The direct connection between the arithmetic logic unit corresponding to each artificial intelligence processor core and the first communication chain can constitute a low-latency, high-bandwidth, and high-efficiency distributed computing network.

[0161] Figure 5 This is a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0162] For example, such as Figure 5 As shown, the electronic device 700 includes at least one processor 701 and at least one memory 702. The at least one memory 702 includes one or more computer program modules. These computer program modules are stored in the memory 702 and configured to be executed by the at least one processor 701. The one or more computer program modules include instructions for performing computational tasks of the aforementioned artificial intelligence chip. When executed by the at least one processor 701, they can perform one or more steps of the computational tasks of the artificial intelligence chip provided in at least one embodiment of this disclosure. The memory 702 and the processor 701 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0163] For example, processor 701 may be a central processing unit (CPU), digital signal processor (DSP), image processor (GPU), general-purpose graphics processor (GPGPU), or other processing unit with data processing capabilities and / or program execution capabilities, such as a field-programmable gate array (FPGA), for example, an artificial intelligence chip used to implement at least one embodiment of this disclosure; for example, the central processing unit (CPU) may be an x86, ARM, RISC-V architecture, etc. Processor 701 may be a general-purpose processor or a special-purpose processor, and may control other components in electronic device 700 to perform desired functions.

[0164] For example, memory 702 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc.

[0165] Figure 6 This is a schematic block diagram of another electronic device provided for at least one embodiment of the present disclosure.

[0166] The electronic devices in at least one embodiment of this disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, personal digital assistants (PDAs), tablet computers (PADs), portable multimedia players (PMPs), in-vehicle terminals (e.g., in-vehicle navigation terminals), wearable electronic devices, and fixed terminals such as digital TVs and desktop computers. Figure 5 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0167] The electronic device includes at least one processor and a memory. The processor may be referred to as processing device 801 as described below, and the memory may include at least one of ROM 802, RAM 803, and storage device 808 as described below. The memory is used to store programs for performing the methods described in the various method embodiments above; the processor is configured to execute the programs stored in the memory. The processor may include a central processing unit (CPU) or other forms of processing unit having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0168] like Figure 6As shown, the electronic device 800 may include a processing unit 801 (e.g., a central processing unit (CPU), digital signal processor (DSP), image processor (GPU), general-purpose graphics processor (GPGPU), artificial intelligence (AI) accelerator, or other forms of processing unit with data processing and / or program execution capabilities), which can perform various appropriate actions and processes according to a program stored in ROM 802 or a program loaded from storage device 808 into RAM 803. RAM 803 also stores various programs and data required for the operation of the electronic device 800. The processing unit 801, ROM 802, and RAM 803 are interconnected via bus 804. Input / output (I / O) interfaces are also connected to bus 804.

[0169] Typically, the following devices can be connected to I / O interface 805: input devices 806 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 807 including, for example, displays, speakers, vibrators, etc.; storage devices 808 including, for example, magnetic tapes, hard disks, etc.; and communication devices 809. Communication device 809 allows electronic device 800 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 6 An electronic device 800 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively.

[0170] Although the present disclosure has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to the embodiments of the present disclosure, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the inventive concept of the present disclosure are within the scope of protection claimed by the present disclosure.

[0171] The following points should be noted regarding this disclosure:

[0172] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0173] (2) For clarity, the thickness of layers or regions in the drawings used to describe embodiments of the present disclosure is enlarged or reduced, i.e., these drawings are not drawn to actual scale.

[0174] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0175] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. An artificial intelligence chip, characterized in that, The artificial intelligence chip includes multiple artificial intelligence processor cores and at least one communication link, and each of the artificial intelligence processor cores includes an arithmetic logic unit. Wherein, the at least one communication chain includes a first communication chain, which communicatively connects the plurality of artificial intelligence processor cores. Each arithmetic logic unit corresponding to the AI ​​processor core establishes a communication connection with the first communication chain, enabling the corresponding arithmetic logic unit to directly send or receive data through the first communication chain. Each of the AI ​​processor cores is configured to execute a first accumulation instruction by a corresponding arithmetic logic unit and directly transmit at least one intermediate calculation result corresponding to the first accumulation instruction through the first communication link. Specifically, for each of the AI ​​processor cores, the arithmetic logic unit is connected to the first communication chain via a first path to directly receive data, and is connected to the first communication chain via a second path to directly send data; The first path is configured to directly and unidirectionally transmit data from the first communication chain to the input port of the arithmetic logic unit corresponding to each AI processor core; the second path is configured to directly and unidirectionally drive the calculation result of the arithmetic logic unit corresponding to each AI processor core to the first communication chain.

2. The artificial intelligence chip according to claim 1, characterized in that, Each of the aforementioned AI processor cores also includes a first computing unit and a first multiplexer. Both the arithmetic logic unit and the first computation unit are connected to the first communication link via the first multiplexer and the second path. The first multiplexer is configured to select, based on a selection signal, one of the first computing unit and the arithmetic logic unit to be connected to the first communication link via the second path.

3. The artificial intelligence chip according to claim 1, characterized in that, Each of the AI ​​processor cores also includes shared memory, and the arithmetic logic unit is communicatively connected to or integrated into the shared memory.

4. The artificial intelligence chip according to claim 1, characterized in that, The plurality of artificial intelligence processor cores includes a first artificial intelligence processor core, the first artificial intelligence processor core includes a first shared memory, and the arithmetic logic unit of the first artificial intelligence processor core is a first arithmetic logic unit. In response to the first AI processor core initiating the first accumulation instruction, the first AI processor core is configured to read first target data from the first shared memory according to the first accumulation instruction, execute the first accumulation instruction on the first target data by the first arithmetic logic unit to obtain first accumulated data, and send the first intermediate calculation result through the first communication link. The first intermediate calculation result includes a data address, the first accumulated data, and a processor core mask. The processor core mask is used to indicate the target AI processor core among the plurality of AI processor cores that executes the first accumulated instruction. The first intermediate calculation result serves as the upstream intermediate calculation result of the next processor core to execute the first accumulated instruction.

5. The artificial intelligence chip according to claim 4, characterized in that, The plurality of AI processor cores includes a second AI processor core, the second AI processor core includes a second shared memory, and the arithmetic logic unit of the second AI processor core is a second arithmetic logic unit. In response to the second AI processor core receiving the first accumulation instruction and not being the last processor core to execute the first accumulation instruction, the second AI processor core is configured to: receive upstream intermediate calculation results via the second arithmetic logic unit through the first communication link; read second target data from the second shared memory according to the first accumulation instruction and the data address; execute the first accumulation instruction on the second target data and the accumulated data included in the upstream intermediate calculation results to obtain second accumulated data; and send the second intermediate calculation results via the first communication link. The second intermediate calculation result includes the data address, the second accumulated data, and the processor core mask. The second intermediate calculation result serves as the upstream intermediate calculation result for the next processor core to execute the first accumulated instruction.

6. The artificial intelligence chip according to claim 4, characterized in that, The plurality of AI processor cores includes a third AI processor core, the third AI processor core includes a third shared memory, and the arithmetic logic unit of the third AI processor core is a third arithmetic logic unit. In response to the third AI processor core receiving the first accumulation instruction and being the last processor core to execute the first accumulation instruction, the third AI processor core is configured to: receive upstream intermediate calculation results through the third arithmetic logic unit via the first communication link; read third target data from the third shared memory according to the first accumulation instruction and the data address; execute the first accumulation instruction on the third target data and the accumulation data included in the upstream intermediate calculation results to obtain final accumulation data; and write the final accumulation data into the third shared memory.

7. The artificial intelligence chip according to claim 1, characterized in that, Each of the AI ​​processor cores is configured to, in response to receiving an upstream intermediate computation result, determine whether it is the processor core executing the first accumulation instruction based on the processor core mask in the upstream intermediate computation result.

8. An artificial intelligence processor core, characterized in that, Includes arithmetic logic units, The arithmetic logic unit is configured to, when connected to an artificial intelligence chip including multiple artificial intelligence processor cores, communicate with a first communication chain that communicates with the multiple artificial intelligence processor cores, and directly send or receive data through the first communication chain; The artificial intelligence processor core is configured such that the arithmetic logic unit executes a first accumulation instruction and directly transmits at least one intermediate calculation result through the first communication link; The arithmetic logic unit is connected to the first communication chain via a first path to directly receive data, and to the first communication chain via a second path to directly send data. The first path is configured to directly and unidirectionally transmit data from the first communication chain to the input port of the arithmetic logic unit; the second path is configured to directly and unidirectionally drive the calculation result of the arithmetic logic unit to the first communication chain.

9. An electronic device, characterized in that, The electronic device includes an artificial intelligence chip as described in any one of claims 1-7 or an artificial intelligence processor core as described in claim 8.

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