Cascade forest model-based FPGA score prediction method, system and device, and medium

Abstract

The invention discloses an FPGA score prediction method, system and device based on a cascade forest model and a medium. The method comprises the following steps: acquiring original match data, and performing offline training on a cascade forest model by using the original match data to obtain model parameter information; burning the model parameter information on an FPGA (Field Programmable Gate Array) chip; and inputting the real-time match data into the FPGA chip for score prediction to obtain a score prediction result output by the FPGA chip. According to the method, the limitation of a traditional random forest model is broken through, and the probability vector output by each layer and the original input features are spliced and progressively constructed through a multi-layer cascade forest module. By means of the design, more complex high-order features can be extracted layer by layer, and the expression ability and prediction precision of the model are remarkably improved. On the aspect of hardware, through accurate scheduling of the reasoning process and effective utilization of hardware resources, efficient operation on edge equipment with limited resources can be achieved, and meanwhile the requirement for real-time performance is met; and the low-power-consumption and high-efficiency reasoning capability is realized.

Description

Technical Field

[0001] This invention relates to the field of random forest inference technology, specifically to an FPGA score prediction method, system, device, and medium based on a cascaded forest model. Background Technology

[0002] With the trend towards intelligent sports analytics and data-driven prediction, match score prediction is gradually evolving from traditional statistical models to intelligent prediction models based on machine learning. Traditional methods based on regression analysis, probability statistics, or expert systems, such as the Poisson distribution model and the ELO scoring system, while having a certain theoretical foundation, are weak in their ability to model nonlinear relationships, feature interactions, and high-dimensional data. In particular, their prediction accuracy is limited when facing complex and dynamically evolving match systems.

[0003] With the development of machine learning and deep learning, more and more researchers are beginning to use methods such as support vector machines (SVM) and neural networks to model competition results. In particular, neural network models (such as CNN, RNN, and LSTM) have achieved remarkable results in tasks such as score prediction due to their powerful nonlinear modeling capabilities and hierarchical feature abstraction capabilities.

[0004] However, these deep learning models generally rely on a large number of training samples and high-performance hardware support, resulting in high computational overhead, high power consumption, and long inference latency, which limits their application in embedded devices, mobile terminals, or real-time prediction scenarios. Moreover, deep neural networks have poor interpretability, which is not conducive to the practical application of models in regulatory, commercial, and scientific research scenarios. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide an FPGA score prediction method, system, device and medium based on a cascaded forest model.

[0006] The first aspect of this invention provides an FPGA score prediction method based on a cascaded forest model, comprising the following steps: Obtain the original competition data and use it to train the cascaded forest model offline to obtain model parameter information. The model parameter information is burned into the FPGA chip; Real-time match data is input into the FPGA chip for score prediction, and the score prediction result output by the FPGA chip is obtained.

[0007] Furthermore, the cascaded forest model is formed by stacking multiple layers, each layer including multiple independent random forest sub-models and an average fusion unit; The random forest sub-model is used to independently process the input data and obtain the probability distribution; The average fusion unit is used to merge the probability distributions output by multiple random forest sub-models into a fused probability vector.

[0008] Furthermore, the offline training of the cascaded forest model using the original competition data to obtain model parameter information specifically includes the following steps: The original competition data is preprocessed to obtain the original feature vectors, and the original feature vector set is constructed. Select several original feature vectors from the original feature vector set as input vectors and input them into the first layer of the cascaded forest model; The layer is trained using the input vector to obtain and output the fusion probability vector; The fusion probability vector output by this layer is concatenated with the original feature vector to obtain the feature enhancement vector; The feature enhancement vector is used as the input vector for the next layer of the cascaded forest model. The process of training the layer using the input vector to obtain the fusion probability vector and outputting it is repeated until all layers of the cascaded forest model have been trained.

[0009] Furthermore, the step of concatenating the fusion probability vector output by this layer with the original feature vector to obtain the feature enhancement vector specifically includes the following steps: When the input vector is input to the target layer of the cascaded forest model, the input vector is cached in sequence; After the target layer outputs the fusion probability vector, the input vector and the fusion probability vector are concatenated bit by bit to obtain the feature enhancement vector.

[0010] Furthermore, the model parameter information consists of node information of each random forest sub-model in each layer of the cascaded forest model; the node information includes feature index information, comparison threshold information, and leaf node probability distribution information.

[0011] Furthermore, the step of programming the model parameter information onto the FPGA chip specifically includes the following steps: The on-chip memory storage address of the FPGA chip is divided into multiple levels of partitions, and an independent partition is made for the probability distribution information of leaf nodes; the levels specifically include model layers, random forest sub-models, decision trees, and tree nodes; The model parameter information is mapped hierarchically to the corresponding partitions of the on-chip memory of the FPGA chip; Dynamic bit-width compression is performed on the model parameter information stored in the on-chip memory according to the score prediction requirements.

[0012] Furthermore, the step of inputting real-time match data into the FPGA chip for score prediction specifically includes the following steps: The computational load of each layer of the cascaded forest model is determined based on the model parameter information stored in the on-chip memory of the FPGA chip. The load is dynamically allocated when the FPGA chip performs score prediction based on the determined computational load.

[0013] Another aspect of the present invention discloses an FPGA score prediction system based on a cascaded forest model, which is loaded with the aforementioned FPGA chip for score prediction; it includes a feature caching unit, a decision tree inference unit, an inter-layer probability caching unit, and an output unit. The feature caching unit is used to cache real-time match data and input it into the first layer of the cascaded forest model in the FPGA chip. The decision tree inference unit is used to call the FPGA chip to predict the score and cache the feature enhancement vector output by each layer in the cascaded forest model in the inter-layer probability cache unit so as to perform vector concatenation in the next layer. The output unit is used to output the fusion probability vector output from the last layer of the cascaded forest model as the score prediction result.

[0014] Another aspect of the present invention discloses an electronic device, including a processor and a memory; The memory is used to store programs; The processor executes the program to implement the above-described FPGA score prediction method based on a cascaded forest model.

[0015] In another aspect, the present invention discloses a computer-readable storage medium storing a program that is executed by a processor to implement the above-described FPGA score prediction method based on a cascaded forest model.

[0016] This invention also discloses a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device can read the computer instructions from the computer-readable storage medium and execute the computer instructions, causing the computer device to perform the aforementioned method.

[0017] The embodiments of this invention have the following beneficial effects: This invention overcomes the limitations of traditional random forest models by constructing a progressive model through multi-layered cascaded forest modules, where the probability vector output by each layer is concatenated with the original input features. This design enables the extraction of more complex high-order features layer by layer, significantly improving the model's expressive power and prediction accuracy. Unlike traditional shallow forests, the multi-layered structure of this invention not only solves the problem of insufficient feature abstraction capabilities but also effectively improves the accuracy and generalization ability in score prediction tasks through deep modeling of features at each layer. In terms of hardware implementation, this invention, through precise scheduling of the inference process and effective utilization of hardware resources, enables the system to run efficiently on resource-constrained edge devices while ensuring real-time requirements. This allows the system to achieve low-power, high-efficiency inference capabilities while ensuring prediction accuracy. This design gives the system strong deployment flexibility on edge devices, adapting to various hardware platforms with different computing capabilities, and greatly expanding the application scope of this technology.

[0018] Additional aspects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description or may be learned by practice of the invention. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a basic implementation flowchart of an FPGA score prediction method based on a cascaded forest model according to the present invention. Figure 2 This is a schematic diagram of the decision tree structure of the random forest sub-model of this invention; Figure 3 This is a schematic diagram of the process by which the probability distributions output by multiple random forest sub-models are merged into a fused probability vector according to the present invention. Figure 4 This is a schematic diagram of the implementation structure of an FPGA score prediction system based on a cascaded forest model according to the present invention. Figure 5 This is a schematic diagram of the structure of an electronic device according to the present invention; Figure 6 This is a schematic diagram of a computer-readable storage medium structure according to the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0022] like Figure 1 As shown, the first embodiment of the present invention discloses an FPGA score prediction method based on a cascaded forest model, comprising the following steps: S1. Obtain the original competition data and use the original competition data to train the cascaded forest model offline to obtain model parameter information; S2. Burn the model parameter information onto the FPGA chip; S3. Input the real-time match data into the FPGA chip to predict the score and obtain the score prediction result output by the FPGA chip.

[0023] This invention implements a deep cascaded forest structure (gcForest) in an FPGA architecture. The class probability distribution output by each layer is concatenated with the original features and then input into the next layer, thereby achieving equivalent modeling of hierarchical high-order feature representation and deep learning functions, which significantly improves the model's expressive power and prediction accuracy.

[0024] The implementation process of each step of this invention is described in detail below: S1. Obtain the original competition data and use it to train the cascaded forest model offline to obtain model parameter information. Specifically, step S1 includes the following steps: S1-1. Perform data preprocessing on the original competition data to obtain the original feature vectors and construct the original feature vector set.

[0025] In this embodiment of the invention, the original match data includes match information extracted from various sports databases, such as scores, players, and match venues. After acquiring the original match data, this embodiment of the invention performs data preprocessing. Preprocessing operations include cleaning the original match data to remove invalid or outliers; normalizing the data to make it conform to the standard format for training models; and feature construction, extracting key feature variables from the original data, ultimately obtaining original feature vectors that meet the model input requirements, and forming an original feature vector set.

[0026] S1-2. Select several original feature vectors from the original feature vector set as input vectors and input them into the first layer of the cascaded forest model.

[0027] The preprocessed original feature vectors have high training quality. In this embodiment of the invention, several original feature vectors can be selected from the original feature vector set based on model training requirements to train the cascaded forest model offline. Specifically, original feature vectors corresponding to different matches can be selected for training based on key indicators such as the match venue and rules, resulting in higher accuracy for the trained cascaded forest model in processing real-time match data corresponding to the match venue and rules.

[0028] S1-3. Train this layer using the input vector to obtain the fusion probability vector and output it; The cascaded forest model disclosed in this embodiment of the invention is formed by stacking multiple layers, each layer including multiple independent random forest sub-models and an averaging fusion unit; wherein the random forest sub-models are used to independently process the input data to obtain probability distributions; the averaging fusion unit is used to merge the probability distributions output by multiple random forest sub-models into a fused probability vector.

[0029] like Figure 2 As shown, in this embodiment of the cascaded forest model, the random forest sub-model deployed at each layer adopts a binary decision tree structure. Each tree consists of several feature indexers, threshold comparators, and MUX nodes. The category output is determined through parallel comparison and path selection, and the prediction result is finally obtained through voting or probability weighting mechanisms. In terms of hardware implementation, this embodiment of the invention adopts a comparator chain structure, combined with on-chip memory and logic units, to achieve low-latency, low-power concurrent inference.

[0030] like Figure 3 As shown, in this embodiment of the invention, based on the random forest sub-model deployed at each layer, multiple independent random forest sub-models deployed at each layer are trained in parallel to enhance the diversity and robustness of the cascaded forest model. During model training, each decision tree (as part of the random forest) outputs leaf node probabilities based on the input data; these probabilities are fused by an averager to form a fused probability vector of a single random forest, which serves as the output data for this layer.

[0031] S1-4. Concatenate the fusion probability vector output by this layer with the original feature vector to obtain the feature enhancement vector.

[0032] Specifically, the fusion probability vector output by this layer is concatenated with the original feature vector to obtain the feature enhancement vector, which includes the following steps: S1-4-1. When input vectors are fed into the target layer of the cascaded forest model, the input vectors are cached in order; S1-4-2. After the target layer outputs the fusion probability vector, the input vector and the fusion probability vector are concatenated bit by bit to obtain the feature enhancement vector.

[0033] Preferably, in this embodiment of the invention, the input of each layer of the cascaded forest model includes two parts: the preprocessed original feature vector and the fusion probability vector from the output of the previous layer (in the first layer at the start of training, the input only includes the original features). The concatenation of the original feature vector and the fusion probability vector forms an "input augmentation mechanism," enabling the model to extract higher-order abstract features layer by layer.

[0034] S1-5. Use the feature enhancement vector as the input vector for the next layer of the cascaded forest model, return to train the layer using the input vector, obtain the fusion probability vector and output it, repeat this step until all layers of the cascaded forest model have been trained.

[0035] In this embodiment of the invention, inter-layer probability fusion and feature concatenation are repeated during training, progressing layer by layer. The output fusion probability vector of each layer is used as the input of the next layer, forming a multi-layer deep structure. Training continues until the model's prediction performance (such as accuracy metrics) on the independent validation set stabilizes, in order to prevent overfitting and ensure model convergence.

[0036] The embodiments of the present invention output a complete probability vector for each tree, and achieve finer-grained prediction output through probability vector fusion and decision cascade structure, thereby improving the interpretability and prediction robustness of the model.

[0037] S2. Burn the model parameter information onto the FPGA chip.

[0038] After completing the offline training of the cascaded forest model, this embodiment of the invention exports the model's parameter information. The model parameter information can reflect the model's structure. For example, the model parameter information consists of the node information of each random forest sub-model in each layer of the cascaded forest model; the node information includes feature index information (feature positions used for decision comparison), comparison threshold information (comparison conditions for decision nodes), and leaf node probability distribution information (the final output of the decision tree).

[0039] The cascaded forest model can be converted into a hardware-friendly format and written to the FPGA's on-chip memory using the model parameter information. The conversion process includes numerical normalization and data alignment, optimizing the bit width of the model parameters and facilitating bit-by-bit compression on the FPGA chip.

[0040] Specifically, the model parameter information is programmed onto the FPGA chip, which includes the following steps: S2-1. Divide the on-chip memory storage address of the FPGA chip into multiple levels of partitions, and divide the probability distribution information of leaf nodes into independent partitions; the specific levels include model layer, random forest sub-model, decision tree and tree node; S2-2. Map the model parameter information hierarchically to the corresponding partitions of the on-chip memory of the FPGA chip; S2-3. Dynamically compress the bit width of the model parameter information stored in the on-chip memory according to the score prediction requirements.

[0041] In this embodiment of the invention, the node information (index + threshold + subtree pointer) of each tree is stored hierarchically in a BRAM (Block RAM) partition, and the probability vectors of all leaf nodes of the sub-models are stored independently in a dedicated probability BRAM group. The address space in the BRAM partition is divided according to the hierarchy of "forest layer → sub-model → tree → node", and dynamic bit width compression is performed to reduce the storage overhead of the probability vectors. Finally, the structured data of the decision tree is burned into the BRAM to construct the FPGA hierarchical inference logic.

[0042] The embodiments of the present invention achieve a good balance among energy consumption, expressive power, and deployment feasibility, providing a practical solution for deploying the cascaded forest model of the present invention on edge devices.

[0043] S3. Input the real-time match data into the FPGA chip to predict the score and obtain the score prediction result output by the FPGA chip.

[0044] In this embodiment of the invention, the cascaded forest model is controlled via a pipeline for pizza prediction. After the Nth layer completes inference, data transfer between layers is achieved through BRAM and FIFO (First Input First Output). Once the BRAM and FIFO data are synchronized, a feature enhancement vector (original feature vector + fused probability vector) is generated in the FPGA chip through a bit-joining circuit. The joined feature enhancement vector serves as the input for the next layer.

[0045] In some embodiments, real-time match data is input into an FPGA chip for score prediction, specifically including the following steps: S3-1. Determine the computational load of each layer of the cascaded forest model based on the model parameter information stored in the on-chip memory of the FPGA chip.

[0046] S3-2. Based on the determined computational load, dynamically allocate the load when the FPGA chip performs score prediction.

[0047] This invention introduces a priority arbitration mechanism to dynamically allocate computing resources to the FPGA chip based on computational load. It automatically adjusts the execution priority between layers according to the computational complexity and data flow of each layer, ensuring that layers with high computational demands receive processing resources first. This makes the computational pace of each layer more similar, thereby minimizing inference latency. The priority arbitration mechanism not only improves system throughput but also ensures the efficiency of the inference process, making it particularly suitable for edge devices with high real-time requirements.

[0048] The second embodiment of this invention discloses an FPGA score prediction system based on a cascaded forest model, which is equipped with the aforementioned FPGA chip for score prediction. Figure 4 As shown, the system includes a feature caching unit, a decision tree inference unit, an inter-layer probability caching unit, and an output unit.

[0049] Feature caching units are used to cache real-time match data and input it into the first layer of the cascaded forest model in the FPGA chip; The decision tree inference unit is used to call the FPGA chip to predict the score and cache the feature enhancement vectors output by each layer in the cascaded forest model in the inter-layer probability cache unit so that the vectors can be concatenated in the next layer. The output unit is used to output the fused probability vector from the last layer of the cascaded forest model as the score prediction result.

[0050] In this embodiment of the invention, each tree in the model on the FPGA chip is controlled by a state machine, which jumps according to the node logic, adapts to the FPGA structure, and improves the running efficiency; it supports the simultaneous operation of multiple tree modules, thereby increasing the throughput; each decision tree is efficiently computed in parallel in hardware, thus solving the computational bottleneck of traditional methods when dealing with complex decision paths, and adapting to application scenarios with high real-time requirements.

[0051] This invention employs a collaborative mechanism of BRAM and FIFO. This module concatenates the probability vector output from each layer with the original input features and stores it in a high-efficiency cache unit, thereby optimizing data flow and feature fusion. Furthermore, to further reduce hardware resource consumption and improve computational efficiency, dynamic bit-width compression is introduced during probability vector concatenation. The bit width of the probability vector is dynamically adjusted according to actual needs, reducing BRAM usage while maintaining sufficient prediction accuracy. This innovation significantly reduces hardware costs and improves system memory utilization.

[0052] This invention provides a high-energy-efficiency, low-latency design suitable for edge computing scenarios. Through precise scheduling of the inference process and effective utilization of hardware resources, the system can operate efficiently on resource-constrained edge devices while ensuring real-time requirements. While ensuring prediction accuracy, the system achieves low-power, high-efficiency inference capabilities, enabling deployment and stable operation even on resource-constrained edge devices. The design of this invention provides the system with strong deployment flexibility on edge devices, adapting to various hardware platforms with different computing capabilities, and greatly expanding the application scope of cascaded forest models.

[0053] Figure 5 This is a schematic diagram of the electronic device proposed in the third embodiment of the present invention. In this embodiment, the memory stores program instructions for implementing an FPGA score prediction method based on a cascaded forest model according to any of the above embodiments. The processor executes the program instructions stored in the memory to perform FPGA score prediction based on the cascaded forest model. The processor can also be called a CPU (Central Processing Unit). The processor may be an integrated circuit chip with signal processing capabilities. The processor can also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor or any conventional processor, etc.

[0054] The methods described in the first embodiment of the present invention are applicable to the embodiments of the present electronic device. The specific functions implemented by the embodiments of the present electronic device are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above methods.

[0055] Figure 6 This is a schematic diagram of the structure of a computer-readable storage medium according to the fourth embodiment of the present invention. The computer-readable storage medium of the fourth embodiment stores program instructions capable of implementing the above-described FPGA score prediction method based on a cascaded forest model. These program instructions can be stored in the storage medium in the form of a software product, including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods of various embodiments of the present invention. The aforementioned computer-readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks, or terminal devices such as computers, servers, mobile phones, and tablets.

[0056] The methods described in the first embodiment of the present invention are applicable to the computer-readable storage medium embodiment. The specific functions implemented by the computer-readable storage medium embodiment are the same as those in the above method embodiment, and the beneficial effects achieved are also the same as those achieved by the above method.

[0057] This embodiment also provides a computer program product that, when run on a computer, causes the computer to perform the aforementioned steps to implement the FPGA score prediction method based on a cascaded forest model provided in the above embodiment.

[0058] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the embodiments of the present invention are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0059] Those skilled in the art will understand that modules in the device of the embodiments of the present invention can be adaptively modified and placed in one or more devices different from those embodiments. Modules, units, or components in the embodiments of the present invention can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components. Except where at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all features disclosed in this specification (including the corresponding claims, abstract, and drawings) and all processes or units of any method or device so disclosed. Unless expressly stated otherwise, each feature disclosed in this specification (including the corresponding claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0060] Through the above description of the embodiments, those skilled in the art will understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0061] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0062] Furthermore, the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. In particular, for embodiments such as apparatus and devices, since they are basically similar to the method embodiments, the relevant parts can be referred to the description of the method embodiments. The apparatus, devices, and other embodiments described above are merely illustrative, and the modules, units, etc., described as separate components may or may not be physically separate, that is, they may be located in one place or distributed in multiple places, such as nodes in a system network. Specifically, some or all of the modules and units can be selected according to actual needs to achieve the purpose of the above-described embodiment solutions. Those skilled in the art can understand and implement this without creative effort.

[0063] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0064] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0065] Furthermore, the terms "first," "second," etc., used in the embodiments of this invention are for descriptive purposes only and should not be construed as indicating or implying relative importance, or implicitly specifying the number of technical features indicated in this embodiment. Therefore, features defined with terms such as "first" and "second" in the embodiments of this invention can explicitly or implicitly indicate that the embodiment includes at least one of those features. In the description of this invention, the word "multiple" means at least two or more, such as two, three, four, etc., unless otherwise explicitly specified in the embodiments.

[0066] In embodiments of the present invention, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of the present invention may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0067] Although embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention. Other embodiments of the present invention will readily conceive of by considering the specification and practicing the invention. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims.

Claims

1. An FPGA score prediction method based on a cascaded forest model, characterized in that, Includes the following steps: Obtain the original competition data and use it to train the cascaded forest model offline to obtain model parameter information. The model parameter information is burned into the FPGA chip; Real-time match data is input into the FPGA chip for score prediction, and the score prediction result output by the FPGA chip is obtained.

2. The FPGA score prediction method based on a cascaded forest model according to claim 1, characterized in that, The cascaded forest model is formed by stacking multiple layers, each layer including multiple independent random forest sub-models and an average fusion unit; The random forest sub-model is used to independently process the input data and obtain the probability distribution; The average fusion unit is used to merge the probability distributions output by multiple random forest sub-models into a fused probability vector.

3. The FPGA score prediction method based on a cascaded forest model according to claim 1, characterized in that, The offline training of the cascaded forest model using the original competition data to obtain model parameter information specifically includes the following steps: The original competition data is preprocessed to obtain the original feature vectors, and the original feature vector set is constructed. Select several original feature vectors from the original feature vector set as input vectors and input them into the first layer of the cascaded forest model; The layer is trained using the input vector to obtain and output the fusion probability vector; The fusion probability vector output by this layer is concatenated with the original feature vector to obtain the feature enhancement vector; The feature enhancement vector is used as the input vector for the next layer of the cascaded forest model. The process of training the layer using the input vector to obtain the fusion probability vector and outputting it is repeated until all layers of the cascaded forest model have been trained.

4. The FPGA score prediction method based on a cascaded forest model according to claim 3, characterized in that, The step of concatenating the fusion probability vector output by this layer with the original feature vector to obtain the feature enhancement vector includes the following steps: When the input vector is input to the target layer of the cascaded forest model, the input vector is cached in sequence; After the target layer outputs the fusion probability vector, the input vector and the fusion probability vector are concatenated bit by bit to obtain the feature enhancement vector.

5. The FPGA score prediction method based on a cascaded forest model according to claim 1, characterized in that, The model parameter information consists of node information of each random forest sub-model in each layer of the cascaded forest model; the node information includes feature index information, comparison threshold information, and leaf node probability distribution information.

6. The FPGA score prediction method based on a cascaded forest model according to claim 5, characterized in that, The process of programming the model parameter information onto the FPGA chip specifically includes the following steps: The on-chip memory storage address of the FPGA chip is divided into multiple levels of partitions, and an independent partition is made for the probability distribution information of leaf nodes; the levels specifically include model layers, random forest sub-models, decision trees, and tree nodes; The model parameter information is mapped hierarchically to the corresponding partitions of the on-chip memory of the FPGA chip; Dynamic bit-width compression is performed on the model parameter information stored in the on-chip memory according to the score prediction requirements.

7. The FPGA score prediction method based on a cascaded forest model according to claim 1, characterized in that, The process of inputting real-time match data into the FPGA chip for score prediction specifically includes the following steps: The computational load of each layer of the cascaded forest model is determined based on the model parameter information stored in the on-chip memory of the FPGA chip. The load is dynamically allocated when the FPGA chip performs score prediction based on the determined computational load.

8. An FPGA score prediction system based on a cascaded forest model, comprising an FPGA chip as described in any one of claims 1-7 for score prediction; characterized in that, It includes a feature caching unit, a decision tree inference unit, an inter-layer probability caching unit, and an output unit; The feature caching unit is used to cache real-time match data and input it into the first layer of the cascaded forest model in the FPGA chip. The decision tree inference unit is used to call the FPGA chip to predict the score and cache the feature enhancement vector output by each layer in the cascaded forest model in the inter-layer probability cache unit so as to perform vector concatenation in the next layer. The output unit is used to output the fused probability vector output from the last layer of the cascaded forest model as the score prediction result.

9. An electronic device, characterized in that, Including the processor and memory; The memory is used to store programs; The processor executes the program to implement an FPGA score prediction method based on a cascaded forest model as described in any one of claims 1-8.

10. A computer-readable storage medium, characterized in that, The storage medium stores a program that is executed by a processor to implement an FPGA score prediction method based on a cascaded forest model as described in any one of claims 1-8.

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