A graph mapping method based on exact synthesis

Abstract

The application discloses a graph mapping method based on exact synthesis, comprising: constructing an exact synthesis structure library based on NPN equivalence class, and inputting a Boolean network; performing k-Cut cutting enumeration on the input Boolean network and calculating a truth table, matching the cutting with a structure in the exact synthesis structure library through Boolean matching, and realizing fast searching in combination with NPN classification; generating a cover network through multi-round mapping optimization, and mining a logic shared node in combination with structure hashing, wherein the multi-round mapping optimization comprises delay-oriented mapping, global area topology optimization and local exact area optimization; generating a new target network based on the optimized cover network, removing redundant nodes and completing final network construction. Through the automatic mapping and redundant removal mechanism of the whole process, the application does not need manual intervention, significantly reduces the manual cost of the technical mapping link in chip design, and is especially suitable for efficient design of complex circuits and emerging majority logic base technologies.

Description

Technical Field

[0001] This application relates to the field of electronic design automation technology, and in particular to a graph mapping method based on precise synthesis. Background Technology

[0002] In digital integrated circuit design, technology mapping is a crucial step in converting technology-independent Boolean networks (such as NAND graphs and majority voting graphs) into technology-dependent structures (such as standard cells and lookup tables), directly impacting chip area, latency, and power consumption performance. Traditional technology mapping methods have significant limitations:

[0003] On the one hand, there is insufficient logical sharing capability. Existing methods mostly rely on a single graph representation (such as only based on AIG) or a fixed cutting strategy, making it difficult to explore the sharing potential between different logical structures, resulting in too many redundant nodes and limited area optimization effects. For example, LUT-based mapping is prone to losing the shared logic of the original network when covering circuits, and additional nodes are introduced after decomposition.

[0004] On the other hand, global optimization capabilities are limited. Traditional methods often employ local greedy strategies (such as optimizing only a single node segment), lacking a coordinated consideration of the global circuit area and delay, and are prone to getting trapped in local optima. At the same time, the manual design mapping process requires adjusting parameters for different technology nodes, which is inefficient and difficult to adapt to the design requirements of complex circuits and emerging technologies (such as adiabatic quantum flux parametric superconducting circuits and quantum dot cellular automata).

[0005] Therefore, there is an urgent need for an efficient mapping method that can dynamically integrate the advantages of multiple graph representations and achieve global optimization and logical sharing, so as to break through the performance bottleneck of traditional methods. Summary of the Invention

[0006] The purpose of this application is to provide a graph mapping method based on precise synthesis to solve one or more technical problems existing in the prior art, or at least to provide a beneficial option or create conditions.

[0007] To achieve the above-mentioned objectives, this application employs the following technical solution:

[0008] This application provides a graph mapping method based on exact synthesis, including:

[0009] Construct a precise synthesis structure library based on NPN equivalence classes and input a Boolean network;

[0010] The input Boolean network is k-cut enumerated and the truth table is calculated. The cuts are matched with the structures in the accurate synthesis structure library through Boolean matching. Combined with NPN classification, fast search is achieved.

[0011] The overlay network is generated through multi-round mapping optimization, and shared nodes are obtained by combining structural hash mining logic. The multi-round mapping optimization includes delay-guided mapping, global area topology optimization, and local precise area optimization.

[0012] A new target network is generated based on the optimized overlay network, redundant nodes are removed, and the final network construction is completed.

[0013] Furthermore, the input Boolean network is k-cut enumerated and a truth table is computed. Boolean matching is used to match the cuts with structures in the precise synthetic structure library. Combined with NPN classification, fast lookup is achieved, including:

[0014] The input Boolean network cut enumeration is performed in topological order, preserving the k-Cut cut and minimizing the truth table. Boolean matching considers both positive and negative polarity to optimize logical sharing.

[0015] Calculate the NPN equivalence class function corresponding to each K-Cut cut, generate the minimum structure of each NPN class with no more than 5 inputs using the exact synthesis tool, and record the parameters of the structure;

[0016] For each NPN class, multiple alternative structures are stored to address different optimization objectives.

[0017] Furthermore, the input Boolean network cut enumeration is performed in topological order, preserving the k-Cut cut and minimizing the truth table. Boolean matching considers both positive and negative polarities to optimize logical sharing, including:

[0018] When preserving the k-Cut cut during cut enumeration, the topological order is ensured by traversing the network through a topological view.

[0019] The cut retention strategy retains at most cut_limit cuts for each node, sorts them by size first and delay second, minimizes the truth table of cuts, and removes variables that do not support functionality.

[0020] For each cut truth table f, the forward and reverse polarity matching synchronously calculates its inverse form ~f, and searches for matching structures in the library to achieve logical sharing.

[0021] Furthermore, the delay-guided mapping selects segments based on arrival time, choosing segments that satisfy the delay, including:

[0022] In delayed guided mapping, the arrival time of the primary input node is initialized to 0;

[0023] The arrival time of a composite node is the maximum of the sum of the arrival times of all its inputs and the delays of the corresponding input pins;

[0024] For the positive and negative phases of each node, calculate the arrival time of the optimal matching structure.

[0025] Furthermore, the global area topology optimization is a global area optimization based on area topology iteration to adjust the cut selection coverage, including:

[0026] In global area topology optimization, area topology is defined as the weighted sum of the area of ​​a node itself and the area topology of all its predecessor nodes in proportion to their fan-out ratio.

[0027] By iteratively updating the area topology in reverse topological order, the area topology of a node accurately reflects its contribution to the global area, thus tending to select cuts with smaller area topologies and reducing global area redundancy.

[0028] Furthermore, the local precise area optimization reduces the area through a precise area algorithm and selects the optimal cutting coverage, including:

[0029] Local area optimization involves traversing nodes in topological order.

[0030] Recursively calculate the precise area of ​​candidate cuts, including:

[0031] First, calculate the area of ​​the logic gate itself;

[0032] Then, based on the reference count of the leaf nodes, their area contribution is recursively accumulated to accurately evaluate the newly added area and select a better cut to reduce the area.

[0033] Furthermore, a new target network is generated based on the optimized coverage network, redundant nodes are removed, and the final network construction is completed, including:

[0034] Traverse the primary inputs of the input Boolean network and create the corresponding input nodes in the target network;

[0035] Based on the optimized coverage network, a matching target structure is created for each node in topological order, and the connection relationship between the nodes is established.

[0036] Perform redundant node removal operation to delete dangling nodes in the target network that are not referenced by the primary output, and complete the final network construction.

[0037] Furthermore, by traversing the primary input of the input Boolean network, corresponding input nodes are created in the target network, including:

[0038] For combinational circuits, directly create nodes with the same number of primary inputs as the input network, and initialize the fanout list to empty;

[0039] For sequential circuits, an additional D flip-flop node is created, with its data input connected to the combinational logic output, clock input connected to the global clock signal, and reset input connected to the global reset signal, so that the timing characteristics are consistent with the original network.

[0040] Furthermore, based on the optimized coverage network, a matching target structure is created for each node in topological order, and connections between nodes are established, including:

[0041] Create nodes strictly according to the topological order, ensuring that all predecessor nodes of the current node have been created;

[0042] For each node, the matching super gate is invoked based on the optimal leaf set {c1,c2,...,ck}, and the output of the leaf node is connected to the input of the super gate;

[0043] If the truth table of cutting requires that a certain leaf c2 be inverted, then an inverter is inserted between c2 and the supergate;

[0044] For the substructures of the supergate, subgates are recursively created and connected according to the topology defined in the library to make the internal structure complete.

[0045] Further, a redundant node removal operation is performed to delete dangling nodes in the target network that are not referenced by the primary output, completing the final network construction, including:

[0046] Starting from the primary output node, traverse all nodes that are directly or indirectly referenced by the node using a depth-first search and mark them as "valid".

[0047] Traverse the target network and delete all nodes marked as "invalid" and all their input and output edges;

[0048] Check if the source and target nodes of all edges exist, remove any dangling edges whose source or target nodes have been deleted, so that there are no invalid connections in the network topology, and complete the final network construction.

[0049] The beneficial effects of this application are as follows:

[0050] This application addresses the heterogeneous characteristics of multi-graph representations in digital logic circuits by performing k-cut enumeration and truth table optimization on nodes based on the topology and functional requirements of the input Boolean network. Combined with NPN equivalence class matching, it obtains a suitable target structure. Furthermore, in multiple rounds of optimization, it coordinates global area flow and local precise area adjustment to dynamically discover logic-shared nodes, rather than relying solely on logic graphs or local cut selections. Compared to traditional technology mapping methods, this approach enables a more comprehensive exploration of the optimization space, achieving coordinated optimization of area and delay for a given circuit. Simultaneously, the fully automated mapping and redundancy removal mechanism requires no manual intervention, significantly reducing the manual cost of technology mapping in chip design, making it particularly suitable for the efficient design of complex circuits and emerging logic-based technologies. Attached Figure Description

[0051] Figure 1This is an overall flowchart of a method for efficiently simplifying digital logic circuits based on deep learning, according to an embodiment of this application.

[0052] Figure 2 This is a schematic diagram illustrating the mapping optimization of circuit segmentation and precise area coverage in a method for efficiently simplifying digital logic circuits based on deep learning, according to an embodiment of this application.

[0053] Figure 3 This is a schematic diagram of a supergate overlay for generating a new network based on a method for efficiently simplifying digital logic circuits using deep learning, according to an embodiment of this application. Detailed Implementation

[0054] The graph mapping method based on precise synthesis presented in this application, on the one hand, builds a unified NPN equivalence class structure library, integrates the adaptability of multiple graph representations (NAND graphs, majority voting graphs, XOR-AND-inverter graphs, etc.), and utilizes precise synthesis to pre-compute the minimum structure combined with forward and reverse polarity matching, breaking through the limitations of logic sharing in traditional logic graphs and effectively tapping the sharing potential between different logic structures. On the other hand, it achieves coordinated optimization of area and delay by leveraging multi-round global-local optimization (delay-guided mapping, area topology optimization, and precise area optimization) and structure hashing techniques, avoiding the performance bottleneck of local greedy strategies. This method reduces manual intervention by automating the cutting enumeration and matching process, significantly improving mapping efficiency (17% higher than traditional methods); it supports flexible conversion between multiple graph representations, can directly adapt to most emerging logic base technologies (such as AQFP superconducting circuits), and is easier to achieve global optimization than fixed-process methods, providing a high-performance mapping solution with advantages in both area and delay for complex circuit designs.

[0055] like Figures 1-3 As shown, this application provides a graph mapping method based on exact synthesis, which specifically includes the following steps:

[0056] S100: Construct a precise synthesis structure library based on NPN equivalence classes and input a Boolean network.

[0057] S200: Perform k-Cut cut enumeration on the input Boolean network and calculate the truth table. Match the cuts with the structures in the precise synthesis structure library through Boolean matching, and achieve fast search by combining NPN classification.

[0058] Specifically, S100 and S200 include:

[0059] Cut enumeration is performed in topological order, preserving the k-Cut cut and minimizing the truth table. Boolean matching considers both positive and negative polarities to optimize logical sharing.

[0060] When retaining k-Cut cuts during cut enumeration, the network topology is traversed using a topology view to ensure topology order, guaranteeing that cut enumeration for parent nodes is completed after that for child nodes, thus avoiding dependency conflicts. The cut retention strategy retains a maximum of `cut_limit` cuts per node (default 49), sorted by size priority, followed by latency priority, prioritizing small-sized, low-latency cuts. Simultaneously, the truth table for each cut is minimized, removing variables without functional support to compress the scale and improve matching efficiency. For forward and reverse polarity matching, for each cut's truth table `f`, its inverse form `~f` is calculated synchronously. Matching structures in the library are searched. If `f` matches a 2-input AND gate (AND2) and `~f` matches a 2-input NAND gate (NAND2), the optimal option is selected based on area and latency. For example, when multiple fan-out nodes require inverted output, a 2-input NAND gate is preferred to reduce the number of inverters and achieve logic sharing.

[0061] Calculate the NPN equivalence class function corresponding to each k-cut cut, and generate the minimum structure (e.g., NAND gate structure for AIG, majority gate structure for MIG, XOR-AND structure for XAG) for each NPN class with up to 5 inputs using an accurate synthesis tool (such as a SAT-based synthesis tool). Record the number of nodes, depth, and other parameters of the structure. For each NPN class, store multiple candidate networks for the same NPN function structure to address different optimization objectives (area-first or delay-first).

[0062] S300: Generates an overlay network through multi-round mapping optimization, and shares nodes by combining structural hash mining logic. The multi-round mapping optimization includes delay-guided mapping, global area topology optimization, and local precise area optimization.

[0063] Specifically, S300 includes:

[0064] Delay-oriented mapping selects cuts based on arrival time, choosing cuts that satisfy the delay:

[0065] The arrival time calculation rule is as follows: the arrival time of the primary input (PI) node is initialized to 0; the arrival time of the combined node is the maximum value of the sum of the arrival times of all its inputs and the corresponding input pin delays, i.e., the arrival time of node n = max(the arrival time of the input leaf + the pin delay from the leaf to n). For the positive and negative phases of each node, the arrival time of the optimal matching structure is calculated separately.

[0066] Global area optimization is based on iterative adjustment of the area topology to select the cover:

[0067] In global area topology optimization, the area topology is defined as the weighted sum of the area of ​​a node itself and the area topologies of all its predecessor nodes according to their fan-out ratio. That is, the area topology of node n = area of ​​node n + Σ(area topology of input leaves × number of fan-outs from leaves to n / total number of fan-outs of leaves), where the weights reflect the proportion of the current node's share of the total fan-outs of leaves. By iteratively updating the area topology in reverse topological order, from primary output to primary input, the area topology of a node more accurately reflects its contribution to the global area, thus favoring cuts with smaller area topologies (such as cuts with high sharing), reducing global area redundancy.

[0068] Local area optimization reduces the area using a precise area algorithm and selects the optimal cut to cover the area.

[0069] Local precise area optimization is performed by traversing nodes in topological order across the entire network: for each node's candidate cuts, the precise area is calculated recursively. During the calculation, the reference count of leaf nodes is incorporated. When a leaf node is shared by multiple cuts, its area contribution to the current cut is recursively accumulated based on the number of times it is referenced by the current cut. Specifically, the area of ​​the logic gate corresponding to the cut is first calculated, and then the area contributed by the leaf nodes is recursively accumulated based on the reference status of the leaf nodes in the current cut. This accurately assesses the actual increase in area of ​​the cut and reduces the area by selecting a better cut.

[0070] To address the issues of insufficient logical sharing capabilities and excessive redundant nodes in traditional mapping methods, structural hashing technology is introduced simultaneously during the overlay network generation process to mine logically shared nodes.

[0071] Specifically, the implementation involves hash encoding the logical structures (such as combinations of supergates and subgates) corresponding to candidate cuts selected after multiple rounds of optimization. A global structural hash table is constructed using the structure's truth table features, input / output polarity, and internal topological connections as hash keys. When the structural hash value of a new candidate cut already exists in the table, it indicates that the logical structure has been reused by other nodes in the network, eliminating the need to rebuild new nodes; existing shared nodes are directly referenced. If the hash value does not exist, the hash key and node reference information of the structure are stored in the table, completing the registration of the new structure. The core purpose of this operation is to proactively reduce redundancy during the coverage network generation phase: by reusing shared nodes to avoid building duplicate logical structures, the global area is directly reduced, and the calculation of node contribution to the global area is made more accurate in subsequent global area topology optimization (reducing interference from duplicate structures on area weights). Simultaneously, the shared nodes mined by structural hashing must meet the latency constraints of the current node to ensure that area optimization does not sacrifice temporal performance.

[0072] S400: Generates a new target network based on the optimized overlay network, removes redundant nodes, and completes the final network construction.

[0073] Specifically, the S400 mentioned above includes:

[0074] Iterate through the primary inputs of the input Boolean network and create the corresponding input nodes in the target network:

[0075] For combinational circuits, directly create nodes with the same number of primary inputs as the input network, label the node type as "input", and initialize the fan-out list to empty; for sequential circuits, additionally create D flip-flop nodes (type "ff"), connect their data inputs to the combinational logic outputs, connect their clock inputs to the global clock signal (defined as rising / falling edge according to the original network), and connect their reset inputs to the global reset signal (active high / active low), ensuring that the timing characteristics are consistent with the original network.

[0076] Based on the optimized coverage network, create matching target structures (such as standard cells, majority gates, etc.) for each node in topological order, and establish connections between nodes:

[0077] Nodes are created strictly in topological order (from input to output), ensuring that all predecessor nodes of the current node have been created. For each node, a matching supergate (e.g., a 3-input majority gate MAJ3) is called based on the optimal leaf set {c1,c2,...,ck}, connecting the output of the leaf node to the input of the supergate; if the Cut truth table requires a certain leaf (e.g., c2) to be inverted, an inverter is inserted between c2 and the supergate. For substructures of the supergate (e.g., MAJ3 consists of 2 AND gates and 1 OR gate), subgates are recursively created and connected according to the topology defined in the library, ensuring the integrity of the internal structure.

[0078] Perform redundant node removal operations to delete dangling nodes in the target network that are not referenced by the primary output, ensuring network integrity:

[0079] Mark all reachable nodes: Starting from the primary output node, traverse all nodes that are directly or indirectly referenced by depth-first search (DFS) and mark them as "valid"; traverse the target network, delete all nodes marked as "invalid" and all their input / output edges to avoid redundant logic; check if the source and target nodes of all edges exist, remove dangling edges whose source or target nodes have been deleted, ensure invalid connections in the network topology, and complete the final network construction.

[0080] Structural hashing actively reuses logical structures during the overlay network generation phase, reducing duplicate nodes from the source; while redundant node removal is done after the target network is built by traversing the reachable nodes of the initial output through a depth-first search, cleaning up unreferenced dangling nodes (including isolated nodes that are not shared and reused and have no actual function).

[0081] As shown in the table below, in the MIG test case of EPFL combinational logic circuits, this embodiment uses a graph mapping algorithm based on precise synthesis to map MIG and AIG circuits. Due to the inherent differences between the two types of circuit structures, performance loss can easily occur during the mapping process. In the experiment, the number of nodes was used as a measure of the AIG circuit area. The results show that when mapping MIG circuits to AIG circuits, compared with the latest Versatile Mapping algorithm, the proposed algorithm reduces the average number of nodes in the AIG circuit by 17.7%, effectively demonstrating the improvement in circuit quality after mapping.

[0082]

[0083] In summary, through the graph mapping method based on precise synthesis described above, this application can address the heterogeneous characteristics of multi-graph representations in digital logic circuits. Based on the topology and functional requirements of the input Boolean network, it performs k-cut enumeration and truth table optimization on nodes, combining NPN equivalence class matching to obtain a suitable target structure. Furthermore, in multiple rounds of optimization, it coordinates global area flow and local precise area adjustment to dynamically discover logic-shared nodes, rather than relying solely on the logic graph or local cut selection. Compared to traditional technical mapping methods, this approach enables a more comprehensive exploration of the optimization space, achieving coordinated optimization of area and delay for a given circuit. Simultaneously, the fully automated mapping and redundancy removal mechanism requires no manual intervention, significantly reducing the manual cost of technical mapping in chip design, making it particularly suitable for the efficient design of complex circuits and emerging logic-based technologies.

[0084] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A graph mapping method based on exact synthesis, characterized in that, include: Construct a precise synthesis structure library based on NPN equivalence classes and input a Boolean network; The input Boolean network is k-cut enumerated and the truth table is calculated. The cuts are matched with the structures in the accurate synthesis structure library through Boolean matching. Combined with NPN classification, fast search is achieved. The overlay network is generated through multi-round mapping optimization, and shared nodes are obtained by combining structural hash mining logic. The multi-round mapping optimization includes delay-guided mapping, global area topology optimization, and local precise area optimization. A new target network is generated based on the optimized overlay network, redundant nodes are removed, and the final network construction is completed. The delay-guided mapping selects segments based on arrival time, choosing segments that meet the delay requirements, including: In delayed guided mapping, the arrival time of the primary input node is initialized to 0; The arrival time of a composite node is the maximum of the sum of the arrival times of all its inputs and the delays of the corresponding input pins; For the positive and negative phases of each node, calculate the arrival time of the optimal matching structure. The global area topology optimization is a global area optimization based on area topology iteration to adjust the cut selection coverage, including: In global area topology optimization, area topology is defined as the weighted sum of the area of ​​a node itself and the area topology of all its predecessor nodes in proportion to their fan-out ratio. By iteratively updating the area topology in reverse topological order, the area topology of a node accurately reflects its contribution to the global area, thus tending to select cuts with smaller area topologies and reducing global area redundancy. The local precise area optimization reduces the area through a precise area algorithm and selects the optimal cut coverage, including: Local area optimization involves traversing nodes in topological order. Recursively calculate the precise area of ​​candidate cuts, including: First, calculate the area of ​​the logic gate itself; Then, based on the reference count of the leaf nodes, their area contribution is recursively accumulated to accurately evaluate the newly added area and select a better cut to reduce the area.

2. The graph mapping method based on exact synthesis according to claim 1, characterized in that, The input Boolean network is k-cut and the truth table is computed. Boolean matching is used to match the cuts with structures in a precise synthetic structure library. Combined with NPN classification, fast lookup is achieved, including: The input Boolean network cut enumeration is performed in topological order, preserving the k-Cut cut and minimizing the truth table. Boolean matching considers both positive and negative polarity to optimize logical sharing. Calculate the NPN equivalence class function corresponding to each K-Cut cut, generate the minimum structure of each NPN class with no more than 5 inputs using the exact synthesis tool, and record the parameters of the structure; For each NPN class, multiple alternative structures are stored to address different optimization objectives.

3. The graph mapping method based on exact synthesis according to claim 2, characterized in that, The input Boolean network cut enumeration is performed in topological order, preserving the k-Cut cut and minimizing the truth table. Boolean matching considers both positive and negative polarities to optimize logical sharing, including: When preserving the k-Cut cut during cut enumeration, the topological order is ensured by traversing the network through a topological view. The cut retention strategy retains at most cut_limit cuts for each node, sorted by "size first, delay second", minimizes the truth table of cuts, and removes variables that do not support functionality. For each cut truth table f, the forward and reverse polarity matching synchronously calculates its inverse form ~f, and searches for matching structures in the library to achieve logical sharing.

4. The graph mapping method based on exact synthesis according to claim 1, characterized in that, A new target network is generated based on the optimized overlay network, redundant nodes are removed, and the final network construction is completed, including: Traverse the primary inputs of the input Boolean network and create the corresponding input nodes in the target network; Based on the optimized coverage network, a matching target structure is created for each node in topological order, and the connection relationship between the nodes is established. Perform redundant node removal operation to delete dangling nodes in the target network that are not referenced by the primary output, and complete the final network construction.

5. A graph mapping method based on exact synthesis according to claim 4, characterized in that, Iterate through the primary inputs of the input Boolean network and create corresponding input nodes in the target network, including: For combinational circuits, directly create nodes with the same number of primary inputs as the input network, and initialize the fanout list to empty; For sequential circuits, an additional D flip-flop node is created, with its data input connected to the combinational logic output, clock input connected to the global clock signal, and reset input connected to the global reset signal, so that the timing characteristics are consistent with the original network.

6. A graph mapping method based on exact synthesis according to claim 4, characterized in that, Based on the optimized coverage network, a matching target structure is created for each node in topological order, and the connection relationships between nodes are established, including: Create nodes strictly according to the topological order, ensuring that all predecessor nodes of the current node have been created; For each node, the matching super gate is invoked based on the optimal leaf set {c1,c2,...,ck}, and the output of the leaf node is connected to the input of the super gate; If the truth table of cutting requires that a certain leaf c2 be inverted, then an inverter is inserted between c2 and the supergate; For the substructures of the supergate, subgates are recursively created and connected according to the topology defined in the library to make the internal structure complete.

7. A graph mapping method based on exact synthesis according to claim 4, characterized in that, Perform redundant node removal operations to delete dangling nodes in the target network that are not referenced by the primary output, completing the final network construction, including: Starting from the primary output node, traverse all nodes that are directly or indirectly referenced by the node using a depth-first search and mark them as "valid". Traverse the target network and delete all nodes marked as "invalid" and all their input and output edges; Check if the source and target nodes of all edges exist, remove any dangling edges whose source or target nodes have been deleted, so that there are no invalid connections in the network topology, and complete the final network construction.

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