SVA generation method and device for hardware comprehensive function verification
By using a large language model generation method, combined with finite state machine extraction and feature selective fusion, and correcting reset and counter overflow check assertions, the problem of high assertion generation error rate and low coverage in existing technologies is solved. This achieves assertion generation with high accuracy and high coverage, thus improving hardware verification efficiency.
Patent Information
- Application Number
- CN202511446437.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-11
- Publication Date
- 2026-02-10
AI Technical Summary
Existing technologies suffer from timing and logic errors when generating assertions, especially those generated for reset functions and counter overflow verification. Furthermore, these assertions have low coverage and make it difficult to achieve complete circuit code verification.
By employing a pre-trained large language model and using finite state machine extraction and feature selective fusion methods, we generate reset check and counter overflow check assertions. Combined with template correction of erroneous assertions, we achieve assertion generation with high accuracy and high coverage.
It effectively generates assertions with high accuracy and high code coverage, shortens hardware verification time, improves vulnerability detection efficiency, and solves the problem of high error rate and low coverage in existing assertion generation technologies.
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Figure CN121503416A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of integrated circuit design automation, in particular to an SVA generation method and device for comprehensive hardware function verification. BACKGROUND
[0002] In the overall process of integrated circuit design verification, verification needs to consume a large amount of manpower and occupy most of the time. The verification effect directly determines whether the chip can be correctly manufactured and the expected function is realized, so a fast and accurate integrated circuit verification process is crucial. Formal verification is a verification method, which uses mathematical methods to solve assertions to judge whether the circuit meets the content described by the assertion. Formal verification has the advantages of no test vectors and covering boundary conditions, and its importance in the verification process is gradually increasing. In practical engineering applications, engineers need to write assertions according to circuit code and design specifications, and then use formal verification tools such as JasperGold for verification. If the verification result is passed, it means that the assertion meets the circuit. Verification engineers adjust the circuit design or the assertion according to the verification result, and finally achieve a high coverage rate or complete the verification of all function points.
[0003] The existing assertion (system Verilog assertion, SVA) generation technology can be divided into two categories. The first category is to manually extract the function points to be verified from the design specification, and use traditional natural language processing algorithms or large language models to generate assertions. The second category does not require manual extraction of function points, and uses design specifications and circuit code as input to automatically output assertions by extracting key information from the design specification. The first category of technology requires too much manual intervention and cannot achieve complete verification assertion generation automation. The comprehensiveness of the verification depends on the professional knowledge of the verification personnel. The second category of method solves the problem of insufficient automation of the first category of method, but the generated assertions have timing errors and logical errors. The generated assertions for specific functions such as reset function and counter overflow are prone to errors, and the coverage rate of the assertions to the circuit code is low, making it difficult to achieve complete verification. SUMMARY
[0004] In order to solve the technical problems of the existing technology that the generated assertions have timing errors and logical errors, the generated assertions for specific functions such as reset function and counter overflow are prone to errors, and the coverage rate of the assertions to the circuit code is low, making it difficult to achieve complete verification, the embodiments of the present application provide an SVA generation method and device for comprehensive hardware function verification. The technical solution is as follows:
[0005] On the one hand, an SVA generation method for comprehensive hardware function verification is provided, which is realized by an SVA generation device for comprehensive hardware function verification. The method comprises:
[0006] S1. Obtain the integrated circuit design specification text and the circuit code to be verified; using a pre-trained large language model, extract the integrated circuit design specification text into a finite state machine by designing the first prompt word to obtain the first finite state machine; using the large language model, extract the circuit code to be verified into a finite state machine by designing the second prompt word to obtain the second finite state machine.
[0007] S2. Based on the pre-trained large language model, a feature selective fusion method is adopted. By designing a third prompt word, the first finite state machine and the second finite state machine are fused to obtain the third finite state machine.
[0008] S3. Input the circuit code to be verified and the third finite state machine into the pre-trained large language model, and generate multiple assertions for circuit function detection of the circuit code through the designed fourth prompt word.
[0009] S4. Design templates for reset check assertions and counter overflow check assertions; input the designed fifth prompt word and the multiple assertions used for circuit function testing into the pre-trained large language model, and correct the erroneous assertions through the designed templates for reset check assertions and counter overflow check assertions to obtain the final assertions used for circuit function testing.
[0010] Optionally, step S1 involves acquiring the integrated circuit design specification text and the code of the circuit to be verified; using a pre-trained large language model, extracting a first finite state machine from the integrated circuit design specification text by designing a first prompt word; and using a pre-trained large language model, extracting a second finite state machine from the code of the circuit to be verified by designing a second prompt word, including:
[0011] S11. Input the first prompt word of the design and the integrated circuit design specification text into the pre-trained large language model. By analyzing the design specification text, extract each state in the circuit and the transition conditions between states. Based on the transition conditions, extract the function corresponding to each state.
[0012] S12. Output each state, the transition conditions between states, and the function corresponding to each state in stateDiagram-v2 format, and save the output as the first finite state machine.
[0013] S13. Input the designed second prompt word and the circuit code to be verified into the pre-trained large language model. By analyzing the circuit code to be verified, extract each state and the transition conditions between states. Based on each state and the transition conditions between states, extract the function corresponding to each state.
[0014] S14, output each state in the to-be-verified circuit, the transition condition between states, and the function corresponding to each state through a stateDiagram-v2 format, and save the output result as a second finite state machine.
[0015] Optionally, the pre-trained large language model-based S2 adopts a feature selective fusion method to fuse the first finite state machine and the second finite state machine by designing a third prompt word to obtain a third finite state machine, comprising:
[0016] The designed third prompt word, the first finite state machine and the second finite state machine are input into the pre-trained large language model to analyze the differences between the first finite state machine and the second finite state machine; wherein, when there is a difference in the state of the first finite state machine and the second finite state machine, the state name of the second finite state machine is adopted; when there is a difference in the function corresponding to the state of the first finite state machine and the function corresponding to the state of the second finite state machine, the function corresponding to the state of the first finite state machine is adopted; the state name of the second finite state machine and the function corresponding to the state of the first finite state machine are selectively fused to obtain the third finite state machine.
[0017] Optionally, the S3 inputs the to-be-verified circuit code and the third finite state machine into the pre-trained large language model to generate a plurality of assertions for circuit function detection of the to-be-verified circuit code through a designed fourth prompt word, comprising:
[0018] The to-be-verified circuit code, the third finite state machine and the designed fourth prompt word are input into the pre-trained large language model to generate assertions of the functions of all states of the third finite state machine and assertions of the state transition conditions.
[0019] Optionally, the S4 inputs the designed fifth prompt word and the plurality of assertions for circuit function detection into the pre-trained large language model to correct error assertions through a designed reset check assertion template and a counter overflow check assertion template to obtain final assertions for circuit function detection, comprising:
[0020] The designed fifth prompt word, the plurality of assertions for circuit function detection, the designed reset check assertion template and the counter overflow check assertion template are input into the pre-trained large language model to evaluate whether there are reset check assertions and counter overflow detection assertions in the plurality of assertions for circuit function detection; if there are, it is judged whether there is a conflict with the designed reset check assertion template and the counter overflow check assertion template, if there is a conflict, a new assertion is generated using the designed reset check assertion template and the counter overflow check assertion template, and the newly generated assertion is taken as the final assertion for circuit function detection.
[0021] In another aspect, an SVA generation device for hardware full function verification is provided, which is applied to an SVA generation method for hardware full function verification, and the device comprises:
[0022] a first obtaining unit configured to obtain an integrated circuit design specification text and a to-be-verified circuit code; a pre-trained large language model is used to extract a first finite state machine from the integrated circuit design specification text by using a first prompt word; and the pre-trained large language model is used to extract a second finite state machine from the to-be-verified circuit code by using a second prompt word;
[0023] a second obtaining unit configured to use a feature selection fusion method to fuse the first finite state machine and the second finite state machine by using a third prompt word based on the pre-trained large language model, and obtain a third finite state machine;
[0024] a generating unit configured to input the to-be-verified circuit code and the third finite state machine into the pre-trained large language model, and generate a plurality of assertions for circuit function detection of the to-be-verified circuit code by using a fourth prompt word;
[0025] a third obtaining unit configured to design a template of a reset check assertion and a template of a counter overflow check assertion; and input the fifth prompt word and the plurality of assertions for circuit function detection into the pre-trained large language model, and correct error assertions by using the template of the reset check assertion and the template of the counter overflow check assertion, and obtain final assertions for circuit function detection.
[0026] Optionally, the first obtaining unit is configured to:
[0027] input the first prompt word and the integrated circuit design specification text into the pre-trained large language model, extract each state and a transition condition between states by analyzing the design specification, and extract a function corresponding to each state based on the transition condition; output each state, the transition condition between states, and the function corresponding to each state in a stateDiagram-v2 format, and save the output result as the first finite state machine; input the second prompt word and the to-be-verified circuit code into the pre-trained large language model, extract each state and a transition condition between states by analyzing the to-be-verified circuit code, and extract a function corresponding to each state based on each state and the transition condition between states; output each state, the transition condition between states, and the function corresponding to each state in a stateDiagram-v2 format, and save the output result as the second finite state machine.
[0028] Optionally, the second obtaining unit is configured to:
[0029] input the designed third prompt word, the first finite state machine and the second finite state machine into the pre-trained large language model to analyze the difference between the first finite state machine and the second finite state machine; when there is a difference between the states of the first finite state machine and the second finite state machine, the state name of the second finite state machine is adopted; when there is a difference between the function corresponding to the state of the first finite state machine and the function corresponding to the state of the second finite state machine, the function corresponding to the state of the first finite state machine is adopted; the state name of the second finite state machine and the function corresponding to the state of the first finite state machine are selectively fused to obtain a third finite state machine.
[0030] Optionally, the generation unit is configured to:
[0031] input the to-be-verified circuit code, the third finite state machine and a designed fourth prompt word into the pre-trained large language model to generate an assertion of the function of all states of the third finite state machine and an assertion of the state transition condition.
[0032] Optionally, the third obtaining unit is configured to:
[0033] input the designed fifth prompt word, the plurality of assertions for circuit function detection, a designed reset check assertion template and a counter overflow check assertion template into the pre-trained large language model to evaluate whether there is a reset check assertion and a counter overflow detection assertion in the plurality of assertions for circuit function detection; if there is, it is judged whether there is a conflict with the designed reset check assertion template and the counter overflow check assertion template, and if there is a conflict, a new assertion is generated by using the designed reset check assertion template and the counter overflow check assertion template, and the newly generated assertion is used as the final assertion for circuit function detection.
[0034] In another aspect, an SVA generation device for hardware full function verification is provided, which comprises a processor and a memory having computer readable instructions stored thereon, wherein the computer readable instructions are executed by the processor to implement any one of the above SVA generation methods for hardware full function verification.
[0035] In another aspect, a computer readable storage medium is provided, which stores at least one instruction, wherein the at least one instruction is loaded and executed by a processor to implement any one of the above SVA generation methods for hardware full function verification.
[0036] The technical scheme provided by the embodiments of the present application has at least the following beneficial effects:
[0037] The embodiment of the application first acquires integrated circuit design specification text and to-be-verified circuit code; adopts a pre-trained large language model to perform finite state machine extraction on the integrated circuit design specification text by designing a first prompt word, to obtain a first finite state machine; adopts the pre-trained large language model to perform finite state machine extraction on the to-be-verified circuit code by designing a second prompt word, to obtain a second finite state machine; secondly, based on the pre-trained large language model, a feature selection fusion method is adopted to fuse the first finite state machine and the second finite state machine by designing a third prompt word, to obtain a third finite state machine; the to-be-verified circuit code and the third finite state machine are input into the pre-trained large language model, and a plurality of assertions for circuit function detection of the to-be-verified circuit code are generated by designing a fourth prompt word; finally, templates of reset check assertions and templates of counter overflow check assertions are designed; the fifth prompt word and the plurality of assertions for circuit function detection are input into the pre-trained large language model, and error assertions are corrected by the templates of reset check assertions and the templates of counter overflow check assertions, to obtain final assertions for circuit function detection.
[0038] The embodiment of the application provides an assertion generation method for comprehensive hardware function verification, and the assertion generation task is divided by introducing a plurality of large language model agents; finite state machines are extracted from integrated circuit design specification text and to-be-verified circuit code; the final finite state machine is obtained by fusing the finite state machines from the two sources; the to-be-verified circuit code is generated under the guidance of the final finite state machine; and the assertions for reset check and counter overflow check are corrected. The embodiment of the application can generate assertions for any sequential logic circuit, solves the problem of high error rate and low coverage rate in the assertion generation task of the prior art, and can effectively generate assertions with high accuracy and high code coverage to shorten the hardware verification time and improve the vulnerability detection efficiency. BRIEF DESCRIPTION OF DRAWINGS
[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0040] Figure 1 is a SVA generation method flowchart provided by the embodiment of the present application for comprehensive hardware function verification;
[0041] Figure 2 is a SVA generation device block diagram provided by the embodiment of the present application for comprehensive hardware function verification;
[0042] Figure 3 is a structural schematic diagram of an SVA generation device for comprehensive hardware function verification provided by an embodiment of the present application. DETAILED DESCRIPTION
[0043] The technical solutions in the present application will be described below with reference to the drawings.
[0044] In the embodiments of the present application, the words such as "example", "for example" and the like are used to represent as an example, illustration or description. Any embodiment or design scheme described as "example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the word "example" is intended to present the concept in a specific manner. In addition, in the embodiments of the present application, the meaning expressed by "and / or" can be both, or can be one of the two.
[0045] In the embodiments of the present application, sometimes the subscript such as W1 may be written in the form of non-subscript such as W1, and when the difference is not emphasized, the meanings expressed are consistent.
[0046] To make the technical problems, technical solutions and advantages to be solved by the present application more clear, the following will be described in detail with reference to the drawings and specific embodiments.
[0047] The embodiments of the present application provide an SVA generation method for comprehensive hardware function verification, which can be implemented by an SVA generation device for comprehensive hardware function verification. The SVA generation device for comprehensive hardware function verification can be a terminal or a server. As shown in the flowchart of the SVA generation method for comprehensive hardware function verification, the processing flow of the method can include the following steps: Figure 1
[0048] S1, obtain an integrated circuit design specification text and a to-be-verified circuit code; adopt a pre-trained large language model to perform finite state machine extraction on the integrated circuit design specification text by designing a first prompt word, to obtain a first finite state machine; adopt the pre-trained large language model to perform finite state machine extraction on the to-be-verified circuit code by designing a second prompt word, to obtain a second finite state machine.
[0049] Optionally, the specific implementation process of S1 includes S11-S14.
[0050] S11, input the designed first prompt word and the integrated circuit design specification text into the pre-trained large language model, extract each state in the circuit and the transition condition between the states by analyzing the design specification, and extract the function corresponding to each state based on the transition condition; wherein each state in the circuit described in the design specification is a numerical value stored in a state register in the circuit.
[0051] In one possible implementation, the pre-trained large language model used by the embodiment of the present application is a GPT4o large language model; the content of the first prompt is "You are a circuit design specification analyzer. I will provide you with the design specification of the circuit. Your task is to extract the state machine of the circuit and include the functions that each state needs to implement in the 'note right of' block in the state machine. The output should be in the stateDiagram-v2 format. This is the design specification you need to analyze." The embodiment of the present application takes the first prompt and the GPT4o large language model as the first agent, inputs the integrated circuit design specification text and the first prompt into the GPT4o large language model, and extracts each state and the transition condition between states in the circuit described in the design specification, wherein the transition condition is, for example, when a certain input signal is high, the circuit state is converted from S1 to S2; and the function corresponding to each state is, for example, when the circuit is in state S1, a certain output signal is low.
[0052] S12, output each state, the transition condition between states, and the function corresponding to each state in the stateDiagram-v2 format, and save the output result as the first finite state machine;
[0053] S13, input the second prompt and the to-be-verified circuit code into the pre-trained large language model, analyze the to-be-verified circuit code, extract each state and the transition condition between states, and extract the function corresponding to each state based on each state and the transition condition between states;
[0054] In one possible implementation, the embodiment of the present application uses the understanding ability of the pre-trained large language model for the circuit code to analyze the to-be-verified circuit code and extract a plurality of states, a plurality of transition conditions between states, and a function that each state needs to implement. This process needs to retain as many signal names as possible.
[0055] S14, output each state, the transition condition between states, and the function corresponding to each state in the to-be-verified circuit in the stateDiagram-v2 format, and save the output result as the second finite state machine.
[0056] In one possible implementation, the second prompt "You are a circuit code analyzer. I will provide you with the code of the circuit. Your task is to extract the state machine from the circuit and include the function corresponding to each state in the 'note right of' block in the state machine. The output should be in the stateDiagram-v2 format and include a plurality of signal names. This is a task example and circuit code." and the GPT4o large language model are taken as the second agent. The to-be-verified circuit code, the task example, and the second prompt are input into the GPT4o large language model to obtain the second finite state machine.
[0057] S2, based on the pre-trained large language model, adopting a feature selective fusion method, fusing the first finite state machine and the second finite state machine by designing a third prompt word, obtaining a third finite state machine.
[0058] Optionally, the specific implementation process of S2 includes:
[0059] The designed third prompt word, the first finite state machine and the second finite state machine are input into the pre-trained large language model to analyze the differences between the first finite state machine and the second finite state machine; wherein, when there is a difference between the states of the first finite state machine and the second finite state machine, the state name of the second finite state machine is adopted; when there is a difference between the function corresponding to the state of the first finite state machine and the function corresponding to the state of the second finite state machine, the function corresponding to the state of the first finite state machine is adopted; the state name of the second finite state machine and the function corresponding to the state of the first finite state machine are selectively fused to obtain the third finite state machine.
[0060] In a feasible implementation, the third prompt word "You are a FSM synthesizer. I will provide you with two state machines for the same circuit. The first one is derived from the design specification and includes the functions that should be implemented. The second one is extracted from the circuit code and includes the definition of signals. Your task is to generate a final finite state machine that integrates all the functions in the specification and as many signal names as possible from the circuit code. The output should be in stateDiagram-v2 format. This is the state machine extracted from the design specification, the state machine extracted from the circuit, and the signal definition file." and the GPT4o large language model are used as the third intelligent agent. The first finite state machine, the second finite state machine, and the signal definition in the circuit code and the third prompt word are input into the GPT4o large language model to obtain the third finite state machine.
[0061] S3, inputting the to-be-verified circuit code and the third finite state machine into the pre-trained large language model, generating a plurality of assertions for circuit function detection of the to-be-verified circuit code through a designed fourth prompt word.
[0062] Optionally, the specific implementation process of S3 includes:
[0063] The to-be-verified circuit code, the third finite state machine, and the designed fourth prompt word are input into the pre-trained large language model to generate assertions of the functions of all states of the third finite state machine and assertions of the state transition conditions.
[0064] In one possible implementation, the fourth prompt "You are an assertion generator. I will give you the state machine of a circuit and its corresponding circuit code. Your task is to generate assertions to verify the functionality of this circuit. The assertions should include two types of verification: 1. State transition verification. 2. Functionality verification of each state. The input is as follows." and the GPT4o large language model are used as the fourth intelligent agent. The third finite state machine, the circuit code to be verified, and the fourth prompt are input into the GPT4o large language model, and a plurality of assertions for circuit functionality detection are output.
[0065] S4, design the template of reset check assertion and the template of counter overflow check assertion; input the fifth prompt designed and the plurality of assertions for circuit functionality detection into the pre-trained large language model, correct the error assertions by the template of reset check assertion and the template of counter overflow check assertion designed, and obtain the final assertions for circuit functionality detection.
[0066] Optionally, the implementation process of S4 includes:
[0067] Input the fifth prompt designed, the plurality of assertions for circuit functionality detection, the template of reset check assertion and the template of counter overflow check assertion designed into the pre-trained large language model, and evaluate whether there are reset check assertions and counter overflow detection assertions in the plurality of assertions for circuit functionality detection; if there are, determine whether there is a conflict with the template of reset check assertion and the template of counter overflow check assertion designed, and if there is a conflict, generate new assertions using the template of reset check assertion and the template of counter overflow check assertion designed, and use the newly generated assertions as the final assertions for circuit functionality detection.
[0068] In one possible implementation, the fifth prompt "You are an assertion optimizer. I will give you some assertions, and if there are the following typical errors, you need to correct them. In the reset check assertion, if the reset signal is high, you need to write '$fell (reset_signal) |-> reset function', and if the reset signal is low, you need to use '$rose (reset_signal)'. When checking the functionality of the counter, you need to consider the overflow and underflow conditions. The template is 'counter == ($past (counter) + 1) % (2 ^ counter_width)'." and the GPT4o large language model are used as the fifth intelligent agent. The assertions for circuit functionality detection and the fifth prompt are input into the GPT4o large language model to correct the errors of the assertions, and the final assertions for circuit functionality detection are obtained.
[0069] The embodiment of the application first acquires integrated circuit design specification text and to-be-verified circuit code; adopts a pre-trained large language model, extracts a first finite state machine from the integrated circuit design specification text by designing a first prompt word, acquires a second finite state machine by extracting a finite state machine from the to-be-verified circuit code by designing a second prompt word, and then adopts a feature selection fusion method, fuses the first finite state machine and the second finite state machine by designing a third prompt word based on the pre-trained large language model, and acquires a third finite state machine; inputs the to-be-verified circuit code and the third finite state machine into the pre-trained large language model, generates a plurality of assertions for circuit function detection of the to-be-verified circuit code by designing a fourth prompt word; finally, designs a template of reset check assertion and a template of counter overflow check assertion; inputs the designed fifth prompt word and the plurality of assertions for circuit function detection into the pre-trained large language model, and corrects the error assertions by the designed template of reset check assertion and the template of counter overflow check assertion, and acquires the final assertion for circuit function detection.
[0070] The embodiment of the application provides an assertion generation method for hardware full function verification, which introduces a plurality of large language model agents to perform assertion generation task division; performs finite state machine extraction on integrated circuit design specification text and to-be-verified circuit code; performs information fusion on the two kinds of finite state machines to obtain a final finite state machine; generates assertions for the to-be-verified circuit code under the guidance of the final finite state machine; and corrects the assertions for reset check and counter overflow check. The embodiment of the application can generate assertions for any sequential logic circuit, solves the problem of high error rate and low coverage rate of existing methods in the assertion generation task, and can effectively generate assertions with high accuracy and high code coverage to shorten the hardware verification time and improve the vulnerability detection efficiency.
[0071] Figure 2 is a SVA generation device block diagram for hardware full function verification according to an exemplary embodiment, which is used for the SVA generation method for hardware full function verification. Referring to Figure 2 , the device comprises a first acquisition unit 210, a second acquisition unit 220, a generation unit 230 and a third acquisition unit 240. Wherein:
[0072] The first acquisition unit 210 is used for acquiring integrated circuit design specification text and to-be-verified circuit code; adopting a pre-trained large language model, extracting a first finite state machine from the integrated circuit design specification text by designing a first prompt word, acquiring a second finite state machine by extracting a finite state machine from the to-be-verified circuit code by designing a second prompt word;
[0073] The second acquisition unit 220 is configured to fuse the first finite state machine and the second finite state machine by designing a third prompt word based on the pre-trained large language model by using a feature selection fusion method, and obtain a third finite state machine;
[0074] The generation unit 230 is configured to input the to-be-verified circuit code and the third finite state machine into the pre-trained large language model, and generate a plurality of assertions for circuit function detection of the to-be-verified circuit code by using a fourth prompt word;
[0075] The third acquisition unit 240 is configured to design a template of a reset check assertion and a template of a counter overflow check assertion, input a fifth prompt word and the plurality of assertions for circuit function detection into the pre-trained large language model, and correct error assertions by using the template of the reset check assertion and the template of the counter overflow check assertion to obtain final assertions for circuit function detection.
[0076] Optionally, the first acquisition unit 210 is configured to:
[0077] input the designed first prompt word and the integrated circuit design specification text into the pre-trained large language model, analyze the design specification text, extract each state and a transition condition between states in the circuit, and extract a function corresponding to each state based on the transition condition;
[0078] output each state, the transition condition between states, and the function corresponding to each state in a stateDiagram-v2 format, and save the output result as the first finite state machine;
[0079] input the designed second prompt word and the to-be-verified circuit code into the pre-trained large language model, analyze the to-be-verified circuit code, extract each state and a transition condition between states, and extract a function corresponding to each state based on each state and the transition condition between states;
[0080] output each state, the transition condition between states, and the function corresponding to each state in the to-be-verified circuit in the stateDiagram-v2 format, and save the output result as the second finite state machine.
[0081] Optionally, the second acquisition unit 220 is configured to:
[0082] The third prompt word, the first finite state machine and the second finite state machine are input into a pre-trained large language model to analyze the difference between the first finite state machine and the second finite state machine; wherein, when there is a difference between the states of the first finite state machine and the second finite state machine, the state name of the second finite state machine is adopted; when there is a difference between the function corresponding to the state of the first finite state machine and the function corresponding to the state of the second finite state machine, the function corresponding to the state of the first finite state machine is adopted; the state name of the second finite state machine and the function corresponding to the state of the first finite state machine are selectively fused to obtain a third finite state machine.
[0083] Optionally, the generation unit 230 is configured to:
[0084] The circuit code to be verified, the third finite state machine and a fourth prompt word designed by the design unit 230 are input into the pre-trained large language model to generate the assertion of the function of all states of the third finite state machine and the assertion of the state transition condition.
[0085] Optionally, the third acquisition unit 240 is configured to:
[0086] The fifth prompt word designed by the design unit 230, the plurality of assertions for circuit function detection, the template of the reset check assertion and the template of the counter overflow check assertion are input into the pre-trained large language model to evaluate whether there is a reset check assertion and a counter overflow detection assertion in the plurality of assertions for circuit function detection; if there is, it is judged whether there is a conflict with the template of the reset check assertion and the template of the counter overflow check assertion designed by the design unit 230, if there is a conflict, a new assertion is generated by using the template of the reset check assertion and the template of the counter overflow check assertion designed by the design unit 230, and the newly generated assertion is used as the final assertion for circuit function detection.
[0087] The embodiment of the application first acquires integrated circuit design specification text and to-be-verified circuit code; adopts a pre-trained large language model, extracts a first finite state machine from the integrated circuit design specification text by designing a first prompt word, acquires a second finite state machine by extracting a finite state machine from the to-be-verified circuit code by designing a second prompt word; secondly, based on the pre-trained large language model, a feature selection fusion method is adopted, the first finite state machine and the second finite state machine are fused by designing a third prompt word, and a third finite state machine is acquired; the to-be-verified circuit code and the third finite state machine are input into the pre-trained large language model, a plurality of assertions for circuit function detection of the to-be-verified circuit code are generated by designing a fourth prompt word; finally, templates of reset check assertions and templates of counter overflow check assertions are designed; the fifth prompt word and the plurality of assertions for circuit function detection are input into the pre-trained large language model, error assertion correction is performed by the designed templates of reset check assertions and the templates of counter overflow check assertions, and finally the assertions for circuit function detection are acquired.
[0088] The embodiment of the application provides an assertion generation method for comprehensive hardware function verification, which introduces a plurality of large language model agents to perform assertion generation task division; performs finite state machine extraction on integrated circuit design specification text and to-be-verified circuit code; performs information fusion on the two sources of finite state machines to obtain a final finite state machine; generates assertions for the to-be-verified circuit code under the guidance of the final finite state machine; and corrects the assertions for reset check and counter overflow check. The embodiment of the application can generate assertions for any sequential logic circuit, solves the problem of high error rate and low coverage rate of existing methods in the assertion generation task, and can effectively generate assertions with high accuracy and high code coverage to shorten hardware verification time and improve vulnerability detection efficiency.
[0089] Figure 3 is a structural schematic diagram of an SVA generation device for comprehensive hardware function verification provided by the embodiment of the application, as Figure 3 indicated, the SVA generation device for comprehensive hardware function verification can include the SVA generation apparatus for comprehensive hardware function verification shown in the above Figure 2 indicated. Alternatively, the SVA generation device for comprehensive hardware function verification 310 can include the first processor 2001.
[0090] Alternatively, the SVA generation device for comprehensive hardware function verification 310 can further include the memory 2002 and the transceiver 2003.
[0091] The first processor 2001, the memory 2002 and the transceiver 2003 can be connected through a communication bus.
[0092] The following is combined with Figure 3 A detailed description of each component of the SVA generation device 310 for comprehensive hardware functional verification is provided below:
[0093] The first processor 2001 is the control center of the SVA generation device 310 for comprehensive hardware functional verification. It can be a single processor or a collective term for multiple processing elements. For example, the first processor 2001 can be one or more central processing units (CPUs), application-specific integrated circuits (ASICs), or one or more integrated circuits configured to implement embodiments of the present invention, such as one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs).
[0094] Optionally, the first processor 2001 can perform various functions of the SVA generation device 310 for hardware full-function verification by running or executing software programs stored in the memory 2002 and calling data stored in the memory 2002.
[0095] In a specific implementation, as one example, the first processor 2001 may include one or more CPUs, for example... Figure 3 CPU0 and CPU1 are shown in the diagram.
[0096] In a specific implementation, as one example, the SVA generation device 310 for hardware full functionality verification may also include multiple processors, for example... Figure 3 The first processor 2001 and the second processor 2004 are shown in the diagram. Each of these processors can be a single-core processor or a multi-core processor. Here, a processor can refer to one or more devices, circuits, and / or processing cores used to process data (such as computer program instructions).
[0097] The memory 2002 is used to store the software program that executes the present invention, and is controlled by the first processor 2001 to execute it. The specific implementation method can be referred to the above method embodiment, and will not be repeated here.
[0098] Optionally, the memory 2002 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. The memory 2002 may be integrated with the first processor 2001 or may exist independently, and may be accessed through the interface circuit of the SVA generation device 310 for full hardware functionality verification. Figure 3 (Not shown in the image) is coupled to the first processor 2001, and this embodiment of the invention does not specifically limit this.
[0099] The transceiver 2003 is used to communicate with network devices or with terminal devices.
[0100] Alternatively, transceiver 2003 may include a receiver and a transmitter. Figure 3 (Not shown separately). The receiver is used to implement the receiving function, and the transmitter is used to implement the transmitting function.
[0101] Alternatively, the transceiver 2003 can be integrated with the first processor 2001 or exist independently, and can be interfaced with the SVA generation device 310, which is designed for full hardware functionality verification. Figure 3 (Not shown in the image) is coupled to the first processor 2001, and this embodiment of the invention does not specifically limit this.
[0102] It should be noted that, Figure 3 The structure of the SVA generation device 310 for full hardware functionality verification shown in the diagram does not constitute a limitation on the router. Actual knowledge structure identification devices may include more or fewer components than shown, or combine certain components, or have different component arrangements.
[0103] Furthermore, the technical effects of the SVA generation device 310 for hardware full functionality verification can be referred to the technical effects of the SVA generation method for hardware full functionality verification described in the above method embodiments, and will not be repeated here.
[0104] It should be understood that the first processor 2001 in the embodiments of the present invention may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.
[0105] It should also be understood that the memory in the embodiments of the present invention can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM).
[0106] The above embodiments can be implemented, in whole or in part, by software, hardware (such as circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive.
[0107] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. A and B can be singular or plural. Additionally, the character " / " in this article generally indicates an "or" relationship between the preceding and following related objects, but it can also represent an "and / or" relationship. Please refer to the context for a more accurate understanding.
[0108] In this invention, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be a single item or multiple items.
[0109] It should be understood that, in various embodiments of the present invention, the order of the above-mentioned process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.
[0110] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.
[0111] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the devices, apparatuses, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0112] In the several embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.
[0113] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0114] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0115] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0116] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A method for generating SVA for comprehensive hardware functional verification, characterized in that, The method includes: S1. Obtain the integrated circuit design specification text and the circuit code to be verified; use a pre-trained large language model to extract the integrated circuit design specification text into a finite state machine by designing the first prompt word, and obtain the first finite state machine; use a pre-trained large language model to extract the circuit code to be verified into a finite state machine by designing the second prompt word, and obtain the second finite state machine. S2. Based on the large language model, a feature-selective fusion method is adopted. By designing a third prompt word, the first finite state machine and the second finite state machine are fused to obtain the third finite state machine. S3. Input the circuit code to be verified and the third finite state machine into the large language model, and generate multiple assertions for circuit function testing of the circuit code through the designed fourth prompt word. S4. Design templates for reset check assertions and counter overflow check assertions; input the designed fifth prompt word and the multiple assertions used for circuit function testing into the large language model, and correct the erroneous assertions through the designed templates for reset check assertions and counter overflow check assertions to obtain the final assertions used for circuit function testing.
2. The SVA generation method for comprehensive hardware functional verification according to claim 1, characterized in that, S1 involves acquiring the integrated circuit design specification text and the code of the circuit to be verified; using a pre-trained large language model, extracting a first finite state machine from the integrated circuit design specification text by designing a first prompt word; and using a pre-trained large language model, extracting a second finite state machine from the code of the circuit to be verified by designing a second prompt word, including: S11. Input the first prompt word of the design and the integrated circuit design specification text into the pre-trained large language model. By analyzing the design specification text, extract each state in the circuit and the transition conditions between states. Based on the transition conditions, extract the function corresponding to each state. S12. Output each state, the transition conditions between states, and the function corresponding to each state in stateDiagram-v2 format, and save the output as the first finite state machine. S13. Input the designed second prompt word and the circuit code to be verified into the pre-trained large language model. By analyzing the circuit code to be verified, extract each state and the transition conditions between states. Based on each state and the transition conditions between states, extract the function corresponding to each state. S14. Output each state, the transition conditions between states, and the function corresponding to each state in the circuit to be verified in the stateDiagram-v2 format, and save the output results as a second finite state machine.
3. The SVA generation method for comprehensive hardware functional verification according to claim 1, characterized in that, The S2, based on a pre-trained large language model, employs a feature-selective fusion method. It fuses the first and second finite-state machines by designing a third cue word to obtain a third finite-state machine, including: The designed third prompt word, the first finite state machine, and the second finite state machine are input into a pre-trained large language model to analyze the differences between the first and second finite state machines. Specifically, when there is a difference between the states of the first and second finite state machines, the state name of the second finite state machine is adopted; when there is a difference between the functions corresponding to the states of the first and second finite state machines, the function corresponding to the states of the first finite state machine is adopted; the state names of the second finite state machine and the functions corresponding to the states of the first finite state machine are selectively fused to obtain the third finite state machine.
4. The SVA generation method for comprehensive hardware functional verification according to claim 1, characterized in that, S3 inputs the circuit code to be verified and the third finite state machine into a pre-trained large language model, and generates multiple assertions for circuit function detection of the circuit code to be verified through a designed fourth prompt word, including: Input the circuit code to be verified, the third finite state machine, and the designed fourth prompt word into the pre-trained large language model to generate assertions of the functionality of all states of the third finite state machine and assertions of the state transition conditions.
5. The SVA generation method for comprehensive hardware functional verification according to claim 1, characterized in that, In step S4, the designed fifth prompt word and the multiple assertions used for circuit function detection are input into the pre-trained large language model. Error assertion correction is performed using the designed templates for reset check assertions and counter overflow check assertions to obtain the final assertions used for circuit function detection, including: The designed fifth prompt word, the multiple assertions for circuit function testing, the templates for the designed reset check assertions and counter overflow check assertions are input into the pre-trained large language model. The model evaluates whether there are reset check assertions and counter overflow check assertions among the multiple assertions for circuit function testing. If they exist, it is determined whether there is a conflict with the templates for the designed reset check assertions and counter overflow check assertions. If there is a conflict, a new assertion is generated using the templates for the designed reset check assertions and counter overflow check assertions, and the newly generated assertion is used as the final assertion for circuit function testing.
6. An SVA generation apparatus for comprehensive hardware functionality verification, wherein the SVA generation apparatus for comprehensive hardware functionality verification is used to implement the SVA generation method for comprehensive hardware functionality verification as described in any one of claims 1-5, characterized in that, The device includes: The system comprises a first acquisition unit, a second acquisition unit, a generation unit, and a third acquisition unit.
7. The SVA generation apparatus for comprehensive hardware functional verification according to claim 6, characterized in that, The first acquisition unit is used for: The first prompt word of the design and the integrated circuit design specification text are input into the pre-trained large language model. By analyzing the design specification text, each state in the circuit and the transition conditions between states are extracted. Based on the transition conditions, the function corresponding to each state is extracted. Each state, the transition conditions between states, and the function corresponding to each state are output in stateDiagram-v2 format, and the output results are saved as the first finite state machine. The designed second prompt word and the circuit code to be verified are input into the pre-trained large language model. By analyzing the circuit code to be verified, each state and the transition conditions between states are extracted. Based on each state and the transition conditions between states, the function corresponding to each state is extracted. Each state in the circuit to be verified, the transition conditions between states, and the function corresponding to each state are output in stateDiagram-v2 format, and the output results are saved as a second finite state machine.
8. The SVA generation apparatus for comprehensive hardware functional verification according to claim 6, characterized in that, The second acquisition unit is used for: The designed third prompt word, the first finite state machine, and the second finite state machine are input into a pre-trained large language model to analyze the differences between the first and second finite state machines. Specifically, when there is a difference between the states of the first and second finite state machines, the state name of the second finite state machine is adopted; when there is a difference between the functions corresponding to the states of the first and second finite state machines, the function corresponding to the states of the first finite state machine is adopted; the state names of the second finite state machine and the functions corresponding to the states of the first finite state machine are selectively fused to obtain the third finite state machine.
9. An SVA generation device for comprehensive hardware functional verification, characterized in that, The SVA generation equipment for comprehensive hardware functional verification includes: processor; A memory storing computer-readable instructions that, when executed by the processor, implement the method as described in any one of claims 1 to 5.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium contains program code that can be invoked by a processor to execute the method as described in any one of claims 1 to 5.