Display device

Abstract

The display device includes: a plurality of sub-pixels connected to a plurality of scan lines and a plurality of data lines; a plurality of light sensing pixels connected to the plurality of sensing scan lines, the plurality of read lines, and the reset control line; a scan driver supplying a plurality of scan signals to the plurality of scan lines; and a controller supplying a start signal to the scan driver. The controller may supply the start signal at a first point in time after a start of a frame during some frame periods among a plurality of frame periods in which a sensing signal is detected from the plurality of light sensing pixels, and supplying the start signal during a remaining frame period at a second point in time after the start of the frame, different from the first point in time.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0105418, filed on August 7, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device and a method for driving the display device, as well as an electronic device including the display device. Background Technology

[0004] With the development of the information society, the demand for display devices for displaying images has increased in various forms. For example, display devices are now used in various electronic devices, such as smartphones, digital cameras, laptops, navigation systems, and smart TVs.

[0005] Display devices may include light-sensing pixels in the display panel to detect fingerprints or illuminance. When the display panel includes light-sensing pixels, methods to improve the accuracy of image sensing are needed. Summary of the Invention

[0006] According to embodiments of the present disclosure, a display device and a method for driving the display device are provided that can improve the accuracy of image sensing.

[0007] According to an embodiment, the display device includes: a plurality of sub-pixels connected to a plurality of scan lines and a plurality of data lines; a plurality of light-sensing pixels connected to a plurality of sensing scan lines, a plurality of readout lines, and a reset control line; a scan driver supplying a plurality of scan signals to the plurality of scan lines; and a controller supplying a start signal to the scan driver. The controller may supply the start signal at a first time point after the start of a frame during some of the plurality of frame periods from which sensing signals are detected from the plurality of light-sensing pixels, and at a second time point different from the first time point after the start of a frame during the remaining frame periods.

[0008] According to an embodiment, the controller can supply a start signal at a first point in time during a frame period in which no sensing signal is detected.

[0009] According to an embodiment, the second time point can be a time point that is shifted by a horizontal time period compared to the first time point.

[0010] According to an embodiment, the second time point can be a time point of a horizontal time period earlier than the first time point.

[0011] According to an embodiment, in response to the shift of the start signal, the clock signal supplied to the scan driver can be shifted by a horizontal time period.

[0012] According to an embodiment, some frame periods may be even-numbered frame periods among multiple frame periods, and the remaining frame periods may be odd-numbered frame periods.

[0013] According to an embodiment, some frame periods may be odd-numbered frame periods among multiple frame periods, and the remaining frame periods may be even-numbered frame periods.

[0014] According to an embodiment, each of the plurality of sub-pixels may include: a light-emitting element disposed between a first power line and a second power line; a first transistor having a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor connected between a data line among the plurality of data lines and the second node, and the second transistor having a gate electrode connected to a first scan line among the plurality of scan lines; and a third transistor connected between the first node and a third power line, and the third transistor having a gate electrode connected to a second scan line among the plurality of scan lines.

[0015] According to an embodiment, the scan driver may include: a write driver that supplies a first scan signal to a first scan line; and an initialization driver that supplies a second scan signal to a second scan line.

[0016] According to an embodiment, a start signal can be supplied to the initialization driver.

[0017] According to an embodiment, the initialization driver can supply a second scan signal at different points in time during some frame periods and the remaining frame periods.

[0018] According to an embodiment, each of the plurality of sub-pixels may further include: a fourth transistor connected between the first node and the third node, and the fourth transistor having a gate electrode connected to a third scan line among the plurality of scan lines; a fifth transistor connected between the first power line and the second node, and the fifth transistor having a gate electrode connected to an emission control line; a sixth transistor connected between the third node and the first electrode of the light-emitting element, and the sixth transistor having a gate electrode connected to an emission control line; and a seventh transistor connected between the first electrode of the light-emitting element and the fourth power line, and the seventh transistor having a gate electrode connected to a fourth scan line among the plurality of scan lines.

[0019] According to an embodiment, each of the plurality of photosensitive pixels may include: a first sensor transistor having a first electrode connected to a power line supplied with a common voltage and a gate electrode connected to a sensor node; a second sensor transistor connected between a power line supplied with a reset voltage and the sensor node, and the second sensor transistor having a gate electrode connected to a reset control line; a third sensor transistor connected between the first sensor transistor and a readout line among a plurality of readout lines, and the third sensor transistor having a gate electrode connected to a sensing scan line among a plurality of sensing scan lines; and a light receiving element connected between the sensor node and a second power line.

[0020] According to an embodiment, the display device may further include: a reset circuit that supplies a reset signal to a reset control line; and a readout circuit that receives sensing signals from multiple readout lines.

[0021] According to an embodiment, the readout circuit can receive sensing signals from a plurality of light-sensing pixels arranged on some odd-numbered horizontal lines during a first frame period of a plurality of frame periods, from a plurality of light-sensing pixels arranged on some even-numbered horizontal lines during a second frame period of a plurality of frame periods, from a plurality of light-sensing pixels arranged on the remaining odd-numbered horizontal lines during a third frame period of a plurality of frame periods, and from a plurality of light-sensing pixels arranged on the remaining odd-numbered horizontal lines during a fourth frame period of a plurality of frame periods.

[0022] According to an embodiment, the display device may further include: a substrate including a display area and a non-display area, the display area including a first area and a second area; a plurality of data lines disposed in each of the first area and the second area; a plurality of readout lines disposed in each of the first area and the second area, the plurality of readout lines being spaced apart from the plurality of data lines; a connecting line extending from the first area to the second area, and the connecting line being electrically connected to the plurality of readout lines disposed in the second area; and a bridging wire extending from the second area to the first area, and the bridging wire being electrically connected to the plurality of data lines disposed in the first area.

[0023] According to embodiments of this disclosure, a display device includes: a plurality of sub-pixels, each of the plurality of sub-pixels including a light-emitting element, receiving a data signal from a data line when a first scan signal is supplied to a first scan line, and initializing the gate electrode of a driving transistor when a second scan signal is supplied to a second scan line; a plurality of light-sensing pixels, each of the plurality of light-sensing pixels including a light-receiving element and detecting external input; a write driver that supplies a first scan signal to the first scan line in response to a write start signal; an initialization driver that supplies a second scan signal to the second scan line in response to an initialization start signal; and a controller that supplies a write start signal and an initialization start signal to the write driver and the initialization driver. The controller may not supply the initialization start signal to the initialization driver during a plurality of frame periods from which sensing signals are detected from the plurality of light-sensing pixels.

[0024] According to an embodiment, the controller may not supply clock signals to the initialization driver during multiple frame periods.

[0025] According to an embodiment, the write start signal may not be supplied to the write driver during multiple frame periods.

[0026] According to embodiments of this disclosure, an electronic device includes: a processor for providing input image data; and a display device for displaying an image based on the input image data. The display device may include: sub-pixels connected to scan lines and data lines; light-sensing pixels connected to sensing scan lines, readout lines, and reset control lines; a scan driver supplying scan signals to the scan lines; and a controller supplying a start signal to the scan driver. The controller may supply the start signal at a first time point after the start of a frame during some of a plurality of frame periods from which the sensing signal is detected from the light-sensing pixels, and at a second time point different from the first time point after the start of a frame during the remaining frame periods.

[0027] The features of the present invention are not limited to those mentioned above, and other technical features not mentioned above will be clearly understood by those skilled in the art from the following description. Attached Figure Description

[0028] Embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings. However, the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, the embodiments may be extended in various ways without departing from the spirit and scope of the present disclosure.

[0029] Figure 1 and Figure 2 This is a schematic plan view of a display device according to an embodiment.

[0030] Figure 3This is a schematic cross-sectional view of a display device according to an embodiment.

[0031] Figure 4 It is shown schematically. Figure 1 A plan view of the data lines, readout lines, bridging lines, connecting lines, first line, and second line in the display device.

[0032] Figure 5 This is a block diagram illustrating a display device according to an embodiment of the present invention.

[0033] Figure 6 It is shown Figure 5 The diagram shows the scan driver.

[0034] Figure 7 It is shown Figure 5 The circuit diagram shown is an embodiment of the sub-pixel and the light-sensing pixel.

[0035] Figure 8 This illustrates an embodiment. Figure 7 The waveform diagram of the operation process of the sub-pixels.

[0036] Figure 9 This illustrates an embodiment. Figure 7 The waveform diagram of the operation process of the light-sensing pixel.

[0037] Figure 10 It shows based on Figure 9 The waveform diagram is a graph showing the sequence of detection of the sensing signal from the light-sensing pixel.

[0038] Figure 11 This is a diagram showing the second scan line according to an embodiment.

[0039] Figure 12 This is a diagram showing the sensed image obtained through the sensed signal.

[0040] Figure 13 This is a diagram illustrating the principle of noise generated from light-sensing pixels in the form of diagonal lines.

[0041] Figure 14 and Figure 16 This illustrates an embodiment. Figure 7 The waveform diagram of the operation process of the light-sensing pixel.

[0042] Figure 15 It shows based on Figure 14 The waveform diagram is a graph of the sensed image obtained from the sensed signal from the light-sensing pixel.

[0043] Figure 17 and Figure 18 This illustrates an embodiment. Figure 7 The waveform diagram of the operation process of the light-sensing pixel.

[0044] Figure 19 This illustrates an embodiment. Figure 7 The waveform diagram of the operation process of the light-sensing pixel.

[0045] Figure 20 This is a block diagram schematically illustrating an electronic device according to an embodiment.

[0046] Figure 21 It is shown schematically. Figure 20 The diagram shows an example of an electronic device implemented as a smartphone.

[0047] Figure 22 It is shown schematically. Figure 20 The diagram shows an example of an electronic device implemented as a tablet personal computer (PC). Detailed Implementation

[0048] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings to enable those skilled in the art to readily implement the present disclosure. The present disclosure may be implemented in various different forms and is not limited to the embodiments described herein.

[0049] To clearly describe the embodiments of this disclosure, components irrelevant to the description have been omitted, and throughout the specification, the same or similar components are referred to by the same reference numerals. Therefore, the same reference numerals can be used in different figures to identify the same or similar elements.

[0050] For better understanding and ease of description, the size and thickness of each element shown in the figures are arbitrary, and therefore this disclosure is not necessarily limited to the size and thickness of the elements shown in the figures. In the figures, sizes and thicknesses may be exaggerated to clearly show layers and regions.

[0051] In this disclosure, the expression "identical" means not only "completely identical" but also "substantially identical." That is, the expression "identical" can be considered identical to the extent that a person skilled in the art would consider them identical. Other expressions may be understood to implicitly include the term "substantially."

[0052] The accompanying drawings depict some embodiments related to functional blocks, units, or modules. Those skilled in the art will understand that such blocks, units, or modules are physically implemented by logic circuitry, individual components, microprocessors, hardwired circuitry, memory elements, wire connections, and other electronic circuitry. This can be formed using semiconductor-based manufacturing processes or other manufacturing steps. Blocks, units, or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform the various functions discussed herein, and may optionally be driven by firmware or software. Additionally, each block, unit, or module may be implemented by dedicated hardware or a combination of dedicated hardware performing some functions and a processor performing functions different from those of the dedicated hardware (e.g., one or more programmed microprocessors and associated circuitry). In embodiments, blocks, units, or modules may be physically divided into two or more separate blocks, units, or modules without departing from the scope of the inventive concept. In embodiments, blocks, units, or modules may be physically combined into more complex blocks, units, or modules without departing from the scope of the inventive concept.

[0053] The term "connection" between two components can include electrical or physical connections. For example, a "connection" used to illustrate a circuit diagram can refer to an electrical connection, while a "connection" used in conjunction with cross-sectional and plan views can refer to a physical connection.

[0054] It will be understood that although terms such as "first" and "second" are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one element from another. Therefore, within the technical spirit of this disclosure, a "first" element described below can be a "second" element.

[0055] The embodiments disclosed herein are not limited to those disclosed below, and can be modified or implemented in various forms. Each embodiment disclosed below can be implemented independently or in combination with at least another embodiment of this disclosure.

[0056] Figure 1 and Figure 2 This is a schematic plan view of a display device DD according to an embodiment.

[0057] exist Figure 1 and Figure 2 In this diagram, for ease of description, the structure of the display device DD is briefly shown, focusing on the display area DA that displays the image, for example, the display panel DP included in the display device DD.

[0058] refer to Figure 1 and Figure 2 The display device DD (or display panel DP) may include a substrate SUB, sub-pixels PXL and light-sensing pixels PSR.

[0059] The display device DD can be implemented in various shapes. For example, the display device DD can be provided in the shape of a rectangular plate with two pairs of parallel sides, but this disclosure is not limited thereto. This embodiment can be applied if the display device DD is an electronic device with a display surface (such as a smartphone, television, tablet PC, mobile phone, video phone, e-book reader, desktop PC, laptop PC, netbook computer, workstation, server, personal digital assistant (PDA), portable multimedia player (PMP), MP3 player, medical device, camera, or wearable device).

[0060] The substrate SUB may include a transparent insulating material to allow light to pass through. The substrate SUB may be a rigid substrate or a flexible substrate.

[0061] The rigid substrate can be, for example, a glass substrate, a quartz substrate, a glass-ceramic substrate, or a crystalline glass substrate.

[0062] The flexible substrate can be either a membrane substrate comprising polymeric organic materials or a plastic substrate. For example, the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0063] The display device DD or display panel DP may include a display area DA in which sub-pixels PXL and light-sensing pixels PSR are arranged, and a non-display area NDA surrounding the display area DA.

[0064] In an embodiment, the display area DA may include a first area DA1 and a second area DA2. For example, the display area DA may be divided into a first area DA1 and a second area DA2 based on the correspondence between the components of the line portion LP. For example, the first area DA1 may be the portion of the display area DA adjacent to the first line LP1 of the line portion LP, and the second area DA2 may be the portion of the display area DA adjacent to the second line LP2 of the line portion LP.

[0065] The first region DA1 can be adjacent to the non-display region NDA where the first line LP1 is placed, and the second region DA2 can be adjacent to the non-display region NDA where the second line LP2 is placed.

[0066] Sub-pixels PXL and light-sensing pixels PSR can be arranged in each of the first region DA1 and the second region DA2.

[0067] Each of the sub-pixels PXL may include a light-emitting element comprising a light-emitting layer. According to embodiments, the light-emitting element may include an organic light-emitting diode or an inorganic light-emitting diode having a size in the range of micrometers to nanometers (or meters), but this disclosure is not limited thereto. The display device DD may display an image in a first region DA1 and a second region DA2 by driving the sub-pixels PXL in response to input image data.

[0068] The display area DA may include a sensing area capable of sensing a user's fingerprint, etc. For example, a first area DA1 and a second area DA2 may be configured as sensing areas capable of sensing a user's fingerprint, etc. If the entire display area DA is configured as a sensing area, the non-display area NDA surrounding the display area DA may be a non-sensing area.

[0069] A light-sensing pixel (PSR) (or light sensor) can be arranged in a first region DA1 and a second region DA2. Each of the light-sensing pixels (PSR) may include a light-receiving element containing a light-receiving layer. In the first region DA1 and the second region DA2, the light-receiving layer of the light-receiving element may be spaced apart from the light-emitting layer of the light-emitting element.

[0070] A photosensitive pixel (PSR) can detect light emitted from a light source (e.g., a light-emitting element) or reflected from an external object (e.g., a user's finger). For example, a user's fingerprint can be detected by each of the photosensitive pixels (PSRs). In the following description, the use of a photosensitive pixel (PSR) to detect fingerprints is primarily illustrated as an example, but it will be understood that the photosensitive pixel (PSR) according to this disclosure can detect various biometric information such as iris or veins. Furthermore, the photosensitive pixel (PSR) can also detect external light and can perform the functions of a gesture sensor, motion sensor, proximity sensor, light sensor, or image sensor.

[0071] The line portion (LP), the pad portion (PDP), and the embedded circuitry for driving the sub-pixels (PXL) and the photosensitive pixels (PSR) can be located in the non-display area (NDA). The non-display area (NDA) may include the fan-out area (FTA) and the pad area (PDA).

[0072] The pad area PDA can be the area of ​​the PDP where the pads are arranged in the non-display area NDA, and can be formed at the edge of the non-display area NDA.

[0073] The fan-out region FTA can be a region of the arrangement line portion LP of the non-display region NDA, and can be formed in the region between the display region DA and the non-display region NDA (e.g., formed in the region between the display region DA and the pad region PDA). For example, the fan-out region FTA can be a region of the non-display region NDA located between the pad region PDA and the display region DA. According to an embodiment, the non-display region NDA may include an electrostatic discharge (ESD) protection circuit region, and an ESD protection circuit electrically connected to the signal lines of the display region DA to prevent the generation of ESD is located in the ESD protection circuit region.

[0074] The line portion (LP) can be set in the fan-out region (FTA), and the pad portion (PDP) can be set in the pad region (PDA).

[0075] The line portion LP can be electrically connected to the sub-pixel PXL and the photosensitive pixel PSR, and transmits predetermined signals received from the driving unit DIC to the signal line. In the fan-out region FTA, the line portion LP can include fan-out lines that electrically connect the driving unit DIC to the sub-pixel PXL and the photosensitive pixel PSR.

[0076] In an embodiment, the line portion LP may include a first line LP1 and a second line LP2.

[0077] The first line LP1 can be disposed in the fan-out region FTA between the first region DA1 and the pad portion PDP. Multiple first lines LP1 can be provided, and may include fan-out lines electrically connected to the photosensitive pixel PSR disposed in the first region DA1. For example, the first line LP1 may include fan-out lines electrically connected to readout lines associated with the photosensitive pixel PSR located in the first region DA1, and transmitting electrical signals (e.g., sensing signals) received from the photosensitive pixel PSR to the driving unit DIC.

[0078] In an embodiment, the first line LP1 may include a fan-out line electrically connected via a connection line extending from the first region DA1 to the second region DA2 to a readout line associated with a photosensitive pixel PSR located in the second region DA2.

[0079] The second line LP2 can be located in the fan-out region FTA between the second region DA2 and the pad portion PDP. Multiple second lines LP2 can be provided, and may include fan-out lines electrically connected to the sub-pixel PXL located in the second region DA2. For example, the second line LP2 may include fan-out lines electrically connected to a data line associated with the sub-pixel PXL located in the second region DA2 and transmitting data signals to the sub-pixel PXL.

[0080] In one embodiment, the second line LP2 may include a fan-out line electrically connected to a data line via a bridging wire extending from the second region DA2 to the first region DA1, the data line being connected to a sub-pixel PXL located in the first region DA1.

[0081] The pad portion PDP can be disposed in the pad area PDA and can supply driving power and signals for driving the sub-pixels PXL and photosensitive pixels PSR arranged in the display area DA. The pad portion PDP can be electrically connected to the line portion LP. In an embodiment, the pad portion PDP may include a first pad portion PDP1 and a second pad portion PDP2.

[0082] The first pad portion PDP1 may include a first pad P1 electrically connected to the first line LP1, and the second pad portion PDP2 may include a second pad P2 electrically connected to the second line LP2.

[0083] Multiple first pads P1 may be provided. Each first pad P1 may include multiple first pads P1 electrically connected via corresponding first lines LP1 to readout lines associated with photosensitive pixels PSR located in the first region DA1. Alternatively, each first pad P1 may include multiple first pads P1 electrically connected via corresponding first lines LP1 to connection lines associated with photosensitive pixels PSR located in the second region DA2.

[0084] Multiple second pads P2 may be provided. Each second pad P2 may include multiple second pads P2 electrically connected via corresponding second lines LP2 to a data line associated with a sub-pixel PXL located in the second region DA2. Alternatively, each second pad P2 may include multiple second pads P2 electrically connected via corresponding second lines LP2 to a bridging line associated with a sub-pixel PXL located in the first region DA1.

[0085] The display device DD may include a circuit board FPCB connected to the display panel DP via pad portions PDP. The circuit board FPCB may be a flexible circuit board, but this disclosure is not limited thereto.

[0086] The circuit board (FPCB) can process various signals input from a printed circuit board (not shown) and output them to a display panel (DP). For this purpose, one end of the FPCB can be attached to the display panel (DP), and the opposite end can be attached to the printed circuit board. The FPCB can be connected to the display panel (DP) and the printed circuit board respectively using conductive adhesive components (e.g., anisotropic conductive film).

[0087] The driver unit (DIC) can be mounted on the circuit board (FPCB). The driver unit (DIC) can be, for example, an integrated circuit (IC). The driver unit (DIC) can include a panel driver unit and a fingerprint detection unit.

[0088] The panel driving unit can sequentially scan the sub-pixels PXL while simultaneously supplying data signals corresponding to the image data signals to the sub-pixels PXL. In this case, the display panel DP can display an image corresponding to the image data. The panel driving unit can supply driving signals to the sub-pixels PXL to cause them to emit light. The light emitted from the sub-pixels PXL can be used as a light source to detect fingerprints in the photosensitive pixel PSR. In an embodiment, the panel driving unit can supply either a driving signal for fingerprint detection or another driving signal to the photosensitive pixel PSR. However, this disclosure is not limited to this, and the driving signal for fingerprint detection can also be provided from the fingerprint detection unit.

[0089] The fingerprint detection unit can detect biometric information such as a user's fingerprint based on sensing signals received from the photosensitive pixel PSR. The fingerprint detection unit can also supply drive signals to the photosensitive pixel PSR or the sub-pixel PXL.

[0090] In the display area DA, the first area DA1 can be arranged on both sides of the second area DA2. For example, the second area DA2 can be placed in the center of the substrate SUB (or display device DD), and the first area DA1 can be placed at the edge of the substrate SUB. In other words, the second area DA2 can be located inside the display panel DP, and the first area DA1 can be located outside the display panel DP.

[0091] In the fan-out region FTA, the first line LP1 can be arranged on both sides of the second line LP2. For example, the second line LP2 can be placed in the center of the fan-out region FTA adjacent to the second region DA2, and the first line LP1 can be placed at the edge of the fan-out region FTA adjacent to the first region DA1. In other words, the second line LP2 can be located inside the fan-out region FTA, and the first line LP1 can be located outside the fan-out region FTA. As a result, the first line LP1 and the second line LP2 can be separated from each other in the fan-out region FTA.

[0092] In the pad area PDA, the first pad portion PDP1 can be located on both sides of the second pad portion PDP2. For example, the second pad portion PDP2 can be placed in the center of the pad area PDA to correspond to the second line LP2, and the first pad portion PDP1 can be placed at the edge of the pad area PDA to correspond to the first line LP1. In other words, the second pad portion PDP2 can be located inside the pad area PDA, and the first pad portion PDP1 can be located outside the pad area PDA.

[0093] Figure 3 This is a schematic cross-sectional view of the display device DD according to an embodiment.

[0094] refer to Figures 1 to 3 The display device DD may include a display module DM and a window WD.

[0095] The display module (DM) may include a display panel (DP) and a touch sensor (TS).

[0096] The touch sensor TS can be directly mounted on the display panel DP, or it can be mounted on the display panel DP with a separate layer (such as an adhesive layer or a substrate (or insulating layer)) between the touch sensor TS and the display panel DP.

[0097] Display panel DP can display images. Display panel DP can be a self-emitting display panel, such as an organic light-emitting display panel (OLED panel). Display panel DP can also be a non-self-emitting display panel, such as a liquid crystal display panel (LCD panel), an electrophoretic display panel (EPD panel), or an electrowetting display panel (EWD panel). When a non-self-emitting display panel is used as display panel DP, display device DD may include a backlight unit for supplying light to display panel DP.

[0098] A touch sensor TS can be placed on the surface of the output image of the display panel DP to receive user touch input. The touch sensor TS can recognize touch events on the display device DD via the user's hand or a separate input device. The touch sensor TS can recognize touch events capacitively.

[0099] The touch sensor TS can detect touch input using either mutual capacitance or self-capacitance.

[0100] Window WD can be provided on the display module DM to protect it from external impacts. Window WD can be combined with the display module DM using optically clear adhesive (OCA).

[0101] Window WD (or covering glass) can have a multi-layered structure selected from the group consisting of a glass substrate, a plastic film, and a plastic substrate. This multi-layered structure can be formed by a continuous process or by an adhesive process using adhesive layers. Window WD can be wholly or partially flexible.

[0102] Figure 4 It is shown schematically. Figure 1 Plan view of data lines D1 to Dk+6, readout lines RX1 to RXk+5, bridge line BRL, connecting line CNL, first line LP1a to LP1m and second line LP2a to LP2m in the display device DD.

[0103] refer to Figures 1 to 4 The display device DD (or display panel DP) may include a substrate SUB, a line portion LP, and a pad portion PDP.

[0104] The pad portion PDP can be located within the pad area PDA and can include a first pad portion PDP1 and a second pad portion PDP2 electrically connected to the line portion LP. The first pad portion PDP1 can include a first pad P1 electrically connected to the first line LP1, and the second pad portion PDP2 can include a second pad P2 electrically connected to the second line LP2. The first pad portion PDP1 and the second pad portion PDP2 can be arranged to be physically and electrically separated from each other within the pad area PDA.

[0105] The line portion LP can be located within the fan-out region FTA and can include a first line LP1 electrically connected to a first pad portion PDP1 and a second line LP2 electrically connected to a second pad portion PDP2. The first line LP1 and the second line LP2 can be arranged to be physically and electrically separated from each other within the fan-out region FTA. For example, the first line LP1 can be arranged adjacent to the edge of the substrate SUB within the fan-out region FTA, and the second line LP2 can be arranged in the center of the fan-out region FTA. The first line LP1 can be positioned within the fan-out region FTA and extend towards the first region DA1, and the second line LP2 can be positioned within the fan-out region FTA and extend towards the second region DA2. The first line LP1 can be located on either side of the second line LP2.

[0106] The first line LP1 may include a first group of first lines electrically connected via a first contact portion CNT1 to read lines RX1 to RX4 and RXk+3 to RXk+5 located in the first region DA1. The first group of first lines may include line (1a) LP1a, line (1c) LP1c, line (1e) LP1e, line (1g) LP1g, line (1h) LP1h, line (1j) LP1j and line (1l) LP1l.

[0107] In an embodiment, the first line LP1 may include a second set of first lines electrically connected via a first contact portion CNT1 to a connecting line CNL extending from the first region DA1 to the second region DA2. The second set of first lines may include line (1b) LP1b, line (1d) LP1d, line (1f) LP1f, line (1i) LP1i, line (1k) LP1k, and line (1m) LP1m.

[0108] The second line LP2 may include a first group of second lines electrically connected to data lines D4 to Dk+2 located in the second region DA2 via the second contact portion CNT2. The first group of second lines may include line (2b) LP2b, line (2d) LP2d, line (2f) LP2f, line (2h) LP2h, line (2j) LP2j and line (2l) PL2l.

[0109] In an embodiment, the second line LP2 may include a second set of second lines electrically connected via a second contact portion CNT2 to a bridging wire BRL extending from the second region DA2 to the first region DA1. The second set of second lines may include line (2a) LP2a, line (2c) LP2c, line (2e) LP2e, line (2g) LP2g, line (2i) LP2i, line (2k) LP2k, and line (2m) LP2m.

[0110] In the following embodiments, when any one of lines (1a) LP1a to (1m) LP1m is indicated, or when lines (1a) LP1a to (1m) LP1m are indicated together, lines (1a) LP1a to (1m) LP1m may be referred to as "first line LP1" or "(multiple) first lines LP1". Additionally, when any one of lines (2a) LP2a to (2m) LP2m is indicated, or when lines (2a) LP2a to (2m) LP2m are indicated together, lines (2a) LP2a to (2m) LP2m may be referred to as "second line LP2" or "(multiple) second lines LP2".

[0111] The substrate SUB may include a display area DA and a non-display area NDA. The display area DA can be divided into a first area DA1 and a second area DA2.

[0112] Signal lines that apply various signals can be arranged in the first region DA1 and the second region DA2. For example, data lines D1 to Dk+6 that apply data signals for controlling the brightness in each sub-pixel PXL can be arranged in the first region DA1 and the second region DA2. Readout lines RX1 to RXk+5 that receive sensing signals from the photosensitive pixel PSR can be arranged in the first region DA1 and the second region DA2. In addition to data lines D1 to Dk+6 and readout lines RX1 to RXk+5, various signal lines such as power lines and scan lines can be arranged in the first region DA1 and the second region DA2.

[0113] In the first region DA1 and the second region DA2, the sub-pixel PXL can be arranged in or located in the region defined by scan lines and data lines (e.g., data lines D1 to Dk+6). In the first region DA1 and the second region DA2, the photosensitive pixel PSR can be arranged in or located in the region defined by scan lines and readout lines (e.g., readout lines RX1 to RXk+5).

[0114] The first data line D1, the second data line D2, the third data line D3, the (k+3)th data line Dk+3, the (k+4)th data line Dk+4, the (k+5)th data line Dk+5, and the (k+6)th data line Dk+6 can be arranged in the first region DA1. For ease of description, Figure 4 Seven data lines arranged in the first region DA1 are shown, but this disclosure is not limited thereto.

[0115] The fourth data line D4, the fifth data line D5, the sixth data line D6, the kth data line Dk, the (k+1)th data line Dk+1, and the (k+2)th data line Dk+2 can be arranged in the second region DA2. For ease of description, Figure 4 Six data lines arranged in the second region DA2 are shown, but this disclosure is not limited thereto.

[0116] The first readout line RX1, the second readout line RX2, the third readout line RX3, the fourth readout line RX4, the (k+3)th readout line RXk+3, the (k+4)th readout line RXk+4, and the (k+5)th readout line RXk+5 can be arranged in the first region DA1. For ease of description, Figure 4 Seven readout lines arranged in the first region DA1 are shown, but this disclosure is not limited thereto.

[0117] The fifth readout line RX5, the sixth readout line RX6, the seventh readout line RX7, the kth readout line RXk, the (k+1)th readout line RXk+1, and the (k+2)th readout line RXk+2 can be arranged in the second region DA2. For ease of description, Figure 4 Six readout lines arranged in the second region DA2 are shown, but this disclosure is not limited thereto.

[0118] The connecting line CNL and the bridging line BRL can be disposed within the display area DA. In an embodiment, the connecting line CNL and the bridging line BRL can be arranged so that they do not overlap with each other within the display area DA. In this case, coupling capacitance that may occur due to the overlap of the connecting line CNL and the bridging line BRL can be prevented.

[0119] In this embodiment, the connecting line CNL can extend from the first region DA1 to the second region DA2. For example, the connecting line CNL can be routed from the edge (or outer side) of the display region DA to the center (or inner side) of the display region DA. The connecting line CNL can be electrically connected to the corresponding first line LP1 through the first contact portion CNT1. The connecting line CNL may include a vertical connecting line disposed in the first region DA1 and extending along the second direction DR2, and a horizontal connecting line electrically connected to the vertical connecting line and extending from the first region DA1 to the second region DA2 along the first direction DR1 intersecting the second direction DR2.

[0120] The connecting line CNL may include a first connecting line CNL1, a second connecting line CNL2, a third connecting line CNL3, a fourth connecting line CNL4, a fifth connecting line CNL5, and a sixth connecting line CNL6. Each of the first connecting line CNL1, the second connecting line CNL2, the third connecting line CNL3, the fourth connecting line CNL4, the fifth connecting line CNL5, and the sixth connecting line CNL6 may include a vertical connecting line disposed in the first region DA1 and extending in the second direction DR2, and a horizontal connecting line extending from the first region DA1 to the second region DA2 in the first direction DR1.

[0121] The vertical connecting line of the first connecting line CNL1 can be electrically connected to the (1b) line LP1b through the first contact portion CNT1, and can be electrically connected to the horizontal connecting line of the first connecting line CNL1 through the third contact hole CH3. The horizontal connecting line can be electrically connected to the seventh readout line RX7 disposed in the second region DA2 through the fourth contact hole CH4. The first connecting line CNL1 can electrically connect the seventh readout line RX7 to the (1b) line LP1b. Therefore, the sensing signal of the photosensitive pixel PSR received from the second region DA2 through the seventh readout line RX7 can be transmitted to the driving unit DIC through the first connecting line CNL1 and the (1b) line LP1b.

[0122] The vertical connecting line of the second connecting line CNL2 can be electrically connected to the (1d) line LP1d through the first contact portion CNT1, and can be electrically connected to the horizontal connecting line of the second connecting line CNL2 through the third contact hole CH3. The horizontal connecting line can be electrically connected to the sixth readout line RX6 disposed in the second region DA2 through the fourth contact hole CH4. The second connecting line CNL2 can electrically connect the sixth readout line RX6 to the (1d) line LP1d. Therefore, the sensing signal of the photosensitive pixel PSR received from the second region DA2 through the sixth readout line RX6 can be transmitted to the driving unit DIC through the second connecting line CNL2 and the (1d) line LP1d.

[0123] The vertical connecting line of the third connecting line CNL3 can be electrically connected to the (1f) line LP1f through the first contact portion CNT1, and can be electrically connected to the horizontal connecting line of the third connecting line CNL3 through the third contact hole CH3. The horizontal connecting line can be electrically connected to the fifth readout line RX5 disposed in the second region DA2 through the fourth contact hole CH4. The third connecting line CNL3 can electrically connect the fifth readout line RX5 to the (1f) line LP1f. Therefore, the sensing signal of the photosensitive pixel PSR received from the second region DA2 through the fifth readout line RX5 can be transmitted to the driving unit DIC through the third connecting line CNL3 and the (1f) line LP1f.

[0124] The vertical connecting line of the fourth connecting line CNL4 can be electrically connected to the (1m) line LP1m through the first contact portion CNT1, and can be electrically connected to the horizontal connecting line of the fourth connecting line CNL4 through the third contact hole CH3. The horizontal connecting line can be electrically connected to the k-th readout line RXk disposed in the second region DA2 through the fourth contact hole CH4. The fourth connecting line CNL4 can electrically connect the k-th readout line RXk to the (1m) line LP1m. Therefore, the sensing signal of the photosensitive pixel PSR received from the second region DA2 through the k-th readout line RXk can be transmitted to the driving unit DIC through the fourth connecting line CNL4 and the (1m) line LP1m.

[0125] The vertical connecting line of the fifth connecting line CNL5 can be electrically connected to the (1k) line LP1k through the first contact portion CNT1, and can be electrically connected to the horizontal connecting line of the fifth connecting line CNL5 through the third contact hole CH3. The horizontal connecting line can be electrically connected to the (k+1) readout line RXk+1 disposed in the second region DA2 through the fourth contact hole CH4. The fifth connecting line CNL5 can electrically connect the (k+1) readout line RXk+1 to the (1k) line LP1k. Therefore, the sensing signal of the photosensitive pixel PSR received from the second region DA2 through the (k+1) readout line RXk+1 can be transmitted to the driving unit DIC through the fifth connecting line CNL5 and the (1k) line LP1k.

[0126] The vertical connecting line of the sixth connecting line CNL6 can be electrically connected to the (1i) line LP1i through the first contact portion CNT1, and can be electrically connected to the horizontal connecting line of the sixth connecting line CNL6 through the third contact hole CH3. The horizontal connecting line can be electrically connected to the (k+2) readout line RXk+2 disposed in the second region DA2 through the fourth contact hole CH4. The sixth connecting line CNL6 can electrically connect the (k+2) readout line RXk+2 to the (1i) line LP1i. Therefore, the sensing signal of the photosensitive pixel PSR received from the second region DA2 through the (k+2) readout line RXk+2 can be transmitted to the driving unit DIC through the sixth connecting line CNL6 and the (1i) line LP1i.

[0127] One end of the vertical connecting line can be electrically connected to the corresponding first line LP1 through the first contact portion CNT1, and the other end of the vertical connecting line can be electrically connected to the corresponding horizontal connecting line through the third contact hole CH3. One end of the horizontal connecting line can be electrically connected to the vertical connecting line through the third contact hole CH3, and the other end of the horizontal connecting line can be electrically connected to the corresponding readout line located in the second region DA2 through the fourth contact hole CH4.

[0128] In an embodiment, the bridging wire BRL can extend from the second region DA2 to the first region DA1. For example, the bridging wire BRL can be routed from the center (or inner side) of the display region DA to the edge (or outer side) of the display region DA. The bridging wire BRL can be electrically connected to the corresponding second line LP2 via the second contact portion CNT2. The bridging wire BRL may include a vertical bridging wire disposed in the second region DA2 and extending along the second direction DR2, and a horizontal bridging wire electrically connected to the vertical bridging wire and extending from the second region DA2 to the first region DA1 along a first direction DR1 intersecting the second direction DR2.

[0129] The bridging line BRL may include a first bridging line BRL1, a second bridging line BRL2, a third bridging line BRL3, a fourth bridging line BRL4, a fifth bridging line BRL5, a sixth bridging line BRL6, and a seventh bridging line BRL7. Each of the first bridging line BRL1, the second bridging line BRL2, the third bridging line BRL3, the fourth bridging line BRL4, the fifth bridging line BRL5, the sixth bridging line BRL6, and the seventh bridging line BRL7 may include a vertical bridging line located in the second region DA2 and extending in the second direction DR2, and a horizontal bridging line extending from the second region DA2 to the first region DA1 in the first direction DR1.

[0130] The vertical bridge wire of the first bridge wire BRL1 can be electrically connected to the (2e) line LP2e through the second contact portion CNT2, and can be electrically connected to the horizontal bridge wire of the first bridge wire BRL1 through the first contact hole CH1. The horizontal bridge wire can be electrically connected to the first data line D1 disposed in the first area DA1 through the second contact hole CH2. The first bridge wire BRL1 can electrically connect the first data line D1 to the (2e) line LP2e. Therefore, the data signal transmitted from the drive unit DIC to the (2e) line LP2e can be transmitted to the first data line D1 via the first bridge wire BRL1.

[0131] The vertical bridge wire of the second bridge wire BRL2 can be electrically connected to the (2c) line LP2c via the second contact portion CNT2, and can be electrically connected to the horizontal bridge wire of the second bridge wire BRL2 via the first contact hole CH1. The horizontal bridge wire can be electrically connected to the second data line D2 disposed in the first area DA1 via the second contact hole CH2. The second bridge wire BRL2 can electrically connect the second data line D2 to the (2c) line LP2c. Therefore, the data signal transmitted from the drive unit DIC to the (2c) line LP2c can be transmitted to the second data line D2 via the second bridge wire BRL2.

[0132] The vertical bridge wire of the third bridge wire BRL3 can be electrically connected to line (2a) LP2a via the second contact portion CNT2, and can be electrically connected to the horizontal bridge wire of the third bridge wire BRL3 via the first contact hole CH1. The horizontal bridge wire can be electrically connected to the third data line D3 located in the first area DA1 via the second contact hole CH2. The third bridge wire BRL3 can electrically connect the third data line D3 to line (2a) LP2a. Therefore, the data signal transmitted from the drive unit DIC to line (2a) LP2a can be transmitted to the third data line D3 via the third bridge wire BRL3.

[0133] The vertical bridge wire of the fourth bridge wire BRL4 can be electrically connected to the (2g) line LP2g via the second contact portion CNT2, and can be electrically connected to the horizontal bridge wire of the fourth bridge wire BRL4 via the first contact hole CH1. The horizontal bridge wire can be electrically connected to the (k+6) data line Dk+6 located in the first area DA1 via the second contact hole CH2. The fourth bridge wire BRL4 can electrically connect the (k+6) data line Dk+6 to the (2g) line LP2g. Therefore, the data signal transmitted from the drive unit DIC to the (2g) line LP2g can be transmitted to the (k+6) data line Dk+6 via the fourth bridge wire BRL4.

[0134] The vertical bridge wire of the fifth bridge wire BRL5 can be electrically connected to the (2i) line LP2i via the second contact portion CNT2, and can be electrically connected to the horizontal bridge wire of the fifth bridge wire BRL5 via the first contact hole CH1. The horizontal bridge wire can be electrically connected to the (k+5) data line Dk+5 located in the first area DA1 via the second contact hole CH2. The fifth bridge wire BRL5 can electrically connect the (k+5) data line Dk+5 to the (2i) line LP2i. Therefore, the data signal transmitted from the drive unit DIC to the (2i) line LP2i can be transmitted to the (k+5) data line Dk+5 via the fifth bridge wire BRL5.

[0135] The vertical bridge wire of the sixth bridge wire BRL6 can be electrically connected to the (2k) line LP2k via the second contact portion CNT2, and can be electrically connected to the horizontal bridge wire of the sixth bridge wire BRL6 via the first contact hole CH1. The horizontal bridge wire can be electrically connected to the (k+4) data line Dk+4 located in the first area DA1 via the second contact hole CH2. The sixth bridge wire BRL6 can electrically connect the (k+4) data line Dk+4 to the (2k) line LP2k. Therefore, the data signal transmitted from the drive unit DIC to the (2k) line LP2k can be transmitted to the (k+4) data line Dk+4 via the sixth bridge wire BRL6.

[0136] The vertical bridge wire of the seventh bridge wire BRL7 can be electrically connected to the (2m) line LP2m via the second contact portion CNT2, and can be electrically connected to the horizontal bridge wire of the seventh bridge wire BRL7 via the first contact hole CH1. The horizontal bridge wire can be electrically connected to the (k+3) data line Dk+3 located in the first area DA1 via the second contact hole CH2. The seventh bridge wire BRL7 can electrically connect the (k+3) data line Dk+3 to the (2m) line LP2m. Therefore, the data signal transmitted from the drive unit DIC to the (2m) line LP2m can be transmitted to the (k+3) data line Dk+3 via the seventh bridge wire BRL7.

[0137] According to the above embodiment, the first pad portion PDP1 (or first pad P1) electrically connected to the readout line and the second pad portion PDP2 (or second pad P2) electrically connected to the data line can be separated from each other in the pad area PDA, and can be respectively centrally disposed in specific areas of the pad area PDA. For example, the second pad portion PDP2 can be located in the center of the pad area PDA to correspond to the second area DA2 of the display area DA, and the first pad portion PDP1 can be located at the two edges of the pad area PDA to correspond to the first area DA1 of the display area DA. In this case, the phenomenon that the sensing signal of the photosensitive pixel PSR transmitted through the first pad portion PDP1 to the driving unit DIC is affected by the data signal transmitted through the second pad portion PDP2 to the data line can be reduced or prevented. In addition, the phenomenon that the data signal transmitted through the second pad portion PDP2 to the data line is affected by the sensing signal of the photosensitive pixel PSR transmitted through the first pad portion PDP1 to the driving unit DIC can be reduced or prevented. If the read pads electrically connected to the read lines and the data pads electrically connected to the data lines are alternately arranged in the pad area PDA, coupling capacitance (or parasitic capacitance) may occur between the read pads and the data pads. Therefore, in the above embodiment, the first pad portion PDP1 and the second pad portion PDP2 can be arranged separately, and each of the first pad portion PDP1 and the second pad portion PDP2 can be located only in a specific area in the pad area PDA, thereby preventing the aforementioned coupling capacitance and improving the reliability of the display device DD.

[0138] According to the above embodiment, the first line LP1 electrically connected to the readout line and the second line LP2 electrically connected to the data line can be separated from each other in the fan-out region FTA, and can be respectively concentrated in specific areas of the fan-out region FTA. For example, the second line LP2 can be located in the center of the fan-out region FTA to correspond to the second area DA2 of the display area DA, and the first line LP1 can be located at the two edges of the fan-out region FTA to correspond to the first area DA1 of the display area DA. In this case, the phenomenon that the sensing signal of the photosensitive pixel PSR transmitted to the first pad portion PDP1 via the first line LP1 is affected by the data signal transmitted to the data line via the second line LP2 can be reduced or prevented. In addition, the phenomenon that the data signal transmitted to the data line via the second line LP2 is affected by the sensing signal of the photosensitive pixel PSR transmitted to the first pad portion PDP1 via the first line LP1 can be reduced or prevented. If the readout fanout line electrically connected to the readout line and the data fanout line electrically connected to the data line are alternately arranged in the fan-out region FTA, coupling capacitance (or parasitic capacitance) may appear between the readout fanout line and the data fanout line. Therefore, in the above embodiments, the first line LP1 and the second line LP2 can be arranged separately, and each of the first line LP1 and the second line LP2 can be located only in a specific area of ​​the fan-out region FTA, thereby preventing the aforementioned coupling capacitor and improving the reliability of the display device DD.

[0139] Figure 5 This is a block diagram illustrating a display device according to an embodiment of the present invention. Figure 6 It is shown Figure 5 The diagram shows the scan driver 2121. Here, it includes... Figure 5 The "i", "j", "k", "m", and "o" in this context can be different from those included in the previous context. Figure 4 The "i", "j", "k", "m", and "o" in the text. For example, including... Figure 4 The letters “i”, “j”, “k”, “m”, and “o” can be used to distinguish lines and are included in Figure 5 The "i", "j", "k", "m" and "o" in the text refer to specific numbers.

[0140] refer to Figure 5 The display unit 112 may include signal lines and sub-pixels PXL (see...). Figure 1 ) and light-sensing pixel PSR (see Figure 1The signal lines may include scan lines S1, ..., Si, ... and Sn, data lines D1, ..., Dj, ... and Dm, readout lines RX1, ..., RXk, ... and RXo, sensing scan lines SS1, ..., SSi, ... and SSn, and a reset control line RSTL (or a reset line). Here, n, m, and o can each be a natural number greater than or equal to 3. Here, i, j, and k can be natural numbers greater than or equal to 1 and less than or equal to n, greater than or equal to 1 and less than or equal to m, and greater than or equal to 1 and less than or equal to 0, respectively.

[0141] Sub-pixels PXL can be arranged in or located in an area (e.g., a pixel region) defined by scan lines S1 to Sn and data lines D1 to Dm. Photosensitive pixels PSR can be arranged in or located in an area defined by sensing scan lines SS1 to SSn and readout lines RX1 to RXo. Sub-pixels PXL and photosensitive pixels PSR can be arranged as a two-dimensional array in the display area DA, but the invention is not limited thereto.

[0142] Each of the sub-pixels PXL can be electrically connected to at least one of the scan lines S1 to Sn and one of the data lines D1 to Dm. Each of the photosensitive pixels PSR can be electrically connected to one of the sensing scan lines SS1 to SSn, one of the readout lines RX1 to RXo, and the reset control line RSTL.

[0143] Drive unit DIC (see Figure 2 It may include at least one of scan driver 2121, data driver 2122, controller 2123 (or timing controller), power supply unit 2124, reset circuit 2141, readout circuit 2142 and sensing scan driver 2143.

[0144] For example, the scan driver 2121, data driver 2122, controller 2123, and power supply unit 2124 may be included in the panel driver, and the reset circuit 2141, readout circuit 2142, and sensing scan driver 2143 may be included in the fingerprint detector. However, the invention is not limited thereto.

[0145] The scan driver 2121 can be electrically connected to the sub-pixel PXL via scan lines S1 to Sn. The scan driver 2121 can generate a scan signal based on the scan control signal SCS (or gate control signal) and provide the scan signal to the scan lines S1 to Sn. Here, the scan control signal SCS may include a start signal and a clock signal, etc., and can be provided to the scan driver 2121 from the controller 2123.

[0146] like Figure 6As shown, the scan driver 2121 may have multiple drivers 2121a, 2121b, 2121c, and 2121d. Each of the scan lines S1 to Sn may have multiple scan lines. For example, the first scan line S1 may include a first first scan line S11, a first second scan line S21, a first third scan line S31, and a first fourth scan line S41. For example, the nth scan line Sn may include an nth first scan line S1n, an nth second scan line S2n, an nth third scan line S3n, and an nth fourth scan line S4n. For example, as... Figure 7 As shown, the i-th scan line Si may include the (1i)-th scan line S1i, the (2i)-th scan line S2i, the (3i)-th scan line S3i, and the (4i)-th scan line S4i.

[0147] The write driver 2121a can sequentially supply first scan signals to the first scan lines S11 to S1n. For example, the write driver 2121a can receive a write start signal WFLM and generate the first scan signal by shifting the write start signal WFLM in response to a clock signal CLK. The first scan signal can be set to a gate on-state voltage, and therefore, the transistor receiving the first scan signal can be turned on.

[0148] The compensation driver 2121c can sequentially supply third scan signals to the third scan lines S31 to S3n. For example, the compensation driver 2121c can receive a compensation start signal CFLM and generate the third scan signal by shifting the compensation start signal CFLM in response to a clock signal CLK. The third scan signal can be set to a gate on-state voltage, and therefore, the transistor receiving the third scan signal can be turned on.

[0149] The control driver 2121d can sequentially supply fourth scan signals to the fourth scan lines S41 to S4n. For example, the control driver 2121d can receive a control start signal BFLM and generate the fourth scan signal by shifting the control start signal BFLM in response to a clock signal CLK. The fourth scan signal can be set to a gate on-state voltage, so that the transistor receiving the fourth scan signal can be turned on.

[0150] In one embodiment, the write driver 2121a, the compensation driver 2121c, and the control driver 2121d can be formed as separate components. In another embodiment, at least two of the write driver 2121a, the compensation driver 2121c, and the control driver 2121d can be integrated and formed as a single component. In another embodiment, the clock signal CLK can consist of multiple signals, and different signals can be supplied to the write driver 2121a, the compensation driver 2121c, and the control driver 2121d. In yet another embodiment, the clock signal CLK can include multiple signals, and at least two of the write driver 2121a, the compensation driver 2121c, and the control driver 2121d can share these signals.

[0151] The initialization driver 2121b can sequentially supply second scan signals to the second scan lines S21 to S2n. For example, the initialization driver 2121b can receive an initialization start signal IFLM and generate the second scan signal by shifting the initialization start signal IFLM in response to clock signals CLK1 and CLK2. The second scan signal can be set to a gate on-state voltage, and therefore, the transistor receiving the second scan signal can be turned on.

[0152] Additionally, the clock signals CLK1 and CLK2 supplied to the initialization driver 2121b can be set in various ways depending on the configuration of the stage circuitry included in the initialization driver 2121b. For example, the initialization driver 2121b can be driven in response to at least one clock signal.

[0153] The sub-pixel PXL selected and driven by the scan driver 2121 can emit light with a brightness corresponding to the data signal provided through the data line. For example, the sub-pixel PXLij selected and driven by the i-th scan line Si can emit light with a brightness corresponding to the data signal provided through the j-th data line Dj.

[0154] The data driver 2122 can generate a data signal (or data voltage) based on the image data DATA2 and the data control signal DCS provided from the controller 2123, and provide the data signal to the display unit 112 (or sub-pixel PXL) via data lines D1 to Dm. Here, the data control signal DCS can be a signal that controls the operation of the data driver 2122, and may include a data enable signal (or load signal) indicating the output of a valid data signal, a level start signal, and a data clock signal, etc.

[0155] The controller 2123 can receive input image data DATA1 and a control signal CS from an external device (e.g., a graphics processor or application processor), generate a scan control signal SCS and a data control signal DCS based on the control signal CS, and convert the input image data DATA1 to generate image data DATA2. The control signal CS may include a vertical synchronization signal, a horizontal synchronization signal, and a reference clock signal, etc. The vertical synchronization signal may indicate the start of frame data (that is, data corresponding to a frame segment displaying a frame of image), and the horizontal synchronization signal may indicate the start of a data line (that is, one of multiple data lines included in the frame data). The controller 2123 can convert the input image data DATA1 into image data DATA2 with a format matching the arrangement of sub-pixels in the display unit 112. Additionally, the controller 2123 can generate a reset control signal RSTL, a readout control signal RCS, and a sensing control signal CCS based on the control signal CS.

[0156] The readout circuit 2142 can receive (or detect) sensing signals from the photosensitive pixel PSR during multiple frame periods. The controller 2123 can supply a start signal to the scan driver 2121 at a first time point after the start of a frame during some of the multiple frame periods in which the sensing signal is detected, and can supply a start signal to the scan driver 2121 at a second time point after the start of a frame during the remaining frame periods in the multiple frame periods. Here, the first time point may be different from the second time point.

[0157] In an embodiment, the second time point may be a time point shifted by a horizontal time interval compared to the first time point. In this case, the scan signal supplied during the remaining frame periods may have a different supply timing than the scan signal supplied during some frame periods.

[0158] In an embodiment, the start signal whose supply timing is controlled by controller 2123 during multiple frame periods when the sensing signal is detected may be an initialization start signal IFLM. Initialization driver 2121b may supply the second scan signal in different timings during the remaining frame periods and some frame periods in response to the initialization start signal IFLM.

[0159] The power supply unit 2124 can provide the power supply voltages VDD, VSS, VRST and VCOM required to drive the sub-pixel PXL and the photosensitive pixel PSR. Figure 5 Several types of power supply voltages, VDD, VSS, VRST, and VCOM, generated by the power supply unit 2124 are shown. The power supply unit 2124 can also generate various power supply voltages corresponding to the structure of the sub-pixel PXL and the photosensitive pixel PSR.

[0160] The first power supply voltage VDD can be a power supply used to supply drive current to the sub-pixel PXL. The second power supply voltage VSS can be a power supply used to receive drive current from the sub-pixel PXL. During the period when the sub-pixel PXL is set to an emitting state, the first power supply voltage VDD can be set to a voltage higher than the second power supply voltage VSS. The reset voltage VRST can be a voltage used to initialize the photosensitive pixel PSR. The common voltage VCOM can be a voltage supplied to the photosensitive pixel PSR.

[0161] The reset circuit 2141 can be connected to all photosensitive pixels (PSRs) provided in the display unit 112 via a common ground connection through a reset control line RSTL. The reset circuit 2141 can simultaneously provide a reset signal RST to multiple photosensitive pixels (PSRs) in response to the reset control signal RSTL. Here, the reset signal RST can be a control signal used to provide a reset voltage VRST to the photosensitive pixels (PSRs). Since the reset signal RST is provided to multiple photosensitive pixels (PSRs) simultaneously, the reset signal RST can be referred to as a global reset signal.

[0162] The readout circuit 2142 can receive sensing signals from the photosensitive pixel PSR via readout lines RX1 to RXo and perform signal processing on the sensing signals. For example, the readout circuit 2142 can perform correlated double sampling (CDS) operation to remove noise from the sensing signals provided by the photosensitive pixel PSR.

[0163] The sensing scan driver 2143 can be electrically connected to the photosensitive pixel PSR via sensing scan lines SS1, ..., SSi, ... and SSn. The sensing scan driver 2143 can generate a sensing scan signal SCAN based on the sensing control signal CCS (see...). Figure 9 The sensing scan driver 2143 provides a sensing scan signal SCAN to sensing scan lines SS1 to SSn. In other words, the sensing scan driver 2143 can select the light-sensing pixel PSR while scanning the display unit 112. The sensing scan driver 2143 can be formed together with the light-sensing pixel PSR in the display unit 112.

[0164] However, the sensing scan driver 2143 is not limited to this. For example, the sensing scan driver 2143 can be implemented as an integrated circuit. Additionally, the sensing scan lines SS1 to SSn can be replaced by scan lines S1 to Sn. For example, the sensing scan lines SS1 to SSn can be replaced by first scan lines S11 to S1n. In this case, the sensing scan driver 2143 can be omitted.

[0165] The light-sensing pixel PSR selected and driven by the sensing scan driver 2143 can output an electrical signal (i.e., a sensing signal (e.g., current or voltage)) corresponding to the detected light to the readout line. For example, the light-sensing pixel PSRik selected and driven by the i-th sensing scan line SSi can output an electrical signal corresponding to the detected light to the k-th readout line RXk.

[0166] The readout circuit 2142 can convert the analog sensing signal into a digital sensing signal (or digital value). The readout sensing signal (or digital sensing signal) can be provided as sensing data to an external device. In an embodiment, biometric authentication (e.g., fingerprint authentication) can be performed based on the sensing data.

[0167] Figure 7 It is shown Figure 5 The circuit diagram shown illustrates an embodiment of sub-pixels and light-sensing pixels. For ease of description, Figure 7 This shows the sub-pixel PXLij located in the i-th horizontal line (or the i-th sub-pixel row) and connected to the j-th data line Dj. For ease of description, Figure 7 This illustrates the photosensitive pixel PSRik, located in the i-th horizontal line (or the i-th sub-pixel row) and connected to the k-th readout line RXk. The i-th scan lines S1i to S4i may be included in... Figure 5 In the i-th scan line Si shown in the figure.

[0168] refer to Figure 7 Sub-pixel PXLij and photosensitive pixel PSRik can be disposed in the i-th horizontal line. Sub-pixel PXLij may include a light-emitting element LD and a pixel circuit PXC. In an embodiment, the pixel circuit PXC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, as well as a storage capacitor Cst.

[0169] A first transistor T1 (or driving transistor) may be connected between a first power supply line PL1 and a first electrode of a light-emitting element LD. The first transistor T1 may include a gate electrode connected to a first node N1. The first transistor T1 may control the amount of current (or driving current) flowing from the first power supply line PL1 through the light-emitting element LD to the second power supply line PL2 in response to the voltage of the first node N1. A first power supply voltage VDD may be provided to the first power supply line PL1, and a second power supply voltage VSS may be provided to the second power supply line PL2, and the first power supply voltage VDD may be set to be higher than the second power supply voltage VSS.

[0170] The second transistor T2 can be connected between the j-th data line Dj and the second node N2. The gate electrode of the second transistor T2 can be connected to the (1i)-th scan line S1i (or the first scan line). The second transistor T2 can be turned on when the first scan signal GW[i] (e.g., a low-level first scan signal GW[i]) is supplied to the (1i)-th scan line S1i to electrically connect the j-th data line Dj and the second node N2. When each of the first transistor T1 and the fourth transistor T4 is turned on, the second transistor T2 can transmit the data signal of the j-th data line Dj to the first node N1 in response to the first scan signal GW[i].

[0171] The third transistor T3 can be connected between the first node N1 and the third power supply line PL3. The gate electrode of the third transistor T3 can be connected to the (2i)th scan line S2i (or the second scan line). The first initialization power supply voltage Vint1 can be provided to the third power supply line PL3. The third transistor T3 can be turned on by the second scan signal GI[i] supplied to the (2i)th scan line S2i. When the third transistor T3 is turned on, the first initialization power supply voltage Vint1 can be supplied to the first node N1 (that is, the gate electrode of the first transistor T1).

[0172] The fourth transistor T4 can be connected between the first node N1 and the third node N3. The gate electrode of the fourth transistor T4 can be connected to the (3i) scan line S3i (or the third scan line). When the third scan signal GC[i] is supplied to the (3i) scan line S3i, the fourth transistor T4 can be turned on. When the fourth transistor T4 is turned on, the first transistor T1 can be connected in the form of a diode.

[0173] The fifth transistor T5 can be connected between the first power supply line PL1 and the second node N2. The gate electrode of the fifth transistor T5 can be connected to the i-th emission control line Ei. The sixth transistor T6 can be connected between the third node N3 and the first electrode (or anode electrode) (or the fourth node N4) of the light-emitting element LD. The gate electrode of the sixth transistor T6 can be connected to the i-th emission control line Ei. When the emission control signal EM[i] (e.g., a high-level emission control signal EM[i]) is supplied to the i-th emission control line Ei, the fifth transistor T5 and the sixth transistor T6 can be turned off, and can be turned on under other conditions.

[0174] The transmit control signal EM[i] can be supplied by a transmit driver (not shown). The transmit control signal EM[i] can be set to a gate cutoff voltage, and therefore, the transistor receiving the transmit control signal EM[i] can be turned off.

[0175] A seventh transistor T7 can be connected between the first electrode (i.e., the fourth node N4) of the light-emitting element LD and the fourth power supply line PL4. The gate electrode of the seventh transistor T7 can be connected to the (4i) scan line S4i (or the fourth scan line). A second initialization power supply voltage Vint2 can be provided to the fourth power supply line PL4. According to an embodiment, the second initialization power supply voltage Vint2 can be the same as or different from the first initialization power supply voltage Vint1. The seventh transistor T7 can be turned on by the fourth scan signal GB[i] supplied to the (4i) scan line S4i to supply the second initialization power supply voltage Vint2 to the first electrode of the light-emitting element LD.

[0176] The storage capacitor Cst can be connected or formed between the first power line PL1 and the first node N1.

[0177] The photosensitive pixel PSRik may include a sensor circuit SCa and a light receiving element LRD. The sensor circuit SCa may include a first transistor M1, a second transistor M2, and a third transistor M3. The first transistor M1 and the third transistor M3 may be connected in series between the second power supply line PL12 and the k-th readout line RXk.

[0178] A first transistor M1 (or a first sensor transistor) can be connected between a second power line PL12 (or a fifth power line) and a third transistor M3. The gate electrode of the first transistor M1 can be connected to a first node N11 (or a sensor node). The first transistor M1 can control the current flowing from the second power line PL12 through the third transistor M3 to the k-th readout line RXk in response to the voltage at the first node N11. A common voltage VCOM can be provided to the second power line PL12.

[0179] In one embodiment, the second power line PL12 may be electrically connected to or integrally formed with the fourth power line PL4, and the common voltage VCOM applied to the second power line PL12 may be equal to the second initial power supply voltage Vint2. However, this disclosure is not limited thereto. For example, the second power line PL12 may be electrically connected to or integrally formed with the third power line PL3, and the common voltage VCOM applied to the second power line PL12 may be equal to the first initial power supply voltage Vint1.

[0180] The third transistor M3 (the third sensor transistor or the switching transistor) can be connected between the first transistor M1 and the k-th readout line RXk. The gate electrode of the third transistor M3 can be connected to the sensing scan line SSi. Here, the sensing scan line SSi can be electrically connected to the (1i) scan line S1i or formed integrally with the (1i) scan line S1i.

[0181] The second transistor M2 (or the second sensor transistor) can be connected between the first power supply line PL11 (or the sixth power supply line) and the first node N11. The gate electrode of the second transistor M2 can be connected to the reset control line RSTL. The reset voltage VRST can be provided to the first power supply line PL11.

[0182] At least one optical receiver element (LRD) can be connected between the first node N11 and the second power line PL2 supplied by the second power supply voltage VSS. The optical receiver element (LRD) can generate charge (or current) based on incident light. That is, the optical receiver element (LRD) can perform photoelectric conversion. For example, the optical receiver element (LRD) can be implemented as a photodiode.

[0183] When the second transistor M2 is turned on by the reset signal RST supplied to the reset control line RSTL, the reset voltage VRST can be supplied to the first node N11. For example, the voltage of the first node N11 can be reset by the reset voltage VRST. After the reset voltage VRST is applied to the first node N11, the optical receiver element LRD can perform photoelectric conversion.

[0184] The voltage of the first node N11 can be changed due to the operation of the optical receiver element LRD. The voltage of the first node N11 (or the charge or current generated in the optical receiver element LRD) can be changed according to the intensity of the light incident on the optical receiver element LRD and the time of light incident (or the time the optical receiver element LRD is exposed to light).

[0185] When the third transistor M3 is turned on by the sensing scan signal SCAN[i] supplied to the sensing scan line SSi, the sensing signal (current and / or voltage) generated based on the voltage of the first node N11 can flow to the k-th readout line RXk.

[0186] In this embodiment, each of the pixel circuit PXC and the sensor circuit SCa may include a P-type transistor and an N-type transistor. In this embodiment, the third transistor T3 and the fourth transistor T4 of the pixel circuit PXC and the second transistor M2 of the sensor circuit SCa may be formed as oxide semiconductor transistors. For example, the third transistor T3 and the fourth transistor T4 of the pixel circuit PXC and the second transistor M2 of the sensor circuit SCa may be N-type oxide semiconductor transistors, and may include an oxide semiconductor layer as an active layer.

[0187] Oxide-semiconductor (OSB) transistors can be fabricated using low-temperature processes and exhibit lower charge mobility than polysilicon (PSB) transistors. This means OSB transistors can possess excellent cutoff current characteristics. Therefore, leakage current in the third transistor T3 and the fourth transistor T4 of the pixel circuit PXC, and the second transistor M2 of the sensor circuit SCa, can be minimized.

[0188] The remaining transistors T1, T2, T5, T6, T7, M1, and M3 can be formed as polycrystalline silicon transistors including silicon semiconductors, and can include a polycrystalline silicon semiconductor layer as an active layer. For example, the active layer can be formed using a low-temperature polycrystalline silicon (LTPS) process. For example, the polycrystalline silicon transistor can be a P-type polycrystalline silicon transistor. Due to the advantage of fast response speed, polycrystalline silicon semiconductor transistors can be used in switching elements that require fast switching.

[0189] Figure 8 This illustrates an embodiment. Figure 7 The waveform diagram of the operation process of the sub-pixels.

[0190] refer to Figure 7 and Figure 8 The transmit control signal EM[i] can be provided to the i-th transmit control line Ei, the second scan signal GI[i] can be provided to the (2i)-th scan line S2i, the third scan signal GC[i] can be provided to the (3i)-th scan line S3i, the fourth scan signal GB[i] can be provided to the (4i)-th scan line S4i, and the first scan signal GW[i] can be provided to the (1i)-th scan line S1i.

[0191] The k-th frame segment FRAME_k may include the non-transmit segment P_NE, and the non-transmit segment P_NE (or the k-th frame segment FRAME_k) may include the initialization segment P_INT, the compensation segment P_C, and the write segment P_W. The write segment P_W may be included in the compensation segment P_C.

[0192] In the non-emission segment P_NE, the emission control signal EM[i] can be high. In response to the high-level emission control signal EM[i], the fifth transistor T5 and the sixth transistor T6 can be turned off, and the sub-pixel PX can stop emitting light.

[0193] In the initialization section P_INT, the second scan signal GI[i] can be high. In response to the high level of the second scan signal GI[i], the third transistor T3 can be turned on, and the first initialization power supply voltage Vint1 of the third power supply line PL3 can be provided to the first node N1 (or the gate electrode of the first transistor T1).

[0194] Subsequently, during the compensation segment P_C, the third scan signal GC[i] can be high. In response to the high level of the third scan signal GC[i], the fourth transistor T4 can be turned on, and the first transistor T1 can be connected as a diode.

[0195] In the write segment P_W, the first scan signal GW[i] can be low. In response to the low-level first scan signal GW[i], the second transistor T2 can be turned on, and the data signal can be provided from the j-th data line Dj to the second node N2. Additionally, since the fourth transistor T4 is turned on in response to the high-level third scan signal GC[i], the data signal can be transmitted from the second node N2 to the first node N1 via the first transistor T1 and the fourth transistor T4. Since the first transistor T1 is connected as a diode through the turned-on fourth transistor T4, the voltage of the first node N1 can be a voltage compensated by the threshold voltage of the first transistor T1 from the data signal.

[0196] Before writing segment P_W, the fourth scan signal GB[i] may be low. In response to the low level of the fourth scan signal GB[i], the seventh transistor T7 may be turned on, and the second initialization power supply voltage Vint2 may be supplied to the first electrode of the light-emitting element LD. The fourth scan signal GB[i] may be the first scan signal provided to the previous row, but this disclosure is not limited thereto.

[0197] After the non-emission segment P_NE ends, the transmit control signal EM[i] can be low. In response to the low-level transmit control signal EM[i], the fifth transistor T5 and the sixth transistor T6 can be turned on, and a current path from the first power line PL1 to the second power line PL2 can be formed via the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the light-emitting element LD. Depending on the operation of the first transistor T1, a drive current responsive to the voltage (e.g., a data signal) of the first node N1 can flow through the light-emitting element LD, and the light-emitting element LD can emit light with a brightness corresponding to the drive current.

[0198] Figure 9 This illustrates an embodiment. Figure 7 The waveform diagram of the operation process of the light-sensing pixel. Figure 10 It shows based on Figure 9 The waveform diagram is a graph showing the sequence from the detection of the sensing signal by the light-sensing pixel. Figure 9 In this context, Vsync can refer to the vertical synchronization signal, and one cycle can represent a frame period. Figure 9 In this context, the SCAN signal, which is set to a low level, indicates that a sensing signal was detected during the corresponding frame period.

[0199] The reset signal RST can be provided to the reset control line RSTL (see...). Figure 7 Sensing scan signal SCAN[i] (see...) Figure 7 ) can be provided to the sensing scan line SSi (see Figure 7 Here, the sensing scan signal SCAN[i] can be the same as the first scan signal GW[i] (see...). Figure 7 The same signal.

[0200] refer to Figure 7 and Figure 9 It can detect sensing signals from the light-sensing pixel PSRik during multiple frame periods (e.g., four frame periods F1, F2, F3, and F4).

[0201] In this embodiment, the reset signal RST can be supplied to the reset control line RSTL before the sensing signal is detected from the photosensitive pixel PSRik. For example, the reset signal RST can be supplied during a frame period.

[0202] When a high-level reset signal RST is emitted from reset circuit 2141 (see...) Figure 5 When the reset control line RSTL is supplied, the second transistor M2 can be turned on. When the second transistor M2 is turned on, the reset voltage VRST can be applied to the first node N11. In this case, the voltage of the first node N11 can be reset by the reset voltage VRST.

[0203] Subsequently, during a predetermined frame time (e.g., exposure time EIT), light can be incident on the light receiving element LRD, and the voltage of the first node N11 can be changed by the photoelectric conversion function of the light receiving element LRD. After the predetermined exposure time EIT, a sensing signal can be detected from the light sensing pixel PSRik in response to the sensing scan signal SCAN during four frame periods F1 to F4.

[0204] When a low-level sensing scan signal SCAN[i] is supplied to the sensing scan line SSi, the third transistor M3 can be turned on. When the third transistor M3 is turned on, in response to the voltage of the first node N11, current (or sensing signal) can flow from the second power supply line PL12 to the k-th readout line RXk.

[0205] For example, when a user's touch input occurs in display unit 112 (see...) Figure 5 When the light reflected by the user (e.g., the user's finger) is applied, the current corresponding to the light reflected by the user can flow to the k-th readout line RXk. The current flowing to the readout line RXk can be a sensing signal, and the user's fingerprint can be detected based on the sensing signal. For example, the user's touch input can be detected based on the sensing signal.

[0206] Considering the readout circuit 2142 (see...) Figure 5 The delay allows sensing signals from the light-sensing pixel PSRik to be detected over multiple frame periods (e.g., four frame periods F1 to F4).

[0207] refer to Figure 10 During the first frame time period F1, the light-sensing pixels PSR located at some odd-numbered horizontal lines can be detected (see...). Figure 1 The sensing signal is detected. For example, during the first frame time period F1, the sensing signal can be supplied from the photosensitive pixels PSR located in the first horizontal line, the fifth horizontal line, the ninth horizontal line, the ... horizontal line to the readout circuit 2142 (see ...). Figure 5 ).

[0208] During the second frame period F2, a sensing signal can be detected from the photosensitive pixels (PSRs) located in some even-numbered horizontal lines. For example, during the second frame period F2, the sensing signal can be supplied to the readout circuit 2142 from the photosensitive pixels (PSRs) located in the second horizontal line, the sixth horizontal line, the tenth horizontal line, the... horizontal line.

[0209] During the third frame period F3, the sensing signal can be detected from the photosensitive pixels PSR located in the remaining odd-numbered horizontal lines. For example, during the third frame period F3, the sensing signal can be supplied to the readout circuit 2142 from the photosensitive pixels PSR located in the third horizontal line, the seventh horizontal line, the eleventh horizontal line, the... horizontal line.

[0210] During the fourth frame period F4, the sensing signal can be detected from the photosensitive pixels (PSRs) located in the remaining even-numbered horizontal lines. For example, during the fourth frame period F4, the sensing signal can be supplied to the readout circuit 2142 from the photosensitive pixels (PSRs) located in the fourth horizontal line, the eighth horizontal line, the twelfth horizontal line, the... horizontal line.

[0211] This process allows for the detection of display unit 112 (see...). Figure 5 Touch input (e.g., fingerprint input) on the device.

[0212] Figure 11 This is a diagram showing the second scan lines S21 to S2n / 2 according to an embodiment. Figure 12 This is a diagram showing the sensed image obtained through the sensed signal.

[0213] refer to Figure 11Each of the second scan lines S21 to S2n / 2 can be electrically connected to the sub-pixel PXL arranged in the two horizontal lines. For example, the first second scan line S21 can be electrically connected to the sub-pixel PXL located in the first horizontal line and the second horizontal line. For example, the second second scan line S22 can be electrically connected to the sub-pixel PXL located in the third horizontal line and the fourth horizontal line. For example, the (n / 2)th second scan line S2n / 2 can be electrically connected to the sub-pixel PXL located in the (n-1)th horizontal line and the nth horizontal line.

[0214] Even if each of the second scan lines S21 to S2n / 2 is connected to the sub-pixel PXL located in the two horizontal lines, the operation of each sub-pixel PXL can be compared with the reference. Figure 7 and Figure 8 The descriptions are the same, and therefore, redundant descriptions will be omitted.

[0215] For reference Figure 4 The connecting line CNL and bridging line BRL can be formed in the display unit 112 (see...). Figure 5 The connecting line CNL and the bridging line BRL can be connected to the scan lines S1 to Sn formed in the display unit 112 (see...). Figure 5 The lines partially overlap (or are positioned adjacent to scan lines S1 to Sn formed on display unit 112), which may cause signal interference due to coupling.

[0216] For example, such as Figure 12 As shown in the figure, when through Figure 9 and Figure 10 The process from light-sensing pixel PSR (see Figure 1 When generating sensing signals, it may be related to contact holes CH1 to CH4 (see...) Figure 4 Noise in the form of diagonal lines was detected in the sensed image corresponding to the shape of the image. For example, noise in the form of diagonal lines may be included in the sensed signal of the light-sensing pixel PSR located in odd-numbered horizontal lines.

[0217] Figure 13 This is a diagram illustrating the principle of noise generated from light-sensing pixels in the form of diagonal lines. Figure 13 In the diagram, time points R1, R2, R3, and R4 represent the times when the readout circuit 2142 (see...) Figure 5 The point in time when the sensing signal was detected. Figure 13 In the diagram, (1,2), (3,4), (5,6), (7,8), and (9,10) can represent the horizontal lines located by the second scan lines S21, S22, S23, S24, and S25.

[0218] refer to Figure 13The second scan signal GI[i] can be sequentially supplied to the second scan lines S21 to S25 at intervals of two horizontal time periods 2H.

[0219] The time point R1 when the sensing signal is detected in the first horizontal line can overlap with the time point when the second scan signal GI[i] is supplied to the first horizontal line (and the second horizontal line) (that is, the time point when the voltage rises from low to high). In this case, since the first and second scan lines S21 are connected to the connecting line CNL (see... Figure 4 ) and bridged connection BRL (see Figure 4 The coupling between the two signals may result in noise being included in the sensing signal.

[0220] The time point R3 when the sensing signal is detected in the third horizontal line can overlap with the time point when the second scan signal GI[i] is supplied to the third horizontal line (and the fourth horizontal line). In this case, noise may be included in the sensing signal due to the coupling between the second scan line S22 and the connecting line CNL and the bridging line BRL.

[0221] The time point R1' when the sensing signal is detected in the fifth horizontal line can overlap with the time point when the second scan signal GI[i] is supplied to the fifth horizontal line (and the sixth horizontal line). In this case, noise may be included in the sensing signal due to the coupling between the third second scan line S23 and the connecting line CNL and the bridging line BRL.

[0222] The time point R3' when the sensing signal is detected in the seventh horizontal line can overlap with the time point when the second scan signal GI[i] is supplied to the seventh horizontal line (and the eighth horizontal line). In this case, noise may be included in the sensing signal due to the coupling between the fourth second scan line S24 and the connecting line CNL and the bridging line BRL.

[0223] The time point R2 when the sensing signal is detected in the second horizontal line can not overlap with the time point when the second scan signal GI[i] is supplied to the first horizontal line (and the second horizontal line) (that is, the time point when the voltage rises from low to high). Therefore, the sensing signal detected at time point R2 may not contain noise.

[0224] The time point R4 when the sensing signal is detected in the fourth horizontal line does not overlap with the time point when the second scan signal GI[i] is supplied to the third (and fourth) horizontal lines. Therefore, the sensing signal detected at time point R4 may not contain noise.

[0225] The time point R2' when the sensing signal is detected in the sixth horizontal line can not overlap with the time point when the second scan signal GI[i] is supplied to the fifth (and sixth) horizontal lines. Therefore, the sensing signal detected at time point R2' may not contain noise.

[0226] The time point R4' when the sensing signal is detected in the eighth horizontal line does not overlap with the time point when the second scan signal GI[i] is supplied to the seventh (and eighth) horizontal lines. Therefore, the sensing signal detected at time point R4' may not contain noise.

[0227] The readout circuit 2142 can be used in the first frame time period F1 (see...) Figure 9 At time points R1 and R1', sensing signals are received from the photosensitive pixels PSR located in the first and fifth horizontal lines, respectively. The readout circuit 2142 can receive sensing signals respectively during the second frame time period F2 (see...). Figure 9 The sensor receives sensing signals from the photosensitive pixels PSR located in the second and sixth horizontal lines at time points R2 and R2', respectively. The readout circuit 2142 can receive sensing signals at the third frame time period F3 (see...). Figure 9 The sensor receives sensing signals from the photosensitive pixels PSR located in the third and seventh horizontal lines at time points R3 and R3', respectively. The readout circuit 2142 can receive sensing signals at the fourth frame time period F4 (see...). Figure 9 Sensing signals are received from the photosensitive pixels PSR located in the fourth and eighth horizontal lines at time points R4 and R4'.

[0228] As described above, the time point when the sensing signal is supplied from the photosensitive pixel PSR located in the odd-numbered horizontal lines can overlap with the time point when the second scan signal GI[i] is supplied. Therefore, as Figure 12 As shown, the sensing signal generated from the photosensitive pixels PSR located in the odd-numbered horizontal lines may include noise in the form of diagonal lines.

[0229] Figure 14 and Figure 16 This illustrates an embodiment. Figure 7 The waveform diagram of the operation process of the light-sensing pixel PSRik. Figure 15 It shows based on Figure 14 The waveform diagram is a graph of the sensed image obtained from the sensed signal from the light-sensing pixel. Figure 14 In this context, Vsync refers to the vertical synchronization signal, and one cycle represents one frame period.

[0230] refer to Figure 7 and Figure 14It can detect sensing signals from the light-sensing pixel PSRik during multiple frame periods (e.g., four frame periods F1, F2, F3, and F4).

[0231] In this embodiment, the reset signal RST can be supplied to the reset control line RSTL before the sensing signal is detected from the photosensitive pixel PSRik. For example, the reset signal RST can be supplied during a frame period.

[0232] When a high-level reset signal RST is emitted from reset circuit 2141 (see...) Figure 5 When the reset control line RSTL is supplied, the second transistor M2 can be turned on. When the second transistor M2 is turned on, the reset voltage VRST can be applied to the first node N11. In this case, the voltage of the first node N11 can be reset by the reset voltage VRST.

[0233] Subsequently, during a predetermined frame time (e.g., exposure time EIT), light can be incident on the light receiving element LRD, and the voltage of the first node N11 can be changed by the photoelectric conversion function of the light receiving element LRD. After the predetermined exposure time EIT, a sensing signal can be detected from the photosensitive pixel PSR in response to the sensing scan signal SCAN during four frame periods F1 to F4.

[0234] When a low-level sensing scan signal SCAN[i] is supplied to the sensing scan line SSi, the third transistor M3 can be turned on. When the third transistor M3 is turned on, in response to the voltage of the first node N11, current (or sensing signal) can flow from the second power supply line PL12 to the k-th readout line RXk.

[0235] For example, when a user's touch input occurs in display unit 112 (see...) Figure 5 When the light reflected by the user (e.g., the user's finger) is applied, the current corresponding to the light reflected by the user can flow to the k-th readout line RXk. The current flowing to the readout line RXk can be a sensing signal, and the user's fingerprint can be detected based on the sensing signal. For example, the user's touch input can be detected based on the sensing signal.

[0236] Taking into account the delay of the readout circuit 2142, the sensing signal from the photosensitive pixel PSRik can be detected during multiple frame periods (e.g., four frame periods F1 to F4).

[0237] In the display device DD (see Figure 1 During the period when it is normally driven, controller 2123 (see Figure 5 The initialization start signal IFLM can be supplied 20 horizontal time periods (20H) after the start of the frame. The scan driver 2121 (or initialization driver 2121b, see [link]) receives the initialization start signal IFLM. Figure 6 The second scan signal GI[i] can be generated after 20 horizontal time periods 20H, and the second scan signal GI[i] can be supplied sequentially to the second scan lines S21 to S2n / 2.

[0238] Additionally, the controller 2123 can change the timing of supplying the initialization start signal IFLM during some of the multiple frame periods in which the sensing signal is detected.

[0239] For example, during the first frame time period F1 and the third frame time period F3 when a sensing signal is detected, the initialization start signal IFLM can be supplied by shifting the time point by a horizontal time period (e.g., 1H). For example, the controller 2123 can supply the initialization start signal IFLM one horizontal time period before (earlier / preceding) the first frame time period F1 and the third frame time period F3. For example, the controller 2123 can supply the initialization start signal IFLM 19 horizontal time periods 19H from the beginning of the frame.

[0240] Additionally, during the first frame period F1 and the third frame period F3, the timing of supplying clock signals CLK1 and CLK2 can also be shifted by a horizontal period in response to the shift of the initialization start signal IFLM. For example, the controller 2123 can supply clock signals CLK1 and CLK2 one horizontal period before the first frame period F1 and the third frame period F3. In this case, the scan driver 2121 (or the initialization driver 2121b) can generate a second scan signal GI[i] one horizontal period before the first frame period F1 and the third frame period F3.

[0241] During the second frame period F2 and the fourth frame period F4, the controller 2123 may supply the initialization start signal IFLM in the same manner as during the normal operation period (that is, after 20 horizontal periods 20H from the beginning of the frame).

[0242] As described above, when the initialization start signal IFLM is supplied one horizontal time interval before the first frame time interval F1 and the third frame time interval F3, the sensed image of the sensed signal detected by the readout circuit 2142 may not include, for example, the initialization start signal IFLM. Figure 15 The noise is shown in the form of diagonal lines.

[0243] like Figure 13 and Figure 16 The readout circuit 2142 shown in the figure (see Figure 2142) Figure 5 It can maintain the time points R1, R2, R3, R4, R1', R2', R3', and R4' at constant time points when the sensed signal is detected, regardless of the initialization start signal IFLM (see [link]). Figure 14 ) shift.

[0244] refer to Figure 16 When the second scan signal GI[i] shifts by a horizontal time interval, the time point R1 may not overlap with the time point when the second scan signal GI[i] is supplied to the first horizontal line (and the second horizontal line) (that is, the time point when the voltage rises from low level to high level). Therefore, the sensing signal detected at time point R1 may not include noise.

[0245] When the second scan signal GI[i] shifts by a horizontal time interval, time point R3 may not overlap with the time point when the second scan signal GI[i] is supplied to the third horizontal line (and the fourth horizontal line). Therefore, the sensing signal detected at time point R3 may not include noise.

[0246] When the second scan signal GI[i] shifts by one horizontal time interval, time point R1' may not overlap with the time point when the second scan signal GI[i] is supplied to the fifth horizontal line (and the sixth horizontal line). Therefore, the sensing signal detected at time point R1' may not include noise.

[0247] When the second scan signal GI[i] shifts by one horizontal time interval, time point R3' may not overlap with the time point when the second scan signal GI[i] is supplied to the seventh horizontal line (and the eighth horizontal line). Therefore, the sensing signal detected at time point R3' may not include noise.

[0248] In other words, in embodiments of this disclosure, during the first frame period F1 and the third frame period F3 when the sensing signal is detected from the photosensitive pixel PSR located in the odd-numbered horizontal lines, a second scan signal GI[i] prior to a horizontal period can be supplied, thereby preventing noise in the form of diagonal lines from being included in the sensing signal.

[0249] Additionally, during the second frame period F2 and the fourth frame period F4, when the sensing signal is detected from the photosensitive pixel PSR located at even-numbered horizontal lines, the second scan signal GI[i] may not be shifted. Therefore, as referenced Figure 13 The time points R2, R4, R2' and R4' may not overlap with the time point when the second scan signal GI[i] is supplied.

[0250] Figure 17 and Figure 18 This illustrates an embodiment. Figure 7 The waveform diagram of the operation process of the light-sensing pixel PSRik.

[0251] refer to Figure 17 It can detect sensing signals from the light-sensing pixel PSRik during multiple frame periods (e.g., four frame periods F1, F2, F3, and F4).

[0252] Controller 2123 (see Figure 5 The initialization start signal IFLM may not be supplied during multiple frame periods (i.e., frame periods F1 to F4) during which the sensing signal is detected from the photosensitive pixel PSRik. The second scan signal GI[i] may not be supplied during multiple frame periods (i.e., frame periods F1 to F4), and therefore, the noise caused by the second scan signal GI[i] may not be included in the sensing signal.

[0253] However, the sub-pixel PXL can retain the data signal of the previous frame during multiple frame periods F1 to F4. Therefore, the display unit 112 can display the same image during multiple frame periods F1 to F4.

[0254] Additionally, the controller 2123 may not supply the write start signal WFLM (see [reference]) during multiple frame periods (i.e., frame periods F1 to F4) during which the sensing signal is detected from the light-sensing pixel PSRik. Figure 6 ), Compensation start signal CFLM (see Figure 6 ) and control start signal BFLM (see Figure 6 Therefore, the first scan signal GW[i], the third scan signal GC[i], and the fourth scan signal GB[i] may not be supplied during multiple frame periods (that is, frame periods F1 to F4).

[0255] like Figure 18 As shown, controller 2123 (see Figure 5 It is possible to not send signals to the scan driver 2121 (see) during multiple frame periods F1 to F4. Figure 5 (or initialize driver 2121b (see)) Figure 6 The controller 2123 supplies clock signals CLK1 and CLK2. Additionally, the controller 2123 may not supply clock signals to the scan driver 2121 (or write driver 2121a) during multiple frame periods F1 to F4. Figure 6 )), Compensation driver 2121c (see Figure 6 ) and control driver 2121d (see Figure 6 Supply clock signal CLK (see) Figure 6 Power consumption can be reduced by not supplying clock signals CLK1 and CLK2 during multiple frame periods F1 to F4.

[0256] Figure 19 This illustrates an embodiment. Figure 7 The waveform diagram of the operation process of the light-sensing pixel PSRik.

[0257] refer to Figure 19It can detect sensing signals from the light-sensing pixel PSRik during multiple frame periods (e.g., four frame periods F1, F2, F3, and F4).

[0258] Considering the readout circuit 2142 (see...) Figure 5 The delay allows sensing signals from the light-sensing pixel PSRik to be detected over multiple frame periods (e.g., four frame periods F1 to F4).

[0259] In the display device DD (see Figure 1 During the period when it is normally driven, controller 2123 (see Figure 5 The initialization start signal IFLM can be supplied 20 horizontal time periods (20H) after the start of the frame. The scan driver 2121 that receives the initialization start signal IFLM (see...) Figure 5 (or initialize driver 2121b (see)) Figure 6 The second scan signal GI[i] can be generated after 20 horizontal time periods 20H, and the second scan signal GI[i] can be supplied sequentially to the second scan lines S21 to S2n / 2.

[0260] The controller 2123 can change the timing of supplying the initialization start signal IFLM during some of the multiple frame periods when the sensing signal is detected.

[0261] For example, during the second frame period F2 and the fourth frame period F4 when the sensing signal is detected, the timing of supplying the initialization start signal IFLM can be shifted by one horizontal period. For example, the controller 2123 can supply the initialization start signal IFLM one horizontal period before the second frame period F2 and the fourth frame period F4. In this case, the controller 2123 can supply the initialization start signal IFLM 19 horizontal periods 19H from the beginning of the frame during the second frame period F2 and the fourth frame period F4.

[0262] Additionally, during the second frame period F2 and the fourth frame period F4, clock signals CLK1 and CLK2 can also be supplied by shifting the time point at which clock signals CLK1 and CLK2 are supplied by a horizontal period in response to the shift of the initialization start signal IFLM. For example, during the second frame period F2 and the fourth frame period F4, controller 2123 can supply clock signals CLK1 and CLK2 one horizontal period in advance. In this case, scan driver 2121 (or initialization driver 2121b) can generate the second scan signal GI[i] one horizontal period in advance during the second frame period F2 and the fourth frame period F4.

[0263] During the first frame period F1 and the third frame period F3, the controller 2123 may supply the initialization start signal IFLM in the same manner as during the normal operation period (that is, after 20 horizontal periods 20H from the beginning of the frame).

[0264] In embodiments of the present invention, the frame in which the initialization start signal IFLM is shifted can be changed according to the type of display device DD. For example, the controller 2123 may shift the initialization start signal IFLM by a horizontal time period during a frame period in which noise in the form of diagonal lines appears among a plurality of frames in which the sensing signal is detected.

[0265] Figure 20 This is a block diagram schematically illustrating an electronic device 1000 according to an embodiment. Figure 21 It is shown schematically. Figure 20 The diagram shows an example of an electronic device 1000 implemented as a smartphone. Figure 22 It is shown schematically. Figure 20 The diagram shows an example of an electronic device 1000 implemented as a tablet PC.

[0266] refer to Figures 20 to 22 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply unit 1050, and a display device 1060. The display device 1060 may be as follows: Figure 1 , Figure 2 and Figure 5 The display device DD is depicted in the figure. The electronic device 1000 may also include several ports capable of communicating with video cards, sound cards, memory cards, and Universal Serial Bus (USB) devices, or with other systems. In embodiments, such as... Figure 21 As shown, the electronic device 1000 can be implemented as a smartphone. In an embodiment, such as Figure 22 As shown, the electronic device 1000 can be implemented as a tablet PC. However, this is merely an example, and the electronic device 1000 is not limited to the example described above. For example, the electronic device 1000 can be implemented as a mobile phone, video phone, smart tablet, smartwatch, car navigation system, computer monitor, laptop computer, or head-mounted display device, etc.

[0267] Processor 1010 can perform specific calculations or tasks. According to embodiments, processor 1010 can be a microprocessor, a central processing unit, or an application processor, etc. Processor 1010 can be connected to other components via address buses, control buses, and data buses, etc. According to embodiments, processor 1010 can also be connected to an expansion bus, such as a peripheral component interconnect (PCI) bus.

[0268] The memory device 1020 can store data required for the operation of the electronic device 1000. For example, the memory device 1020 may include non-volatile memory devices (such as erasable programmable read-only memory (EPROM) devices, electrically erasable programmable read-only memory (EEPROM) devices, flash memory devices, phase-change random access memory (PRAM) devices, resistive random access memory (RRAM) devices, nano-floating gate memory (NFGM) devices, polymer random access memory (PoRAM) devices, magnetic random access memory (MRAM) devices, or ferroelectric random access memory (FRAM) devices) and / or volatile memory devices (such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, or mobile DRAM devices).

[0269] Storage device 1030 may include solid-state drives (SSDs), hard disk drives (HDDs), or optical disc read-only memory (CD-ROMs), etc.

[0270] Input / output device 1040 may include input devices such as a keyboard, keypad, touchpad, touchscreen, and mouse, and output devices such as a speaker and printer. According to an embodiment, display device 1060 may be included in input / output device 1040.

[0271] The power supply unit 1050 can supply the power required for the operation of the electronic device 1000. For example, the power supply unit 1050 can be a power management integrated circuit (PMIC).

[0272] The display device 1060 can display an image corresponding to the visual information of the electronic device 1000. In this case, the display device 1060 can be an organic light-emitting display device or a quantum dot light-emitting display device, but this disclosure is not limited thereto. The display device 1060 can be connected to other components via a bus or other communication link.

[0273] The display device and the method for driving the display device according to embodiments of the present disclosure can prevent noise from being included in the sensing signal by changing the timing when the scan signal is supplied during some of the multiple frame periods from which the sensing signal is detected from the light-sensing pixel.

[0274] However, the effects and features of this disclosure are not limited to those described above, and may be extended in different ways without departing from the spirit and scope of this disclosure.

[0275] As described above, embodiments of the present disclosure have been described with reference to the accompanying drawings. However, those skilled in the art will appreciate that various modifications and changes can be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A display device, wherein, The display device includes: Multiple subpixels are connected to multiple scan lines and multiple data lines; Multiple light-sensing pixels are connected to multiple sensing scan lines, multiple readout lines, and a reset control line; A scan driver supplies multiple scan signals to the multiple scan lines; and The controller supplies a start signal to the scan driver. The controller supplies the start signal at a first time point after the start of a frame during some of the multiple frame periods from which the sensing signal is detected from the plurality of light-sensing pixels, and supplies the start signal at a second time point different from the first time point after the start of the frame during the remaining frame periods.

2. The display device according to claim 1, wherein, The controller supplies the start signal at the first time point during a frame period in which the sensing signal is not detected.

3. The display device according to claim 2, wherein, The second time point is a time point that is shifted by one horizontal time period compared to the first time point.

4. The display device according to claim 3, wherein, The second time point is a time point in a horizontal time period earlier than the first time point.

5. The display device according to claim 3, wherein, In response to the shift of the start signal, the clock signal supplied to the scan driver is shifted by a horizontal time period.

6. The display device according to claim 1, wherein, Some of the frame periods are even-numbered frame periods among the plurality of frame periods, and the remaining frame periods are odd-numbered frame periods.

7. The display device according to claim 1, wherein, Some of the frame periods are odd-numbered frame periods among the plurality of frame periods, and the remaining frame periods are even-numbered frame periods.

8. The display device according to claim 1, wherein, Each of the plurality of sub-pixels includes: A light-emitting element is disposed between the first power line and the second power line; The first transistor has a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; A second transistor is connected between a data line among the plurality of data lines and the second node, and the second transistor has a gate electrode connected to a first scan line among the plurality of scan lines; and A third transistor is connected between the first node and the third power line, and the third transistor has a gate electrode connected to a second scan line among the plurality of scan lines.

9. The display device according to claim 8, wherein, The scan driver includes: Write driver, supply first scan signal to first scan line; and Initialize the driver and supply the second scan signal to the second scan line.

10. The display device according to claim 9, wherein, The start signal is supplied to the initialization driver.

11. The display device according to claim 10, wherein, The initialization driver supplies the second scan signal at different points in time during some frame periods and the remaining frame periods.

12. The display device according to claim 8, wherein, Each of the plurality of sub-pixels further includes: A fourth transistor is connected between the first node and the third node, and the fourth transistor has a gate electrode connected to a third scan line among the plurality of scan lines; A fifth transistor is connected between the first power line and the second node, and the fifth transistor has a gate electrode connected to the emitter control line; A sixth transistor is connected between the third node and the first electrode of the light-emitting element, and the sixth transistor has a gate electrode connected to the emission control line; and A seventh transistor is connected between the first electrode of the light-emitting element and the fourth power line, and the seventh transistor has a gate electrode connected to the fourth scan line among the plurality of scan lines.

13. The display device according to claim 1, wherein, Each of the plurality of light-sensing pixels includes: The first sensor transistor has a first electrode connected to a power line supplied with a common voltage and a gate electrode connected to a sensor node. A second sensor transistor is connected between the power line supplied with the reset voltage and the sensor node, and the second sensor transistor has a gate electrode connected to the reset control line. A third sensor transistor is connected between the first sensor transistor and one of the plurality of readout lines, and the third sensor transistor has a gate electrode connected to one of the plurality of sensing scan lines; and A light receiving element is connected between the sensor node and the second power line.

14. The display device according to claim 13, wherein, The display device further includes: A reset circuit supplies a reset signal to the reset control line; and The readout circuit receives the sensing signal from the plurality of readout lines.

15. The display device according to claim 14, wherein, The readout circuit: The sensing signal is received from a photosensitive pixel among the plurality of photosensitive pixels, which is positioned on some odd-numbered horizontal lines, during the first frame period of the plurality of frame periods. The sensing signal is received from a photosensitive pixel among the plurality of photosensitive pixels, which is positioned on some even-numbered horizontal lines, during the second frame period of the plurality of frame periods. The sensing signal is received from the photosensitive pixels among the plurality of photosensitive pixels, which are located on the remaining odd-numbered horizontal lines, during the third frame period of the plurality of frame periods. The sensing signal is received from the light-sensing pixels among the plurality of light-sensing pixels, which are located on the remaining even-numbered horizontal lines, during the fourth frame period of the plurality of frame periods.

16. The display device according to claim 1, wherein, The display device further includes: The substrate includes a display area and a non-display area, wherein the display area includes a first area and a second area; The multiple data lines are disposed in each of the first region and the second region; The plurality of readout lines are disposed in each of the first region and the second region, and the plurality of readout lines are spaced apart from the plurality of data lines; A connecting line extends from the first region to the second region, and the connecting line is electrically connected to the plurality of readout lines disposed in the second region; and A bridging wire extends from the second region to the first region, and the bridging wire is electrically connected to the plurality of data lines disposed in the first region.

Images