Multi-channel power distribution system and method for large-size wafer etching

Abstract

The invention belongs to the technical field of semiconductor manufacturing, and provides a multi-channel power distribution system and method for large-size wafer etching. The multichannel power distribution system for large-size wafer etching is characterized in that the multichannel power distribution system comprises a main power unit, distributed sub power units, an impedance matching and power distribution network and an etching chamber, the main power unit generates a reference radio frequency signal and distributes power to each sub power unit; each sub-power unit comprises a plurality of power amplification channels, and the power amplification channels are connected in parallel and output distributed power; the etching chamber comprises an upper electrode and / or a lower electrode, the upper electrode / the lower electrode is divided into concentric annular partitions from the center to the edge, and the partitions are connected with different power amplification channels. According to the invention, through multi-channel independent control and asymmetric power distribution facing edge compensation, the'edge attenuation 'effect can be actively and accurately corrected, and the etching uniformity of the large-size wafer is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more specifically to a multi-channel power distribution system and method for etching large-size wafers. Background Technology

[0002] As semiconductor devices develop towards higher density and smaller size, 12-inch wafers have become mainstream, while 18-inch wafers are gradually entering the mass production verification stage. In wafer etching processes, 400kHz low-frequency radio frequency power supplies are one of the core devices for etching high aspect ratio (e.g., greater than 50:1) structures because they can precisely control ion energy.

[0003] However, the radial dimensions of large-size wafers (especially 18-inch wafers) increase significantly, and traditional 400kHz RF power supplies, which use a "single-channel power output + single power divider" architecture, suffer from the following technical challenges: Power distribution edge attenuation: During the radial transmission of 400kHz RF power from a single channel on the wafer, the electromagnetic field distribution and gas flow field in the etching chamber are affected, which can easily lead to the phenomenon of "excessive power at the center and insufficient power at the edge", which cannot meet the requirements of advanced processes for etching precision. Etching steps at the junction of partitions: Some existing solutions attempt to use "multi-channel fixed power output", but the lack of precise synchronization control between channels results in a phase difference of more than ±2° for the 400kHz RF signal, which leads to obvious etching steps (height difference > 5nm) at the junction of wafer partitions, affecting the integrity of the device structure. Poor size adaptability: Traditional multi-channel systems require the replacement of hardware power dividers for different wafer sizes (12-inch / 18-inch), which not only increases equipment costs but also requires downtime for debugging (debugging time > 2 hours), reducing production efficiency; Low power conversion efficiency: The power conversion efficiency of traditional RF power supplies is usually only around 70%, which does not conform to the current development trend of green manufacturing. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a multi-channel power distribution system and method for etching large-size wafers, thereby solving the problems of etching steps and poor etching accuracy that are common in current large-size wafer etching.

[0005] In a first aspect, the present invention provides a multi-channel power distribution system for large-size wafer etching, comprising a main power unit, distributed sub-power units, an impedance matching and power distribution network, and an etching chamber. The main power unit generates a reference radio frequency signal and distributes power to each of the sub-power units; The sub-power unit includes a multi-channel radio frequency power source, which includes several power amplification channels. Each power amplification channel outputs the allocated power, and the initial power of each power amplification channel is allocated by the main power unit in relation to the etching recipe and the number of wafer size partitions. The impedance matching and power distribution network is used to achieve dynamic impedance matching and to couple the power of each power amplification channel to the etching chamber. The etching chamber includes an upper electrode and / or a lower electrode. The upper / lower electrode is divided into concentric rings from the center to the edge. Each zone is connected to a different power amplification channel, with the power amplification channel connected to the edge zone having the highest power.

[0006] As can be seen from the above technical solution, the multi-channel power distribution system provided by the present invention can actively and accurately correct the "edge attenuation" effect and improve the uniformity of large-size wafer etching by means of multi-channel independent control and edge-compensated asymmetric power distribution.

[0007] Optionally, the power distribution of the etching chamber for the uniformity of etching across the entire wafer is modeled as follows: , in, Let be the two-dimensional position vector on the wafer surface. Let be the objective functional, representing the combined cost of etching inhomogeneity and total power constraint. For position RF power density at that location For position The etching rate at that location, The average etching rate of the wafer surface. Total radio frequency power; The allocated power of each power amplification channel is obtained by minimizing the objective functional.

[0008] Optionally, the impedance matching and power distribution network includes an impedance matching network, which is based on a plasma load dynamic model and obtains the equivalent impedance through real-time solution. Achieving dynamic conjugate matching ; The equivalent impedance of the plasma load dynamic model is expressed as: Where t represents time, This is the equivalent complex impedance of the plasma. This is the equivalent resistance of the plasma. The equivalent inductance of the plasma, This is the equivalent capacitance of the plasma. With electron density Related.

[0009] Optionally, it also includes a uniformity monitoring unit, used to: obtain the etching depth of each partition of the wafer and feed it back to the main power unit; When the etching depth deviation rate is greater than a preset deviation threshold, the main power unit controls each power amplification channel of the sub-power unit to enter the power compensation stage.

[0010] Optionally, the power compensation stage employs a partitioned adaptive compensation algorithm, including: Establish a discrete optimization problem; the discrete optimization problem is as follows: The constraints are , The RF power allocated to the i-th partition, , These are the lower and upper limits of the allowed power for the i-th partition, respectively.

[0011] Optionally, the sub-power unit maintains synchronization of each power amplification channel through a synchronization calibration mechanism, including: Phase calibration: At each first preset time interval, the main power unit sends a phase calibration signal to each sub-power unit, and each sub-power unit feeds back the phase data of its local 400kHz signal to the main power unit; if the phase difference of a certain power amplification channel exceeds the second preset threshold, the main unit sends a phase compensation command. Timing synchronization: Based on phase-locked loop, the clock signal of each sub-power unit is locked to the reference clock of the main power unit; The closed-loop transfer function is , Transfer function of loop filter , , Let be the time constant of the loop filter, and s represent the complex parameter. For the gain of the phase detector, This is the gain of the voltage-controlled oscillator; Synchronized creation time , The damping coefficient is... The frequency of the system's undamped natural oscillation is denoted as .

[0012] Optionally, it also includes an energy recovery module for: The power reflected during impedance matching is rectified and fed back to the input side of the multi-channel RF power source.

[0013] Secondly, the present invention provides a multi-channel power allocation method, based on a multi-channel power allocation system provided by any possible implementation of the first aspect, comprising: S1. Load the number of partitions of the wafer size and the initial power of each power amplification channel of the sub-power unit, and control each power amplification channel to execute the initial power; the initial power of each power amplification channel is allocated by the main power unit in association with the etching recipe and the number of partitions of the wafer size; S2. The uniformity monitoring unit collects the etching depth of each partition of the wafer in real time. If the etching depth deviation rate is greater than the first preset threshold, proceed to S3; otherwise, proceed to S4. S3. Determine whether the power is insufficient or excessive, and dynamically adjust the power of each sub-power unit; S4. Calibrate the signal phase of each power amplification channel to ensure that the phase difference is less than the second preset threshold and avoid partition steps; S5. After the etching depth of each zone in the entire wafer reaches the standard and stabilizes, output the etching uniformity and step height.

[0014] By adopting the above technical solution, this application has the following beneficial effects: Significantly improved etching uniformity: By solving the power distribution optimization functional, multi-channel independent control, and edge-compensation-oriented asymmetric power allocation, the "edge attenuation" effect can be actively and accurately corrected.

[0015] Eliminating etching steps: The multi-channel synchronous calibration mechanism ensures that the phase difference between channels is less than 0.2°, significantly reducing the height difference of etching steps at the boundary of partitions and improving the structural integrity of the device. High stability: reference signal frequency drift <0.01Hz, power adjustment accuracy ±0.1W, ensuring parameter stability during long-term etching and improving yield. Based on Lyapunov function. The designed control law ensures the asymptotic stability of the power regulation process and avoids the oscillation problem that may occur in traditional PID control. Enhanced process flexibility: Different etching process formulations (such as different etching materials, gas types, and chamber pressures) have different power distribution requirements. This system can quickly adjust the power distribution through compensation algorithms, which greatly enhances the process window and flexibility. Significantly improve energy efficiency: Adopting a multi-channel Class D / E high-efficiency power amplifier architecture and combining it with a common impedance matching device to ensure that each power amplifier operates at the optimal load point, and combined with an energy recovery module, the overall power conversion efficiency (PCE) of the system can be significantly improved, meeting green manufacturing standards and reducing energy consumption and operating costs. Excellent scalability: The architecture can be easily scaled to more channels to meet the challenges of larger wafer sizes and higher uniformity requirements in the future. Attached Figure Description

[0016] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0017] Figure 1 A flowchart of a multi-channel power distribution system for large-size wafer etching provided by an embodiment of the present invention is shown; Figure 2 This shows a top view of the upper electrode partition of the etching chamber provided in an embodiment of the present invention; Figure 3 A schematic diagram of a possible power divider provided by an embodiment of the present invention is shown; Figure 4 A schematic diagram of a common impedance matching device provided in an embodiment of the present invention is shown; Figure 5 A flowchart of a multi-channel power allocation method provided by an embodiment of the present invention is shown. Detailed Implementation

[0018] The embodiments of the technical solution of the present invention will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of the present invention and are therefore merely examples, and should not be construed as limiting the scope of protection of the present invention. It should be noted that, unless otherwise stated, the technical or scientific terms used in this application should have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains.

[0019] Example 1 like Figure 1 As shown, a multi-channel power distribution system for large-size wafer etching is provided, including a main power unit, distributed sub-power units, an impedance matching and power distribution network, and an etching chamber. The main power unit generates a reference radio frequency signal and distributes power to each sub-power unit; The sub-power unit includes a multi-channel RF power source, which includes several power amplification channels. Each power amplification channel outputs the allocated power. The initial power of each power amplification channel is allocated by the main power unit in relation to the etching recipe and the number of wafer size partitions. Impedance matching and power distribution network is used to achieve dynamic impedance matching and couple the power of each power amplification channel to the etching chamber; The etching chamber includes an upper electrode and / or a lower electrode. The upper / lower electrode is divided into concentric rings from the center to the edge. Each zone is connected to a different power amplification channel, with the power amplification channel connected to the edge zone having the highest power.

[0020] Figure 2 Taking a top view of the upper electrode partition of the etching chamber as an example, the correspondence between the concentric annular partitions of the electrode and each power amplification channel is shown; the electrode is a roughly circular conductor divided into multiple concentric annular electrically isolated partitions. Specifically... Figure 2 The electrode is divided into three zones: the central zone, a circular area at the very center of the electrode; the middle zone, a ring-shaped area surrounding the central zone; and the outermost ring-shaped area. Each zone is fed by an independent power supply line. Figure 2 (Indicated by arrows) is connected to a specific output channel of the power distribution network. Crucially, the power channels driving the edge region are designed to provide maximum power output capability (e.g., ...). Figure 2 The label “Channel N (highest power)” is designed to actively compensate for “edge attenuation” caused by electromagnetic field edge effects and plasma characteristics, thereby ensuring the etching uniformity of the entire wafer surface, especially the edge region.

[0021] Depending on the power supply connection method, there are three configuration methods for upper and lower electrodes, with both upper and lower electrodes existing simultaneously; Mode 1: Lower electrode driven, upper electrode grounded (single electrode drive); Mode 2: Upper electrode driven, lower electrode grounded (single electrode drive); Mode 3: Both upper and lower electrodes are connected to RF power supply (dual electrode drive).

[0022] See Figure 1 The main power unit includes a 400kHz RF signal generator, a central controller, and a wireless synchronization main module. 400kHz RF signal generator: It adopts a combination of phase-locked loop (PLL) and oven-controlled crystal oscillator (OCXO) to ensure that the reference signal frequency drift is <0.01Hz / hour; Central Controller: Based on an FPGA chip, it stores a "zone-power" mapping database for the 12 / 18-inch wafer, receives feedback data from each sub-power unit, and outputs power adjustment commands. As the control core of the system, it receives real-time process data from the uniformity diagnostic and feedback unit within the etching process chamber and runs a built-in power distribution control algorithm. Based on the algorithm results, it sends independent control signals to the multi-channel RF power sources to precisely set the output power of each channel.

[0023] Wireless synchronization main module: adopts IEEE 802.11ad millimeter wave protocol to send synchronization clock signals to each sub-power unit (synchronization accuracy ±0.05ns).

[0024] The sub-power unit includes a multi-channel RF power source, a power detection module, and a wireless synchronization slave module, specifically: The multi-channel RF power source receives a single, stable 400kHz main RF signal from a 400kHz RF signal generator at its input. Working in conjunction with a wireless synchronization module, it ensures all channels are in phase and frequency synchronization. It includes N (N≥3) parallel power amplification channels, each comprising a digitally adjustable attenuator, a programmable gain amplifier, and a Class D / Class E high-efficiency power amplifier. Each channel independently receives control signals from the main controller, enabling precise and independent control of its own output power.

[0025] Power detection module: integrates a directional coupler and an RMS detection chip to collect the output power of the sub-unit in real time and feed it back to the central controller of the main power unit; Wireless synchronization slave module: Receives the synchronization clock signal from the main power unit and controls the phase difference between the 400kHz signal output by the sub-power unit and the reference signal to <0.2° through a phase compensation circuit.

[0026] Impedance matching and power distribution network is the core physical structure for achieving uniformity control in this embodiment. It is located downstream of the power amplification channel and coupled to the upper or lower electrode of the etching chamber.

[0027] Impedance matching and power distribution networks include power dividers and common impedance matching circuits, specifically: The power divider employs an asymmetric power distribution structure. It selectively and asymmetrically feeds power from N input channels to different regions of the electrodes through a coupling network composed of multiple inductors and capacitors. Specifically, the electrodes are designed in a concentric ring-shaped partitioned structure (e.g., central region, middle ring, outer ring, etc.), with each partition corresponding to one or more power channels. In particular, the power output upper limit of the power channels allocated to the electrode partitions at the wafer edge is designed to be higher than that of the central channels, specifically to compensate for "edge attenuation."

[0028] Figure 3 A circuit diagram of a possible power divider is shown, which is a multi-port coupled network. (Example) Figure 3 As shown, the input signals from the three power channels (P1, P2, P3) are fed to the corresponding loads—namely, the electrode sections and the plasma loads (Z) on them—through an LC network consisting of inductors (L1, L2, L3) and capacitors (C1a / / C1b, C2a / / C2b, C3a / / C3b). center Z middle Z edgeThe specific working principle is as follows: by precisely designing the component parameters of each group of inductors and capacitors, the power transfer coefficient from each input port to each output port can be controlled. For example, by optimizing the values ​​of L3 and C3a / / C3b, the power of channel P3 can be transferred to the edge region load Z more efficiently. edge Instead of being coupled to the central or intermediate region, it achieves asymmetric power distribution. This design allows the system to inject more power into the edge region than into the central region, physically overcoming "edge attenuation".

[0029] The common impedance matching circuit, using an L-type, π-type, or automatic matching network, is responsible for transforming the composite impedance of the entire electrode system (including the plasma load) to near the optimal load impedance required by each power amplifier, ensuring that all power amplifier channels can operate in the high-efficiency region. Figure 4 A schematic diagram of a matching network, taking an L-shaped model as an example, is shown.

[0030] To achieve uniform etching across the entire wafer size, this embodiment models the power distribution of uniform etching across the entire wafer size based on the etching chamber, specifically: , in, Let be the two-dimensional position vector on the wafer surface. Let be the objective functional, and let represent the combined cost of etching inhomogeneity and total power constraint. For position RF power density at that location For position The etching rate at that location, The average etching rate of the wafer surface. Total radio frequency power; The allocated power of each power amplification channel is obtained by minimizing the objective functional.

[0031] Optionally, the impedance matching and power distribution network includes an impedance matching network. The plasma load within the etching chamber is a time-varying nonlinear system, and the impedance matching network is based on a dynamic model of the plasma load, obtaining the equivalent impedance through real-time solution. Achieving dynamic conjugate matching To ensure efficient power transmission; The equivalent impedance of the plasma load dynamic model is expressed as: Where t represents time, This is the equivalent complex impedance of the plasma. This is the equivalent resistance of the plasma. The equivalent inductance of the plasma, This is the equivalent capacitance of the plasma. With electron density Related.

[0032] Optionally, the system also includes a uniformity monitoring unit for: acquiring the etching depth of each zone of the wafer, where there is a one-to-one correspondence between each zone of the wafer and the annular zones of the upper / lower electrodes, and feeding back the etching depth of each zone to the main power unit. The uniformity monitoring unit can be an OES probe, which determines the etching depth by acquiring plasma emission intensity data of each zone.

[0033] When the etching depth deviation rate of the main power unit exceeds a preset deviation threshold, it controls each power amplification channel of the sub-power unit to enter the power compensation stage. The preset deviation threshold is set empirically, for example, it can be set to 0.5%.

[0034] The power compensation stage employs a partitioned adaptive compensation algorithm, including: Establish a discrete optimization problem; the discrete optimization problem is as follows: The constraints are , The RF power allocated to the i-th partition, , These are the lower and upper limits of the allowed power for the i-th partition, respectively.

[0035] The algorithm is designed based on Lyapunov stability theory to ensure etching uniformity error. It can asymptotically converge to zero.

[0036] Optionally, the sub-power unit maintains synchronization of each power amplification channel through a synchronization calibration mechanism, including: Phase calibration: At each first preset time interval, the main power unit sends a phase calibration signal to each sub-power unit, and each sub-power unit feeds back the phase data of its local 400kHz signal to the main power unit; if the phase difference of a certain power amplification channel exceeds the second preset threshold, the main unit sends a phase compensation command. Timing synchronization: Based on phase-locked loop, the clock signal of each sub-power unit is locked to the reference clock of the main power unit; The closed-loop transfer function is , Transfer function of loop filter , , Let be the time constant of the loop filter, and s represent the complex parameter. For the gain of the phase detector, This is the gain of the voltage-controlled oscillator; Synchronized creation time , The damping coefficient is... The frequency of the system's undamped natural oscillation is denoted as .

[0037] Optionally, the system also includes an energy recovery module, which rectifies the power reflected during impedance matching and feeds it back to the power input side to improve the overall energy efficiency of the power supply.

[0038] Based on the system provided in this embodiment, the specific workflow is as follows: T1. At the start of the process, the main controller calls the preset initial power distribution parameters according to the selected process etching formula; Initial power is as follows: channel power P1 at the center, channel power P2 at the edge, and P2>P1; for an 18-inch wafer etching device, P1 can be set to 3.5kW and P2 can be set to 4.2kW ​​to form an edge-enhanced power distribution.

[0039] T2. The main power unit generates a 400kHz main signal, which is distributed to each channel. For an 18-inch wafer etching apparatus, there are 8 channels. Each power amplification channel outputs RF energy according to the initial power parameters, which is injected into the corresponding electrode partition via an asymmetric distribution network to excite plasma within the chamber. The reflected power generated during this process is recovered in real time, rectified, and fed back to the power supply bus for energy reuse.

[0040] T3. Each power amplification channel outputs a radio frequency signal of a specific power according to the initial parameters. The signal is coupled to different sections of the electrode via a power divider to excite plasma in the cavity. The reflected power is collected, rectified, and fed back to the input side of the multi-channel radio frequency power source.

[0041] T4. The uniformity monitoring unit collects etching uniformity data in real time and feeds it back to the central controller.

[0042] T5. The central controller compares the feedback data with the target value and fine-tunes the attenuators and gain amplifiers of each channel in real time through a partitioned adaptive compensation algorithm, changing the power injection of each partition until optimal etching uniformity is achieved. For example, if the feedback data is 5% lower than the target value, the power of the corresponding channel will be increased from 4.2kW ​​to 4.5kW within 200ms, while the power of 2.5kW will be slightly reduced to 3.4kW.

[0043] The technical solution based on this embodiment has at least the following technical effects: Significantly improved etching uniformity: By solving the power distribution optimization functional, multi-channel independent control, and edge-compensation-oriented asymmetric power allocation, the "edge attenuation" effect can be actively and accurately corrected.

[0044] Eliminating etching steps: The multi-channel synchronous calibration mechanism ensures that the phase difference between channels is less than 0.2°, significantly reducing the height difference of etching steps at the boundary of partitions and improving the structural integrity of the device. High stability: reference signal frequency drift <0.01Hz, power adjustment accuracy ±0.1W, ensuring parameter stability during long-term etching and improving yield. Based on Lyapunov function. The designed control law ensures the asymptotic stability of the power regulation process and avoids the oscillation problem that may occur in traditional PID control. Enhanced process flexibility: Different etching process formulations (such as different etching materials, gas types, and chamber pressures) have different power distribution requirements. This system can quickly adjust the power distribution through compensation algorithms, which greatly enhances the process window and flexibility. Significantly improve energy efficiency: Adopting a multi-channel Class D / E high-efficiency power amplifier architecture and combining it with a common impedance matching device to ensure that each power amplifier operates at the optimal load point, and combined with an energy recovery module, the overall power conversion efficiency (PCE) of the system can be significantly improved, meeting green manufacturing standards and reducing energy consumption and operating costs. Excellent scalability: The architecture can be easily scaled to more channels to meet the challenges of larger wafer sizes and higher uniformity requirements in the future.

[0045] Example 2 like Figure 5 As shown, a multi-channel power allocation method is provided, based on the multi-channel power allocation system provided in Embodiment 1, including: S1. Load the initial power of each power amplification channel of the sub-power unit and control each power amplification channel to execute the initial power; the initial power of each power amplification channel is allocated by the main power unit in association with the etching recipe and the number of wafer size partitions.

[0046] For different wafer sizes, the central controller automatically calls the corresponding "number of partitions - initial power" parameter and sends the initial power to the sub-power unit. The "number of partitions - initial power" parameter is a preset value.

[0047] Based on the power feedback of each channel corresponding to the wafer partition and the etching depth data, the output power of each power amplification channel is dynamically adjusted to counteract the edge attenuation effect. A correspondence between "partition power - etching depth" is established by combining the data detected by the power detection module of the sub-power unit.

[0048] S2. Real-time acquisition of sub-unit output power (accuracy ±0.5%). The uniformity monitoring unit acquires the etching depth of each partition of the wafer in real time and feeds it back to the central controller. If the etching depth deviation rate is greater than the first preset threshold, proceed to S3; otherwise, proceed to S4. Specifically, the etching depth deviation rate includes the deviation rate of etching depth below the target value and the deviation rate of etching depth above the target value. The first preset threshold can be determined as 0.5%.

[0049] S3. Determine if the power is insufficient or excessive, and dynamically adjust the power of each sub-power unit. Adjustment accuracy: ±0.1W.

[0050] If the deviation rate of the etching depth below the target value is greater than the first preset threshold, the power is determined to be insufficient; if the deviation rate of the etching depth above the target value is greater than the first preset threshold, the power is determined to be excessive. For partitions with insufficient power (such as the edge area of ​​a 12-inch wafer), the main power unit sends a power increase command to the corresponding sub-power unit (the specific compensation value is dynamically calculated based on the "partition-power" mapping database); for partitions with excessive power (such as the central area), a power decrease command is sent.

[0051] S4. Calibrate the signal phase of each power amplification channel to ensure that the phase difference is less than the second preset threshold and avoid phase step. The second preset threshold can be determined to be 0.2°.

[0052] S5. After the etching depth of each zone in the entire wafer reaches the standard and stabilizes, output the etching uniformity and step height.

[0053] The above embodiments are only used to provide a detailed description of the technical solutions of this application. However, the descriptions of the above embodiments are only for helping to understand the methods of the embodiments of the present invention and should not be construed as limiting the embodiments of the present invention. Variations or substitutions that can be easily conceived by those skilled in the art should be covered within the protection scope of the embodiments of the present invention.

Claims

1. A multi-channel power distribution system for large-size wafer etching, characterized in that, It includes the main power unit, distributed sub-power units, impedance matching and power distribution network, and etching chamber. The main power unit generates a reference radio frequency signal and distributes power to each of the sub-power units; The sub-power unit includes a multi-channel radio frequency power source, which includes several power amplification channels. Each power amplification channel is connected in parallel and outputs the allocated power. The initial power of each power amplification channel is allocated by the main power unit in relation to the etching recipe and the number of wafer size partitions. The impedance matching and power distribution network is used to achieve dynamic impedance matching and to couple the power of each power amplification channel to the etching chamber. The etching chamber includes an upper electrode and / or a lower electrode. The upper / lower electrode is divided into concentric rings from the center to the edge. Each zone is connected to a different power amplification channel, with the power amplification channel connected to the edge zone having the highest power.

2. The system according to claim 1, characterized in that, The power distribution of the etching chamber on the uniformity of etching across the entire wafer is modeled as follows: ， in, Let be the two-dimensional position vector on the wafer surface. Let be the objective functional, representing the combined cost of etching inhomogeneity and total power constraint. For position RF power density at that location For position The etching rate at that location, The average etching rate of the wafer surface. Total radio frequency power; The allocated power of each power amplification channel is obtained by minimizing the objective functional.

3. The system according to claim 2, characterized in that, The impedance matching and power distribution network includes an impedance matching network, which is based on a plasma load dynamic model and obtains the equivalent impedance through real-time solution. Achieving dynamic conjugate matching ; The equivalent impedance of the plasma load dynamic model is expressed as: ; Where t represents time. This is the equivalent complex impedance of the plasma. This is the equivalent resistance of the plasma. The equivalent inductance of the plasma, This is the equivalent capacitance of the plasma. With electron density Related.

4. The system according to claim 3, characterized in that, It also includes a uniformity monitoring unit, used to: obtain the etching depth of each partition of the wafer and feed it back to the main power unit; When the etching depth deviation rate is greater than a preset deviation threshold, the main power unit controls each power amplification channel of the sub-power unit to enter the power compensation stage.

5. The system according to claim 4, characterized in that, The power compensation stage employs a partitioned adaptive compensation algorithm, including: Establish a discrete optimization problem; the discrete optimization problem is as follows: The constraints are , The RF power allocated to the i-th partition, , These are the lower and upper limits of the allowed power for the i-th partition, respectively.

6. The system according to claim 1, characterized in that, The sub-power unit maintains synchronization of each power amplification channel through a synchronization calibration mechanism, including: Phase calibration: At each first preset time interval, the main power unit sends a phase calibration signal to each sub-power unit, and each sub-power unit feeds back the phase data of its local 400kHz signal to the main power unit; if the phase difference of a certain power amplification channel exceeds the second preset threshold, the main unit sends a phase compensation command. Timing synchronization: Based on phase-locked loop, the clock signal of each sub-power unit is locked to the reference clock of the main power unit; The closed-loop transfer function is , Transfer function of loop filter , , Let be the time constant of the loop filter, and s represent the complex parameter. For the gain of the phase detector, This refers to the gain of the voltage-controlled oscillator; Synchronized creation time , The damping coefficient is... The frequency of the system's undamped natural oscillation is denoted as .

7. The system according to claim 1, characterized in that, It also includes an energy recovery module for: The power reflected during impedance matching is rectified and fed back to the input side of the multi-channel RF power source.

8. A multi-channel power allocation method, characterized in that, The system based on any one of claims 1-7 includes: S1. Load the initial power of each power amplification channel of the sub-power unit and control each power amplification channel to execute the initial power; the initial power of each power amplification channel is allocated by the main power unit in relation to the etching recipe and the number of wafer size partitions; S2. The uniformity monitoring unit collects the etching depth of each partition of the wafer in real time. If the etching depth deviation rate is greater than the first preset threshold, proceed to S3; otherwise, proceed to S4. S3. Determine whether the power is insufficient or excessive, and dynamically adjust the power of each sub-power unit; S4. Calibrate the signal phase of each power amplification channel to ensure that the phase difference is less than the second preset threshold and avoid partition steps; S5. After the etching depth of each zone in the entire wafer reaches the standard and stabilizes, output the etching uniformity and step height.

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