Power grid switching operation anti-misoperation verification method and device based on real-time topology

Abstract

The invention discloses a power grid switching operation anti-misoperation verification method and device based on real-time topology, and relates to the technical field of power grid anti-misoperation, and the method comprises the following steps: collecting the phasor data of target equipment and the real-time active power flow direction of a power grid, constructing a real-time directed topological graph, and extracting a to-be-reconstructed sub-graph associated with an operation instruction of the target equipment; converting the target equipment operation instruction into an impedance correction term, constructing an estimated impedance matrix based on the to-be-reconstructed sub-graph, and calculating a corresponding power flow transfer vector; performing double-layer constraint decoupling on the topological structure of the to-be-reconstructed sub-graph to generate a source flow path chain set; and generating a verification result based on the power flow transfer vector, the source flow path chain set and a preset anti-error rule. The method is used for solving the problems of electrical rehearsal real-time lagging and complex topology anti-error logic confusion in a complex power grid environment.

Description

Technical Field

[0001] This invention relates to the field of power grid error prevention technology, and more specifically, to a method and apparatus for error prevention verification of power grid switching operations based on real-time topology. Background Technology

[0002] Switching operations are a core component of power grid operation adjustment and fault handling, and their safety is directly related to the stable operation of the power system.

[0003] Existing anti-misoperation technologies for switching operations have the following problems when operating in complex power grids: First, when simulating switching operations, it is difficult to provide real-time feedback on the voltage and current change trends after the operation, which can easily lead to electrical safety accidents due to the inability to promptly detect branch overload or voltage limit exceedance risks caused by the operation. Second, when dealing with complex topologies such as ring networks or multiple power sources, it is difficult to effectively avoid search interference caused by physical loops, and it is impossible to decouple shared physical conducting branches into independent logical power supply paths, making it difficult to construct clear and orderly source-current path relationships, thereby affecting the logical accuracy of anti-misoperation verification.

[0004] Therefore, there is an urgent need for a power grid switching operation error prevention and verification method that can take into account both electrical state prediction and power supply path logic decoupling in complex network environments. Summary of the Invention

[0005] To overcome the aforementioned deficiencies of the prior art, embodiments of the present invention provide a method and apparatus for preventing errors in power grid switching operations based on real-time topology. By rapidly calculating power flow transfer and decoupling from double-layer constraints, the method and apparatus solve the technical problems of real-time lag in electrical simulation and confusion in the parsing of error prevention logic in complex power grid environments.

[0006] To achieve the above objectives, the present invention provides the following technical solution: A method for preventing errors in power grid switching operations based on real-time topology includes the following steps: Collect phasor data of the target device and real-time active power flow of the power grid, construct a real-time directed topology graph, and extract the subgraph to be reconstructed associated with the operation commands of the target device; The target equipment operation command is converted into an impedance correction term, an estimated impedance matrix is ​​constructed based on the subgraph to be reconstructed, and the corresponding power flow transfer vector is calculated. The topology of the subgraph to be reconstructed is decoupled by two layers of constraints to generate a set of source flow path chains; Based on the power flow transfer vector, the source flow path chain set, and the preset error prevention rules, the verification result is generated.

[0007] In a preferred embodiment, the construction of the real-time directed topology graph includes: determining the source-load attributes of nodes based on the active power flow direction of the gateway nodes; constructing a set of device states using remote signaling signals from the power grid, and correcting the set of device states based on phasor data from the target device side; extracting electrical nodes based on the static model of the power grid to form a set of nodes; determining the conduction state and power flow direction of branches using the source-load attributes and the corrected set of device states, and generating a set of directed edges; and constructing a real-time directed topology graph from the set of nodes and the set of directed edges.

[0008] In a preferred embodiment, the step of extracting the subgraph to be reconstructed associated with the target device operation command includes: locating the target device and its two connected nodes in a real-time directed topology graph; taking the two connected nodes as the starting point, performing a bidirectional breadth-first search along the directed connection relationship of the branches in the topology graph until the search path reaches a node with an out-degree of zero or an electrical gateway node with a source attribute; extracting the nodes, directed edges, and associated electrical parameters within the search path to generate the subgraph to be reconstructed, wherein the electrical parameters include branch impedance parameters and branch admittance parameters.

[0009] In a preferred embodiment, the step of converting the target device operation command into an impedance correction term includes: constructing a node association vector based on the flow direction of the directed edge where the target device is located; identifying the command type of the target device operation command and determining the admittance change based on the branch impedance parameters in the subgraph to be reconstructed; and calculating the impedance correction term using a low-rank matrix update algorithm based on the node association vector and the admittance change.

[0010] In a preferred embodiment, constructing the node association vector includes: determining the dimension based on the total number of nodes in the subgraph to be reconstructed, and constructing a sparse zero initial vector; determining the inflow node and outflow node based on the flow direction of the directed edge where the target device is located; and assigning values ​​to the components corresponding to the inflow node and outflow node in the initial vector based on the node index in the subgraph to be reconstructed, thereby obtaining the node association vector.

[0011] In a preferred embodiment, the calculation of the power flow transfer vector includes: constructing the ground state admittance matrix of the subgraph to be reconstructed based on the branch admittance parameters and preset reference nodes, and superimposing an impedance correction term to obtain an estimated impedance matrix; calculating the estimated voltage components based on the estimated impedance matrix and the phasor data of the nodes in the subgraph to be reconstructed, and obtaining the estimated current values ​​in combination with the branch admittance parameters; and sorting and combining the estimated current values ​​according to a preset index order to obtain the power flow transfer vector.

[0012] In a preferred embodiment, the two-layer constraint decoupling includes: based on the subgraph to be reconstructed, starting from the source attribute gateway port node, performing a search along the directed edge direction, and removing feedback edges pointing to traversed nodes, transforming the subgraph to be reconstructed into a directed acyclic structure; and based on the directed acyclic structure, establishing a node relationship mapping table.

[0013] In a preferred embodiment, the two-layer constraint decoupling further includes: selecting nodes with an out-degree of zero as backtracking starting points in the subgraph to be reconstructed; using the node relationship mapping table as a path index to perform depth-first backtracking; and during the backtracking process, differentiating backtracking paths containing shared directed edges into independent logical paths and integrating them to generate a set of source flow path chains.

[0014] In a preferred embodiment, generating the verification result includes: superimposing the power flow transfer vector onto real-time operating data to obtain estimated electrical state quantities; comparing the estimated electrical state quantities with electrical safety thresholds in preset error prevention rules to generate electrical safety criteria; obtaining the series logical relationship of the target device in the source flow path chain set; matching the logical interlocking conditions in the preset error prevention rules based on the series logical relationship to generate logical interlocking criteria; and outputting the verification result based on the electrical safety criteria and the logical interlocking criteria.

[0015] A real-time topology-based power grid switching operation error prevention and verification device includes the following units: a graph construction unit, used to collect phasor data of the target equipment and the real-time active power flow direction of the power grid, construct a real-time directed topology graph, and extract the subgraph to be reconstructed associated with the operation command of the target equipment; a matrix deduction unit, used to convert the operation command of the target equipment into an impedance correction term, construct an estimated impedance matrix based on the subgraph to be reconstructed, and calculate the corresponding power flow transfer vector; a traversal generation unit, used to perform double-layer constraint decoupling on the topology structure of the subgraph to be reconstructed, and generate a set of source-current path chains; and a verification unit, used to generate verification results based on the power flow transfer vector, the set of source-current path chains, and preset error prevention rules.

[0016] The technical effects and advantages of the present invention, a method and device for preventing misoperation during power grid switching operations based on real-time topology, are as follows: 1. This invention improves the real-time performance of electrical state prediction for switching operations in complex power grid environments by extracting the subgraph to be reconstructed and converting the operation command into an impedance correction term, while directly calculating the power flow transfer vector using the estimated impedance matrix. This enables rapid perception of the risk of electrical values ​​exceeding limits caused by the operation.

[0017] 2. This invention employs a two-layer constraint decoupling mechanism based on graph traversal algorithms to resolve physically complex mesh topologies into a logically clear set of source-flow path chains. This avoids interference from physical loops on logical verification, achieves accurate decoupling under complex topologies, provides a reliable topological logic foundation for preventing false verification, and avoids the risk of misjudgment caused by path identification confusion. Attached Figure Description

[0018] Figure 1 This is a schematic flowchart of a power grid switching operation anti-misoperation verification method based on real-time topology, provided for an embodiment of the present invention.

[0019] Figure 2 This is a logical schematic diagram of the two-layer constraint decoupling mechanism in an embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram of the power flow transfer verification results in an embodiment of the present invention.

[0021] Figure 4 This is a schematic diagram of a power grid switching operation error prevention and verification device unit based on real-time topology, provided for an embodiment of the present invention. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0023] Example 1, Figure 1 This invention presents a method for preventing errors in power grid switching operations based on real-time topology, comprising the following steps: S1. Collect phasor data of the target device and real-time active power flow of the power grid, construct a real-time directed topology graph, and extract the subgraph to be reconstructed associated with the operation commands of the target device; In this embodiment, the construction of a real-time directed topology graph in step S1 includes: S101. Determine the source-load attributes of the nodes based on the active power flow direction of the power gateway interface nodes, as follows: By deploying SCADA (Supervisory Control and Data Acquisition) systems within substations, telemetry data of the gateway lines are collected in real time, thereby obtaining the real-time active power flow direction of the gateway gateway nodes. The gateway gateway nodes are the high-voltage side busbars or tie lines that connect the local power grid with the upper-level power grid, adjacent regional power grids, or large power plants. The source-load attribute of the gate node is determined based on the positive or negative sign of the power flow. Specifically, if the collected active power value is positive, it indicates that the power is injected into the local power grid from the outside, and the gate node is determined to have the source attribute; if the active power value is negative or zero, it indicates that the power is flowing out or is in a hot standby floating state, and it is determined to be a load node.

[0024] S102. Construct a set of equipment states using remote signaling signals from the power grid, and correct the set of equipment states based on phasor data from the target equipment side, as follows: Remote signaling signals from the power grid are collected through the data interface of the SCADA system. These remote signaling signals are digital status bits uploaded by the auxiliary contacts of primary equipment such as circuit breakers and disconnectors after their operation. Typically, 0 represents opening or disconnection, and 1 represents closing or closure. Based on the remote signaling signals, a set of device statuses is constructed. This set of device statuses is represented as a hash mapping table with the unique global ID of the device as the key and the opening / closing status as the value. The system captures the moment when the remote signaling signal of the target device undergoes a state transition (i.e., from "0" to "1" or from "1" to "0"), and extracts the timestamp recorded at that moment as a reference timestamp. A preset search range is set as the time window, centered on the reference timestamp, for example, 2 seconds before and after the reference timestamp. Within the time window, sampling is performed using a PMU (Phasor Measurement Unit) deployed on the target device side of the substation. The system retrieves the closest frame of valid PMU phasor data to the reference timestamp. The phasor data includes voltage amplitude, voltage phase angle, current amplitude, and current phase angle. Using the phasor data as the verification basis, when the remote signaling signal of the target device in the device status set shows "open", and the current amplitude on either side is greater than the preset zero drift threshold and the voltage phase difference on both sides is less than the preset equipotential threshold, then according to the physical principle of "current carrying and equipotentiality equals closure", the remote signaling signal is determined to be distorted, and the status of the device in the device status set is forcibly corrected to "closed". The zero drift threshold can be 0.1A, and the equipotential threshold can be 5 degrees. Conversely, if the remote signaling signal shows "closed", but the current amplitude on either side is less than the zero drift threshold and the voltage phase difference is greater than the equipotential threshold, then the device is determined to be actually disconnected, and its status is corrected to "open". To illustrate the above verification process more intuitively, a portion of the switching equipment in a substation is selected as an example, and the comparison of its status before and after correction is shown in Table 1. Table 1

[0025] Through the above correction steps, the logical contradictions in the source data are eliminated, ensuring that the subsequently generated ground state admittance matrix and source-current path chain set can truly reflect the physical connection structure of the power grid.

[0026] S103. Based on the static power grid model, electrical nodes are extracted to form a node set, as follows: The static power grid model is loaded by parsing the CIM (Common Information Model) file or E language format file stored in the Energy Management System (EMS) database. The static power grid model contains the unique global ID of the equipment, the topology connection relationship, and the inherent electrical parameters, including the resistance, reactance, conductance, susceptance, and ground susceptance of the lines, as well as the rated voltage level of the busbars, power gateway nodes and lines. According to the IEC 61970 topology standard, the device types associated with the connection nodes in the static power grid model through the endpoints are retrieved; if a connection node is found to be associated with three or more AC line segments and not connected to any bus segment entity through the endpoints, the connection node is determined to be a line T-connector, and the unique global ID of the connection node is used as the unique global ID of the line T-connector, and the rated voltage level of the associated AC line segment is used as the rated voltage level of the line T-connector. The line T-junction, the physical busbar in the power grid static model, and the power gateway interface node are created as graph theory node objects and stored in a node set. The node object contains a unique global ID and a rated voltage level attribute.

[0027] S104. Using the source load attributes and the corrected set of device states, determine the conduction state and power flow direction of the branch, and generate a set of directed edges, as follows: Traverse all branch elements such as lines and transformers in the static model. Based on the corrected set of equipment states, retrieve the operating status of all series-connected switching devices (including terminals at both ends and in the middle) associated with the branch. If all series-connected switching devices are in the "closed" state, the branch is determined to have electrical conduction conditions and instantiated as a conducting branch object. Otherwise, the branch is determined to be disconnected and removed. Based on the source load properties and rated voltage level, the nodal potential energy level of all nodes in the node set is defined, and the potential energy levels from high to low are as follows: Level 1 potential energy: The gateway interface node defined as a "source attribute"; Secondary potential energy: Nodes with undefined source load attributes but rated voltage levels higher than or equal to a preset main grid voltage threshold, where the main grid voltage threshold can be 110kV; Level 3 potential energy: power gateway nodes defined as "load attributes", and nodes with undefined source load attributes and rated voltage levels lower than the preset main grid voltage threshold. Based on real-time active power and nodal potential energy levels, the direction of the conducting branch is determined as follows: First, if the conducting branch is equipped with a real-time measurement device and the detected absolute value of active power is greater than the preset measurement dead zone, the direction of the directed edge is directly defined according to the positive direction of power flow. For example, if the power flows from node A to node B, the direction of the edge is from A to B. Secondly, if the conducting branch has no real-time measurement or the active power value is not greater than the measurement dead zone, the rated voltage levels of the nodes at both ends of the branch are compared, and the direction is defined as from the high potential energy level node to the low potential energy level node; for example, from the first-level potential energy node to the second-level potential energy node, or from the 110kV bus node to the 10kV bus node. Finally, if the potential energy level and rated voltage level of the nodes at both ends of the conducting branch are the same, the interconnection direction is defined according to the lexicographical order of the node's unique global ID. For example, the direction is specified as pointing from the end with the smaller ID value to the end with the larger ID value. Based on the defined directional attributes, the connected branches are encapsulated as directed edge objects with start and end nodes, ultimately forming a set of directed edges.

[0028] S105. Construct a real-time directed topology graph from the set of nodes and the set of directed edges, as follows: A real-time directed topology graph is constructed using an adjacency list approach, including allocating memory space for each node object in the node set and creating an empty linked list; Based on the set of directed edges, read the unique global IDs of the start and end nodes of the directed edges respectively; Index the directed edge object and the unique global ID of the termination node based on the unique global ID of the starting node; The adjacency list data structure, which contains all node objects and corresponding directed edge linked lists, serves as a real-time directed topology graph reflecting the current operating status of the power grid.

[0029] In this embodiment, the step S1 of extracting the sub-graph to be reconstructed associated with the target device operation command includes: S106. Locate the target device and its two connected nodes in the real-time directed topology graph, as follows: By parsing the target device's operation instructions, the unique global ID of the target device is obtained. By querying the static power grid model, the two electrical endpoints corresponding to the target device in terms of physical connection are identified, and the unique global IDs of the graph theory nodes to which these two endpoints belong are further indexed. In the adjacency list data structure of the real-time directed topology graph, the unique global ID of the two nodes is used as the hash key to locate and read the corresponding node objects and the head of the linked list, thereby locking the access position of the target device in the real-time directed topology graph and the two end nodes connected to the target device. S107. Taking the nodes connected at both ends as the starting point, perform a bidirectional breadth-first search along the directed connection relationships of the branches in the topology graph until the search path reaches a node with an out-degree of zero or a gateway interface node with source attributes, as follows: Construct a first-in-first-out search queue and push the two endpoints into the queue as the search starting point; at the same time, construct a visited set to record the IDs of the nodes that have been visited to prevent duplicate searches; Take a node from the head of the queue and read its linked list in the adjacency list; traverse all directed edge objects stored in the linked list and the IDs of the adjacent nodes they point to; if the adjacent node does not exist in the visited set, mark it as visited and push it to the tail of the search queue; repeat the above steps until the search queue is empty. During the traversal, for each search path, the search in that direction will terminate when the following two types of nodes are encountered, meaning that the downstream nodes of that node will no longer be added to the queue: If the node is defined as a first-level potential energy in S104, that is, a power gateway interface node with source attributes, then it is determined that the path has reached the power boundary, and the search of that branch will stop; if the node has an out-degree of zero in the adjacency list, that is, the linked list is empty and there are no downstream connections, then it is determined that the path has extended to the end of the network (load end), and the search of that branch will stop.

[0030] S108. Extract the nodes, directed edges, and associated electrical parameters within the search path to generate a subgraph to be reconstructed. The electrical parameters include branch impedance parameters and branch admittance parameters, as detailed below: During the search and traversal process, all visited node objects and traversed directed edge objects are collected synchronously; and the unique global ID of the directed edge object is used as an index to call the static power grid model to extract electrical parameters including resistance, reactance, conductance and susceptance. The extracted set of nodes, set of directed edges, and their complete electrical parameters are encapsulated to generate a subgraph to be reconstructed.

[0031] This step improves the efficiency of subsequent calculations by integrating multi-source measurement data with a static physical model and extracting the power grid sub-network associated with the operation commands, ensuring the real-time performance and physical authenticity of the data foundation used for error prevention verification.

[0032] S2. Convert the target equipment operation command into an impedance correction term, construct the estimated impedance matrix based on the subgraph to be reconstructed, and calculate the corresponding power flow transfer vector; In this embodiment, step S2, converting the target device operation command into an impedance correction term, includes: S201. Based on the flow direction of the directed edge containing the target device, construct the node association vector as follows: The total number of nodes in the subgraph to be reconstructed is counted and defined as the baseline dimension N; a sparse zero initial vector with dimension N×1 is constructed, in which all elements of the vector are zero in the initial state; Read the IDs of the start and end nodes in the directed edge object where the target device is located. Based on the flow direction of the node traversal order when the subgraph to be reconstructed is generated, determine the local index positions of these two nodes in the subgraph node set and mark them as the inflow node index and outflow node index, respectively. Based on the inflow node index and outflow node index, the sparse zero initial vector is assigned a value, with the component corresponding to the inflow node index in the vector assigned a value of +1 and the component corresponding to the outflow node index in the vector assigned a value of -1; thereby obtaining a node association vector that can mathematically represent the connection position of the target device in the subgraph.

[0033] S202. Identify the instruction type of the target device operation command, and determine the admittance change based on the branch impedance parameters in the subgraph to be reconstructed, as follows: By parsing the target device's operation commands, the command type can be identified: if the command type is "closing operation" (i.e., the device changes from open to closed), it means that a conducting branch has been added to the topology; if the command type is "opening operation" (i.e., the device changes from closed to open), it means that a conducting branch has been removed. It should be noted that, for switch-type devices such as circuit breakers and disconnect switches whose impedance is approximately zero in physical design, in order to avoid numerical overflow errors with zero denominator in subsequent calculations, this embodiment pre-sets a non-zero virtual minimum impedance value for them. For example, the impedance value can be 0.0001+j0.0001. In the subgraph to be reconstructed, the resistance and reactance of the branch corresponding to the target device are extracted, the original admittance value of the branch is calculated, and the admittance change is determined according to the instruction type. The formula for calculating the admittance change is as follows: , in, The change in admittance. For resistance, For reactance, The imaginary unit; This is the operation coefficient; when the instruction type is "closing operation"... When it is a "shutdown operation" .

[0034] S203. Based on the node correlation vector and the change in admittance, the impedance correction term is calculated using a low-rank matrix update algorithm, as follows: The upstream power source node of the power gateway interface node or the search starting point, which is defined as the "source attribute" in the subgraph to be reconstructed, is selected as the preset reference ground potential node to ensure the invertibility of the node admittance matrix and the convergence of the calculation. In order to ensure the invertibility of the matrix, the corresponding row and column of the reference ground potential node in the matrix are set to zero to generate a reduced-order non-singular matrix. Traverse each node in the subgraph to be reconstructed, generate an N×N ground state admittance matrix according to the Kirchhoff's Law (KCL), and set the corresponding row and column of the reference ground potential node in the matrix to 0. The forms of expression are as follows: , In the ground-state admittance matrix, the diagonal elements corresponding to the reference ground potential nodes are set to 1; the remaining diagonal elements... The formula is as follows: , , , in, Let p be the set of adjacent nodes connected to node p. For the series admittance parameters of the branch, For the node's parallel admittance to ground, For conductivity to ground, For ground susceptance; The remaining off-diagonal elements in the ground state admittance matrix The definition rules include: if there is a direct branch connection between node p and node q, then If there is no direct connection, then ; Invert the reduced ground state admittance matrix to obtain the initial impedance matrix that reflects the state before operation; Based on the mathematical properties of the low-rank matrix update algorithm (Sherman-Morrison formula), the impact of the target device (single branch) state change on the impedance matrix is ​​modeled as a "rank-1 disturbance," which is the product of the outer product of the node correlation vectors and the scalar of the admittance change; wherein, the node correlation vectors are used outer product Spatial location representing topological changes using scalars Characterizing the varying electrical strength; Based on the aforementioned "rank-1 perturbation", the impedance correction term is calculated using the following formula: , in, For N×N impedance correction terms, The initial impedance matrix, It is the transpose of the node association vector; It should be noted that this step utilizes the mathematical properties of the Sherman-Morrison formula to transform the complex operation of inverting the entire network dimension matrix into a low-order operation based on scalar denominators. This reduces computational complexity.

[0035] In this embodiment, calculating the power flow transfer vector in step S2 includes: S204. Based on the branch admittance parameters and the preset reference node, construct the ground state admittance matrix of the subgraph to be reconstructed, and superimpose the impedance correction term to obtain the estimated impedance matrix; Based on S203, the initial impedance matrix is ​​obtained by further inverting the ground state admittance matrix; the estimated impedance matrix is ​​obtained by combining the matrix correction terms with matrix addition. S205. Based on the estimated impedance matrix and the phasor data of the nodes in the subgraph to be reconstructed, calculate the estimated voltage components and, in conjunction with the branch admittance parameters, obtain the estimated current value, as follows: The retrieved valid PMU phasor data, including voltage amplitude, voltage phase angle, current amplitude, and current phase angle, are retrieved. Based on Euler's formula, the voltage amplitude and voltage phase angle are converted into branch current phasors, and the current amplitude and current phase angle are converted into voltage phasors. The conversion formulas are as follows: , in, For the transformed complex phasor, For amplitude sampling data, This is phase angle sampling data; The equivalent injection excitation source is calculated according to the type of the operation command of the target equipment: if it is a tripping operation, the equivalent injection excitation source is the opposite of the branch current vector; if it is a closing operation, the voltage phasor difference is calculated based on the voltage vectors on both sides of the target equipment, and multiplied with the series admittance parameter of the target equipment to obtain the equivalent injection excitation source.

[0036] Using the electrical distance characteristics described by the estimated impedance matrix, the equivalent injected excitation source is mapped to voltage variation components at each node. Based on Ohm's law, the current variation values ​​flowing through each non-operating branch, i.e., the estimated current values, are calculated using the voltage variation components between nodes. The specific formula is as follows: , , in, For voltage variation components, For the initial impedance matrix, To inject an equivalent source of motivation; For the first The estimated current value of the branch circuit. , For the first The indexes of the two endpoints of the branch, For the first The series admittance parameters of each branch.

[0037] S206. Based on a preset index order, sort and combine the estimated current values ​​to obtain the power flow transfer vector, as follows: The preset index order refers to the fixed traversal number assigned to each branch when generating the directed edge set; according to the index order, the calculated estimated current values ​​of each branch are sequentially filled into the array, and the final column vector is the power flow transfer vector.

[0038] It should be noted that traditional power flow prediction mechanisms typically rely on iterative solutions using the Newton-Raphson method for the entire network model. The computational complexity increases non-linearly with node size, making it difficult to meet millisecond-level response requirements when faced with real-time, high-frequency error correction requests. This invention, by using a low-rank matrix update algorithm in the subgraph to be reconstructed, reduces the reconstruction operation of the high-dimensional entire network matrix to a linear superposition of local impedance correction terms. This achieves rapid decoupling and quantitative prediction of the impact on power flow distribution, improving the online computational efficiency and real-time early warning capability of the error correction system under complex power grid topology changes.

[0039] S3. Perform two-level constraint decoupling on the topology of the subgraph to be reconstructed to generate a set of source flow path chains; In this embodiment, the double-layer constraint decoupling in S3 includes: based on the subgraph to be reconstructed, starting from the source attribute gateway interface node, performing a search along the directed edge direction, and removing feedback edges pointing to already traversed nodes, transforming the subgraph to be reconstructed into a directed acyclic structure; based on the directed acyclic structure, establishing a node relationship mapping table, as follows: Establish a node hierarchy record table to record the topology hierarchy values ​​assigned to all visited nodes; Construct a first-in-first-out search queue, push the source nodes with the potential energy level of "first-level potential energy" in the subgraph to be reconstructed into the queue, and initialize the topological level of the source nodes to 0.

[0040] Then, the loop is started, as follows: S301. Take a node from the head of the queue as the current upstream node, and retrieve all outgoing directed edges and their corresponding downstream nodes in its adjacency list; S302. For each child node, perform feedback edge verification and processing, as follows: If the downstream node does not exist in the node level record table, it is the first time it has been reached by the search path. The corresponding directed edge is determined to be a valid forward edge. The level index of the downstream node is assigned the value of "current upstream node level + 1" and recorded in the table. At the same time, the downstream node is pushed to the end of the search queue to wait for the next round of expansion. If a downstream node already exists in the node hierarchy record table, meaning it has been visited by a previous path, then read the assigned topology hierarchy value of the downstream node and make a judgment: if the topology hierarchy value of the downstream node is greater than the current upstream node hierarchy, it means that the directed edge corresponding to the downstream node is a cross-level forward edge pointing to a deeper level, and it is retained but not pushed into the queue again. If the topological level value of the downstream node is not greater than the current upstream node level, it means that the directed edge corresponding to the downstream node is a reverse edge pointing to a peer node or an upstream node, which is a feedback edge. At the same time, the feedback edge is temporarily blocked logically, i.e., it is treated as a virtual break and is not added to the set of valid edges of the subgraph to be reconstructed.

[0041] Repeat steps S301 and S302 until all nodes in the search queue have been traversed; the topology composed of all nodes in the subgraph to be reconstructed and all valid forward edges that have passed the verification is the directed acyclic structure of the subgraph to be reconstructed. Based on the aforementioned directed acyclic structure, a node relationship mapping table is established. This mapping table is a many-to-many predecessor index table, and the establishment process is as follows: During the breadth-first search process, whenever a directed edge is verified as a valid forward edge or a cross-layer forward edge, it is recorded in the node relationship mapping table: the unique global ID of the downstream node pointed to by the directed edge is used as the key, and the unique global ID of the upstream node is appended to the predecessor node list corresponding to the key; for example, if node C is powered by both node A and node B, and both power supply paths are forward edges, then the record of node C in the node relationship mapping table is {ID_C: [ID_A, ID_B]}.

[0042] In this embodiment, the double-layer constraint decoupling in S3 further includes: selecting nodes with an out-degree of zero as the backtracking starting point in the subgraph to be reconstructed; using the node relationship mapping table as the path index to perform depth-first backtracking; during the backtracking process, differentiating backtracking paths containing shared directed edges into independent logical paths and integrating them to generate a set of source flow path chains, as detailed below: Traverse the subgraph to be reconstructed, identify all nodes with an out-degree of 0 that form a terminal set; and for each terminal node in the set, call the preset recursive backtracking function. The recursive backtracking function is a path reversal tracing algorithm built on the depth-first search principle, and its specific execution logic is as follows: The function takes the current node ID and the current accumulated path stack as input parameters; on the initial call, the current node ID is the same as the end node ID, and the path stack only contains this end node; Using the current node ID as the key, query the list of upstream nodes corresponding to the current node ID in the node relationship mapping table; If the query result is empty, or the current node is a first-level potential energy node, it is determined that the backtracking has reached the power boundary. At this time, the node sequence in the current cumulative path stack is reversed, that is, adjusted to the order from source to end. Combined with the conduction branch parameters of the connection between nodes, it is encapsulated into a complete source flow path chain, stored in the result set, and the recursion of the path is terminated. If the queried predecessor node list contains one or more upstream nodes, perform a path differentiation operation: for each upstream node, clone a copy of the current cumulative path stack, push the upstream node onto the top of the copy stack, and use the upstream node as the new current node ID and the copy stack as a parameter to call the recursive backtracking function again. Through this differentiation operation, when tracing back to the intermediate node (such as the substation bus or T-junction) that serves as a common connection point, the physically shared downstream path is automatically disassembled and combined with different upstream power paths to generate logically independent power supply links. After all recursive calls to the terminal node have been executed, all generated source flow path chains are collected to form a source flow path chain set; the source flow path chain is represented as a linear full sequence list of "source attribute node → [directed edge + intermediate node] → terminal node"; like Figure 2 As shown, the left side of the figure is the local structure of the subgraph to be reconstructed, where the blue dashed lines pointing to the traversed nodes are identified as feedback edges and considered as disconnected to eliminate physical loops; the right side of the figure is the set of source flow path chains generated after depth-first backtracking and path differentiation. It can be seen that the physically shared intermediate nodes are decoupled, forming logically independent "path chain 1" and "path chain 2", thus providing a clear linear structure for subsequent logical verification.

[0043] It should be noted that traditional topology analysis mechanisms are prone to getting stuck in algorithmic infinite loops due to the presence of logical loops or low computational efficiency due to path combination explosion when faced with multi-source loop operation or complex mesh structures. This invention adopts a two-layer constraint decoupling strategy, first eliminating feedback edges to construct a directed acyclic structure, and then differentiating the complex shared mesh topology into a set of independent linear source-flow path chains. This achieves a dimensionality reduction mapping of physical topology to standardized logical links in complex power grid environments, providing a loop-free data foundation with clear causal relationships for subsequent risk sequence inference.

[0044] S4. Based on the power flow transfer vector, the source-current path chain set, and the preset error prevention rules, the verification results are generated as follows: S401. Superimpose the power flow transfer vector onto the real-time operating data to obtain the estimated electrical state variables; compare the estimated electrical state variables with the electrical safety thresholds in the preset error prevention rules to generate electrical safety criteria, as follows: Through the data interface of the SCADA system, the real-time running data of all directed edges in the subgraph to be reconstructed before the execution of the operation command is obtained. The real-time running data is represented as a column vector with the same dimension as the power flow transfer vector and includes the measured current amplitude of each directed edge. The power flow transfer vector is superimposed on the real-time running data to obtain the estimated electrical state of the power grid after the target device operation is completed. The preset anti-misoperation rules include physical safety constraints, specifically manifested as an electrical safety threshold mapping table indexed by the unique global ID of the equipment. The electrical safety threshold is obtained by reading the attribute fields in the CIM model, automatically extracting static parameters such as the rated current and thermal stability limit of each line and transformer, and correcting them in combination with the current season or ambient temperature coefficient. For example, by reading the design specifications of the B-type overhead line with branch ID A2, its preset electrical safety threshold is 600A under summer conditions and 700A under winter conditions. Iterate through each component in the estimated electrical state quantity and use the device ID to index the physical safety constraint set. Compare the estimated current value with the corresponding electrical safety threshold. If all components are not greater than the electrical safety threshold, it is determined that the power flow distribution after the operation is within the safe range, and an electrical safety criterion with the state "safe" is generated. If any component of the estimated electrical state variables exceeds the electrical safety threshold, such as Figure 3 As shown, Figure 3 The diagram shows the power flow transfer verification results before and after the operation. The diagram shows that the estimated current of line A2 is 650A, which exceeds the safety threshold of 600A. Therefore, it is determined that the operation will cause an overload risk, and an electrical safety criterion with the status of "unsafe" is generated and marked "Line A2 overloaded, estimated current is 650A".

[0045] S402. Obtain the serial logical relationship of the target device in the source flow path chain set; based on the serial logical relationship, match the logical interlocking conditions in the preset anti-misoperation rules, and generate logical interlocking criteria, as follows: Based on the unique global ID of the target device, retrieve the path chain containing the target device and locate the node position of the target device; based on the node position, obtain the front and rear adjacent topology of the target device and construct a series logical relationship containing the type of the target device; for example, if the target device is disconnector QS1, and it is identified in the path chain that its upstream is directly connected to circuit breaker CB1 and its downstream extends to the load side, then the extracted series logical relationship is expressed as: "[Upstream: Circuit breaker CB1] → [Target device: Disconnector QS1] → [Downstream: Effective load]"; Based on the device type in the series logic relationship, the logical interlock conditions are matched with the logical interlock constraint set; the logical interlock conditions are Boolean logic expressions preset based on the five-prevention regulations of the power industry standard; for example, the general interlock condition for the device type of disconnect switch is preset as: "IF (downstream has effective load) AND (upstream circuit breaker status = closed) THEN (operation is prohibited)". Using the device IDs of all associated devices identified in the series logic relationship, the corresponding real-time remote signaling data is indexed, and truth value judgment is performed in combination with the matched logical expression. For example, if the target device type is a disconnector, the detection is performed according to the series logic relationship: if the downstream of the disconnector is a node with an outgoing degree of 0, that is, there is an effective load, and the real-time remote signaling data of the upstream circuit breaker is "closed", then it is determined that the five-prevention prohibition is triggered, a logic interlock criterion with the status of "locked" is generated, and the reason for the violation is output; conversely, if the real-time remote signaling data of the upstream circuit breaker is detected as "open", or there is no effective load in the downstream path, then it is determined that the operation meets the logic interlock conditions, and a logic interlock criterion with the status of "passed" is generated.

[0046] S403. Based on the electrical safety criteria and logic interlocking criteria, output the verification result as follows: When the electrical safety criterion is "safe" and the logic interlock criterion is "passed", the final verification result of "operation allowed" is output; otherwise, the verification result of "operation prohibited" is output, and specific risk details are returned at the same time, such as "branch A1 overload" or "violation of disconnector operation logic".

[0047] Example 2, Figure 4 A real-time topology-based power grid switching operation error prevention and verification device is presented, comprising the following units: The graph construction unit is used to collect phasor data of the target device and the real-time active power flow direction of the power grid, construct a real-time directed topology graph, and extract the subgraph to be reconstructed associated with the operation commands of the target device. The matrix derivation unit is used to convert the target equipment operation command into impedance correction terms, construct the estimated impedance matrix based on the subgraph to be reconstructed, and calculate the corresponding power flow transfer vector. Traverse the generation unit to perform double-layer constraint decoupling on the topology of the subgraph to be reconstructed and generate a set of source flow path chains; The verification unit is used to generate verification results based on the power flow transfer vector, the source flow path chain set, and preset error prevention rules.

[0048] The above formulas are all dimensionless calculations. The formulas are derived from software simulations based on a large amount of collected data to obtain the most recent real-world results. The preset parameters in the formulas are set by those skilled in the art according to the actual situation.

[0049] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, in the form of a computer program product.

[0050] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0051] In addition, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module.

[0052] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0053] In conclusion, the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for preventing errors in power grid switching operations based on real-time topology, characterized in that, Includes the following steps: Collect phasor data of the target device and real-time active power flow of the power grid, construct a real-time directed topology graph, and extract the subgraph to be reconstructed associated with the operation commands of the target device; The target equipment operation command is converted into an impedance correction term, an estimated impedance matrix is ​​constructed based on the subgraph to be reconstructed, and the corresponding power flow transfer vector is calculated. The topology of the subgraph to be reconstructed is decoupled by two layers of constraints to generate a set of source flow path chains; Based on the power flow transfer vector, the source flow path chain set, and the preset error prevention rules, the verification result is generated.

2. The method for preventing misoperation of power grid switching operations based on real-time topology according to claim 1, characterized in that, The construction of the real-time directed topology graph includes: The source-load attributes of a node are determined based on the active power flow direction of the gateway node. A set of device states is constructed using remote signaling signals from the power grid, and the set of device states is corrected based on phasor data from the target device side. Electrical nodes are extracted from the static power grid model to form a node set; Using the source load attributes and the corrected set of device states, the conduction state and power flow direction of the branch are determined, and a set of directed edges is generated. A real-time directed topology graph is constructed from the set of nodes and the set of directed edges.

3. The method for preventing misoperation of power grid switching operations based on real-time topology according to claim 2, characterized in that, The extraction of the sub-graph to be reconstructed associated with the target device operation instructions includes: Locate the target device and its two connected nodes in a real-time directed topology graph; Starting from the nodes connected at both ends, perform a bidirectional breadth-first search along the directed connection relationship of the branches in the topology graph until the search path reaches a node with an out-degree of zero or a power gateway interface node with source attributes. The nodes, directed edges, and associated electrical parameters within the search path are extracted to generate a subgraph to be reconstructed. The electrical parameters include branch impedance parameters and branch admittance parameters.

4. The method for preventing misoperation of power grid switching operations based on real-time topology according to claim 3, characterized in that, The process of converting the target device operation command into an impedance correction term includes: Construct node association vectors based on the flow direction of the directed edge where the target device is located; Identify the instruction type of the target device operation command and determine the admittance change based on the branch impedance parameters in the subgraph to be reconstructed; The impedance correction term is calculated using a low-rank matrix update algorithm based on the node correlation vector and the admittance change.

5. The method for preventing misoperation of power grid switching operations based on real-time topology according to claim 4, characterized in that, The construction of the node association vector includes: The dimension is determined based on the total number of nodes in the subgraph to be reconstructed, and a sparse zero initial vector is constructed. Determine the inflow node and outflow node based on the flow direction of the directed edge where the target device is located; Based on the node indices in the subgraph to be reconstructed, the components corresponding to the inflow and outflow nodes in the initial vector are assigned values ​​to obtain the node association vector.

6. The method for preventing misoperation of power grid switching operations based on real-time topology according to claim 5, characterized in that, The calculation of the corresponding power flow transfer vector includes: Based on the branch admittance parameters and the preset reference node, the ground state admittance matrix of the subgraph to be reconstructed is constructed, and the impedance correction term is superimposed to obtain the estimated impedance matrix. Based on the estimated impedance matrix and the phasor data of the nodes in the subgraph to be reconstructed, the estimated voltage component is calculated, and the estimated current value is obtained by combining the branch admittance parameters. The estimated current values ​​are sorted and combined according to a preset index order to obtain the power flow transfer vector.

7. The method for preventing misoperation of power grid switching operations based on real-time topology as described in claim 6, characterized in that, The dual-layer constraint decoupling includes: Based on the subgraph to be reconstructed, starting from the source attribute gateway port node, a search is performed along the directed edge direction, and feedback edges pointing to traversed nodes are removed, transforming the subgraph to be reconstructed into a directed acyclic structure. Based on the aforementioned directed acyclic structure, a mapping table of relationships between nodes is established.

8. The method for preventing misoperation of power grid switching operations based on real-time topology according to claim 7, characterized in that, The dual-layer constraint decoupling also includes: In the subgraph to be reconstructed, select the node with an out-degree of zero as the backtracking starting point; The node relationship mapping table is used as a path index to perform a depth-first backtracking; During the backtracking process, backtracking paths containing shared directed edges are differentiated into independent logical paths and integrated to generate a set of source flow path chains.

9. The method for preventing misoperation of power grid switching operations based on real-time topology as described in claim 8, characterized in that, The generation of verification results includes: By superimposing the power flow transfer vector onto the real-time operating data, the estimated electrical state variables are obtained. By comparing the estimated electrical state quantities with the electrical safety thresholds in the preset error prevention rules, electrical safety criteria are generated. Obtain the serial logical relationship of the target device in the source flow path chain set; Based on the serial logical relationship, the logical interlocking conditions in the preset error prevention rules are matched to generate logical interlocking criteria; Based on electrical safety criteria and logic interlock criteria, output the verification results.

10. A power grid switching operation error prevention and verification device based on real-time topology, characterized in that, Includes the following units: The graph construction unit is used to collect phasor data of the target device and the real-time active power flow direction of the power grid, construct a real-time directed topology graph, and extract the subgraph to be reconstructed associated with the operation commands of the target device. The matrix derivation unit is used to convert the target equipment operation command into impedance correction terms, construct the estimated impedance matrix based on the subgraph to be reconstructed, and calculate the corresponding power flow transfer vector. Traverse the generation unit to perform double-layer constraint decoupling on the topology of the subgraph to be reconstructed and generate a set of source flow path chains; The verification unit is used to generate verification results based on the power flow transfer vector, the source flow path chain set, and preset error prevention rules.

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