Digital control charge pump circuit and control method of charge pump module

Abstract

The invention provides a digital control charge pump circuit and a control method of a charge pump module. The digital control charge pump circuit comprises a comparison module, a control module, a driving module, a reference module, a clock source, the charge pump module and a feedback module, the output end of the comparison module is electrically connected with the control module, the control module is electrically connected with the driving module, the charge pump module comprises N charge pump units, the driving module is electrically connected with the N charge pump units, and the N charge pump units jointly form the output end of the charge pump module and are electrically connected with the input end of the feedback module. The output end of the feedback module is electrically connected with the input end of the comparison module; the clock source is electrically connected with the control module and the driving module so as to provide clock signals for the control module and the driving module. The reference module is electrically connected with the input end of the comparison module so as to provide at least one reference voltage for the comparison module. According to the method, the LCO phenomenon can be effectively eliminated, and meanwhile, the investment cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, and in particular to a digital control charge pump circuit and a control method of a charge pump module. BACKGROUND

[0002] In an MRAM memory, in order to reduce the size of the memory cell, the bit transistor is usually designed to be small in size, but this design limits the driving current capability of the transistor.

[0003] Taking an STT-MRAM memory as an example, when the bit line voltage is zero and the source line voltage is a preset value during a write operation, the resistance of the magnetic tunnel junction (MTJ) causes the source potential of the bit transistor to rise. At this time, in order to ensure that the MTJ can obtain sufficient flipping current, the driving voltage of the word line must be increased to enhance the on ability of the bit transistor. For this purpose, the existing system usually uses a charge pump to generate a high-voltage signal output higher than the power supply voltage, and the word line driver transmits the high-voltage signal to the gate of the corresponding bit transistor according to the address signal and other control signals.

[0004] In order to ensure that the STT-MRAM memory can realize reliable read and write operations in the full power supply voltage range, the output voltage of the charge pump needs to be stabilized in the target range through closed-loop control. The traditional analog control methods, such as PWM, PFM, and On / Off control methods, all have obvious limitations. For example, the PWM control method has high implementation complexity, and the PFM and On / Off control methods will cause large output voltage ripple.

[0005] Although the existing digital control method can also be used to ensure that the output voltage of the charge pump is stabilized in the target range, it also has problems such as low system stability, large chip area, and high power consumption overhead. There are two main methods of digital control charge pump at present.

[0006] One is that the digital control charge pump controls the output voltage of the charge pump to be equal to a certain set value through negative feedback. However, the actual charge pump charge circuit has limited output resolution and has ripple, and cannot make the output voltage of the charge pump exactly stabilize at the set value, and the loop bandwidth is limited, so the output voltage of the charge pump will oscillate around a certain value, which is called limit cycle oscillation (LCO), thereby affecting the stability of the system.

[0007] The other method of digital control charge pump is to eliminate the limit cycle oscillation by reducing the output voltage ripple of the charge pump, but the corresponding control architecture needs to configure an independent comparator for each charge pump unit, which will significantly increase the chip area and chip power consumption overhead.

[0008] Therefore, finding a balance between performance and cost while ensuring that the output voltage of the charge pump remains stable within the target range has become an urgent problem to be solved. Summary of the Invention

[0009] To address the aforementioned issues, the present invention provides a digital control charge pump circuit and a control method for the charge pump module. By comparing the voltage to two voltage thresholds and adjusting the output of the charge pump unit based on the comparison result, the invention effectively eliminates the LCO phenomenon while reducing the cost of investment.

[0010] In a first aspect, the present invention provides a digitally controlled charge pump circuit, which includes: a comparison module, a control module, a drive module, a reference module, a clock source, a charge pump module, and a feedback module;

[0011] The output of the comparison module is electrically connected to the control module, the control module is electrically connected to the drive module, the charge pump module includes N charge pump units, the drive module is electrically connected to the N charge pump units, the N charge pump units together constitute the output of the charge pump module and are all electrically connected to the input of the feedback module, and the output of the feedback module is electrically connected to the input of the comparison module.

[0012] The clock source is electrically connected to the control module and the drive module respectively to provide clock signals to the control module and the drive module respectively; the reference module is electrically connected to the input terminal of the comparator module to provide at least one reference voltage to the comparator module.

[0013] The feedback module provides a feedback voltage to the comparison module. At least one reference voltage and the feedback voltage provide the comparison module with two voltage thresholds of different magnitudes and a comparison voltage. The comparison module determines the magnitude of the comparison voltage relative to the two voltage thresholds and outputs the determination result.

[0014] The control module outputs an N-bit enable digital signal and keeps the enable digital signal unchanged when the comparison voltage is within the stable range, and changes the enable digital signal when the comparison voltage is outside the stable range. The stable range is the range formed by two voltage thresholds, and the bits of the enable digital signal correspond one-to-one with the charge pump unit.

[0015] The drive module is used to regulate the output of N charge pump units according to the enable digital signal.

[0016] Optionally, the comparison module includes: a first comparator and a second comparator;

[0017] One input terminal of the first comparator and one input terminal of the second comparator are both electrically connected to the reference module. The other input terminal of the first comparator and the other input terminal of the second comparator are both electrically connected to the feedback module. The output terminal of the first comparator and the output terminal of the second comparator are both electrically connected to the control module.

[0018] The first comparator is used to determine the magnitude of the comparison voltage relative to one of the two voltage thresholds, and the second comparator is used to determine the magnitude of the comparison voltage relative to the other of the two voltage thresholds.

[0019] Optionally, the two voltage thresholds are a high threshold and a low threshold, with the high threshold being greater than the low threshold;

[0020] The first comparator is used to determine the magnitude of the comparison voltage relative to the high threshold. It outputs a low level when the comparison voltage is greater than the high threshold and outputs a high level when the comparison voltage is less than or equal to the high threshold.

[0021] The second comparator is used to determine the magnitude of the comparison voltage relative to the low threshold. It outputs a high level when the comparison voltage is greater than or equal to the low threshold and outputs a low level when the comparison voltage is less than the low threshold.

[0022] The control module is used to reduce the voltage output by the charge pump module by driving the drive module when the first comparator outputs a low level and the second comparator outputs a high level, and to increase the voltage output by the charge pump module by driving the drive module when the first comparator outputs a high level and the second comparator outputs a low level.

[0023] Optionally, the control module includes: a register set;

[0024] The control module is used to decrease the number of start identifiers stored in the register group when it receives a low level output from the first comparator and a high level output from the second comparator, and to increase the number of start identifiers stored in the register group when it receives a high level output from the first comparator and a low level output from the second comparator.

[0025] The driver module controls the number of charge pump units to be turned on based on the number of start identifiers stored in the register group, so that the number of charge pump units turned on is consistent with the number of start identifiers stored in the register group.

[0026] Optionally, the register set includes a bidirectional shift register;

[0027] The control module also includes: a first inverter, an XOR gate, and a NAND gate;

[0028] The input of the first inverter and one input of the XOR gate are both electrically connected to the output of the second comparator. The output of the first inverter is electrically connected to one input of the NAND gate. The other input of the XOR gate and the other input of the NAND gate are both electrically connected to the output of the first comparator. The output of the XOR gate and the NAND gate are respectively electrically connected to the input of the register group.

[0029] The clock source is electrically connected to the register group, and the output of the register group is electrically connected to the driver module.

[0030] Optionally, the drive module is used to convert the clock signal into a two-phase N-bit non-overlapping clock signal according to the enable digital signal. The two-phase non-overlapping clock signals are an in-phase clock signal and an out-of-phase clock signal, respectively. The bits in the in-phase clock signal correspond one-to-one with the bits in the out-of-phase clock signal, and each bit in the in-phase clock signal can change synchronously with the clock signal. The bits of the two-phase non-overlapping clock signal correspond one-to-one with the bits of the enable digital signal.

[0031] The bit of the enable digital signal is used to store the start identifier or the stop identifier;

[0032] The driver module is used to control the corresponding bit in the in-phase clock signal to change synchronously with the clock signal when the bit of the enabled digital signal stores the start flag, and to control the corresponding bit in the in-phase clock signal to stop changing synchronously with the clock signal when the bit of the enabled digital signal stores the stop flag.

[0033] The charge pump unit is used to keep the corresponding bit in the in-phase clock signal on when it changes synchronously with the clock signal, and to keep the corresponding bit in the in-phase clock signal off when it stops changing synchronously with the clock signal.

[0034] Optionally, the drive module includes: a non-overlapping clock circuit unit, a non-inverting clock signal control unit, and an inverting clock signal control unit;

[0035] The input terminal of the non-overlapping clock circuit unit is electrically connected to the clock source. The input terminal of the in-phase clock signal control unit is electrically connected to the first output terminal of the non-overlapping clock circuit unit. The input terminal of the inverting clock signal control unit is electrically connected to the second output terminal of the non-overlapping clock circuit unit. The output terminals of both the in-phase and inverting clock signal control units are electrically connected to N charge pump units. The control terminals of both the in-phase and inverting clock signal control units are electrically connected to the output terminal of the comparator module.

[0036] The non-overlapping clock circuit unit is used to convert the clock signal into an in-phase clock signal and an out-of-phase clock signal. The in-phase clock signal is transmitted to the in-phase clock signal control unit through the first output terminal, and the out-of-phase clock signal is transmitted to the out-of-phase clock signal control unit through the second output terminal.

[0037] The in-phase clock signal control unit is used to adjust the impedance state of the corresponding bit in the in-phase clock signal according to the stored content of each bit in the enable digital signal. When the corresponding bit in the enable digital signal stores the start identifier, it outputs the corresponding bit in the in-phase clock signal. When the corresponding bit in the enable digital signal stores the stop identifier, it changes the corresponding bit in the in-phase clock signal to a high impedance state.

[0038] The inverting clock signal control unit is used to adjust the impedance state of the corresponding bit in the inverting clock signal according to the stored content of each bit in the enabling digital signal. When the corresponding bit in the enabling digital signal stores the start identifier, it outputs the corresponding bit in the inverting clock signal. When the corresponding bit in the enabling digital signal stores the stop identifier, it changes the corresponding bit in the inverting clock signal to a high impedance state.

[0039] Optionally, the non-overlapping clock circuit unit includes: a second inverter, a first buffer, a first NOR gate, a second NOR gate, a first delay device, a second delay device, a second buffer, and a third buffer;

[0040] The input terminals of the second inverter and the first buffer are both electrically connected to the clock source. The output terminal of the second inverter is electrically connected to one input terminal of the first NOR gate. The output terminal of the first NOR gate is electrically connected to the input terminal of the first delay element. The output terminal of the first buffer is electrically connected to one input terminal of the second NOR gate. The output terminal of the second NOR gate is electrically connected to the input terminal of the second delay element.

[0041] The output of the first delay device is electrically connected to the input of the first buffer and the other input of the second NOR gate, respectively. The output of the second delay device is electrically connected to the input of the second buffer and the other input of the first NOR gate, respectively. The output of the first buffer is electrically connected to the input of the in-phase clock signal control unit, and the output of the second buffer is electrically connected to the input of the in-phase clock signal control unit.

[0042] Optionally, both the in-phase clock signal control unit and the out-of-phase clock signal control unit include N parallel tri-state gates;

[0043] The control terminals of the tri-state gates in both the in-phase clock signal control unit and the inverted clock signal control unit are electrically connected to the output terminals of the comparator module. The tri-state gates in the in-phase clock signal control unit correspond one-to-one with the bits of the enable digital signal, and the tri-state gates in the inverted clock signal control unit correspond one-to-one with the bits of the enable digital signal.

[0044] If the bit corresponding to the enable digital signal stores a start flag, it indicates that the enable digital signal is at a high level at the current bit; if it stores a stop flag, it indicates that the enable digital signal is at a low level at the current bit.

[0045] When the control terminal of the tri-state gate in the in-phase clock signal control unit and the inverting clock signal control unit is high, the signal at the input terminal can be transmitted to the output terminal; when the control terminal is low, the output terminal is in a high-impedance state.

[0046] The input terminals of the N tri-state gates in the in-phase clock signal control unit are electrically connected to the first output terminal, and the output terminals of the N tri-state gates in the in-phase clock signal control unit are electrically connected to the N charge pump units one-to-one.

[0047] The input terminals of the N tri-state gates in the inverting clock signal control unit are electrically connected to the second output terminal, and the output terminals of the N tri-state gates in the non-inverting clock signal control unit are electrically connected to the N charge pump units one-to-one.

[0048] In a second aspect, the present invention provides a control method for a charge pump module, the control method being applied to a digitally controlled charge pump circuit as described in any of the first aspects, the control method comprising:

[0049] Determine whether the voltage output by the charge pump module is within a predetermined range;

[0050] When the voltage output by the charge pump module is not within the predetermined range, adjust the power supply capability of the charge pump module so that the voltage output by the adjusted charge pump module is within the predetermined range.

[0051] The charge pump module maintains its power supply capability while the output voltage of the charge pump module is within a predetermined range.

[0052] The digital control charge pump circuit and charge pump module control method provided in this embodiment of the invention can stabilize the output voltage of the charge pump module within a fixed range by judging the magnitude of the comparison voltage compared with two voltage thresholds and dynamically adjusting the output of the charge pump unit based on the judgment result. This is equivalent to introducing a control dead zone into the charge pump module, thereby avoiding the occurrence of LCO phenomenon. At the same time, in the process of adjusting the output voltage of the charge pump module, only the comparison unit needs to be compared with two voltage thresholds, which reduces the complexity of the comparison module and thus reduces the power consumption and manufacturing cost of the digital control charge pump circuit. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1This is a partial schematic circuit diagram of a digitally controlled charge pump circuit according to an embodiment of this application;

[0055] Figure 2 This is a schematic circuit diagram of a control module according to an embodiment of this application;

[0056] Figure 3 This is a schematic circuit diagram of a driving module according to an embodiment of this application;

[0057] Figure 4 This is a partial schematic circuit diagram of a digitally controlled charge pump circuit according to an embodiment of this application. Detailed Implementation

[0058] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0060] It should be noted that when an element is referred to as "fixedly connected" to another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intervening element. Conversely, when an element is referred to as being "directly on" another element, there is no intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0061] It should also be understood that the terms “including / comprise” or “have” specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0062] In a first aspect, one embodiment of the present invention provides a digitally controlled charge pump circuit, see [link to previous section]. Figure 1 The digitally controlled charge pump circuit includes: a comparator module, a control module, a drive module, a reference module, a clock source, a charge pump module, and a feedback module.

[0063] The output of the comparator module is electrically connected to the control module, and the control module is electrically connected to the drive module. The charge pump module includes N charge pump units, and the drive module is electrically connected to the N charge pump units. The N charge pump units together constitute the output of the charge pump module and are all electrically connected to the input of the feedback module. The output of the feedback module is electrically connected to the input of the comparator module. Here, N is a positive integer greater than 1.

[0064] The clock source is electrically connected to the control module and the drive module respectively to provide clock signals to the control module and the drive module respectively; the reference module is electrically connected to the input terminal of the comparator module to provide at least one reference voltage to the comparator module.

[0065] The feedback module is used to provide a feedback voltage to the comparison module. At least one reference voltage and the feedback voltage provide the comparison module with two voltage thresholds of different magnitudes and a comparison voltage. The comparison module is used to determine the magnitude of the comparison voltage relative to the two voltage thresholds and output the determination result.

[0066] The control module outputs an N-bit enable digital signal. It maintains the enable digital signal unchanged when the comparison voltage is within the stable range, and changes the enable digital signal when the comparison voltage is outside the stable range. The stable range is formed by two voltage thresholds, and each bit of the enable digital signal corresponds one-to-one with a charge pump unit.

[0067] The drive module is used to regulate the output of N charge pump units according to the enable digital signal.

[0068] It is understood that the output of the charge pump module is also electrically connected to the word line driver to power the bit transistors in the MRAM memory. In this embodiment, the MRAM memory is an STT-MRAM memory, but it is not limited to this.

[0069] The digitally controlled charge pump circuit provided in this embodiment can stabilize the output voltage of the charge pump module within a fixed range by judging the magnitude of the comparison voltage compared with two voltage thresholds and dynamically adjusting the output of the charge pump unit based on the judgment result. This is equivalent to introducing a control dead zone into the charge pump module, thereby avoiding the occurrence of LCO phenomenon. At the same time, in the process of adjusting the output voltage of the charge pump module, it is only necessary to compare the comparison unit with two voltage thresholds, which reduces the complexity of the comparison module, thereby reducing the power consumption and manufacturing cost of the digitally controlled charge pump circuit.

[0070] It is understood that the two voltage thresholds can be provided by either the reference module or the feedback module. The specific values ​​of the two voltage thresholds can be set according to the specific scenario, and this embodiment does not limit this. In this embodiment, the two voltage thresholds are provided by the reference module.

[0071] Specifically, the reference module includes a first reference unit and a second reference unit; the output terminals of the first and second reference units are electrically connected to the input terminal of the comparison module, and each outputs a voltage threshold of different magnitudes. The output terminal of the feedback module is used to provide a comparison voltage to the comparison module.

[0072] It is understood that the first reference unit and the second reference unit can be circuit modules with the same structure and the same parameters of each component in the circuit module. Their input terminals are respectively connected to voltage terminals that can provide different voltages. Alternatively, they can be circuit modules with the same structure and the same voltage terminals as their input terminals, but the parameters of each component in the two are not exactly the same, so that the first reference unit and the second reference unit can output two reference voltages respectively. This embodiment does not limit the specific structure of the reference module.

[0073] For the feedback module, after receiving the total voltage VOUT output by the charge pump module, it can output a feedback signal according to a certain feedback ratio α, and use it as a reference voltage VFB1, i.e., FB1 = αVOUT. Here, α can be any positive number. When α equals 1, the feedback module can be directly regarded as its ideal connected line for transmitting the total voltage output by the charge pump module. In this embodiment, α is less than 1, such as 0.8, 0.5, 0.3, or 0.1. By limiting the value of α, the comparison module can use a smaller voltage for numerical comparison, which not only reduces the power consumption of the overall circuit but also reduces the safety risk of the overall circuit. Specifically, the feedback module can be implemented through at least one of resistor voltage division or transistor voltage division, which will not be elaborated in this embodiment.

[0074] In a further optional embodiment of this example, the comparison module includes a first comparator and a second comparator. The first comparator is also known as comparator 1, and the second comparator is also known as comparator 2.

[0075] One input terminal of the first comparator and one input terminal of the second comparator are both electrically connected to the reference module. The other input terminal of the first comparator and the other input terminal of the second comparator are both electrically connected to the feedback module. The output terminal of the first comparator and the output terminal of the second comparator are both electrically connected to the control module.

[0076] The first comparator is used to determine the magnitude of the comparison voltage relative to one of the two voltage thresholds, and the second comparator is used to determine the magnitude of the comparison voltage relative to the other of the two voltage thresholds.

[0077] In this embodiment, the output terminal of the first reference unit is electrically connected to the positive input terminal of the first comparator to provide a voltage threshold VREFH to the first comparator; the output terminal of the second reference unit is electrically connected to the negative input terminal of the second comparator to provide a voltage threshold VREFL to the second comparator; the output terminal of the feedback module is electrically connected to the negative input terminal of the first comparator and the positive input terminal of the second comparator, respectively. VREFH is greater than VREFL.

[0078] In a further optional embodiment of this embodiment, the two voltage thresholds are a high threshold VREFH and a low threshold VREFL, with the high threshold being greater than the low threshold. That is, the minimum value in the stable interval is the low threshold, and the maximum value in the stable interval is the high threshold.

[0079] The first comparator is used to determine the magnitude of the comparison voltage relative to the high threshold. It outputs a low level when the comparison voltage is greater than the high threshold and a high level when the comparison voltage is less than or equal to the high threshold.

[0080] The second comparator is used to determine the magnitude of the comparison voltage relative to the low threshold. It outputs a high level when the comparison voltage is greater than or equal to the low threshold and outputs a low level when the comparison voltage is less than the low threshold.

[0081] The control module is used to reduce the voltage output by the charge pump module by driving the drive module when the first comparator outputs a low level and the second comparator outputs a high level, and to increase the voltage output by the charge pump module by driving the drive module when the first comparator outputs a high level and the second comparator outputs a low level.

[0082] Specifically, the control module outputs an N-bit enable digital signal D[N-1:0] based on the outputs of the first and second comparators, and adjusts the N charge pump units through the drive module. Specifically, when the comparison voltage is less than a low threshold, the number of enable identifiers in the enable digital signal D[N-1:0] is increased, thereby increasing the number of charge pump units that are enabled or increasing the output power of the charge pump units, thus increasing the total output voltage of the charge pump module. When the comparison voltage is greater than a high threshold, the number of enable identifiers in D[N-1:0] is decreased, thereby decreasing the number of charge pump units that are enabled or reducing the output power of the charge pump units, thus decreasing the total output voltage of the charge pump module. When the output voltage is neither greater than the high threshold nor less than the low threshold, the number of enable identifiers in D[N-1:0] remains unchanged, thus maintaining the total output voltage of the charge pump module.

[0083] The internal circuitry of the control module can be control logic that generates shift direction signals or increment / decrement signals to change the value of the shift register or the value of the counter; the weighted form of the N-bit enable digital signal can be adjusted according to the current capability of the output charge pump unit, or it can be a one-hot code or a binary weighted code.

[0084] In this embodiment, the control module includes a register group, which includes a bidirectional shift register. The bit of the enable digital signal is used to store a start identifier or a stop identifier; each bit in the bidirectional shift register stores 1 or 0, where 1 corresponds to the start identifier (high level) and 0 corresponds to the stop identifier (low level); the enable digital signal output by the bidirectional shift register is a thermometer code.

[0085] The control module is used to reduce the number of start identifiers stored in the register group when it receives a low level output from the first comparator and a high level output from the second comparator, that is, to reduce the number of 1s stored in the register group and increase the number of 0s stored in the register group.

[0086] The control module is also used to increase the number of start identifiers stored in the register group when the first comparator outputs a high level and the second comparator outputs a low level, that is, to increase the number of 1s stored in the register group and decrease the number of 0s stored in the register group.

[0087] The driver module controls the number of charge pump units to be turned on based on the number of start identifiers stored in the register group, so that the number of charge pump units turned on is consistent with the number of start identifiers stored in the register group.

[0088] In a further optional embodiment of this example, the numerical range greater than the stable range is decomposed into multiple different overvoltage ranges, and similarly, the numerical range less than the stable range is also decomposed into multiple different undervoltage ranges.

[0089] When the judgment module determines that the comparison voltage of the current cycle is not within the stable range, it continues to determine which overvoltage or undervoltage range the comparison voltage is in, and obtains a secondary judgment result. Based on the secondary judgment result, it increases or decreases the number of start identifiers stored in the register group in the current cycle.

[0090] For example, the range of possible voltage values ​​can be divided into three overvoltage ranges, two overvoltage ranges, one overvoltage range, one voltage stabilization range, one undervoltage range, two undervoltage ranges, and three undervoltage ranges, from high to low.

[0091] When the secondary judgment result indicates that the comparison voltage is in the first-level overvoltage or undervoltage range, the number of start identifiers stored in the register group in the current cycle is decreased by 1 or increased by 1, and the number of corresponding stop identifiers is increased by 1 or decreased by 1. When the secondary judgment result indicates that the comparison voltage is in the second-level overvoltage or undervoltage range, the number of start identifiers stored in the register group in the current cycle is decreased by 2 or increased by 2, and the number of corresponding stop identifiers is increased by 2 or decreased by 2. When the secondary judgment result indicates that the comparison voltage is in the third-level overvoltage or undervoltage range, the number of start identifiers stored in the register group in the current cycle is decreased by 3 or increased by 3, and the number of corresponding stop identifiers is increased by 3 or decreased by 3.

[0092] In this embodiment, the range of values ​​that the comparison voltage may reach includes: a first-level overvoltage range, a regulated range, and a first-level undervoltage range. When the determination result is that the comparison voltage is not in the regulated range, the number of start identifiers stored in the register group in the current cycle is decreased by 1 or increased by 1, and the number of corresponding stop identifiers is increased by 1 or decreased by 1.

[0093] The specific range of the corresponding overvoltage and undervoltage ranges can be adjusted according to the specific application scenario, and this embodiment does not limit this.

[0094] In a further optional embodiment of this embodiment, combined with Figure 2 The control module also includes: a first inverter INV1, an XNOR gate, and a NAND gate.

[0095] The inputs of the first inverter and one input of the NAND gate are both electrically connected to the output of the second comparator. The output of the first inverter is electrically connected to one input of the NAND gate. The other inputs of the NAND gate and the other input of the NAND gate are both electrically connected to the output of the first comparator. The outputs of the NAND gate and the NAND gate are respectively electrically connected to the inputs of the register bank. The clock source is electrically connected to the register bank. The output of the register bank is electrically connected to the driver module.

[0096] Specifically, the signals CO1 and CO2 output from the first comparator are passed through an XOR gate to generate a hold signal HD. When the hold signal HD is high, the values ​​of each bit in the bidirectional shift register remain unchanged. When HD is low, the values ​​of each bit in the bidirectional shift register can be changed. Specifically, the inverted signals CO1 and CO2 are passed through a NAND gate to generate a direction control signal LR. When the direction control signal LR is high, the value of the bidirectional shift register shifts left and is padded with 1s in the low-order bits. When the direction control signal LR is low, the value of the bidirectional shift register shifts right and is padded with 0s in the high-order bits.

[0097] In a further optional embodiment of this example, the driving module is used to convert the clock signal into a two-phase N-bit non-overlapping clock signal according to the enable digital signal. The two non-overlapping clock signals are an in-phase clock signal and an out-of-phase clock signal; the bits in the in-phase clock signal correspond one-to-one with the bits in the out-of-phase clock signal; each bit in the in-phase clock signal can change synchronously with the clock signal; and the bits of both non-overlapping clock signals correspond one-to-one with the bits of the enable digital signal.

[0098] It's understandable that a two-phase non-overlapping clock signal can also be understood as two sets of alternating signals. Specifically, the value stored in any relative bit of the two-phase non-overlapping clock signal is different in any period. Taking the comparison voltage being in a stable range from period m to period (m+s) as an example, in period m, if the clock signal bit is high, then the level of bit x in the in-phase clock signal is high, and the level of bit x in the corresponding inverted clock signal is low; in period (m+1), if the clock signal bit is low, then the level of bit x in the in-phase clock signal is low, and the level of bit x in the corresponding inverted clock signal is high; in period (m+2), if the clock signal bit is high, then the level of bit x in the in-phase clock signal is high, and the level of bit x in the corresponding inverted clock signal is low, and so on. This is how bit x in the two-phase non-overlapping clock signal alternates with the clock signal from period m to period (m+s).

[0099] Furthermore, the driver module is used to control the corresponding bit in the in-phase clock signal to change synchronously with the clock signal when the bit of the enabled digital signal stores the start flag; and to control the corresponding bit in the in-phase clock signal to stop changing synchronously with the clock signal when the bit of the enabled digital signal stores the stop flag.

[0100] In this embodiment, the driving module converts the clock signal CLK into two-phase non-overlapping clock signals DB[N-1:0] and DBN[N-1:0] according to the enable control signal D[N-1:0] output by the control module. DB[X] and DBN[X] are one-to-one corresponding non-overlapping clock signals, controlled by D[X] in the enable control signal, where X is any integer from 0 to N-1. When D[X] is high, the corresponding DB[X] and DBN[X] can follow the clock changes, outputting non-overlapping clock signals; when D[X] is low, the corresponding DB[X] and DBN[X] do not follow the clock signal changes.

[0101] The charge pump unit is used to keep the corresponding bit in the in-phase clock signal on when it changes synchronously with the clock signal, and to keep the corresponding bit in the in-phase clock signal off when it stops changing synchronously with the clock signal.

[0102] In this embodiment, the charge pump module is used to boost the voltage between the input and output terminals of the charge pump module. The outputs of N charge pump units are connected together to form VOUT. One charge pump unit requires non-overlapping clock signals DB[N] and DBN[N], and N charge pumps require exactly 2N signals. When the drive signal is working normally, the charge pump unit can boost the voltage and output a certain current. The more charge pumps working simultaneously, the greater the output current, and vice versa.

[0103] It is understandable that each charge pump unit in the charge pump module is a non-overlapping charge pump. The charge pump unit will only start when it receives two non-overlapping signals, i.e., it will remain in the on state; otherwise, it will remain in the off state.

[0104] Specifically, when the content stored in the x-th bit of the enable digital signal changes from 1 to 0 within the m+s+1-th cycle, it means that the x-th charge pump unit needs to be turned off. At this time, the x-th bit in the in-phase clock signal and the x-th bit in the out-of-phase clock signal will both stop following the clock signal changes.

[0105] It is understandable that, in the current cycle, there are two ways in which the corresponding bit in the in-phase clock signal stops following the clock signal's changes. One is that the content stored in the corresponding bit in the current cycle remains consistent with the content stored in the previous cycle; the other is that the corresponding bit in the in-phase clock signal remains in a high-impedance state in the current cycle.

[0106] In a further optional embodiment of this embodiment, combined with Figure 3 The driving module includes: a non-overlapping clock circuit unit, a non-inverting clock signal control unit, and an inverting clock signal control unit.

[0107] The input terminal of the non-overlapping clock circuit unit is electrically connected to the clock source. The input terminal of the in-phase clock signal control unit is electrically connected to the first output terminal of the non-overlapping clock circuit unit. The input terminal of the inverting clock signal control unit is electrically connected to the second output terminal of the non-overlapping clock circuit unit. The output terminals of both the in-phase and inverting clock signal control units are electrically connected to N charge pump units. The control terminals of both the in-phase and inverting clock signal control units are electrically connected to the output terminal of the comparator module.

[0108] The non-overlapping clock circuit unit is used to convert the clock signal into an in-phase clock signal and an out-of-phase clock signal. The in-phase clock signal is transmitted to the in-phase clock signal control unit through the first output terminal, and the out-of-phase clock signal is transmitted to the out-of-phase clock signal control unit through the second output terminal.

[0109] The in-phase clock signal control unit is used to adjust the impedance state of the corresponding bit in the in-phase clock signal according to the stored content of each bit in the enable digital signal. When the corresponding bit in the enable digital signal stores the start identifier, it outputs the corresponding bit in the in-phase clock signal. When the corresponding bit in the enable digital signal stores the stop identifier, it changes the corresponding bit in the in-phase clock signal to a high impedance state.

[0110] The inverting clock signal control unit is used to adjust the impedance state of the corresponding bit in the inverting clock signal according to the stored content of each bit in the enabling digital signal. When the corresponding bit in the enabling digital signal stores the start identifier, it outputs the corresponding bit in the inverting clock signal. When the corresponding bit in the enabling digital signal stores the stop identifier, it changes the corresponding bit in the inverting clock signal to a high impedance state.

[0111] Among them, the non-overlapping clock circuit unit receives the clock signal CLK, and after conversion, outputs two-phase non-overlapping clocks PH1 and PH2.

[0112] Combination Figure 3 The non-overlapping clock circuit unit includes: a second inverter INV2, a first buffer BUFFER1, a first NOR gate NOR1, a second NOR gate NOR2, a first delay device, a second delay device, a second buffer BUFFER2, and a third buffer BUFFER3.

[0113] The input terminals of the second inverter and the first buffer are both electrically connected to the clock source. The output terminal of the second inverter is electrically connected to one input terminal of the first NOR gate. The output terminal of the first NOR gate is electrically connected to the input terminal of the first delay element. The output terminal of the first buffer is electrically connected to one input terminal of the second NOR gate. The output terminal of the second NOR gate is electrically connected to the input terminal of the second delay element.

[0114] The output of the first delay device is electrically connected to the input of the first buffer and the other input of the second NOR gate, respectively. The output of the second delay device is electrically connected to the input of the second buffer and the other input of the first NOR gate, respectively. The output of the first buffer is electrically connected to the input of the in-phase clock signal control unit, and the output of the second buffer is electrically connected to the input of the in-phase clock signal control unit.

[0115] In this embodiment, both the first delay device and the second delay device are used to extend the signal transmission time, and the extension time of the two devices is equal. The specific structure of the first delay device and the second delay device is not limited in this embodiment.

[0116] In a further optional embodiment of this embodiment, both the in-phase clock signal control unit and the out-of-phase clock signal control unit include N parallel tri-state gates TGATE;

[0117] The control terminals of the tri-state gates in both the in-phase and inverted clock signal control units are electrically connected to the output terminals of the comparator module. The tri-state gates in the in-phase clock signal control unit correspond one-to-one with the bits of the enable digital signal, and the tri-state gates in the inverted clock signal control unit also correspond one-to-one with the bits of the enable digital signal.

[0118] If the bit corresponding to the enable digital signal stores a start flag, it indicates that the enable digital signal is at a high level at the current bit. If the bit corresponding to the enable digital signal stores a stop flag, it indicates that the enable digital signal is at a low level at the current bit.

[0119] In the in-phase clock signal control unit and the inverting clock signal control unit, when the control terminal is high, the signal at the input terminal can be transmitted to the output terminal, that is, the signal received at the input terminal is A, and the signal output at the output terminal is also A; when the control terminal is low, the output terminal is in a high impedance state.

[0120] The input terminals of the N tri-state gates in the in-phase clock signal control unit are electrically connected to the first output terminal, and the output terminals of the N tri-state gates in the in-phase clock signal control unit are electrically connected to the N charge pump units one-to-one.

[0121] The input terminals of the N tri-state gates in the inverting clock signal control unit are electrically connected to the second output terminal, and the output terminals of the N tri-state gates in the non-inverting clock signal control unit are electrically connected to the N charge pump units one-to-one.

[0122] By using tri-state gates to construct the in-phase clock signal control unit and the in-phase clock signal control unit, the complexity of the structure of the in-phase clock signal control unit and the in-phase clock signal control unit can be effectively reduced, thereby reducing the manufacturing cost of the digital control charge pump circuit.

[0123] The digitally controlled charge pump circuit provided in this embodiment has a simple structure and effectively solves the limiting cycle oscillation problem existing in charge pumps implemented by digital control, thereby reducing output voltage ripple. Furthermore, this digitally controlled charge pump circuit uses digital control, making it more adaptable to advanced integrated circuit process nodes.

[0124] Secondly, an embodiment of the present invention provides another digitally controlled charge pump circuit, which differs from the digitally controlled charge pump circuit in the first aspect in that it combines... Figure 4In this embodiment, the feedback module includes: a first feedback unit and a second feedback unit; the first feedback unit and the second feedback unit are electrically connected to the output terminal of the charge pump module and the input terminal of the judgment module, respectively; the first feedback unit is used to output the unit output by the charge pump module to the judgment module according to a first ratio, and the second feedback unit is used to output the unit output by the charge pump module to the judgment module according to a second ratio, wherein the first ratio and the second ratio are different; the reference module is used to provide a reference voltage to the comparison module.

[0125] Thirdly, an embodiment of the present invention provides a control method for a charge pump module. The control method is applied to a digitally controlled charge pump circuit as described in the first or second aspect. The control method includes: determining whether the voltage output by the charge pump module is within a predetermined range using a judgment module; adjusting the power supply capability of the charge pump module using a control module and a drive module when the voltage output by the charge pump module is not within the predetermined range, so that the voltage output by the adjusted charge pump module is within the predetermined range; and maintaining the power supply capability of the charge pump module when the voltage output by the charge pump module is within the predetermined range.

[0126] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0127] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0128] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A digitally controlled charge pump circuit, characterized in that, The digitally controlled charge pump circuit includes: a comparator module, a control module, a drive module, a reference module, a clock source, a charge pump module, and a feedback module; The output terminal of the comparison module is electrically connected to the control module, the control module is electrically connected to the drive module, the charge pump module includes N charge pump units, the drive module is electrically connected to the N charge pump units, the N charge pump units together constitute the output terminal of the charge pump module and are all electrically connected to the input terminal of the feedback module, and the output terminal of the feedback module is electrically connected to the input terminal of the comparison module. The clock source is electrically connected to the control module and the drive module respectively to provide clock signals to the control module and the drive module respectively; the reference module is electrically connected to the input terminal of the comparison module to provide at least one reference voltage to the comparison module. The feedback module is used to provide a feedback voltage to the comparison module. The at least one reference voltage and the feedback voltage provide the comparison module with two voltage thresholds of different magnitudes and a comparison voltage. The comparison module is used to determine the magnitude of the comparison voltage compared to the two voltage thresholds and output the determination result. The control module is used to output an N-bit enable digital signal, and keeps the enable digital signal unchanged when the comparison voltage is within the stable range, and changes the enable digital signal when the comparison voltage is not within the stable range; the stable range is the range formed by the two voltage thresholds, and the bits of the enable digital signal correspond one-to-one with the charge pump unit; The drive module is used to regulate the output of N charge pump units according to the enable digital signal.

2. The circuit according to claim 1, characterized in that, The comparison module includes: a first comparator and a second comparator; One input terminal of the first comparator and one input terminal of the second comparator are both electrically connected to the reference module, the other input terminal of the first comparator and the other input terminal of the second comparator are both electrically connected to the feedback module, and the output terminal of the first comparator and the output terminal of the second comparator are both electrically connected to the control module. The first comparator is used to determine the magnitude of the comparison voltage relative to one of the two voltage thresholds, and the second comparator is used to determine the magnitude of the comparison voltage relative to the other of the two voltage thresholds.

3. The circuit according to claim 2, characterized in that, The two voltage thresholds are a high threshold and a low threshold, wherein the high threshold is greater than the low threshold; The first comparator is used to determine the magnitude of the comparison voltage relative to the high threshold, and outputs a low level when the comparison voltage is greater than the high threshold, and outputs a high level when the comparison voltage is less than or equal to the high threshold; The second comparator is used to determine the magnitude of the comparison voltage relative to the low threshold, and outputs a high level when the comparison voltage is greater than or equal to the low threshold, and outputs a low level when the comparison voltage is less than the low threshold; The control module is used to reduce the voltage output by the charge pump module through the driving module when the first comparator outputs a low level and the second comparator outputs a high level, and to increase the voltage output by the charge pump module through the driving module when the first comparator outputs a high level and the second comparator outputs a low level.

4. The circuit according to claim 2, characterized in that, The control module includes: a register group; The control module is used to decrease the number of start identifiers stored in the register group when it receives a low level output from the first comparator and a high level output from the second comparator, and to increase the number of start identifiers stored in the register group when it receives a high level output from the first comparator and a low level output from the second comparator. The driving module is used to control the number of charge pump units turned on according to the number of start identifiers stored in the register group, so that the number of charge pump units turned on is consistent with the number of start identifiers stored in the register group.

5. The circuit according to claim 4, characterized in that, The register group includes a bidirectional shift register; The control module further includes: a first inverter, an XOR gate, and a NAND gate; The input terminal of the first inverter and one input terminal of the XNOR gate are both electrically connected to the output terminal of the second comparator. The output terminal of the first inverter is electrically connected to one input terminal of the NAND gate. The other input terminals of the XNOR gate and the NAND gate are both electrically connected to the output terminal of the first comparator. The output terminals of the XNOR gate and the NAND gate are respectively electrically connected to the input terminals of the register group. The clock source is electrically connected to the register group, and the output of the register group is electrically connected to the driver module.

6. The circuit according to claim 1, characterized in that, The driving module is used to convert the clock signal into a two-phase N-bit non-overlapping clock signal according to the enable digital signal. The two phases of the non-overlapping clock signal are an in-phase clock signal and an out-of-phase clock signal, respectively. The bits in the in-phase clock signal correspond one-to-one with the bits in the out-of-phase clock signal, and each bit in the in-phase clock signal can change synchronously with the clock signal. The bits of the two phases of the non-overlapping clock signal correspond one-to-one with the bits of the enable digital signal. The bits of the enable digital signal are used to store a start identifier or a stop identifier; The driving module is used to control the corresponding bit in the in-phase clock signal to change synchronously with the clock signal when the bit of the enable digital signal stores the start flag, and to control the corresponding bit in the in-phase clock signal to stop changing synchronously with the clock signal when the bit of the enable digital signal stores the stop flag. The charge pump unit is configured to remain in an on state when the corresponding bit in the in-phase clock signal changes synchronously with the clock signal, and to remain in a off state when the corresponding bit in the in-phase clock signal stops changing synchronously with the clock signal.

7. The circuit according to claim 6, characterized in that, The driving module includes: a non-overlapping clock circuit unit, a non-in-phase clock signal control unit, and an inverted clock signal control unit; The input terminal of the non-overlapping clock circuit unit is electrically connected to the clock source. The input terminal of the in-phase clock signal control unit is electrically connected to the first output terminal of the non-overlapping clock circuit unit. The input terminal of the inverting clock signal control unit is electrically connected to the second output terminal of the non-overlapping clock circuit unit. The output terminals of both the in-phase and inverting clock signal control units are electrically connected to N charge pump units. The control terminals of both the in-phase and inverting clock signal control units are electrically connected to the output terminal of the comparison module. The non-overlapping clock circuit unit is used to convert the clock signal into an in-phase clock signal and an out-of-phase clock signal, and transmits the in-phase clock signal to the in-phase clock signal control unit through the first output terminal, and transmits the out-of-phase clock signal to the out-of-phase clock signal control unit through the second output terminal. The in-phase clock signal control unit is used to adjust the impedance state of the corresponding bit in the in-phase clock signal according to the stored content of each bit in the enable digital signal. When the corresponding bit in the enable digital signal stores a start identifier, it outputs the corresponding bit in the in-phase clock signal. When the corresponding bit in the enable digital signal stores a stop identifier, it changes the corresponding bit in the in-phase clock signal to a high impedance state. The inverting clock signal control unit is used to adjust the impedance state of the corresponding bit in the inverting clock signal according to the stored content of each bit in the enabling digital signal. When the corresponding bit in the enabling digital signal stores a start identifier, it outputs the corresponding bit in the inverting clock signal. When the corresponding bit in the enabling digital signal stores a stop identifier, it changes the corresponding bit in the inverting clock signal to a high impedance state.

8. The circuit according to claim 7, characterized in that, The non-overlapping clock circuit unit includes: a second inverter, a first buffer, a first NOR gate, a second NOR gate, a first delay device, a second delay device, a second buffer, and a third buffer; The input terminals of the second inverter and the first buffer are both electrically connected to the clock source. The output terminal of the second inverter is electrically connected to one input terminal of the first NOR gate. The output terminal of the first NOR gate is electrically connected to the input terminal of the first delay element. The output terminal of the first buffer is electrically connected to one input terminal of the second NOR gate. The output terminal of the second NOR gate is electrically connected to the input terminal of the second delay element. The output terminal of the first delay device is electrically connected to the input terminal of the first buffer and the other input terminal of the second NOR gate device, respectively. The output terminal of the second delay device is electrically connected to the input terminal of the second buffer and the other input terminal of the first NOR gate device, respectively. The output terminal of the first buffer is electrically connected to the input terminal of the in-phase clock signal control unit, and the output terminal of the second buffer is electrically connected to the input terminal of the in-phase clock signal control unit.

9. The circuit according to claim 7, characterized in that, Both the in-phase clock signal control unit and the inverted clock signal control unit include N parallel tri-state gates; The control terminals of the tri-state gates in the in-phase clock signal control unit and the in-phase clock signal control unit are electrically connected to the output terminal of the comparison module. The tri-state gates in the in-phase clock signal control unit correspond one-to-one with the bits of the enable digital signal, and the tri-state gates in the in-phase clock signal control unit correspond one-to-one with the bits of the enable digital signal. If the corresponding bit of the enable digital signal stores a start flag, it indicates that the enable digital signal is at a high level at the current bit; if it stores a stop flag, it indicates that the enable digital signal is at a low level at the current bit. When the control terminal of the tri-state gate in the in-phase clock signal control unit and the inverting clock signal control unit is high, the signal at the input terminal can be transmitted to the output terminal; when the control terminal is low, the output terminal is in a high-impedance state. The input terminals of the N tri-state gates in the in-phase clock signal control unit are electrically connected to the first output terminal, and the output terminals of the N tri-state gates in the in-phase clock signal control unit are electrically connected one-to-one to the N charge pump units. The input terminals of the N tri-state gates in the inverting clock signal control unit are electrically connected to the second output terminal, and the output terminals of the N tri-state gates in the non-inverting clock signal control unit are electrically connected one-to-one to the N charge pump units.

10. A control method for a charge pump module, characterized in that, The control method is applied to a digitally controlled charge pump circuit as described in any one of claims 1 to 9, and the control method includes: Determine whether the voltage output by the charge pump module is within a predetermined range; When the voltage output by the charge pump module is not within the predetermined range, the power supply capability of the charge pump module is adjusted so that the voltage output by the adjusted charge pump module is within the predetermined range. The power supply capability of the charge pump module is maintained when the voltage output by the charge pump module is within a predetermined range.

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