Package carrier and preparation method thereof

Abstract

The invention provides a package carrier and a preparation method thereof, and the package carrier comprises a first substrate which comprises a first through hole, a first conductive column and a seed layer, the first conductive column and the seed layer are located in the first through hole, and the seed layer is located between the first conductive column and the hole wall of the first through hole; the second substrate is arranged on one side of the first substrate and is in contact with the first substrate, the second substrate comprises a second through hole and a second conductive column filled in the second through hole, and the second conductive column is in contact with the hole wall of the second through hole; wherein the first through hole and the second through hole are at least partially communicated, and the first conductive column and the second conductive column are electrically connected at the contact interface. According to the invention, the first substrate and the second substrate are stacked and contacted, and high-difficulty manufacturing of the through hole is decomposed into respective filling of the low-aspect-ratio through hole and the blind hole, so that the manufacturing difficulty of the high-aspect-ratio through hole is reduced, and the filling effect is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a packaging substrate and its preparation method. Background Technology

[0002] In recent years, research on through-glass vias (TGVs) has been deepening both domestically and internationally. TGVs have broad application prospects, including optical communication, RF modules, optoelectronic system integration, MEMS packaging, consumer electronics, electronic gas amplifiers, and medical devices. However, there are many challenges in the TGV filling process, and improving this process has become an urgent problem to be solved. Summary of the Invention

[0003] In view of this, the purpose of this application is to propose a packaging substrate and its preparation method, so as to realize the preparation of deep holes in the packaging substrate and improve the reliability of the packaging substrate.

[0004] For the purposes described above, this application provides a packaging carrier board, comprising: A first substrate includes a first through hole and a first conductive post and a seed layer located within the first through hole, wherein the seed layer is located between the first conductive post and the hole wall of the first through hole; A second substrate is disposed on one side of the first substrate and in contact with the first substrate. The second substrate includes a second through hole and a second conductive post filling the second through hole. The second conductive post is in contact with the hole wall of the second through hole. The first through hole and the second through hole are at least partially connected, and the first conductive post and the second conductive post are electrically connected at the contact interface.

[0005] Optionally, in a direction perpendicular to the first substrate, the orthographic projection of the first through hole at least partially overlaps with the orthographic projection of the second through hole; Optionally, in a direction perpendicular to the first substrate, the orthographic projection of the second through hole is located within the orthographic projection range of the first through hole.

[0006] Optionally, the end face of the first conductive post away from the second conductive post is coplanar with the surface of the first substrate away from the second substrate; the end face of the second conductive post away from the first conductive post is coplanar with the surface of the second substrate away from the first substrate.

[0007] Optionally, the packaging carrier board further includes: The first wiring layer is disposed on the side of the first substrate away from the second substrate and is electrically connected to the first conductive pillar. And / or, the packaging substrate further includes a second rewiring layer, which is disposed on the side of the second substrate away from the first substrate and electrically connected to the second conductive post.

[0008] Optionally, the packaging carrier board further includes: A first protective layer covers the first redistribution layer, and the first protective layer includes a first opening that exposes a portion of the first redistribution layer. And / or, the package carrier further includes a second protective layer covering the second redistribution layer, the second protective layer including a second opening exposing a portion of the second redistribution layer.

[0009] Based on the same inventive concept, this application also provides a method for preparing a packaging carrier, the method comprising: A first substrate and a second substrate are provided, and a first through-hole is formed on the first substrate and a second through-hole is formed on the second substrate; A seed layer and a first conductive post are formed, the first conductive post being located within the first through hole, and the seed layer being located at least between the first conductive post and the hole wall of the first through hole; The second substrate is disposed on one side of the first substrate, such that the second through hole exposes at least a portion of the first conductive post, forming a blind via; A second conductive post is formed inside the blind hole. The second conductive post is in contact with the wall of the second through hole and is electrically connected to the first conductive post.

[0010] Optionally, the step of forming the seed layer and the first conductive pillar includes: forming the seed layer continuously on the hole wall of the first through hole and on the opposite two side surfaces of the first substrate.

[0011] Optionally, before disposing the second substrate on one side of the first substrate, the method further includes: The surface of the first substrate that is in contact with the second substrate is ground so that the end face of the first conductive post is coplanar with the surface of the first substrate.

[0012] Optionally, after forming the second conductive post within the second through-hole, the method further includes: The surface of the first substrate away from the second substrate is ground so that the end face of the first conductive post is coplanar with the surface of the first substrate. The surface of the second substrate away from the first substrate is ground so that the end face of the second conductive post is coplanar with the surface of the second substrate.

[0013] Optionally, after forming the second conductive post within the second through-hole, the method further includes: A first redistribution layer is provided on the side of the first substrate away from the second substrate, and the first redistribution layer is electrically connected to the first conductive pillar. And / or, a second redistribution layer is provided on the side of the second substrate away from the first substrate, and the second redistribution layer is electrically connected to the second conductive pillar.

[0014] The packaging substrate provided in this application is formed by stacking and contacting a first substrate and a second substrate. Multiple low aspect ratio vias can be connected to form high aspect ratio vias. The manufacturing of high aspect ratio vias is decomposed into the separate filling of low aspect ratio vias and blind vias, thereby reducing the manufacturing difficulty of high aspect ratio vias and improving the filling effect. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the main structure of the packaging carrier provided in one embodiment of this application; Figure 2 This is a schematic diagram of the structure of a packaging carrier provided in an embodiment of this application; Figure 3 This is a schematic diagram of the main structure of the packaging carrier provided in another embodiment of this application; Figure 4 This is a schematic diagram of the structure of a packaging carrier provided in another embodiment of this application; Figure 5 This is a schematic flowchart of a method for preparing a packaging substrate according to an embodiment of this application; Figure 6 This is a flowchart of some process steps of the method for preparing a packaging substrate provided in one embodiment of this application; Figure 7 This is a flowchart of some process steps of the method for preparing a packaging substrate provided in one embodiment of this application; Figure 8 This is a flowchart of some process steps of the method for preparing a packaging substrate provided in one embodiment of this application.

[0017] Marker explanation: 100. Packaging carrier board; 10. First substrate; 11. First through-hole; 12. First conductive pillar; 13. Seed layer; 20. Second substrate; 21. Second through hole; 22. Second conductive post; 31. First wiring layer; 32. Second wiring layer; 41. First protective layer; 411. First opening; 42. Second protective layer; 421. Second opening; 50. Conductive bump. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0019] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0020] With the development of high-performance chips, chip integration is increasing, and interconnect density is becoming increasingly dense. Traditional organic substrates can no longer meet the requirements in terms of flatness, fine circuitry, and signal transmission speed. During the packaging process, glass can withstand higher temperatures better than organic substrates, and its coefficient of thermal expansion is similar to silicon, thus reducing stress warping problems caused by thermal mismatch. Furthermore, the higher flatness and lower roughness of the glass surface allow for denser wiring. Its lower dielectric constant and dielectric loss improve signal transmission speed and signal integrity. Simultaneously, its excellent chemical stability effectively resists environmental corrosion from moisture, acids, and alkalis. With its superior physical, chemical, and electrical properties, glass can replace organic substrates.

[0021] The most crucial part of glass substrates is TGV fabrication, especially the drilling and filling of TGV with high aspect ratios (e.g., 8:1 or higher), which remains a technical challenge that the substrate industry needs to solve.

[0022] The inventors of this application discovered that when integrating multiple chips together, the glass substrate needs a certain thickness to maintain strength. However, the thicker the glass, the larger the aspect ratio of the TGV, and the more difficult it is to drill and fill holes. In related technologies, the fabrication of high aspect ratio TGVs faces problems such as uneven seed layer coverage and incomplete filling, leading to a decrease in electrical connection reliability.

[0023] Based on this, this application provides a solution for packaging carrier and preparation method to reduce the difficulty of manufacturing high aspect ratio TGV.

[0024] like Figures 1 to 4 As shown, an embodiment of this application provides a packaging carrier 100, which includes a first substrate 10 and a second substrate 20. The first substrate 10 includes a first through-hole 11 and a first conductive post 12 and a seed layer 13 located within the first through-hole 11. The seed layer 13 is located between the first conductive post 12 and the wall of the first through-hole 11. The second substrate 20 is disposed on one side of the first substrate 10 and is in contact with the first substrate 10. The second substrate 20 and the first substrate 10 are specifically connected by a bonding process. The second substrate 20 includes a second through-hole 21 and a second conductive post 22 filling the second through-hole 21. The second conductive post 22 is in contact with the wall of the second through-hole 21.

[0025] The first through-hole 11 and the second through-hole 21 are partially or completely connected, and the first conductive post 12 and the second conductive post 22 are electrically connected at the contact interface. The contact interface between the second substrate 20 and the first substrate 10 is also the bonding interface.

[0026] The first through hole 11 and the second through hole 21 are partially connected, meaning that the orthographic projection of the first through hole 11 on the contact interface between the first substrate 10 and the second substrate 20 partially overlaps with the orthographic projection of the second through hole 21 on the same contact interface.

[0027] The first through hole 11 and the second through hole 21 are completely connected, meaning that the first through hole 11 and the second through hole 21 are aligned, and the orthographic projection of the larger through hole on the contact interface completely covers the orthographic projection of the other through hole with a smaller or the same diameter on the contact interface.

[0028] Specifically, a seed layer 13 is attached to the wall of the first through hole 11, and a first conductive post 12 is formed in the seed layer 13 by electroplating and fills the first through hole 11. When the first substrate 10 and the second substrate 20 are in contact, the first through hole 11 and the second through hole 21 are aligned, and the second through hole 21 and the first conductive post 12 form a blind hole. The end of the first conductive post 12 serves as the bottom of the blind hole, and the blind hole is used to fill and form the second conductive post 22.

[0029] For example, before filling the first through-hole 11 of the first substrate 10, a continuous seed layer 13 is deposited on the hole wall of the first through-hole 11 and on the upper and lower surfaces of the first substrate 10 by PVD (physical vapor deposition) sputtering process. Subsequently, the first through-hole 11 is grown and filled on the seed layer 13 by electroplating copper to form a first conductive pillar 12. Both the first conductive pillar 12 and the second conductive pillar 22 are made of copper.

[0030] The seed layer 13 helps to achieve uniform current distribution and dense electroplating filling. The seed layer 13 also improves the adhesion between the first conductive post 12 and the glass wall of the first through-hole 11, preventing detachment or cracking during use. The seed layer 13 includes, but is not limited to, Ti / Cu or TiW / Cu composite layers formed by physical vapor deposition (PVD), or Cu, Ni, Co, and their alloy layers formed by electroless plating.

[0031] The packaging substrate 100 provided in this application embodiment integrates a low aspect ratio through-hole structure and a blind via filling structure in the vertical direction by stacking a first substrate 10 and a second substrate 20, thereby achieving the effect of a high aspect ratio TGV and reducing the manufacturing difficulty.

[0032] Specifically, when filling the second through-hole 21, copper ions in the electroplating copper solution can be directly deposited and grown on the first conductive pillar 12 within the blind hole, without the need for a seed layer. Therefore, the copper material of the finally formed second conductive pillar 22 is in direct contact with the glass hole wall of the second through-hole 21.

[0033] Before forming the second conductive pillar 22, the wall of the second through hole 21 can be plasma cleaned or treated with an adhesion promoter to enhance the bonding strength between the electroplated copper and the glass hole wall.

[0034] For example, the packaging substrate 100 includes a first substrate 10 and a second substrate 20. The second substrate 20 is bonded to the upper side of the first substrate 10. The aspect ratio of the first through-hole 11 of the first substrate 10 can be designed to be 2:1, and the aspect ratio of the second through-hole 21 of the second substrate 20 can be designed to be 6:1. After the first substrate 10 and the second substrate 20 are bonded, the overall equivalent aspect ratio can meet the requirements.

[0035] like Figure 1 As shown, in some embodiments, the diameter D1 of the first through hole 11 is larger than the diameter D2 of the second through hole 21.

[0036] For example, the aperture D1 of the first through hole 11 on the first substrate 10 is 5 μm, and the aperture D2 of the second through hole 21 on the second substrate 20 is 3 μm.

[0037] Specifically, the first through hole 11 and the second through hole 21 form a stepped structure at the contact interface, wherein the aperture D1 of the first through hole 11 and the aperture D2 of the second through hole 21 can satisfy: D1-D2≥2δ, where δ is a preset bonding alignment accuracy tolerance.

[0038] In this design, the first substrate 10 serves as the bottom layer, and its aperture is larger than that of the second substrate 20, forming a stepped structure. During the bonding alignment process, even if a slight misalignment occurs, it ensures that the bottom of the second through-hole 21 exposes the end face of the first conductive post 12, thereby reducing contact with the insulating glass.

[0039] The first substrate 10 uses a low aspect ratio via, which makes it easier to perform finishing and filling. In addition, after the second substrate 20 is bonded to the first substrate 10, the second via 21 forms a blind via with the first conductive post 12 as the bottom. The blind via filling process is relatively mature and has a good filling effect.

[0040] In other embodiments, the aperture D1 of the first through-hole 11 may also be less than or equal to the aperture D2 of the second through-hole 21. This reduces the precision requirements of the bonding process and allows for a larger cross-sectional area for the second conductive post 22 to reduce resistance.

[0041] In some embodiments, the end face of the first conductive post 12 away from the second conductive post 22 is coplanar with the surface of the first substrate 10 away from the second substrate 20. The end face of the second conductive post 22 away from the first conductive post 12 is coplanar with the surface of the second substrate 20 away from the first substrate 10.

[0042] For example, before bonding, the first substrate 10, which has already been filled with the first conductive post 12, is surface-polished to remove the copper layer and seed layer on one side (specifically, the side used for bonding contact), so that the end face of the first conductive post 12 is flush with the first substrate 10. After completing the blind via filling to form the second conductive post 22, the surfaces of the first substrate 10 and the second substrate 20 facing away from each other are surface-polished again to remove excess copper layer, so that the end faces of the first conductive post 12 and the second conductive post 22 are flush with the corresponding glass surfaces.

[0043] The first grinding process ensures the flatness of the contact interface, guaranteeing bonding quality. The two grinding processes together ensure the planarization of the surfaces on both sides of the two substrates after bonding, providing a substrate for subsequent fabrication.

[0044] Specifically, the metal and seed layer on one side surface (e.g., the upper surface) of the first substrate 10 are ground off before being bonded to the second substrate 20, while the entire metal layer on the other side surface (lower surface) is retained for bonding to the second substrate 20 and then electroplating to fill blind holes. The metal retained on the lower surface can serve as a seed layer.

[0045] like Figure 3 , Figure 4 As shown, in some embodiments, the packaging substrate 100 further includes a first redistribution layer 31, which is disposed on the side of the first substrate 10 away from the second substrate 20 and is electrically connected to the first conductive post 12.

[0046] Furthermore, the packaging substrate 100 also includes a first protective layer 41, which covers the first redistribution layer 31 and includes a first opening 411 that exposes a portion of the first redistribution layer 31.

[0047] Optionally, the packaging substrate 100 further includes a second wiring layer 32, which is disposed on the side of the second substrate 20 away from the first substrate 10, and is electrically connected to the second conductive post 22.

[0048] Furthermore, the packaging substrate 100 also includes a second protective layer 42, which covers the second redistribution layer 32 and includes a second opening 421 that exposes a portion of the second redistribution layer 32.

[0049] Specifically, a first redistribution layer 31 is provided on the side of the first substrate 10 away from the contact interface, and the first redistribution layer 31 is electrically connected to the first conductive post 12. A second redistribution layer 32 is provided on the side of the second substrate 20 away from the contact interface, and the second redistribution layer 32 is electrically connected to the second conductive post 22.

[0050] For example, a first redistribution layer 31 is formed on the surface of the first substrate 10 away from the contact interface, and a second redistribution layer 32 is formed on the surface of the second substrate 20 away from the contact interface. The first redistribution layer 31 and the second redistribution layer 32 are formed through processes such as PVD sputtering of a copper seed layer, photolithography, copper electroplating, and etching, which can rearrange the pads of the first conductive pillar 12 and / or the second conductive pillar 22 to positions more suitable for soldering. Subsequently, a photosensitive protective layer (such as green ink) is correspondingly coated on the redistribution layer, and openings are formed by exposure and development to expose the pads to be soldered. Finally, the pads exposed at the first opening 411 and the second opening 421 are surface treated to form corresponding surface treatment layers.

[0051] The high-density TGV connection points are fanned out into larger-spaced pads through the first routing layer 31 and the second routing layer 32, adapting to the solder joint layout requirements of the PCB board or chip and achieving signal redistribution. The first protective layer 41 and the second protective layer 42 prevent short circuits, avoid mechanical damage and environmental pollution, and provide electrical protection. At the same time, the first opening 411 and the second opening 421 define the corresponding soldering areas, ensuring the reliability of the soldering process.

[0052] In a specific example of the packaging carrier 100, the first substrate 10 serves as the core layer of the bonding structure, and its material can be borosilicate glass or aluminosilicate glass. A plurality of first vias 11 are formed on the first substrate 10. The depth-to-width ratio of the first vias 11 is low, preferably 1:1 to 5:1, more preferably 3:1 to 4:1. The first vias 11 are formed by laser-induced wet etching, a method that yields vias with smooth walls and high perpendicularity, which is beneficial for subsequent metal filling.

[0053] The first conductive pillar 12 fills the first through-hole 11. Its formation process includes: First, a seed layer 13 is deposited on the hole wall of the first through-hole 11 and the surface of the first substrate 10 by physical vapor deposition. The seed layer 13 is a composite structure including an adhesion layer and a conductive layer. For example, a 50-100 nm thick titanium (Ti) or titanium nitride (TiN) layer is deposited as the adhesion layer, followed by a 200-500 nm thick copper (Cu) layer as the conductive layer. Then, copper is electroplated into the entire first through-hole 11 using the seed layer 13 as the cathode, forming a dense, pore-free first conductive pillar 12. Finally, excess copper and the seed layer on the bonding side of the first substrate 10 are removed by chemical mechanical polishing, making the end face of the first conductive pillar 12 coplanar with the surface of the first substrate 10.

[0054] The second substrate 20 is bonded to the side of the first substrate 10 where the surface copper layer and seed layer have been removed. The material of the second substrate 20 may be the same as or different from that of the first substrate 10. A second via 21 is formed on the second substrate 20. The aspect ratio of the second via 21 can be designed as needed; for example, the depth of the second via 21 is greater than that of the first via 11. The aspect ratio of the second substrate 20 is preferably 3:1 to 6:1, more preferably 4:1. The aperture D2 of the second via 21 is smaller than the aperture D1 of the first via 11.

[0055] The second substrate 20, whose through-holes have been fabricated but not filled, is bonded to one side of the first substrate 10, whose first conductive post 12 has been filled and whose surface copper layer and seed layer have been removed, using anodic bonding or hybrid bonding. During bonding, it is ensured that the second through-hole 21 is precisely aligned with the first conductive post 12 below it. After bonding, the bottom of the second through-hole 21 contacts the end face of the first conductive post 12, forming a blind hole with the first conductive post 12 at the bottom.

[0056] Subsequently, the blind via is filled into the second through-hole 21 to form the second conductive pillar 22. Since there is no step of depositing a thin film seed layer inside the deep via, problems such as uneven seed layer coverage and excessively high resistance are avoided. After filling, CMP (chemical mechanical polishing) is performed again to remove excess copper from the surface of the second substrate 20, making the end face of the second conductive pillar 22 coplanar with the surface of the second substrate 20.

[0057] Both the first wiring layer 31 and the second wiring layer 32 include one or more alternating stacked metal wiring layers and dielectric layers. The metal wiring layers are typically formed using mature semiconductor processes (such as sputtering seed layers, photolithography, electroplating, and etching), and are made of copper. Their function is to electrically connect and rearrange the pads on top of the high-density TGV onto pads with better positioning and spacing for bonding with external chips or PCBs. The dielectric layers (such as polyimide or ABF) are used to isolate the metal wiring layers and enable interlayer interconnection through internal vias.

[0058] The first protective layer 41 covers the first redistribution layer 31, and the second protective layer 42 covers the second redistribution layer 32. Their core function is to define and protect the circuit using a photosensitive polymer (such as epoxy resin). For example, a first opening 411 on the first protective layer 41 precisely exposes the target pads of the first redistribution layer 31. A second opening 421 on the second protective layer 42 precisely exposes the target pads of the second redistribution layer 32.

[0059] The exposed pads at the first opening 411 and the second opening 421 are respectively surface treated to form corresponding surface treatment layers.

[0060] Conductive bumps 50 (such as tin alloy solder balls or copper pillars) can be fabricated on a surface-treated layer within these second openings 421 and make conductive contact with the pads of the underlying second rewiring layer 32 through the surface-treated layer. The second rewiring layer 32 provides electrical connection points, the second protective layer 42 provides insulation protection and solder joint positioning, while the conductive bumps 50 serve as the final physical connection bridge and stress-reducing structure.

[0061] Based on the same inventive concept, embodiments of this application also provide a method for preparing a packaging carrier plate, used to prepare the packaging carrier plate 100 in any of the above embodiments.

[0062] like Figure 5 As shown, the method for preparing the packaging substrate 100 includes the following steps: Step S10: Provide a first substrate 10 and a second substrate 20, and form a first through-hole 11 on the first substrate 10 and a second through-hole 21 on the second substrate 20; see reference Figure 6 .

[0063] Step S20: Forming a seed layer 13 and a first conductive post 12, wherein the first conductive post 12 is located within the first through hole 11, and the seed layer 13 is located at least between the first conductive post 12 and the wall of the first through hole 11; Reference Figure 7 .

[0064] Step S30: Place the second substrate 20 on one side of the first substrate 10, so that the second through hole 21 exposes at least part of the first conductive post 12, forming a blind hole; Step S40: A second conductive post 22 is formed within the blind hole. The second conductive post 22 contacts the wall of the second through hole 21, and the second conductive post 22 is electrically connected to the first conductive post 12. (Reference) Figure 8 .

[0065] For example, firstly, through-holes with different apertures are formed on the first substrate 10 and the second substrate 20 using laser-induced wet etching. Then, a seed layer is sputtered into the through-holes of the first substrate 10 and filled with copper by electroplating to form a first conductive pillar 12. Next, the second substrate 20 is bonded to one side of the first substrate 10, forming a blind via with the second through-hole 21 and the first conductive pillar 12. A second conductive pillar 22 is then formed by filling the blind via.

[0066] The packaging substrate preparation method provided in this application embodiment decomposes the highly difficult process into multiple mature and less difficult processes through the process of "separation followed by assembly and step-by-step filling", thereby achieving the overall manufacturability of high aspect ratio TGV.

[0067] Specifically, the methods for forming the first through-hole 11 and the second through-hole 21 include any one of laser-induced wet etching, laser ablation, focused ion beam processing, or plasma etching. The bonding process includes at least one of anodic bonding, hot-press bonding, or eutectic bonding.

[0068] For example, using an anodic bonding process: the first substrate 10 and the second substrate 20 are heated to 300-450°C, while a DC voltage of several hundred to several thousand volts is applied between them. Under the combined effect of the electric field and temperature, cations (such as Na+) in the glass migrate, forming a strong electrostatic force at the interface, which bonds the first substrate 10 and the second substrate 20 together.

[0069] The advantages of anodic bonding are high bond strength, good interface sealing, and no introduction of additional materials. It is suitable for applications requiring extremely high interface purity and long-term reliability. The disadvantages are that the types of glass materials applicable are limited (they must contain mobile ions), and the high-temperature and high-voltage processes may cause oxidation of the metal wires or generate thermal stress.

[0070] Alternatively, a hybrid bonding process can be used: First, the first substrate 10 and the second substrate 20 are pre-aligned and bonded at room temperature under high flatness and cleanliness conditions, so that the insulating dielectric layer on the surface is initially bonded by intermolecular forces; then, heat treatment is carried out in an inert atmosphere at 250-400℃. Under the combined action of temperature and pressure, copper atoms at the interface diffuse into each other and form a dense metallurgical connection. At the same time, the insulating dielectric layer also forms a strong covalent bond, realizing the electrical and mechanical bonding of the first substrate 10 and the second substrate 20.

[0071] Step S20, forming a seed layer 13 and a first conductive pillar 12, includes forming a continuous seed layer 13 on the hole wall of the first through hole 11 and on the opposite two side surfaces of the first substrate 10.

[0072] Specifically, when filling the first through hole 11 of the first substrate 10, a composite layer of Ti with a thickness of 50 nm and Cu with a thickness of 200 nm is sputtered using a PVD device as a seed layer 13. The continuous seed layer 13 covers the hole wall of the first through hole 11 and the opposite two side surfaces of the first substrate 10. Then, copper sulfate electroplating solution is used for electroplating until the hole is completely filled with copper to form the first conductive pillar 12.

[0073] The seed layer 13 ensures filling quality, enabling the first via 11 to be filled with high quality and without defects, thus laying the foundation for subsequent processes. The PVD and electroplating processes used are mature technologies in the semiconductor and packaging fields, guaranteeing process stability and yield.

[0074] Besides using PVD to prepare the seed layer 13, the first via 11 can also be formed by electroless plating. For example, the glass wall of the first via 11 can be sensitized and activated (e.g., using a Pd activator), and then a 0.5-1 μm thick electroless copper layer can be deposited by electroless plating. The advantage of this method is that it has excellent step coverage, can form a uniform coating even for complex hole shapes, and the equipment cost is relatively lower than PVD. Alternatively, similarly, an amorphous nickel-phosphorus (Ni-P) alloy can be electrolessly plated as a seed layer through activation. The Ni-P layer has good adhesion to the glass and can itself act as a diffusion barrier layer to prevent copper ions from diffusing into the glass. After forming the electroless plated seed layer, the subsequent electroplating filling copper steps remain unchanged.

[0075] When electroplating the first through-hole 11, an acidic copper sulfate plating solution or a copper cyanide plating solution can be used. Acidic copper sulfate plating solution is low in cost and has a fast deposition rate. For applications requiring higher bottom filling consistency and void-free filling capabilities, plating additives with excellent filling capabilities can be used in conjunction with an acidic copper sulfate system, or a copper cyanide plating system with even stronger filling capabilities can be used.

[0076] In some embodiments, before step S30, where the second substrate 20 is disposed on one side of the first substrate 10, the method for preparing the encapsulation carrier 100 further includes the following steps: Step S23: Grind the side surface of the first substrate 10 used for bonding so that the end face of the first conductive post 12 is coplanar with the surface of the first substrate 10.

[0077] In some embodiments, after forming the second conductive post 22 in the second through hole 21 in step S40, the method for preparing the encapsulation carrier 100 further includes the following steps: Step S50: Grind the surface of the first substrate 10 away from the second substrate 20 so that the end face of the first conductive post 12 is coplanar with the surface of the first substrate 10; grind the surface of the second substrate 20 away from the first substrate 10 so that the end face of the second conductive post 22 is coplanar with the surface of the second substrate 20.

[0078] For example, before bonding, the first substrate 10, which has been filled with the first conductive post 12, is subjected to CMP to remove excess copper layer from the surface, so that the end face of the copper post is flush with the glass surface. After the blind via is filled by electroplating, the surface of the second substrate 20 is subjected to CMP again to remove excess copper layer, so that the end face of the second conductive post 22 is flush with the glass surface.

[0079] The first grinding process ensures the flatness of the contact interface, guaranteeing bonding quality. The two grinding processes together ensure the planarization of both sides of the substrate, providing a base for the subsequent fabrication of the high-precision redistribution layer 30.

[0080] In some embodiments, the method for preparing the packaging substrate 100 further includes the following steps: Step S60: A first redistribution layer 31 is formed on the side of the first substrate 10 away from the second substrate 20, so that the first redistribution layer 31 is electrically connected to the first conductive post 12. A second redistribution layer 32 is formed on the side of the second substrate 20 away from the first substrate 10, so that the second redistribution layer 32 is electrically connected to the second conductive post 22.

[0081] Optionally, the method for preparing the packaging substrate 100 further includes the following steps: Step S70: Form a first protective layer 41 covering the first redistribution layer 31. The first protective layer 41 includes a first opening 411 that exposes a portion of the first redistribution layer 31. A second protective layer 42 is formed to cover the second rewiring layer 32, the second protective layer 42 including a second opening 421 that exposes a portion of the second rewiring layer 32.

[0082] For example, consider the fabrication of a second redistribution layer 32 on the surface of a second substrate 20. First, a new seed layer is deposited across the entire lower surface using PVD. Then, photoresist is spin-coated, exposed, and developed to form the desired circuit pattern. Next, pattern electroplating is performed to thicken the copper layer in the circuit area to 5-10 μm. Finally, the photoresist is removed, and the seed layer not protected by electroplated copper is etched away with a fast etchant to obtain independent copper circuits, i.e., the second redistribution layer 32. This process can be repeated multiple times to form multiple redistribution layers, with layers isolated by dielectric layers and connected through vias in the dielectric layers.

[0083] A permanent second protective layer 42 is formed on the second redistribution layer 32 through processes such as coating, exposure, and development. The material is typically a green photosensitive epoxy resin or polyimide. Its function is to protect the circuit from mechanical damage, corrosion, and to prevent soldering short circuits. The second opening 421 on the second protective layer 42 precisely exposes the conductive structure of the second redistribution layer 32, such as the solder pads that need to be soldered.

[0084] Furthermore, a surface treatment is performed on the exposed second wiring layer 32 to protect the conductive surfaces and provide solderability.

[0085] For example, an ENEPIG (Enhanced Electroless Nickel-Palladium-Gold) surface treatment is used, first electrolessly plating a layer of Ni (as a barrier layer and solderable substrate), then plating a thin layer of Pd (to prevent Ni corrosion), and finally plating a thin layer of Au (to provide excellent solderability and oxidation resistance). This method is compatible with gold wire bonding and soldering. Alternatively, an organic solderable preservative (OSP) surface treatment can be used to form an organic protective film on the copper surface. This method is low-cost and simple, but the protection period and heat resistance are relatively poor. Finally, a conductive bump 50, i.e., a solder bump, is formed at the second opening 421.

[0086] One method involves using solder ball placement, where pre-formed tin alloy solder balls (such as SAC305) are placed onto the pads using a ball placement machine, and then reflow soldering is performed to form bumps. Alternatively, solder paste can be printed onto the pads using a stencil, followed by reflow soldering. Another method is electroplating bumps, which use photolithography and electroplating processes similar to those used for redistribution layers to directly form copper pillars or high-lead solder bumps on the pads, suitable for higher density interconnects.

[0087] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0088] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A package substrate, characterized by, The package substrate comprises: a first substrate comprising a first through hole, a first conductive post in the first through hole, and a seed layer between the first conductive post and a hole wall of the first through hole; a second substrate arranged on one side of the first substrate and in contact with the first substrate, the second substrate comprising a second through hole and a second conductive post filled in the second through hole, the second conductive post being in contact with a hole wall of the second through hole; wherein the first through hole and the second through hole are at least partially communicated, and the first conductive post and the second conductive post are electrically connected at a contact interface.

2. The package board according to claim 1, wherein In a direction perpendicular to the first substrate, a projection of the first through hole and a projection of the second through hole at least partially overlap. Preferably, in the direction perpendicular to the first substrate, a projection of the second through hole is within a range of a projection of the first through hole.

3. The package board according to claim 1, wherein An end surface of the first conductive post away from the second conductive post is coplanar with a surface of the first substrate away from the second substrate, and an end surface of the second conductive post away from the first conductive post is coplanar with a surface of the second substrate away from the first substrate.

4. The package board according to claim 1, wherein The package substrate further comprises: a first redistribution layer arranged on a side of the first substrate away from the second substrate and electrically connected with the first conductive post; and / or, the package substrate further comprises a second redistribution layer arranged on a side of the second substrate away from the first substrate and electrically connected with the second conductive post.

5. The package board according to claim 4, wherein The package substrate further comprises: a first protective layer covering the first redistribution layer, the first protective layer comprising a first opening exposing part of the first redistribution layer; and / or, the package substrate further comprises a second protective layer covering the second redistribution layer, the second protective layer comprising a second opening exposing part of the second redistribution layer.

6. A method of manufacturing a package substrate, characterized by, The method comprises: providing a first substrate and a second substrate, and forming a first through hole on the first substrate and a second through hole on the second substrate; forming a seed layer and a first conductive post, the first conductive post being in the first through hole, and the seed layer being between the first conductive post and a hole wall of the first through hole; arranging the second substrate on one side of the first substrate to expose at least part of the first conductive post by the second through hole, forming a blind hole; forming a second conductive post in the blind hole, the second conductive post being in contact with a hole wall of the second through hole, and the second conductive post being electrically connected with the first conductive post.

7. The method of claim 6, wherein the encapsulation of the package substrate is performed by a method comprising: The step of forming the seed layer and the first conductive post comprises: forming a continuous seed layer on the hole wall of the first through hole and the opposite two side surfaces of the first substrate.

8. The method of claim 7, wherein the encapsulation of the package substrate is performed by a method comprising: Before the step of arranging the second substrate on one side of the first substrate, the method further comprises: grinding a side surface of the first substrate for contact with the second substrate to make an end surface of the first conductive post coplanar with a surface of the first substrate.

9. The method of claim 7, wherein the encapsulation of the package substrate is performed by a method comprising: After the step of forming the second conductive post in the second through hole, the method further comprises: grinding a side surface of the first substrate away from the second substrate to make an end surface of the first conductive column coplanar with a surface of the first substrate; grinding a side surface of the second substrate away from the first substrate to make an end surface of the second conductive column coplanar with a surface of the second substrate.

10. The method of claim 7, wherein the encapsulation of the package substrate is performed by a method comprising: After forming the second conductive column in the second through hole, the method further comprises: providing a first redistribution layer on a side of the first substrate away from the second substrate, the first redistribution layer being electrically connected with the first conductive column; and / or, providing a second redistribution layer on a side of the second substrate away from the first substrate, the second redistribution layer being electrically connected with the second conductive column.

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