Integrated circuit

Abstract

An integrated circuit includes a programmable circuit configured to generate a first oscillator signal in response to a first control signal and a second oscillator signal in response to a second control signal; and a controller configured to provide the first control signal and the second control signal to the programmable circuit, receive the first oscillator signal and the second oscillator signal, and determine a concentration trend of propagation delays of the programmable circuit using the first oscillator signal and the second oscillator signal. According to the design, a large amount of propagation delay measurement values can be generated, and in consideration of various different types of propagation delay measurement values, a test structure which occupies less on-chip space and is fixed in a programmable design structure is used in the design; therefore, the design of the invention has cost effectiveness.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and more particularly to an integrated circuit. Background Technology

[0002] An integrated circuit can include digital logic circuits, such as arrangements of digital logic gates that output digital signals (e.g., combinations of high-voltage bits and low-voltage bits) based on digital signals received at or generated by the integrated circuit. Digital logic gates (or digital logic doors) are typically formed using transistors fabricated on integrated circuits.

[0003] The physical parameters of transistors on an integrated circuit typically limit the speed at which a digital signal propagates from one digital logic gate to the next. For example, a transistor turns on or off once its gate voltage reaches a threshold voltage, and transistors usually have some gate capacitance, which takes some time to charge to the voltage of the signal received at the gate. The time required for a signal to travel from the input to the output of a set of one or more logic gates is called the propagation delay of that set of logic gates.

[0004] Computer simulation tools, such as static timing analysis (STA) tools, can estimate the propagation delay of digital logic gates before manufacturing by measuring the propagation delay of previously manufactured integrated circuits. In the prior art, hundreds of test structures with different configurations might be needed to generate the required number of measurements, which could be very costly. Summary of the Invention

[0005] In view of this, the present invention provides an integrated circuit to solve the problems or deficiencies of the prior art. The integrated circuit of the present invention is more cost-effective and has a more universal measurement design, so that the propagation delay of different integrated circuits can be measured without excessive test structures.

[0006] According to a first aspect of the present invention, an integrated circuit is disclosed, comprising:

[0007] A programmable circuit, configured to generate a first oscillator signal in response to a first control signal and to generate a second oscillator signal in response to a second control signal; and

[0008] The controller is configured to provide the first control signal and the second control signal to the programmable circuit, receive the first oscillator signal and the second oscillator signal, and use the first oscillator signal and the second oscillator signal to determine the central tendency of the propagation delay of the programmable circuit.

[0009] According to a second aspect of the present invention, an integrated circuit is disclosed, comprising:

[0010] A programmable ring oscillator, including a delay path, is configured to propagate an oscillator signal along the delay path.

[0011] The delay path includes an oscillator stage, which can switch in and out of the delay path based on corresponding control signals.

[0012] According to a third aspect of the present invention, an integrated circuit is disclosed, comprising:

[0013] A programmable delay path, including a path delay tuner configured to: receive a control signal; and add cell delay and lead delay amounts based on the control signal to the programmable delay path; and

[0014] The controller is configured to provide the control signal to the programmable delay path, receive a signal from the programmable delay path, and compare the signal with a reference signal.

[0015] According to a fourth aspect of the invention, an integrated circuit is disclosed, comprising at least one circuit selected from the group consisting of:

[0016] A first circuit includes: a programmable ring oscillator, including a first programmable delay path, the programmable ring oscillator being configured to propagate an oscillator signal along the first programmable delay path; wherein the first programmable delay path includes an oscillator stage, the oscillator stage being switchable into and out of the first programmable delay path based on a corresponding first control signal; and / or

[0017] The second circuit includes: a second programmable delay path, including a path delay tuner configured to: receive a second control signal, and add a cell delay amount and a lead delay amount based on the second control signal to the second programmable delay path; and the second circuit further includes: a controller configured to provide the second control signal to the second programmable delay path, receive a signal from the second programmable delay path, and compare the signal with a reference signal.

[0018] The integrated circuit of the present invention includes: a programmable circuit configured to generate a first oscillator signal in response to a first control signal and a second oscillator signal in response to a second control signal; and a controller configured to provide the first control signal and the second control signal to the programmable circuit, receive the first oscillator signal and the second oscillator signal, and use the first oscillator signal and the second oscillator signal to determine the central tendency of the propagation delay of the programmable circuit. The design of the present invention can generate a sufficiently large number of propagation delay measurements, and considering various types of propagation delay measurements, the design of the present invention uses a fixed test structure with a programmable structure that occupies less on-chip space than previously used designs; therefore, the design of the present invention is cost-effective. Attached Figure Description

[0019] Figure 1 This is a block diagram illustrating an exemplary integrated circuit including a programmable ring oscillator (ROSC) circuit and a programmable delay path circuit according to some embodiments.

[0020] Figure 2 This is a block diagram illustrating alternative exemplary integrated circuits including a programmable ROSC circuit and a programmable delay path circuit according to some embodiments.

[0021] Figure 3 This illustrates that, according to some embodiments, it may include... Figure 2 A block diagram of an exemplary ROSC controller in an integrated circuit.

[0022] Figure 4 The illustration may include, according to some embodiments, the following: Figure 2 A block diagram of several exemplary programmable ring oscillators (ROSCs) in an integrated circuit.

[0023] Figure 5 This illustrates some embodiments. Figure 4 A block diagram of one of the programmable ROSCs, which includes multiple ROSC stages.

[0024] Figure 6 This illustrates some embodiments. Figure 5 The circuit diagram of ROSC can be programmed.

[0025] Figure 7 This is a flowchart illustrating an exemplary method for determining the propagation delay of an integrated circuit according to some embodiments.

[0026] Figure 8 This is a flowchart illustrating an alternative exemplary method for determining the propagation delay of an integrated circuit according to some embodiments.

[0027] Figure 9 This illustrates that, according to some embodiments, it can be included Figure 2 A block diagram of an exemplary delay path controller in an integrated circuit.

[0028] Figure 10 The illustration may include, according to some embodiments, the following: Figure 2 A block diagram of several exemplary programmable delay paths in an integrated circuit.

[0029] Figure 11 This is an explanation based on some embodiments. Figure 10 A block diagram of one of the programmable delay paths, which includes multiple clock delay tuners and path tuners.

[0030] Figure 12 This is an explanation based on some embodiments. Figure 11 A block diagram of one of the clock delay tuners.

[0031] Figure 13 The illustrations are based on some embodiments. Figure 11 A block diagram of one of the path tuners.

[0032] Figure 14 This is a flowchart of an exemplary method for determining the path delay of an integrated circuit according to some embodiments. Detailed Implementation

[0033] In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form part of the invention, and which illustrate specific preferred embodiments in which the invention can be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice them, and it should be understood that other embodiments may be utilized, and mechanical, structural, and procedural changes may be made, without departing from the spirit and scope of the invention. Therefore, the following detailed description should not be construed as limiting, and the scope of the embodiments of the invention is defined only by the appended claims.

[0034] It will be understood that although the terms “first,” “second,” “third,” “primary,” “secondary,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another. Therefore, without departing from the teachings of the inventive concept, the first or primary element, component, region, layer, or portion discussed below may be referred to as a second or secondary element, component, region, layer, or portion.

[0035] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “under,” “above,” and “above” may be used herein to describe the relationship of an element or feature to it. Another element or feature is shown in the figure. In addition to the orientation described in the figure, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly. Additionally, it will be understood that when a “layer” is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more intermediate layers.

[0036] The terms “about,” “roughly,” and “about” generally mean a range of ±20%, ±10%, ±5%, ±3%, ±2%, ±1%, or ±0.5% of a specified value. The specified values ​​in this invention are approximate. Unless otherwise specified, the specified values ​​include the meanings of “about,” “roughly,” and “about.” The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular terms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0037] It will be understood that when an “element” or “layer” is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it can be directly on, connected to, coupled to, or adjacent to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “immediately adjacent to” another element or layer, there are no intermediate elements or layers.

[0038] Note: (i) the same features will be indicated by the same reference numerals throughout the series and will not necessarily be described in detail in every figure in which they appear, and (ii) a series of figures may show different aspects of a single item, each of which is associated with various reference labels that may appear throughout the series or only in selected figures of the series.

[0039] The inventors recognized several drawbacks of prior art for measuring propagation delay in integrated circuits. One such drawback is that propagation delay test structures are not implemented on-chip in a cost-effective manner. For example, prior test structures relied on using multiple different structures on the integrated circuit to generate sufficient delay data for accurate measurements. For instance, in some applications, measuring the average propagation delay of an integrated circuit might require delay measurements over hundreds of different logic gate configurations, which, according to prior art, would likely require hundreds of different configurations of test structures to generate the required number of measurements. Similarly, measuring variations in the propagation delay of an integrated circuit might require even more test structures than average measurements. The inventors recognized that variance measurement is particularly useful for incorporating estimations of post-manufacturing performance during simulation, as the variance of propagation delay in an integrated circuit increases as the integrated circuit is fabricated to include denser logic gate configurations.

[0040] In some applications, even more specialized test structures may be required to measure different types of propagation delay in integrated circuits, such as cell delay due to propagation through logic gates, wire delay due to propagation through leads between logic gates, and delay due to transistor voltage thresholds. By relying on a large number of different structures to obtain useful propagation delay measurements, prior art test structures occupy significant on-chip space, making them expensive to implement and unsuitable for obtaining a wide variety of propagation delay measurements.

[0041] Another drawback is that the measurement circuitry used to measure the propagation delay from on-chip test structures is implemented externally to the integrated circuit, which increases the complexity of transmitting signals from the chip for measurement. As mentioned above, test structures can be large and occupy expensive on-chip space, hindering on-chip measurement circuitry from measuring the propagation delay generated by the test structures. Since the measurement circuitry is implemented externally, the signal generated by the test structure must be extracted for off-chip measurement, which may require placing large test pads on the integrated circuit to read the generated signal via bond wires. For example, since the propagation delay on the integrated circuit is typically on the order of picoseconds or less, the signal generated by the integrated circuit is not compatible with standard input / output (I / O) interface standards such as the Joint Test Action Group (JTAG) interface standard. The large test pads used to read signals from the integrated circuit for measurement also increase implementation costs due to their significant chip space requirements.

[0042] To overcome the aforementioned drawbacks of prior art, the inventors have developed an improved technique for measuring the propagation delay of integrated circuits, which facilitates on-chip propagation delay measurement. In some embodiments, the integrated circuit described herein may include a programmable circuit and a controller configured to provide control signals to the programmable circuit to generate signals for measuring the propagation delay of the integrated circuit. For example, in some embodiments, the programmable circuit system may include a programmable oscillator having multiple oscillator stages that can be switched into and out of a delay path based on control signals from the controller. In this example, switching oscillator stages inside and outside a delay path using control signals from the controller, based on received control signals, can allow the same programmable oscillator to generate many different oscillator signals (e.g., using different combinations of oscillator stages). In some embodiments, the controller may be configured to determine the central tendency and / or variance of the propagation delay of the integrated circuit, for example, using signals generated using different combinations of oscillator stages of the programmable oscillator. Furthermore, in some embodiments, the programmable circuit described herein may include multiple oscillators, each including transistors with different voltage thresholds, facilitating the measurement of propagation delays at different voltage thresholds.

[0043] In some embodiments, the programmable circuitry of an integrated circuit may include multiple programmable delay paths configured to provide an amount of cell delay and an amount of lead delay based on control signals from a controller. For example, each programmable delay path may include a path tuner configured to add different amounts of cell and lead delay to the delay path based on control signals. In this example, adding cell and lead delays based on control signals can allow the same programmable delay path to generate signals for measuring the delay caused by the cell and lead delays of the integrated circuit (e.g., using different tuner configurations). In some embodiments, each programmable delay path may include transistors with different channel widths to facilitate the measurement of propagation delays at different channel widths.

[0044] Therefore, the programmable circuit and controller described herein can generate a sufficiently large number of propagation delay measurements, and / or take into account measurements of various different types of propagation delays, using a fixed test structure with less on-chip space than previously employed programmable structures. By consuming less on-chip space, the programmable circuit described herein is cost-effective for implementation in integrated circuits. Furthermore, by including a controller within the integrated circuit, the controller can be configured to perform measurements on the integrated circuit and offload data from the chip using a standard interface.

[0045] It should be understood that the techniques described herein can be used alone or in combination.

[0046] Figure 1 This is a block diagram illustrating an exemplary integrated circuit 100a including a programmable ring oscillator (ROSC) circuit 200a and a programmable delay path circuit 300a according to some embodiments. Figure 1 As shown, integrated circuit 100a also includes a test access port (TAP) 110, which is configured to receive input parameters 112a from outside the integrated circuit 100a and transmit one or more outputs (output signals) 112b to the outside of the integrated circuit 100a. Also as... Figure 1 As shown, integrated circuit 100a can be configured to receive a clock (CLK) signal and provide the CLK signal to programmable ROSC circuit 200a and / or programmable delay path circuit 300a. In some embodiments, integrated circuit 100a may include a digital logic gate array. For example, integrated circuit 100a may be a field programmable gate array (FPGA). Alternatively, integrated circuit 100a may be an application-specific integrated circuit (ASIC).

[0047] In some embodiments, the programmable ROSC circuit 200a and / or the programmable delay path circuit 300a may include a group of logic gates (a set, a group, or a set of logic gates) formed on the integrated circuit 100a. In some embodiments, the programmable ROSC circuit 200a may be configured to measure propagation delay in the integrated circuit 100a. For example, in some embodiments, the programmable ROSC circuit 200a may be configured to generate and measure an oscillator signal indicating the propagation delay of the programmable ROSC circuit 200a. In some embodiments, the programmable ROSC circuit 200a may be configured to determine the central tendency and / or variance of the propagation delay of the programmable ROSC circuit 200a. In some embodiments, the programmable delay path circuit 300a may be configured to measure various types of propagation delay in the integrated circuit 100a and compare them with a threshold delay amount. For example, in some embodiments, the programmable delay path circuit 300a may be configured to propagate a signal along a programmable delay path having configurable cell delay and / or lead delay amounts and compare the propagated signal with a reference signal to determine if the delay path in the programmable delay exceeds a threshold delay amount. In some embodiments, the programmable delay path circuit 300a can be configured to control the cell delay amount and / or lead delay amount of the programmable delay path.

[0048] As further described herein, in some embodiments, the programmable ROSC circuit 200a and / or the programmable delay path circuit 300a can be programmed to operate according to control signals(s) received via TAP 110. In some embodiments, TAP 110 can be configured to send one or more of the input parameters 112a configured to control the operation of the programmable ROSC circuit 200a to the programmable ROSC circuit 200a, and to send one or more of the input parameters 112a configured to control the operation of the programmable delay path circuit 300a to the programmable delay path circuit 300a. For example, the input parameters 112a configured to control the operation of the programmable ROSC circuit 200a may include parameters controlling the generation and / or measurement of oscillator signals, and the input parameters 112a configured to control the operation of the programmable delay path circuit 300a may include parameters controlling the delay in the programmable delay path. In some embodiments, TAP 100 may be configured to receive output signal 112b from programmable ROSC circuit 200a and programmable delay path circuit 300a for transmission outside integrated circuit 100a. For example, output signal 112b may indicate whether the propagation delay measured by programmable ROSC circuit 200a and / or the delay in the signal propagated by programmable delay path circuit exceeds a threshold delay amount.

[0049] In some embodiments, TAP 110 can be configured as a parallel and / or serial port interface controller, which is configured to send and / or receive coded signals to another circuit outside of integrated circuit 100a via parallel and / or serial communication media (e.g., one or more cables and one or more electrical connectors). For example, in some embodiments, TAP 110 can be compatible with the JTAG interface standard.

[0050] It should be understood that integrated circuit 100a may include any combination of field-programmable and pre-programmable digital logic circuits. It should also be understood that, according to various embodiments, it may include only programmable ROSC circuitry 200a (e.g., with or without TAP 110), or it may include only programmable delay path circuitry 300a (e.g., with or without TAP 110).

[0051] Figure 2This is a block diagram illustrating an alternative exemplary integrated circuit 100b, according to some embodiments, including a programmable ROSC circuit 200b (e.g., also referred to as a first circuit) and a programmable delay path circuit 300b (e.g., also referred to as a second circuit). In some embodiments, integrated circuit 100b may be in combination with the components described herein with respect to integrated circuit 100a. Figure 1 The configuration can be configured in a manner described herein. For example, in some embodiments, the programmable ROSC circuit 200b and the programmable delay path circuit 300b can be configured in a manner described herein with... Figure 1 The related programmable ROSC circuit 200a and programmable delay path circuit 300a are also mentioned. In other words, the programmable ROSC circuit 200b can be used for... Figure 1 The programmable ROSC circuit 200a and programmable delay path circuit 300b can be used for Figure 1 The programmable delay path circuit 300a.

[0052] like Figure 2 As shown, TAP 110 can be configured to receive input parameters 112c from outside integrated circuit 100b, send ROSC parameter signals 114a (one or more) to programmable ROSC circuit 200b and path parameters 116a to programmable delay path circuit 300b, and send output (output signal) 112d to outside integrated circuit 100b. For example, in Figure 2In the circuit, input parameter 112c includes test reset (trst), test mode select (tms), test clock (tck), and test data input (tdi), and output 112d includes test data output (tdo). For example, each of parameters trst, tms, tck, tdi, and tdo may have its own dedicated input / output (I / O) pin on integrated circuit 100b. In some embodiments, the test data in tdi may include serial data transmitted according to the test clock tck and control parameters of programmable ROSC circuit 200b and / or programmable delay path circuit 300b. For example, the control parameters may be transmitted to programmable ROSC circuit 200b as ROSC parameter signal 114a and / or to programmable delay path circuit 300b as path parameter 116a. In some embodiments, the test data output tdo may include serial data, which includes outputs (output signals) from the programmable ROSC circuit 200b and / or the programmable delay path circuit 300b that can be transmitted according to the test clock tck. For example, the output may be received from the programmable ROSC circuit as output (output signal) 114b (one or more) and / or from the programmable delay path circuit 300b as output (output signal) 116b (one or more).

[0053] like Figure 2 As shown, in some embodiments, the programmable ROSC circuit 200b may include a ROSC controller 210 and one or more ROSCs 230. In some embodiments, the ROSC controller 210 may be configured to control the operation (or execution) of the ROSCs 230 to generate an output signal (e.g., an oscillator signal), and the ROSC controller 210 may be configured to measure the propagation delay of the ROSCs 230 based on the generated output signal. For example, as Figure 2As shown, ROSC controller 210 can be configured to send one or more ROSC control signals 202 and one or more ROSC selection signals 204 to ROSC 230. In some embodiments, ROSC controller 210 can be configured to generate ROSC control signals 202 and ROSC selection signals 204 based on ROSC parameter signals 114a received via TAP 110. In the illustrated example, ROSC 230 can be configured to generate, select one or more ROSC output signals 206 based on ROSC control signals 202 and ROSC selection signals 204, and transmit one or more ROSC output signals 206 to ROSC controller 210. In some embodiments, ROSC controller 210 can be configured to measure the propagation delay of ROSC 230 based on ROSC output signals 206. In some embodiments, ROSC controller 210 can be configured to determine the central tendency and / or variance of the propagation delay of ROSC 230. In some embodiments, the ROSC controller 210 may be configured to transmit output 114b to TAP 110, wherein output 114b indicates the delay of propagating ROSC 230 (e.g., the central tendency and / or variance of the propagation delay). In embodiments of the invention, the programmable ROSC circuit 200b may be referred to as a programmable circuit, which may include having multiple oscillator stages (hereinafter referred to as...). Figure 5 The programmable oscillator described below is a ROSC-232a-n type oscillator (ROSC 230 or as described below). Figure 5 The described ROSC 230a). The programmable circuit (programmable ROSC circuit 200b) may also include a ROSC controller 210 (or controller), which uses multiple oscillator signals generated by multiple oscillator stages to determine the central tendency and / or variance of the propagation delay of the ROSC 230.

[0054] like Figure 2 As shown, in some embodiments, the programmable delay path circuit 300b may include a delay path controller 310 and one or more delay paths 330. In some embodiments, the delay path controller 310 may be configured to control the operation (or execution) of the delay path 330 to generate an output signal, and the delay path controller 310 may be configured to compare the received output signal with a reference signal to determine whether the propagation delay of the delay path 330 exceeds a threshold delay amount. For example, as Figure 2As shown, the delay path controller 310 can be configured to transmit one or more path and / or clock control signals 301 and one or more path selection signals 306 to the delay path 330. In some embodiments, the delay path controller 310 can be configured to generate the path and / or clock control signals 301 and the path selection signals 306 based on the path parameter signals 116a received via TAP 110. In some embodiments, the delay path 330 can be configured to generate and select one or more path output signals 308 based on the path and / or clock control signals 301 and the path selection signals 306, and send the path output signals 308 to the delay path controller 310. For example, in some embodiments, the delay path 330 can be configured to modify the amount (delay amount) of the cell delay and / or lead delay based on the path and / or clock control signals 301. In some embodiments, the delay path controller 310 can be configured to compare the received output signal (path output signal) 308 with one or more reference signals to determine whether the delay in the output signal 308 exceeds a threshold delay amount. In some embodiments, the delay path controller 310 may be configured to transmit output 116b to TAP 110, wherein output 116b indicates whether the delay in the output signal (path output signal) 308 exceeds a threshold delay amount.

[0055] It should be understood that the TAP 110 can be configured to send and / or receive data with... Figure 2 Different signals and / or different quantities are shown, because the embodiments described herein are not limited thereto.

[0056] Figure 3 This is a block diagram illustrating an exemplary ROSC controller 210 that may be included in integrated circuit 100a or 100b according to some embodiments. Figure 3 As shown, the ROSC controller 210 may include a state machine 212, a thermometer encoding circuit 214, a fast clock counter 216, a ROSC counter 218, a hit counter 220, and a central tendency calculator 222. In some embodiments, the ROSC controller 210 may be configured to send ROSC control signals 202 (one or more) and ROSC selection signals 204 to the ROSC 230, the ROSC controller 210 is configured to receive ROSC outputs 206 (e.g., one or more oscillator signals) from the ROSC 230, and the ROSC controller 210 is further configured to use the ROSC outputs 206 to determine the central tendency and / or variance of the propagation delay of the ROSC 230.

[0057] In some embodiments, state machine 212 may be configured to generate ROSC control signals 202(one or more) using thermometer encoding circuitry 214 and send them to ROSC 230. For example, in some embodiments, state machine 212 may be configured to transmit ROSC parameter signals 114a configured to control the value of control signals 202 to thermometer encoding circuitry 214. In some embodiments, thermometer encoding circuitry 214 may be configured to convert the received signals into parallel thermometer encoding bits suitable for use by ROSC 230. For example, as further described herein, ROSC(one or more) 230 may have multiple ROSC levels or stages, each configured to receive thermometer encoding bits to control multiple ROSC levels active during delayed measurements. In some embodiments, state machine 212 may be configured to receive ROSC selection signal 204 from ROSC parameter signals 114a from TAP 110 and send ROSC selection signal 204 to ROSC(one or more) 230. In some embodiments, ROSC 230 may generate ROSC output (output signal) 206 and provide ROSC output (output signal) 206 to ROSC controller 210 in response to a received ROSC control signal 202.

[0058] In some embodiments, state machine 212 may be configured to determine the propagation delay of ROSC output 206 by using fast clock counter 216 and ROSC counter 218 to determine the pulse width of ROSC output (output signal) 206. For example, in some embodiments, fast clock counter 216 may be configured to receive pulses of a fast clock signal (e.g., included in the ROSC parameter signal 114a received from TAP 110) and increment accordingly. In this example, ROSC counter 218 may be configured to receive pulses of ROSC output 206 and increment accordingly. Furthermore, in this example, state machine 212 may be configured to determine the pulse width of ROSC output 206 by dividing the fast count from fast clock counter 216 by the count of pulses of ROSC output (output signal) 206 from ROSC counter 218. In some embodiments, the ROSC controller 210 (or its state machine 212) is configured to determine the pulse widths of a plurality of oscillator signals (generated by a plurality of oscillator stages), and to use these pulse widths to determine the central tendency of the propagation delay of the programmable circuit (determining the central tendency of the propagation delay of ROSC 230). For example, in one embodiment, ROSC 230 may include a first oscillator stage and a second oscillator stage, the first oscillator stage generating a first oscillator signal and the second oscillator stage generating a second oscillator signal, and the ROSC controller 210 (or its state machine 212) is configured to determine a first pulse width and a second pulse width of the first oscillator signal and the second oscillator signal, respectively, and to use the first pulse width and the second pulse width to determine the central tendency of the propagation delay of the programmable circuit (ROSC 230). Specifically, the ROSC controller 210 (or the state machine 212 of the ROSC controller 210) is configured to, for example, obtain a third pulse width by subtracting the second pulse width from the first pulse width, and then determine the central tendency of the propagation delay of the programmable circuit (ROSC 230) based on the first pulse width and the third pulse width.

[0059] In some embodiments, state machine 212 may be further configured to use hit counter 220 to determine sampling parameters for determining the propagation delay of ROSC output (output signal) 206. For example, in the embodiment described in the previous paragraph, ROSC output 206 includes a first oscillator signal and / or a second oscillator signal, and state machine 212 (hit counter 220 of state machine 212) is configured to use the first oscillator signal and / or the second oscillator signal (ROSC output signal 206) to determine sampling parameters that can be used to determine the central tendency of the propagation delay. In some embodiments, state machine 212 may be configured to determine a prescaler value for fast clock counter 216 and / or ROSC counter 218 based on the pulse count of ROSC output (output signal) 206 stored in hit counter 220. For example, the count stored in hit counter 220 can indicate the number of pulses of ROSC output 206 counted during a measurement cycle. If the number of pulses is less than a threshold number of pulses stored in hit counter 220, state machine 212 can be configured to adjust the prescaler value of fast clock counter 216 and / or ROSC counter 218. Fast counter 216 and / or ROSC counter 218 can be configured to increment configurably relative to the pulses of fast clock and / or ROSC output (output signal) 206, where the frequency can be configured based on the prescaler value. For example, in some embodiments, if less than a threshold number of pulses are stored in hit counter 220 after a measurement cycle, ROSC controller 210 can be configured to adjust the prescaler value to increase the number of counted pulses of ROSC output (output signal) 206 during the next measurement cycle.

[0060] In some embodiments, state machine 212 may be configured to use central tendency calculator 222 to determine the central tendency and / or variance of the propagation delay of ROSC 230. Therefore, ROSC controller 210 is also configured to determine the variance of the propagation delay of the programmable circuit (programmable ROSC circuit 200b or ROSC 230). For example, in some embodiments, state machine 212 may be configured to generate propagation delay measurements for multiple levels of ROSC 230 and provide these propagation delay measurements to central tendency calculator 222 to calculate the central tendency of the multiple levels of propagation delay measurements, such as the mean, median, or mode of the propagation delay measurements. In some embodiments, state machine 212 may also be configured to provide a second set of propagation delay measurements for multiple levels to central tendency calculator 222, and central tendency calculator 222 may be further configured to calculate the variance of the propagation delay measurements. For example, central tendency calculator 222 may also be configured to determine the deviation of each propagation delay measurement from the mean (and / or other central tendency) of the propagation delay and use the mean and deviation to calculate the variance. In some embodiments, the central tendency calculator 222 may alternatively or additionally be configured to calculate the standard deviation of the propagation delay. In embodiments of the invention, the central tendency of the propagation delay of the programmable circuit (programmable ROSC circuit 200b or ROSC 230) may be the average propagation delay of the programmable circuit (programmable ROSC circuit 200b or ROSC 230).

[0061] Figure 4 This is a block diagram illustrating a plurality of exemplary programmable ROSC 230s that may be included in integrated circuits 100a or 100b according to some embodiments. Figure 4As shown, each ROSC 230 can be coupled to the input of a multiplexer (MUX) 240 and configured to receive ROSC control signals 202 (one or more) from a ROSC controller 210. The MUX 240 can be configured to receive ROSC outputs (output signals) 206a-m from the ROSC 230 and a ROSC selection signal 204 from the ROSC controller 210, and select from the ROSC outputs 206a-m as the ROSC output 206 to be output to the ROSC controller 210. In some embodiments, each ROSC 230 can be configured to generate ROSC outputs 206a-m, which may include an oscillator signal generated in response to the ROSC control signal 202. In some embodiments, each ROSC 230 can be configured with different physical parameters. For example, in some embodiments, the transistors of each ROSC 230 can be configured with different gate voltage thresholds. For example, a first programmable ring oscillator (e.g., programmable ROSC 230a) Figure 4 The ROSC_0 includes a first transistor (one or more), and the second programmable ring oscillator (e.g., a programmable ROSC230b (not shown)) Figure 4 ROSC_1) includes a second transistor (one or more), the control terminal threshold voltage of the second transistor is different from the control terminal threshold voltage of the first transistor.

[0062] Figure 5 This illustrates, according to some embodiments, a plurality of ROSC grades 232a-n. Figure 4 A block diagram of the programmable ROSC230a (or ROSC 230a). In some embodiments, Figure 4 Each of the ROSC 230 shown can be configured in the manner described herein with respect to ROSC 230a. In some embodiments, each of the ROSC stages 232a-n is coupled to at least one other ROSC stage, and each of the ROSC stages 232a-n can be configured to receive a corresponding control signal of the ROSC control signal 202 from the controller 210. The ROSC stages 232a-n are selectable in the programmable ROSC 230a, for example, selected using the corresponding control signal to cause the corresponding ROSC stage to produce a ROSC output (oscillator signal). In embodiments of the invention, it can be described that the programmable ROSC 230a has selectable oscillator stages (e.g., multiple selectable oscillator stages ROSC stages 232a-n). For example, in Figure 5 In this context, the first ROSC stage 232a can be configured to receive the Nth control signal (e.g., the Nth bit or byte (or a set of bits)) of the ROSC control signal 202. Figure 5The second ROSC stage 232b can be configured to receive the (N-1)th control signal (e.g., the (N-1)th bit or byte (or bit group, set of bits)) of the ROSC control signal 202. Figure 5 The ROSC control signal is 202[N-1], etc. The control signals for different ROSC levels can be different. For example... Figure 5 As shown, the first ROSC stage 232a can be configured to generate a ROSC output 206a, and the final ROSC stage 232n can be configured to receive a fixed control signal value. Figure 5 In the example, the value is zero (0). Figure 5 The ROSC control signal 202 is shown in the figure [0]. In one embodiment, the programmable ROSC 230a may include multiple subsets, each subset may include one or more of ROSC levels 232a-n, and the ROSC levels included in each subset may be repeated or not. The multiple subsets may include a first subset and a second subset, the first subset may include a first oscillator level (e.g., the first ROSC level 232a), the second subset may include a second oscillator level (e.g., the second ROSC level 232b). The multiple subsets may also include more subsets in a manner similar to the above example, and the first subset may also include a first oscillator level (e.g., the first ROSC level 232a) and a second oscillator level (e.g., the second ROSC level 232b), the second subset may include a third oscillator level (e.g., the third ROSC level 232c), the second subset may also include a third oscillator level (e.g., the third ROSC level 232c) and a fourth oscillator level (e.g., the fourth ROSC level 232d), and so on.

[0063] In some embodiments, ROSC stages 232a-n can be configured as programmable delay paths, and ROSC 230a can be configured to propagate a signal (e.g., an oscillator signal) along the delay path. For example, as Figure 5As shown, each ROSC level 232a-n can be programmable to send and / or receive signals to and / or from at least one other ROSC level. In some embodiments, ROSC levels 232a-n can be switched into and out of a delay path based on ROSC control signal 202. For example, in some embodiments, when a ROSC level switches into a delay path, the ROSC level can be configured to propagate signals received from at least one ROSC level to at least another ROSC level, and when a ROSC level switches out of a delay path, the ROSC level can be configured to prevent signals from at least one ROSC level from reaching at least another ROSC level (stage). In this example, switching ROSC levels 232a-n into and out of a delay path can change the amount of propagation delay in the signal propagating along the programmable delay path, which can be indicated in the ROSC output (output signal) 206a generated at the first ROSC level 232a.

[0064] In some embodiments, subsequent ROSC stages 232a-n (e.g., ROSC stages 232c-d) can be programmable to communicate with and disconnect from previous ROSC stages (e.g., ROSC stages 232a-b). For example, in some embodiments, the ROSC control signal 202 may be thermometer encoded. In this example, in some embodiments, a first state of the ROSC control signal 202 may include an Nth control signal with one bit (1) and the remaining ROSC control signal 202 may have zero bits (0), and a second state of the ROSC control signal 202 may include an Nth control signal with one bit (1), an (N-1)th control signal with one bit (1), and the remaining ROSC control signal 202 may have zero bits (0). Figure 5 In the example, the first state of the ROSC control signal 202 can be configured to switch ROSC level 232a into the delay path and switch all other ROSC levels out of the delay path, and the second state of the ROSC control signal 202 can be configured to switch ROSC levels 232a and 232b into the delay path and switch all other ROSC levels out of the delay path.

[0065] It should be understood that different and / or multiple ROSC stages 232 can be configured to provide ROSC output 206a to the MUX 240. It should also be understood that in some embodiments, the fixed bits received at ROSC stage 232n may include one and / or may include a group of bits. As described above in the embodiments of the present invention, the present invention uses control signals provided to each ROSC stage to generate oscillator signals, and then uses these oscillator signals to determine the central tendency of the propagation delay of the programmable circuit. Therefore, the solution of the present invention is more versatile, and the more general measurement design makes the integrated circuit of the present invention more cost-effective, thus enabling the measurement of the propagation delay of different integrated circuits without requiring excessive test structures.

[0066] Figure 6 The illustration may include, according to some embodiments, the following: Figure 4 The circuit diagram of the programmable ROSC230x in the ROSC 230. In some embodiments, the ROSC 230x can be configured in the manner described herein with respect to the ROSC 230a, including in conjunction with Figure 5 For example, such as Figure 6 As shown, ROSC 230x may include ROSC stages 232a'-n', each ROSC stage 232a'-n' being coupled to at least one other ROSC stage and configured to receive a corresponding control signal from ROSC control signal 202. Also as... Figure 6 As shown, ROSC stage 232a' is configured to generate ROSC output (output signal) 206a' (e.g., for sending to MUX 240), and ROSC stage 232n' is configured to receive a fixed control signal with a zero value.

[0067] In some embodiments, ROSC stages 232a'-n' can be configured as programmable delay paths, and ROSC230x can be configured to propagate the oscillator signal along the delay path. For example, in Figure 6In this example, ROSC stage 232a' includes AND gates 234a and 234b, with multiple logic gates located between them. AND gates 234a and 234b are configured to propagate the oscillator signal. In this example, when the Nth control signal of ROSC control signal 202 is a single bit (1), AND gate 234a can be configured to propagate a zero value through multiple logic gates to generate a single bit (1) at the input of AND gate 234b. This can then generate a single bit (1) at ROSC output 206a' as the rising edge of the oscillator signal at ROSC output 206a'. Similarly, in this example, when a bit (1) appears at ROSC output 206a', the bit (1) at ROSC output 206a' and the Nth control signal can cause AND gate 234a to propagate a value through multiple logic gates to generate a zero at one of the inputs of AND gate 234b. This can then generate a zero at ROSC output 206a' as the falling edge of the oscillator signal at ROSC output 206a'. In some embodiments, ROSC stage 232a' can be configured to continue generating rising and falling edges at ROSC output 206a' to generate pulses of the oscillator signal.

[0068] In some embodiments, ROSC stages 232a'-n' can be switchably entered and exited (switched out) from delay paths based on ROSC control signal 202. For example, in Figure 6 In this context, ROSC stage 232b' includes AND gate 234c and multiple logic gates that are programmable to send oscillator signals to and receive oscillator signals from ROSC stage 232a'. For example, in... Figure 6 In this configuration, when the (N-1)th control signal of ROSC control signal 202 is a zero bit (0), ROSC stage 232b' can be configured to provide a zero bit (0) to ROSC stage 232a'. This prevents signals propagated by multiple logic gates of ROSC stage 232b' from reaching ROSC stage 232a'. For example, a zero bit (0) can maintain one bit (1) as one of the inputs of AND gate 234b, preventing the input of AND gate 234b from changing as signals propagate through multiple logic gates. In this example, ROSC stage 232b' can switch out of the delay path. Alternatively, when the (N-1)th control signal of ROSC control signal 202 is one bit (1), ROSC stage 232b' can be configured to provide one bit (1) to ROSC stage 232a'. This allows the oscillator signal to reach the AND gate 234b of ROSC stage 232a' through AND gate 234c and multiple logic gates propagating ROSC stage 232b', thereby switching ROSC stage 232b' to the delay path. Figure 6As shown, subsequent ROSC stages of ROSC 230x can switch in and out of the delay path in the manner described in this paper for ROSC stage 232b'. It should be understood that, in Figure 6 In the context of the Nth ROSC control signal 202 being a zero bit (0), the ROSC stage 232a' can be configured to switch into and out of the delay path without generating a falling edge at the ROSC output (output signal) 206a'.

[0069] exist Figure 6 In the example, switching the ROSC stage input and output delay paths of ROSC stages 232a'-n' can change the amount of propagation delay in the oscillator signal propagating along the programmable delay path, which can be indicated in the ROSC output (output signal) 206a' generated by the first ROSC stage (stage) 232a'. For example, as described above, when the Nth and (N-1th)th control signals of the ROSC control signal 202 are 1 and 0 bits respectively, the rising and falling edges of the oscillator signal can be generated at the ROSC output 206a' based on the propagation time of the oscillator signal through AND gates 234a and 234b and other logic gates of ROSC stage 232a'. Therefore, the propagation delay of AND gates 234a and 234b and other logic gates of ROSC stage 232a' contributes (helpfully) to the elapsed time between the rising and falling edges of the oscillator signal. As described above, when the Nth and (N-1th)th control signals of ROSC control signal 202 are both 1 bit (1), the rising and falling edges of the oscillator signal can be generated at ROSC output 206a' based on the propagation time of the oscillator signal through AND gates 234a, 234b, and 234c, and other logic gates of ROSC stages 232a' and 232b'. Therefore, the propagation delay of AND gates 234a, 234b, and 234c, and other logic gates of ROSC stages 232a' and 232b', contributes to the elapsed time between the rising and falling edges of the oscillator signal.

[0070] Figure 7 This is a flowchart illustrating an exemplary method 700 for determining the propagation delay of an integrated circuit according to some embodiments. In some embodiments, method 700 may use methods including, but are not limited to, combining... Figure 1-5 The described programmable ROSC circuits 200a and / or 200b are used to perform this. For example, in some embodiments, a ROSC controller coupled to one or more programmable ROSCs may be used to perform method 700. Figure 7As shown, method 700 may include determining a delay sampling parameter for measuring ROSC pulses in step 720, determining the propagation delay of ROSC level (stage) of one or more ROSCs in step 740, and determining the central tendency and / or variance of the propagation delay of one or more ROSCs in step 760.

[0071] In some embodiments, determining the delay sampling parameter at 720 may include determining whether at least a threshold number of ROSC output pulses have been received during a first measurement period. For example, in some embodiments, the ROSC controller may send ROSC control signals to one or more ROSCs, receive outputs from one or more ROSCs, and count the number of ROSC output pulses during the measurement period (e.g., until the fast clock counter of the ROSC controller reaches a predetermined limit). In some embodiments, when it is determined that the number of ROSC output pulses counted during the first measurement period is less than a threshold, method 700 may include adjusting the sampling parameter. For example, in some embodiments, the ROSC controller may adjust the fast clock counter and / or the prescaler value of the ROSC output counter for counting ROSC output pulses and running a second measurement period. In this example, step 720 of determining the delay sampling parameter may be repeated for the second measurement period. It should be understood that some embodiments omit step 720 and proceed to step 740.

[0072] In some embodiments, determining the propagation delay of a ROSC stage of one or more programmable ROSCs in step 740 may include receiving ROSC outputs from the ROSC stage, counting the number of pulses of the ROSC outputs during a measurement period, and counting the number of pulses of a fast clock during the measurement period. For example, in some embodiments, the ROSC controller may divide the number of fast clock pulses counted during the measurement period by the number of ROSC output pulses counted during the measurement period to determine the pulse width of the ROSC outputs in the fast clock pulses. In this example, the frequency of the fast clock may be known such that the pulse width of the ROSC outputs in the fast clock pulses can be converted to time in seconds, for example, via the ROSC controller and / or via another device communicatively coupled to the ROSC controller. In some embodiments, step 740 may be repeated for multiple ROSC stages or for each ROSC stage of a ROSC. In some embodiments, step 720 may be performed for some or each ROSC stage before performing step 740 for a ROSC stage. In some embodiments, the propagation delay determined for a previous ROSC stage may be used to determine the propagation delay of subsequent ROSC stages. For example, a ROSC with ROSC stages A and B, switchable entry and exit (switchout) delay paths, and configured to receive thermometer-encoded control signals, can first determine the propagation delay (first propagation delay) of the delay path including ROSC stage A, then determine the propagation delay (second propagation delay) of the delay path including ROSC stages A and B, and subtract the first propagation delay from the second propagation delay to obtain the propagation delay of ROSC stage B. In some embodiments, for example, ROSC 230 may include a first oscillator stage (first ROSC stage) and a second oscillator stage (second ROSC stage), the first oscillator stage generating a first oscillator signal, the second oscillator stage generating a second oscillator signal, and ROSC controller 210 (or state machine 212 of ROSC controller 210) configured to determine a first pulse width and a second pulse width of the first oscillator signal and the second oscillator signal, respectively, and use the first pulse width and the second pulse width to determine the central tendency of the propagation delay of the programmable circuit (ROSC 230). Specifically, the ROSC controller 210 (or the state machine 212 of the ROSC controller 210) is configured to, for example, obtain a third pulse width by subtracting the second pulse width from the first pulse width, and then determine the central tendency of the propagation delay of the programmable circuit (ROSC 230) based on the first pulse width and the third pulse width.

[0073] In some embodiments, determining the central tendency and / or variance of the propagation delay of ROSC in step 760 may include calculating the central tendency and / or variance using the propagation delay determined in step 740. In some embodiments, step 760 may be performed once step 740 has been performed for multiple ROSC stages of ROSC. For example, in some embodiments, determining the central tendency of the propagation delay of ROSC may include determining the average propagation delay of the ROSC stages for which step 740 was performed. In some embodiments, step 740 may be performed once before determining the central tendency of the propagation delay (e.g., for each ROSC stage) and again after determining the central tendency of the propagation delay (e.g., for each ROSC stage). For example, in some embodiments, step 760 may include determining the variance of the propagation delay using the deviation of the propagation delay of each ROSC stage from the central tendency (e.g., the mean).

[0074] Figure 8 This is a flowchart illustrating an alternative exemplary method 800 for determining the propagation delay of an integrated circuit according to some embodiments. Figure 8 As shown, method 800 may include determining delay sampling parameters for measuring ROSC pulses in step 820, determining the propagation delay of the ROSC phase of one or more ROSCs in step 840, and determining the ability and / or variance of the propagation delay of the ROSC determined at step 860, which can be combined with Figure 7 This is performed here in the manner described for steps 720, 740 and 760 of method 700, and is further described below.

[0075] like Figure 8 As shown, determining the delay sample parameters for measuring the ROSC pulses in step 820 may include initializing the delay sample parameters in step 822. In some embodiments, initializing the delay sample parameters in step 822 may include initializing the prescaler values ​​of the fast clock counter and / or the ROSC counter of the ROSC controller. For example, in some embodiments, the prescaler values ​​may determine how many fast clock pulses pass through each increment of the fast clock counter and / or how many ROSC output pulses pass through each increment of the ROSC counter. In some embodiments, the prescaler values ​​may be set such that initially each increment of the fast clock counter passes through a small number of fast clock pulses and each increment of the ROSC passes through a large number of ROSC output pulse counters. In some embodiments, the prescaler values ​​may be set based on input parameters received via a TAP (e.g., TAP 110).

[0076] In some embodiments, step 820 may further include sampling the ROSC output from ROSC at step 824. For example, in some embodiments, sampling the ROSC output may include incrementing (or accumulating, summing) the ROSC counter based on the pulses of the ROSC output using a delayed sampling parameter (e.g., a parameter initialized in step 822 and / or adjusted in step 828). In this example, the ROSC output may be sampled over one measurement cycle, for example, until the fast clock counter reaches a predetermined count limit and / or the ROSC counter reaches a predetermined count limit.

[0077] In some embodiments, step 820 may further include determining at step 826 whether the count of ROSC output pulses sampled during the measurement period is at least equal to (or greater than) a counting threshold. In some embodiments, step 826 may include comparing a value stored in a hit counter of the ROSC controller after the measurement period with the counting threshold. For example, in some embodiments, the counting threshold may be received via a TAP. In some embodiments, in response to determining that the count of ROSC output pulses is at least not equal to the counting threshold, step 820 may further include adjusting the delay sampling parameters at step 828. For example, in some embodiments, the ROSC controller may change the prescaler value of the fast clock counter and / or the ROSC counter, for example by increasing the number of fast clock pulses passed per increment of the fast clock counter and / or decreasing the number of ROSC output pulses passed per increment of the ROSC counter. The inventors recognize that ROSC output pulses with at least one threshold count per measurement period (e.g., more than 1000 pulses in some applications) can ensure that propagation delay calculations rely on a sufficiently large set of delay measurements to produce accurate results. In some embodiments, the ROSC counter prescaler values ​​can be adjusted until they (ROSC counter prescaler values) reach their minimum values ​​before adjusting the fast clock counter prescaler values. This can increase the number of ROSC counter pulses counted during the measurement period without increasing the duration of the measurement period.

[0078] In some embodiments, after adjusting the delay sample parameter in step 828, method 800 may return to sampling the ROSC output in step 824 using the adjusted sample delay parameter. In some embodiments, if the count of ROSC output pulses is greater than or equal to a count threshold, method 800 may continue to determine the propagation delay of the ROSC level in step 840.

[0079] like Figure 8As shown, determining the propagation delay of the ROSC level of one or more ROSCs in step 840 may include sampling the ROSC output in step 842. In some embodiments, sampling the ROSC output in step 842 may include incrementing a ROSC counter based on the pulses of the ROSC output using delay sampling parameters initialized and / or adjusted during step 820. In this example, the ROSC output may be sampled over one measurement cycle, for example, until the fast clock counter reaches a predetermined count limit and / or the ROSC counter reaches a predetermined count limit.

[0080] In some embodiments, step 840 may further include determining the propagation delay at the ROSC level in step 844, which may be described herein for purposes including Figure 7 Step 840 is performed in the manner described in step 740. In some embodiments, step 840 may further include determining whether a central tendency of the propagation delay of ROSC has been determined prior to step 846. For example, in some embodiments, step 840 may be performed multiple times for the same or multiple ROSC stages, wherein a first iteration of step 840 results in the calculation of the central tendency of the propagation delay (e.g., at step 864), and a second iteration of step 840 results in the calculation of the variance of the propagation delay (e.g., at step 866). In some embodiments, in response to determining that a central tendency of the propagation delay has been previously determined, method 800 may continue at step 848 to determine the difference between the central tendency of the propagation delay and the central tendency of the propagation delay determined for the ROSC level (stage). For example, in some embodiments, the difference between the central tendency of the propagation delay and the propagation delay determined in step 844 may be used to determine the variance of the propagation delay (e.g., at step 866).

[0081] In some embodiments, in response to determining a central tendency for propagation delay that has not been previously determined, and / or after step 848, method 800 may continue to step 850 to determine whether there are additional ROSC levels (stages) for determining propagation delay. In some embodiments, determining whether there are additional ROSC stages may include determining whether all ROSC levels (stages) have been sampled. For example, in some embodiments, in response to determining that one or more ROSC levels (stages) have not been sampled, method 800 may return to and / or repeat steps 820 and / or 840 for the ROSC levels (one or more) that have not been sampled. In this example, steps 820 and / or 840 may be performed one at a time for a single ROSC level (stage). In some embodiments, the determination at step 850 may take into account input parameters received from the TAP indicating which ROSC levels (stages) should be sampled. For example, in some embodiments, input parameters received from the TAP may indicate that only one or a subset of ROSC levels (stages) should be sampled during the execution of method 800. In some embodiments, when it is determined that there are no remaining ROSC stages (or levels) to sample, method 800 may proceed to step 860 to determine the central tendency and / or variance of the propagation delay.

[0082] like Figure 8 As shown, determining the central tendency and / or variance of the propagation delay of ROSC in step 860 may include determining at step 862 whether the central tendency of the propagation delay has been previously determined. In some embodiments, in response to determining that the central tendency of the propagation delay has not been previously determined, method 800 may continue to determine the central tendency of the propagation delay in step 864. Alternatively, in some embodiments, in response to determining a deviation of the central tendency due to a previously determined propagation delay, method 800 may continue to determine the variance of the propagation delay in step 866. In some embodiments, this may be used in conjunction with Figure 7 Step 760 describes the manner in which the determination of the central tendency and / or variance of the propagation delay is performed. In some embodiments, after determining the central tendency of the delay in step 864, method 800 may return to and / or repeat steps 820, 840, and / or 860. For example, in some embodiments, steps 820 and 860 may be performed (e.g., repeated) for each ROSC phase to be sampled (e.g., sampled in previous iterations of steps 820, 840). In some embodiments, method 800 may also include outputting the central tendency and / or variance of the propagation delay to the TAP.

[0083] Figure 9 This illustrates an exemplary delay path controller 310 that can be included in integrated circuit 100a or 100b according to some embodiments (e.g., Figure 2 The block diagram shown is as follows. Figure 9As shown, the delay path controller 310 includes a state machine 312, a clock divider 314, a clock controller 316, a comparator 318, and a hit counter 320. In some embodiments, the delay path controller 310 can be configured to generate and / or transmit path and / or clock control signals 301 and path selection signals 306 to the delay path 330 based on path parameters 116a received from TAP 110. For example, as Figure 9 As shown, the path and / or clock control signal 301 may include a path clock control signal 302, a path delay control signal 304, and a path shift control signal 305. In some embodiments, the delay path controller 310 may be configured to receive a path output (path output signal) 308 from the delay path 330, compare the path output (path output signal) 308 with one or more reference signals, and output the comparison result to TAP 110 as output 116b.

[0084] In some embodiments, state machine 312 may be configured to send a path delay control signal (delay control signal) 304, a path shift control signal 305, and a path selection control signal 306 to the delayed path 330 based on path parameters 116a received from TAP 110. For example, in some embodiments, state machine 312 may be configured to send the path delay control signal 304, path shift control signal 305, and path selection control signal 306 to the delayed path 330 in a manner that signals are received from TAP 110 in input parameters 116a. In some embodiments, state machine 312 may also be configured to generate one or more reference signals for comparator 318 to compare with path output 308. For example, in some embodiments, the reference signals may include a delayed clock signal received from clock divider 314 and / or clock controller 316, and / or a path shift signal received from TAP 110.

[0085] In some embodiments, clock divider 314 and clock controller 316 may be configured to generate a path clock control signal 302 based on a control signal for path parameter 116a received from TAP 110 and send the path clock control signal 302 to the delay path 330. For example, in some embodiments, clock divider 314 may receive a clock divider control signal in path parameter 116a and divide the clock signal based on the clock divider control signal. In some embodiments, clock divider 314 may be configured to provide the divided clock signal to state machine 312 for generating a reference signal. In some embodiments, clock controller 316 may be configured to output a control signal for controlling the clock delay tuner of delay path 330 based on a clock delay control signal received in path parameter 116a.

[0086] In some embodiments, comparator 318 may be configured to receive path output (path output signal) 308 from delay path 330 and generate an output indicating a comparison between path output (path output signal) 308 and one or more reference signals. For example, in some embodiments, comparator 318 may also be configured to receive reference signals (one or more) from state machine 312. In some embodiments, comparator 318 may be configured to determine whether the delay amount of path output (path output signal) 308 and / or indicated by path output (path output signal) 308 is greater than a threshold delay amount. For example, in some embodiments, comparator 318 may be configured to generate a first output when the delay amount of path output (path output signal) 308 and / or indicated by path output (path output signal) 308 is greater than a reference signal and / or indicated by a reference signal, and a second output when the delay amount of path output (path output signal) 308 and / or indicated by path output (path output signal) 308 is less than or equal to the delay amount of reference signal and / or indicated by reference signal.

[0087] In some embodiments, the hit counter 320 may be configured to count the measurement periods for the delay amount of the path output (path output signal) 308 and / or the delay amount indicated by the path output 308 being less than or equal to (or, alternatively, greater than) a threshold delay amount. For example, in some embodiments, the comparator 318 may be configured to output an indication of whether the delay amount of the path output 308 and / or the delay amount indicated by the path output is less than or equal to and / or greater than the threshold delay amount to hit the counter 320, which may be configured to increment for each indication for which the threshold delay amount is not (or, alternatively, is) exceeded. In some embodiments, the hit counter 320 may be configured to output its count to TAP 110 in output 116b.

[0088] It should be understood that in some embodiments, state machine 312 may alternatively or additionally be configured to provide outputs among (a plurality of) outputs 116b.

[0089] Figure 10 This is a block diagram illustrating a plurality of exemplary programmable delay paths 330 that may be included in integrated circuit 100a or 100b according to some embodiments. Figure 10As shown, each programmable delay path 330 can be configured to receive a path clock control signal 302, a path delay control signal 304, and a path shift control signal 305 from a delay path controller 310, and each programmable delay path 330 can be coupled to a MUX 340 to provide path outputs (path output signals) 308a-m as inputs to the MUX 340. In some embodiments, the MUX 340 can be configured to receive a path selection signal 306 from the delay path controller 310 and select from the path outputs (path output signals) 308a-m to provide to the delay path controller 310 as a path output (path output signal) 308. In some embodiments, each programmable delay path 330 can be configured to generate path outputs (path output signals) 308a-308m based on the path clock control signal 302, the path delay control signal 304, and the path shift control signal 305. For example, in some embodiments, the programmable delay path 330 may be configured to propagate a shift control signal using a clock delay based on the path clock control signal 302 and a cell and / or lead delay based on the path delay control signal 304. In some embodiments, the programmable delay path 330 may include a plurality of transistors, each programmable delay path 330 may have a transistor with a channel width different from the channel width of the transistors of the other programmable delay paths 330.

[0090] Figure 11 This is an explanation based on some embodiments. Figure 10 The block diagram of the programmable delay path 330a includes an input clock delay tuner (clock delay tuner) 332a-p, an output clock delay tuner 334a-q, and a path tuner 338a-n. For example... Figure 11 As shown, the delay path 330a may further include input flip-flops 336a-b and output flip-flops 336c. In some embodiments, input flip-flops 336a-b may be configured to receive clock signals from input clock delay tuners 332a-p and path shift control signals 305a and 305b from the delay path controller 310, and provide path shift control signals 305a and 305b to path tuners 338a-n and output flip-flops 336c based on the clock signals. In some embodiments, output flip-flops 336c may also be configured to receive clock signals from output clock delay tuners 334a-q.

[0091] In some embodiments, delay path 330a can be configured to generate path output 308a based on clock control signals 302a and 302b. For example, in some embodiments, input clock delay tuners 332a-332p can be configured to receive a delay between the corresponding control signals (e.g., bits or bytes (or a set of bits)) of clock control signal 302a when path shift element control signal 305a is received at input flip-flops 336a-b and path shift element control signal 305a reaches output flip-flop 336c based on clock control signal 302a via path tuners 338a-n. For example, in Figure 11 In the example, input clock delay tuner 332a receives clock control signal 302a[0], input clock delay tuner 332p receives clock control signal 302a[P], and so on. In this example, input clock delay tuners 332a-332p can be configured to add a delay to the clock signal provided to input flip-flops 336a-b (e.g., received from path delay controller 310). Alternatively or additionally, in some embodiments, between receiving path shift control signal 305a at output flip-flop 336c and generating path output 308a at output flip-flop 336c, output clock delay tuners 334a-q can be configured to receive a corresponding control signal (e.g., a bit or byte (or a set of bits)) of clock control signal 302b and control the delay. For example in Figure 11 In the example, input clock delay tuner 334a receives clock control signal 302b[0], input clock delay tuner 334q receives clock control signal 302b[Q], and so on. For example, in some embodiments, output clock delay tuners 334a-q can be configured to add a delay to the clock signal provided to output flip-flop 336c (e.g., the same clock signal provided to input clock delay tuners 332a-p).

[0092] In some embodiments, the delay path 330a can be further configured to generate a path output (path output signal) 308a based on the received path shift signal and path delay control signal 304. For example, in some embodiments, path tuners 338a-n can be configured to receive individual control signals (e.g., bits or bytes (or a set of bits)) of the path delay control signal 304 and add a certain amount of cell delay and / or lead delay based on the path delay control signal 304. For example, in Figure 11In the example, path tuner 338a is operated based on path delay control signal 304[N], path tuner 338n is operated based on path delay control signal 304[0], and so on. In some embodiments, path tuners 338a-n can be configured to add a programmable scale of cell delay and / or lead delay to the path shift signal. Alternatively or additionally, in some embodiments, path tuners 338a-n can be configured to use a version of the path shift signal propagated by transistors with different voltage thresholds based on the output of path delay control signal 304. In some embodiments, each path tuner 338a-n can be individually programmable (e.g., via a corresponding control signal of path delay control signal 304) to provide different amounts of cell delay and / or lead delay and / or output using path shift signals propagated by transistors with different voltage thresholds.

[0093] Figure 12 This is an explanation based on some embodiments. Figure 11 A block diagram of the input clock delay tuner (clock delay tuner) 332a. In some embodiments, each input clock delay tuner 332a-p and / or output clock delay tuner 334a-q can be configured in the manner described herein with respect to the input clock delay tuner 332a.

[0094] In some embodiments, the input clock delay tuner 332a can be configured to propagate a path clock signal (e.g., from the delay path controller 310) along one or more sub-paths to add a delay to the path clock signal. Figure 12 As shown, the clock delay tuner 332a may include multiple sub-paths 350, including sub-paths 350a-b, each sub-path 350 including one or more logic gates 352, and each sub-path 350 is configured to receive a path clock signal. In some embodiments, each sub-path 350 may be configured to add a different number of unit delays to the path clock signal than other sub-paths 350. For example, in some embodiments, each sub-path 350 may have a different number of logic gates 352 than other sub-paths 350. For example, the number of logic gates 352 in sub-path 350a is different from the number of logic gates 352 in sub-path 350b. For example, the input clock delay tuner 332a may be referred to as the first path delay tuner, and the sub-paths 350a-b may be referred to as optional sub-paths. For example, sub-path 350a may be referred to as the first optional sub-path, including one logic gate 352, and sub-path 350b may be referred to as the second optional sub-path, including two logic gates 352.

[0095] In some embodiments, the clock delay tuner 332a may be further configured to output a version having a path clock signal with a delay amount based on the clock control signal 302. For example... Figure 12As shown, the clock delay tuner 332a may include a MUX 354, which is configured to receive signals from each sub-path 350 and corresponding control signals (e.g., the Pth group of bits of the path clock control signal 302a) of the path clock control signal 302 (clock control signal 302), for example in Figure 12 In the example, the path clock control signal is 302a[P]. For example, in some embodiments, the MUX 354 can be configured to output one of the signals received from the sub-path 350 based on the corresponding path clock control signal received from the delay path controller 310.

[0096] Figure 13 This is an explanation based on some embodiments. Figure 11 A block diagram of path tuner 338a is provided. In some embodiments, each path tuner 338a-n may be configured in the manner described herein with respect to path tuner 338a. In some embodiments, path tuner 338a may be configured to propagate a path shift signal from input flip-flops 336a and / or 336b along one or more sub-paths, add a programmable amount of cell and / or lead delay to the path shift signal, and use logic gates with transistors having selected voltage thresholds. Figure 13 As shown, path tuner 338a may include unit and / or lead delay tuner 360 and voltage threshold tuner 370. In some embodiments, unit and / or lead delay tuner 360 may be configured to receive a first portion (e.g., the Nth) of a corresponding (e.g., the path delay control signal 304) control signal. Figure 13 In the example, 304[N][0] (which may be referred to as the first part of the path delay control signal or the first path delay control signal) and voltage threshold tuner 370 can be configured to receive the second part of the corresponding (e.g., the Nth) control signal of the path delay control signal 304 (e.g., the second part of the path delay control signal 304). Figure 13 In the example, 304[N][1], 304[N][1] may be referred to as the second part of the path delay control signal or the second path delay control signal. The voltage threshold tuner 370 may include a multiplexer 372.

[0097] The unit and / or lead delay tuner 360 can be configured to add a programmable amount of unit and / or lead delay to the received path shift signal based on the path delay control signal 304. For example... Figure 13As shown, the cell and / or lead delay tuner 360 may include a plurality of subpaths 362, including subpaths 362a-d, each subpath 362 including one or more logic gates 364 (e.g., inverters), and each subpath 362 is configured to receive a path shift signal. In some embodiments, some subpaths 362 may be configured to add a cell and / or lead delay amount to the path shift signal that is different from that of other subpaths 362. For example, as Figure 13 As shown, subpaths 362a and 362b can have different numbers of logic gates 364. In this example, the subpath with fewer logic gates can add more lead delay to the path shift signal than the cell delay, and the subpath with more logic gates can add more cell delay to the path shift signal than the lead delay. Also... Figure 13 As shown, the unit and / or lead delay tuner 360 may include multiplexers (MUX) 366a-d, each of which may be configured to receive a path shift signal from the corresponding sub-path pair (a pair of sub-paths) 362 and output one of the path shifts based on the path delay control signal 304.

[0098] In some embodiments, the voltage threshold tuner 370 may be configured to selectively output a path shift signal from the cell and / or lead delay tuner 360, the signal being propagated by logic gates having transistors with different voltage thresholds based on the path delay control signal 304. For example, in some embodiments, logic gates 364 of sub-paths 362a-b may include transistors having a first voltage threshold and logic gates 364 of sub-paths 362c-d may include transistors having a second voltage threshold different from the first voltage threshold.

[0099] Figure 14 This is a flowchart of an exemplary method 1400 for determining the path delay of an integrated circuit according to some embodiments. In some embodiments, method 1400 may be performed using programmable delay path circuits 300a and / or 300b, as included herein. Figure 1-2 and Figure 9-13 As described. For example, in some embodiments, method 1400 can be performed using a path delay controller coupled to one or more programmable delay paths. Figure 14 As shown, method 1400 may include configuring cell delays and lead delays for one or more programmable delay paths in step 1402, and comparing one or more delay path signals with one or more reference signals in step 1404 (or comparing them separately if there are multiple reference signals).

[0100] In some embodiments, configuring the cell delay and lead delay of the programmable delay path in step 1402 may include a delay path controller transmitting multiple control signals to the programmable delay path. For example, in some embodiments, the multiple control signals may include a clock delay control signal, a path delay control signal, and / or a path shift control signal. In some embodiments, the delay path controller may receive and / or generate the control signals in response to path parameters received via TAP. In some embodiments, the programmable delay path may generate a delay path signal based on the received control signals. For example, in some embodiments, the programmable delay path may add a certain amount of cell delay and / or a certain amount of lead delay to the path based on the received control signals. In some embodiments, the multiple control signals may include a path selection signal for selecting a delay path signal from multiple delay path outputs from multiple programmable delay paths. In some embodiments, the delay path controller may receive a delay path signal from the programmable delay path for comparison with a reference signal in step 1404.

[0101] In some embodiments, comparing the delayed path signal with a reference signal may include the delayed path controller generating a reference clock signal and / or a reference path shift signal and comparing the delayed path signal with the reference clock and / or path shift signal. For example, in some embodiments, comparing the delayed path signal with the reference clock and / or path shift signal may generate an output indicating the amount of delay in the delayed path signal. In this example, the output may indicate whether the amount of delay in the delayed path signal is less than or equal to (or, alternatively, greater than) a threshold delay. In some embodiments, steps 1402 and 1404 may be repeated for multiple measurement cycles, and the hit counter of the delayed path controller may count the number of measurement cycles in which the amount of delay in the delayed path is less than or equal to (or, optionally, greater than) the threshold delay. In some embodiments, the delayed path controller may output this number (the number of measurement cycles) from the hit counter via a TAP.

[0102] The various aspects of the apparatus and techniques described herein can be used alone, in combination, or in various arrangements not specifically discussed in the embodiments described above, and are therefore not limited to the combination of the details and arrangements set forth in the foregoing description or shown in the accompanying drawings. For example, an aspect described in one embodiment can be combined in any way with aspects described in other embodiments.

[0103] Although the embodiments and advantages of the present invention have been described in detail, it should be understood that various changes, substitutions, and modifications can be made to the invention without departing from the spirit and scope defined by the claims. The described embodiments are for illustrative purposes only and are not intended to limit the invention. The scope of protection of the invention is defined by the appended claims. Those skilled in the art will be able to make various modifications and refinements without departing from the spirit and scope of the invention.

Claims

1. An integrated circuit, characterized in that, include: A programmable delay path, including a path delay tuner, is configured to receive control signals; And add the cell delay and lead delay based on the control signal to the programmable delay path; as well as The controller is configured to provide the control signal to the programmable delay path, receive a signal from the programmable delay path, and compare the signal with a reference signal.

2. The integrated circuit as described in claim 1, characterized in that, The controller is configured to determine whether the delay of the programmable delay path exceeds a threshold delay by comparing the signal with the reference signal.

3. The integrated circuit as described in claim 1, characterized in that, The path delay tuner includes a first path delay tuner configured as follows: Receive the first control signal from the control signal; When the first control signal has a first state, select the first unit delay amount and the first lead delay amount to add to the programmable delay path; as well as When the first control signal has a second state, the second lead delay amount and the second unit delay amount are selected to the programmable delay path.

4. The integrated circuit as described in claim 3, characterized in that: The first path delay tuner includes: a first optional subpath, including a first number of logic gates; and a second optional subpath, including a second number of logic gates, the second number being different from the first number of logic gates; and The first path delay tuner is configured to select the first optional sub-path when the first control signal has a first state, and to select the second optional sub-path when the first control signal has a second state.

5. The integrated circuit as described in claim 4, characterized in that: The first path delay tuner also includes a third optional sub-path having the first number of logic gates and a fourth optional sub-path having the second number of logic gates. The first optional sub-path and the second optional sub-path include a first transistor, and the third optional sub-path and the fourth optional sub-path include a second transistor. The second transistor has a different control terminal voltage threshold than the first transistor. as well as The first path delay tuner is further configured to receive a second control signal in the control signal, select the first optional sub-path and the second optional sub-path when the second control signal has a first state, and select the third optional sub-path and the fourth optional sub-path when the second control signal has a second state.

6. The integrated circuit as claimed in claim 1, characterized in that, Also includes: The second programmable delay path includes a second path delay tuner configured to receive a second control signal. And add the cell delay and lead delay based on the second control signal to the second programmable delay path. The controller is further configured to provide the second control signal to the second programmable delay path, receive the second signal path from the programmable delay, and compare the second signal with the second reference signal; as well as The programmable delay path includes a first transistor and the second programmable delay path includes a second transistor having a different channel width than the first transistor.

7. An integrated circuit, characterized in that, Includes at least one circuit selected from the group consisting of: A first circuit includes: a programmable ring oscillator, including a first programmable delay path, the programmable ring oscillator being configured to propagate an oscillator signal along the first programmable delay path; wherein the first programmable delay path includes an oscillator stage, the oscillator stage being switchable into and out of the first programmable delay path based on a corresponding first control signal; and / or The second circuit includes: a second programmable delay path, including a path delay tuner configured to: receive a second control signal, and add a cell delay amount and a lead delay amount based on the second control signal to the second programmable delay path; and the second circuit further includes: a controller configured to provide the second control signal to the second programmable delay path, receive a signal from the second programmable delay path, and compare the signal with a reference signal.

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