Solid-state relay control chip circuit
By combining a photodiode and a P-JFET discharge circuit, the problem of solid-state relays being susceptible to interference and malfunctioning under no-light conditions is solved, a stable discharge path is achieved, and the circuit's anti-interference capability and photosensitive surface fill rate are improved.
Patent Information
- Application Number
- CN202511736932.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-25
- Publication Date
- 2026-02-10
AI Technical Summary
Existing solid-state relays are susceptible to dv/dt interference in the absence of light, which can lead to false opening. Furthermore, they lack an effective discharge path, which affects circuit stability.
A photodiode is used to detect photocurrent. Combined with a thyristor control circuit and a P-JFET discharge circuit, the discharge path is closed when there is no light, ensuring stable discharge from the power switch to GND. The discharge path is opened by the P-JFET when the relay is off.
It improves the resistance to dv/dt interference, avoids the use of optoelectronic devices, increases the fill rate of the photosensitive surface, and prevents the reduction of optical power from affecting the control circuit.
Smart Images
Figure CN121508512A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of analog integrated circuit technology, and in particular to a solid-state relay control chip circuit. Background Technology
[0002] A solid-state relay is a component entirely composed of microelectronic devices. It achieves electrical isolation through the photoelectric or electromagnetic conversion characteristics of semiconductor devices and controls the gate of the subsequent power MOSFET to complete the switching. Solid-state relays have many advantages: long lifespan, electrical isolation between the control and output terminals, small size, and short switching time.
[0003] Currently, most solid-state relays on the market use thyristor circuits for discharge. Without light, and after the discharge circuit is complete, there is no low-impedance path between the gate and source terminals of the power transistor at the output. If the drain terminal of the power transistor is disturbed and experiences a high voltage, due to the parasitic parameter C at the gate terminal of the power transistor... gs and C gd The two capacitors couple the high voltage at the drain of the power transistor to the gate. If the coupled gate voltage exceeds the threshold voltage, the power transistor will turn on erroneously. Therefore, this circuit not only requires light to close the discharge circuit and no light to open the discharge circuit, but also needs a branch that can discharge after the discharge is complete in the absence of light. The impedance of this branch increases when there is light. Summary of the Invention
[0004] To address the problem of erroneous activation caused by the aforementioned disturbances, this invention proposes a novel solid-state relay control chip circuit structure. By detecting photocurrent, the thyristor structure is turned off, avoiding the use of optoelectronic devices and improving the fill rate of the photosensitive surface. By introducing a P-JFET (junction field-effect transistor), a discharge path from the power switch to GND (ground) is provided when the relay is off, improving the immunity to dv / dt interference.
[0005] The technical solution of this invention is as follows: A solid-state relay control chip circuit includes: a photodiode, a thyristor control circuit, a thyristor discharge circuit, and a junction field-effect transistor (P-JFET) discharge circuit; the photodiode converts optical signals into electrical signals; the thyristor control circuit controls the opening and closing of the thyristor circuit; the P-JFET discharge circuit is connected to a Zener transistor at the output terminal; the thyristor discharge circuit and the P-JFET discharge circuit are used to close when there is light and open when there is no light.
[0006] The thyristor control circuit includes a first PNP transistor Qp1 and a second NPN transistor Qn2; the thyristor discharge circuit includes a second PNP transistor Qp2 and a first NPN transistor Qn1; and the P-JFET discharge circuit includes a POLY resistor Rpoly and a P-JFET. The specific connection method is as follows: The first PNP transistor Qp1 has a dual-collector structure. Its emitter is connected to the anode of the photodiode, and its base is shorted to the first collector C1 and connected to the output port. The second collector C2 is connected to the base of the second NPN transistor Qn2. The emitter of the second PNP transistor Qp2 is connected to the output port, its base is connected to the anode of the photodiode, and its collector is connected to the base of the first NPN transistor Qn1. The emitter of the first NPN transistor Qn1 is connected to the GND port, and its base is connected to the collector of the second PNP transistor Qp2. The collector of Qp2 is connected to the base of the second PNP transistor Qp2. The emitter of the second NPN transistor Qn2 is connected to the GND port, and its base is connected to the second collector C2 of the first PNP transistor Qp1. The collector of Qp2 is connected to the collector of the second PNP transistor Qp2. The P-JFET source is connected to the cathode of the POLY resistor Rpoly, the drain is connected to the GND port, and the gate is connected to the output port. POLY resistor Rpoly anode connection output port V O The cathode is connected to the collector of the second NPN transistor Qn2.
[0007] The emitter and base of the third PNP transistor Qp3 are shorted together and connected to the output port V. O Connect the collector to the GND port.
[0008] The beneficial technical effects of this invention are as follows: This invention proposes a novel solid-state relay control chip circuit structure. It achieves the shutdown of the thyristor structure by detecting photocurrent, avoiding the use of optoelectronic devices and improving the fill rate of the photosensitive surface. By introducing a P-JFET, a discharge path from the power switch to GND is provided when the relay is off, improving the immunity to dv / dt interference. (See attached figures) To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0009] Figure 1 This is a circuit diagram of a solid-state relay control chip circuit provided in an embodiment of the present invention. Detailed Implementation
[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0011] This invention proposes a solid-state relay control chip circuit, specifically including: a photodiode, a thyristor control circuit, a thyristor discharge circuit, and a P-JFET discharge circuit. The photodiode is used to convert optical signals into electrical signals. The thyristor control circuit includes a first PNP transistor and a second NPN transistor, used to control the opening and closing of the thyristor circuit. The thyristor discharge circuit includes a second PNP transistor and a first NPN transistor. The P-JFET discharge circuit includes a POLY resistor Rpoly and a P-JFET (junction field-effect transistor), used to connect the gate and source of the output power transistor. The thyristor discharge circuit and the P-JFET discharge circuit are used to close when there is light and open when there is no light, discharging the gate charge of the power transistor to complete rapid shutdown.
[0012] Figure 1 The circuit diagram of the solid-state relay control chip circuit proposed in this invention shows that the first PNP transistor Qp1 has a dual-collector structure, with its emitter connected to the anode of the photodiode, and its base shorted to the first collector C1 and connected to the output port V. O The second collector C2 is connected to the base of the second NPN transistor Qn2, and the emitter of the second PNP transistor Qp2 is connected to the output port V. O The base is connected to the anode of the photodiode, and the collector is connected to the base of the first NPN transistor Qn1.
[0013] The emitter and base of the third PNP transistor Qp3 are shorted together and connected to the output port V. O Connect the collector to the GND port.
[0014] The emitter of the first NPN transistor Qn1 is connected to the GND port, and its base is connected to the collector of the second PNP transistor Qp2. The collector of Qp2 is connected to the base of the second PNP transistor Qp2. The emitter of the second NPN transistor Qn2 is connected to the GND port, and its base is connected to the second collector C2 of the first PNP transistor Qp1. The collector of Qp2 is connected to the collector of the second PNP transistor Qp2.
[0015] The source of the first P-JFET is connected to the cathode of the first POLY resistor Rpoly, the drain is connected to the GND port, and the gate is connected to the output port V. O The first POLY resistor Rpoly is connected to the output port V via its anode. O The cathode is connected to the collector of the second NPN transistor Qn2.
[0016] Figure 1 This is a circuit diagram of the solid-state relay control chip circuit proposed in this invention. Its principle is as follows: when there is light, Q... p1 The current will split into two paths. Collector C1 charges Vo, and collector C2 charges Q. n2 Base current, so that Q n2 Conduction, thereby enabling Q n1 The base and emitter are shorted, making Q... n1 Close. Q p2 The base and Q p1 The emitter is shorted, Q p2 emitter and Q p1 When the base is shorted, Q... p1 When forward-biased, its emitter voltage is greater than its base voltage, therefore Q P2 The emitter voltage is less than the base voltage, therefore Q P2 It is also turned off, therefore the thyristor discharge circuit is closed. The photocurrent mainly charges Vo, and the photocurrent loses more maintenance Q compared to the circuit on the previous board. n2 The current at which the light is applied will be low, therefore its peak voltage Vo will be slightly lower. When the light disappears, no photocurrent flows into Q. n2 The base, therefore Q n2 Close. Q p2 The base of the diode will discharge current through the diode, the base voltage will continuously decrease, and the base current will flow through Q. p2 Amplification occurs when the collector current flows into Q. n1 The base, Q n1 The base current is amplified, and its collector current flows into Q. p2 The base of the amplified electrode receives positive feedback until Q is reached. p2 Open, Q n1 The base is pulled up, the emitter is shorted to ground, the emitter junction is forward biased, Q n1 It also turns on, so a thyristor structure turn-on time is also required. Then Vo communicates via Q... p2 Discharge, its collector current flows into Q n1 The base, Q n1 The base current is amplified, and its collector current flows into Q. p2The base of the transistor is positively fed back for amplification. During high-current discharge, when Vo discharges to a certain level, the thyristor structure will shut down, resulting in a tailing phenomenon. Finally, analyzing the branch containing the P-JFET, when Vo is greater than its pinch-off voltage, the P-JFET turns off; when it is less than the pinch-off voltage, it turns on. Its pinch-off voltage must be less than the voltage at which the tailing phenomenon occurs during discharge; otherwise, the tailing phenomenon will occur prematurely. This is because if the pinch-off voltage is greater than the voltage at which the tailing begins, then when the large current Vo discharges to the pinch-off voltage, the P-JFET turns on, and Q... n1 The base and emitter are shorted, Q n1 Therefore, the voltage required to turn on the tail is the greater of the minimum voltage required for the thyristor circuit and the P-JFET pinch-off voltage. Q p3 It is a Zener transistor.
[0017] The advantages of this circuit are as follows: By introducing a P-JFET, the P-JFET is turned on when the relay is off. It forms a loop with the poly resistor, providing a discharge path from the power switch to GND, thus improving the immunity to dv / dt interference. The turn-off of the thyristor structure is achieved by detecting the photocurrent, avoiding the use of optoelectronic devices and improving the fill rate of the photosensitive surface. Furthermore, it prevents the control circuit from being affected by the decrease in light power due to the aging of the LED.
[0018] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A solid-state relay control chip circuit, characterized in that, include: The system includes a photodiode, a thyristor control circuit, a thyristor discharge circuit, and a junction field-effect transistor (P-JFET) discharge circuit. The photodiode converts optical signals into electrical signals. The thyristor control circuit controls the opening and closing of the thyristor circuit. The P-JFET discharge circuit is connected to the Zener transistor at the output terminal. The thyristor discharge circuit and the P-JFET discharge circuit are used to turn off when there is light and turn on when there is no light.
2. The solid-state relay control chip circuit according to claim 1, characterized in that, The thyristor control circuit includes a first PNP transistor Qp1 and a second NPN transistor Qn2; the thyristor discharge circuit includes a second PNP transistor Qp2 and a first NPN transistor Qn1; and the P-JFET discharge circuit includes a POLY resistor Rpoly and a P-JFET. The specific connection method is as follows: The first PNP transistor Qp1 has a dual-collector structure. Its emitter is connected to the anode of the photodiode, and its base is shorted to the first collector C1 and connected to the output port. The second collector C2 is connected to the base of the second NPN transistor Qn2. The emitter of the second PNP transistor Qp2 is connected to the output port, its base is connected to the anode of the photodiode, and its collector is connected to the base of the first NPN transistor Qn1. The emitter of the first NPN transistor Qn1 is connected to the GND port, and its base is connected to the collector of the second PNP transistor Qp2. The collector of Qp2 is connected to the base of the second PNP transistor Qp2. The emitter of the second NPN transistor Qn2 is connected to the GND port, and its base is connected to the second collector C2 of the first PNP transistor Qp1. The collector of Qp2 is connected to the collector of the second PNP transistor Qp2. The P-JFET source is connected to the cathode of the POLY resistor Rpoly, the drain is connected to the GND port, and the gate is connected to the output port. POLY resistor Rpoly anode connection output port V O The cathode is connected to the collector of the second NPN transistor Qn2.
3. The solid-state relay control chip circuit according to claim 2, characterized in that, The Zener transistor is a third-generation PNP transistor Qp3, with its emitter and base shorted and connected to the output port V. O Connect the collector to the GND port.
4. A solid-state relay control chip circuit according to claim 3, characterized in that, The voltage required to initiate the tailing process is the greater of the minimum voltage required for the thyristor circuit and the pinch-off voltage of the P-JFET.