Full duplex digital isolator

Abstract

The invention relates to a full duplex digital isolator. A circuit is provided. The circuit comprises: a first transmitter circuit having a first input terminal arranged to receive first input data and a first node arranged to transmit first intermediate data corresponding to the first input data; a first receiver circuit including a second node arranged to receive the first intermediate data and a first output terminal arranged to generate first output data corresponding to the first input data; comprising a second input terminal and said second node, the second input terminal arranged to receive second input data, the second node further arranged to transmit second intermediate data corresponding to the second input data; and a second receiver circuit comprising a first node and a second output terminal, the first node being further arranged to receive the second intermediate data, and the second output terminal being arranged to generate second output data corresponding to the second input data.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 681,463, entitled “Full Duplex Digital Isolator,” filed August 9, 2024, which is hereby incorporated by reference in its entirety for all purposes. Technical Field

[0003] The described implementation generally relates to electrical isolation in power converters, and more specifically, this implementation relates to a full-duplex digital isolator for signal isolation in power converters. Background Technology

[0004] Electronic devices such as computers, servers, and televisions employ one or more power conversion circuits to convert one form of electrical energy into another. Some power conversion circuits use a circuit topology called a DC-DC converter to convert high (or low) DC voltage to lower (or higher) DC voltage. Because many electronic devices are sensitive to the size and efficiency of power conversion circuits, newer power converters can offer relatively high efficiency and a smaller size for newer electronic devices. Power converters can utilize isolators. Isolators can be implemented to separate circuits or sections of circuitry from each other, protecting them from unwanted influences such as, but not limited to, other circuits or sections of circuitry, to minimize the effects of common-mode transients (CMT), radiated or electromagnetic interference, and crosstalk between circuits or sections of circuitry. Capacitive isolation can be used for electrical isolation to isolate high voltages from each other or to isolate low-voltage command circuitry from high-voltage power supply circuitry. Summary of the Invention

[0005] In some embodiments, a circuit is disclosed. The circuit includes: a first transmitter circuit including a first input terminal and a first node, the first input terminal being configured to receive first input data, and the first node being configured to transmit first intermediate data corresponding to the first input data; a first receiver circuit including a second node and a first output terminal, the second node being configured to receive the first intermediate data, and the first output terminal being configured to generate first output data corresponding to the first input data; a second transmitter circuit including a second input terminal and a second node, the second input terminal being configured to receive second input data, and the second node being further configured to transmit second intermediate data corresponding to the second input data; and a second receiver circuit including the first node and a second output terminal, the first node being further configured to receive the second intermediate data, and the second output terminal being configured to generate second output data corresponding to the second input data.

[0006] In some implementations, the first node includes a first pair of differential isolation capacitors.

[0007] In some implementations, the second node includes a second pair of differential isolation capacitors.

[0008] In some implementations, each of the first pair of differential isolation capacitors includes a first top plate and a first bottom plate, each of the first top plates being coupled to the second node, and each of the first bottom plates being coupled to the first transmitter circuit.

[0009] In some embodiments, each of the first pair of differential isolation capacitors further includes a second top plate attached to the first top plate and a second bottom plate separate from the first bottom plate.

[0010] In some implementations, each of the second top plates is coupled to the second node, and each of the second bottom plates is coupled to the second receiver circuit.

[0011] In some implementations, each of the second pair of differential isolation capacitors includes a third top plate and a third bottom plate, wherein each of the third top plates is coupled to a corresponding first top plate.

[0012] In some implementations, each of the third base plates is coupled to the first receiver circuit.

[0013] In some embodiments, each of the second pair of differential isolation capacitors further includes a fourth top plate attached to the third top plate and a fourth bottom plate separate from the third bottom plate.

[0014] In some implementations, each of the fourth base plates is coupled to the second transmitter circuit.

[0015] In some implementations, the first transmitter circuit and the second receiver circuit are arranged to operate relative to a first ground, and the first receiver circuit and the second transmitter circuit are arranged to operate relative to a second ground.

[0016] In some implementations, the second input data includes fault data from the high side of the half-bridge circuit.

[0017] In some implementations, the second input data includes over-temperature or over-current condition data from the high side of the half-bridge circuit.

[0018] In some embodiments, a method for operating a circuit is disclosed. The method includes: providing a first transmitter circuit, the first transmitter circuit including a first input terminal and a first node; providing a first receiver circuit, the first receiver circuit including a second node and a first output terminal; providing a second transmitter circuit, the second transmitter circuit including a second input terminal and a second node; providing a second receiver circuit, the second receiver circuit including the first node and a second output terminal; receiving first input data by the first transmitter circuit; transmitting first intermediate data corresponding to the first input data by the first transmitter circuit; receiving the first intermediate data by the second receiver circuit; and generating first output data corresponding to the first input data by the first receiver circuit.

[0019] In some implementations, the method further includes receiving second input data by the second transmitter circuit; transmitting second intermediate data corresponding to the second input data by the second transmitter circuit; receiving the second intermediate data by the second receiver circuit; and generating second output data corresponding to the second input data by the second receiver circuit.

[0020] In some embodiments, a circuit is disclosed. The circuit includes: a first transmitter circuit having a first input terminal and a first node, the first input terminal being arranged to receive first input data, and the first node being arranged to transmit first intermediate data corresponding to the first input data; a first receiver circuit having a second node and a first output terminal, the second node being arranged to receive the first intermediate data, and the first output terminal being arranged to generate first output data corresponding to the first input data; and a second transmitter circuit having a second input terminal and a second node, the second input terminal being arranged to receive second input data, and the second node being further arranged to transmit second intermediate data corresponding to the second input data. Attached Figure Description

[0021] Figure 1 A full-duplex digital isolator based on several implementation schemes was demonstrated;

[0022] Figure 2A and 2B Demonstrates according to some implementation schemes Figure 1 The data modulation scheme for the forward channel of a full-duplex digital isolator; and

[0023] Figure 3A and 3B A full-duplex communication scheme with multiplexed return channels is demonstrated according to some implementation schemes. Detailed Implementation

[0024] The circuits, apparatuses, and related techniques disclosed herein generally relate to electrical isolation in power converters. More specifically, the circuits, apparatuses, and related techniques disclosed herein relate to full-duplex digital isolators in power converters and traction inverters. In some embodiments, the full-duplex digital isolator may include bidirectional data transmission. In various embodiments, in addition to a forward channel, the full-duplex digital isolator may have a feedback channel. The feedback channel may be arranged to transmit status information and / or transmit low-bit stream data, such as, but not limited to, the operating temperature and / or fault condition signals of the power converter. The circuits and techniques disclosed herein enable the use of relatively low speeds in the feedback channel.

[0025] Furthermore, the techniques disclosed herein can generate backhaul data that may have relatively relaxed distortion constraints. In current methods, a specific reverse channel can be used for backhaul. This can be relatively costly due to the use of additional high-voltage capacitors and / or transformers. It can also have relatively high current consumption. In addition, using a specific reverse channel can increase die size and limit package selection. The embodiments disclosed herein enable data backhaul through the same isolator channel without the need for additional differential capacitor isolation channels.

[0026] In some implementations, a full-duplex digital isolator may include a forward isolation channel using differential capacitors and a feedback channel that may use the same differential capacitors. The forward channel may include a transmitter, an isolator, and a receiver. The transmitter may include a first modulator and a first driver, and is arranged to receive input data and generate output data transmitted to the receiver via the differential capacitors. The receiver may include a first receiver and a first demodulator, and may be arranged to receive signals from the differential capacitors. The transmitter may operate with reference to a first ground (low ground), and the receiver may operate with reference to a second ground (high ground).

[0027] The feedback channel may have a feedback channel transmitter including a second modulator and a second driver, and may be arranged to transmit feedback data through the same differential capacitor. The feedback channel may further include a feedback receiver, which may include a second receiver and a second demodulator. The isolation capacitor may use the same top plate as the top plate used for transmitting forward data, but may additionally include a differential base plate. In some embodiments, the capacitive isolation channel may include a common top plate and separate base plates. In this way, the number of high-voltage bonding wires between the low-voltage ground die and the high-voltage ground die can remain the same, thereby saving cost and package space.

[0028] In various embodiments, the forward channel may include transmitter circuitry having input terminals arranged to receive input data and transmission nodes arranged to transmit intermediate data corresponding to the input data. The forward channel may also include receiver circuitry having receiving nodes arranged to receive intermediate data and output terminals arranged to generate output data corresponding to the input data. The forward channel may further include dV / dt detector circuitry, which controls the generation of output data based at least in part on the sensed rate of change of voltage.

[0029] In some implementations, the power converter may use gallium nitride (GaN)-based switches or silicon carbide (SiC)-based switches. Compared to silicon-based switches, these switches can operate at relatively higher frequencies and switch relatively quickly, thus potentially causing relatively fast dV / dt events in these power converters, leading to severe ringing and EMI. Embodiments of this disclosure can handle relatively fast dV / dt events, thereby ensuring data transmission integrity, reducing ringing, and reducing EMI. Furthermore, embodiments of this disclosure can reduce parasitic elements in the data transmission channel, further reducing ringing and EMI. Various inventive embodiments, including methods, processes, systems, apparatuses, etc., are described herein.

[0030] Several illustrative embodiments will now be described with respect to the accompanying drawings, which form a part thereof. The following description provides embodiments only and is not intended to limit the scope, applicability, or configuration of this disclosure. Rather, the subsequent description of embodiments will provide those skilled in the art with a feasible description for implementing one or more embodiments. It should be understood that various changes may be made in terms of the function and arrangement of elements without departing from the spirit and scope of this disclosure. In the following description, specific details are set forth for illustrative purposes to provide a thorough understanding of certain inventive embodiments. However, it will be apparent, however, that various embodiments may be practiced without these specific details. The drawings and description are not intended to be limiting. The words “example” or “exemplary” are used herein to mean “serves as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” or “example” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0031] Figure 1 A full-duplex digital isolator according to some embodiments is illustrated. The full-duplex digital isolator 100 may include a forward channel 102 and a feedback channel 104. The forward channel 102 may include a modulator 106 and a driver 108. The modulator 106 and the driver 108 may form a transmitter segment of the forward channel 102. The driver 108 may be differentially coupled to a differential capacitor 110. The differential capacitor 110 may be coupled to a differential capacitor 118 via wire bonding 116. The differential capacitor 118 may be coupled to a receiver 124. The receiver 124 may be coupled to a demodulator 127. The receiver 124 and the demodulator 127 may form a receiver segment of the forward channel 102.

[0032] Feedback channel 104 may include a modulator 126 coupled to driver 128. Modulator 126 and driver 128 may form the transmitter segment of feedback channel 104. Driver 128 may be coupled to differential capacitor 118. Differential capacitor 118 may be coupled to differential capacitor 110 via wire bonding 116. Differential capacitor 110 may be coupled to receiver 130. Receiver 130 may be coupled to demodulator 132. Receiver 130 and demodulator 132 may form the receiver segment of feedback channel 104. Forward channel 102 may be arranged to receive input data 150 and generate output data 152. Feedback channel 104 may be arranged to receive input data 154 and generate output data 156.

[0033] To enable the feedback channel to use the same isolation capacitors, each top plate of the differential capacitor 110 can have a relatively small increase in area, as shown in 112 and 114. Relatively smaller bottom plates corresponding to 112 and 114 can also be added to each differential capacitor in the differential capacitor 110. Additionally, each top plate of the differential capacitor 118 can have a relatively small increase in size, as shown in 120 and 122. Relatively smaller bottom plates corresponding to 120 and 122 can also be added to the differential capacitor 118. In this way, the feedback channel 104 can use the same isolation capacitors as the forward channel 102. The left side of the full-duplex digital isolator 100 can operate with reference to GND1, while the right side of the full-duplex digital isolator 100 can operate with reference to GND2. In some embodiments, GND1 can be a low-voltage ground, and GND2 can be a high-voltage ground.

[0034] In some embodiments, receiver 124 can operate at a common-mode current level suitable for relatively high levels of dV / dt events. This reduces the sensitivity of receiver 124 because it can use a relatively low common-mode input impedance value. The circuitry and techniques disclosed herein enable the use of receiver 130, which can operate with reduced dV / dt robustness, since feedback channel 104 can transmit at a relatively low data rate in the absence of dV / dt events. In this way, the sensitivity of receiver 130 can be improved, thereby enabling a relatively small input differential signal. Therefore, the added capacitor plate segments 112, 114, 120, and 122 can have a relatively small size. In some embodiments, the increase in size of differential capacitors 110 and 118 can be, for example, 10% to 20% of their original size.

[0035] To prevent a fault status signal transmitted by feedback channel 104 from blocking data transmission in forward channel 102, the transmitter section of feedback channel 104 can listen for transmissions in forward channel 102 before attempting to transmit data through the feedback channel. In this way, when a fault is detected on the high-voltage section of the circuit operating on reference GND2, the low-voltage section operating on reference GND1 can prevent the transmitter section of forward channel 102 from transmitting data during a fault condition, thus protecting the system. The output of forward channel 102 can determine the presence of a fault when feedback channel 104 is transmitting a fault status signal. When this condition occurs, receiver 124 can ignore its input signal, as it may be corrupted by driver 128. Modulator 106 may not yet be aware that the secondary side is attempting to transmit a fault status signal. Driver 108 can continue transmitting data between transitions; however, driver 128 can transmit a relatively fast fault signal that can be detected by receiver 130. In this way, driver 108 can continue transmitting data.

[0036] In some implementations, the high-voltage section of the circuit can self-protect by setting its output to zero. In various implementations, this can optionally be performed via a soft disconnect, and the high-voltage section of the circuit can stop listening to the low-voltage section. In some implementations, the high-voltage section can attempt to send feedback to the low-voltage section via feedback channel 104. In various implementations, the transmitter section of the forward channel 102 may not continuously transmit transients at relatively high frequencies (e.g., in power electronics applications, where the bit current may be relatively low, such as below 1 Mb / s). In various implementations, such as in pulse modulation, the transmitter on the forward channel 102 may be inactive for periods of time (e.g., hundreds of nanoseconds).

[0037] In such implementations, when a fault condition needs to be reported, feedback channel 104 may transmit a modulation pattern, for example, at tens of MHz, which may be an HF carrier. While feedback channel 104 transmits this pattern for several microseconds, there may be a period when the transmitter of the forward channel may be inactive, allowing receiver 130 to be enabled to receive the feedback signal transmitted by feedback channel 104. Receiver 130 may receive the same signal while the transmitter of the forward channel is transmitting data, where the received signal may be filtered and / or blanked. In the event of a relatively high dV / dt event, the input of receiver 130 may enter its ESD track, thereby blanking any received signal. In such cases, receiver 130 may be self-blanking. When the dV / dt event is relatively small, in the event of a detected fault, receiver 130 may be able to receive the feedback signal from the transmitter of the feedback channel.

[0038] refer to Figure 1When the low-voltage segment operating with reference to GND1 determines that a fault condition needs to be cleared, the duration of the fault feedback can be limited. In this embodiment, when the input data rate is below, for example, 1 Mb / s, the full-duplex digital isolator 100 can modulate the fault data on the feedback channel 104 for, for example, a few microseconds. In some embodiments, the time period can be increased when a relatively high dv / dt is detected. In this way, the low-voltage segment can detect a fault within, for example, a few microseconds. Once detected, the microcontroller on the low-voltage segment can disable the low-voltage segment for the desired time period. When the disable condition is removed, the gain on the high-voltage side can be activated. The full-duplex digital isolator 100 can repeat this sequence as long as a fault condition exists.

[0039] Figure 2A and 2B A data modulation scheme for the forward channel 102 according to some embodiments is shown. In some embodiments, the modulation scheme shown can be used for low-power and / or low-activity modulation. Segments 202, 204, 206, 208, and 210 are marked as silent periods. In the shown embodiments, the forward channel transmitter may not transmit. For example, when CK = 3MHz and data IN < 1MHz, each of segments 202, 204, 206, 208, and 210 is approximately 300 nanoseconds. In the shown example, when the feedback channel transmitter transmits back a 30MHz carrier in the event of a fault during a 4-microsecond period, the forward channel transmitter can detect four consecutive edges [S(220) / R(222) / S(224) / R(226)] within a 200-nanosecond period, thereby triggering a fault state (FLT) on the forward channel transmitter side. Any activity on the forward channel transmitter can reset the fault detector receiver, or digital filtering can be used. Fault conditions can be detected, for example, within 1 microsecond.

[0040] refer to Figure 1A full-duplex communication scheme is described according to some embodiments. The forward channel 102 can use a specific modulation in which information is transmitted on edges. Each edge can be precisely detected, i.e., a rising edge (setting) or a falling edge (resetting). In this scheme, additional high-pass filtering may not be used, as such filtering could add a tail after each edge. Due to various circuit mismatches, a minimum signal threshold can be used to safely detect setting or resetting. The feedback channel 104 can use a scheme based on a relatively fast periodic signal, which can have self-sufficient redundancy. In this way, the corresponding detector may not use a minimum detection threshold. In this modulation scheme, changes are detected. Therefore, embodiments of this disclosure enable the use of receivers with higher sensitivity to small signals. Since tailing is not a problem in this scheme, additional filtering of common-mode current can be used. In the disclosed full-duplex communication scheme (fast forward, slow reverse), the high-frequency carrier used by driver 128 can be relatively small, so as not to trigger receiver 124, but large enough to trigger receiver 130. The embodiments of this disclosure enable the use of driver 108 without damaging the data used by receiver 130. Due to the relatively low-frequency modulation of the forward channel 102, very few edges can be used in the shown modulation scheme. Digital filtering at demodulator 132 can remove such crosstalk pulses.

[0041] Figure 3A and 3B A full-duplex communication scheme with a multiplexed return channel is illustrated according to some embodiments. In the illustrated communication scheme, the feedback channel 104 can transmit continuous setting, continuous reset, alternating S / R, or nothing. Those skilled in the art will understand, and benefit from, that other modes can be used, and said other modes are also within the scope of this disclosure. For example, when the detector receives the first edge, if the second edge is within approximately 4 nanoseconds, the second edge can be blanked. The above four modes may be corrupted by a small amount of S / R signal from the low-frequency modulation of the forward channel. However, redundant filtering of the previous modes can be used. With these four modes, the feedback channel 104 can, for example, transmit "1" or "0" to two different registers while using a single transmission channel.

[0042] In some implementations, combinations of the circuits and methods disclosed herein can be used to provide full-duplex digital isolation. While circuits and methods are described and illustrated herein for several specific configurations of full-duplex digital isolation, embodiments of this disclosure are suitable for other configurations of signal isolation in power converters. For example, solid-state lighting and / or traction inverter systems may employ embodiments of the full-duplex signal isolation disclosed herein.

[0043] In the foregoing description, numerous specific details have been described with reference to embodiments of this disclosure, which may vary depending on the specific implementation. Therefore, the description and drawings should be considered illustrative rather than restrictive. The unique and exclusive indication of the scope of this disclosure, and what the applicant wishes to define as the scope of this disclosure, is the literal and equivalent scope of the claims published in this application, taking the specific form published by those claims, including any subsequent amendments. Specific details of particular embodiments may be combined in any suitable manner without departing from the spirit and scope of embodiments of this disclosure.

[0044] Additionally, spatially relative terms, such as “bottom” or “top,” may be used to describe the relationship of one element and / or feature to another, as illustrated in the figures. It should be understood that spatially relative terms are intended to cover different orientations of the device in use and / or operation than those depicted in the figures. For example, if the device in the figures is flipped, the element described as the “bottom” surface may then be oriented “above” other elements or features. The device may be oriented in other ways (e.g., rotated 90 degrees or otherwise) and may be interpreted accordingly by the spatially relative descriptors used herein.

[0045] As used herein, the terms “and,” “or,” and “and / or” can have a variety of meanings, which are also expected to depend at least in part on the context in which the terms are used. Generally, “or,” when used in a list of associations (such as A, B, or C), is intended to mean A, B, and C (used herein in an inclusive sense) and A, B, or C (used herein in an exclusive sense). Additionally, the term “one or more” as used herein can be used to describe any feature, structure, or property in the singular form, or can be used to describe some combination of features, structures, or properties. However, it should be noted that this is merely an illustrative example and the claimed subject matter is not limited to this example. Furthermore, the term “at least one of…” when used in a list of associations (such as A, B, or C) can be interpreted as meaning any combination of A, B, and / or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, etc.

[0046] Throughout this specification, references to “an example,” “example,” “some examples,” or “exemplary embodiment” mean that a particular feature, structure, or characteristic described in conjunction with a feature and / or example may be included in at least one feature and / or example of the claimed subject matter. Therefore, the phrases “in an example,” “example,” “in some examples,” “in some embodiments,” or other similar phrases appearing throughout this specification do not necessarily refer to the same feature, example, and / or limitation. Furthermore, a particular feature, structure, or characteristic may be combined into one or more examples and / or features.

[0047] In the foregoing detailed description, numerous specific details have been set forth to provide a thorough understanding of the claimed subject matter. However, those skilled in the art will understand that the claimed subject matter can be practiced without these specific details. In other instances, methods and apparatus known to those of ordinary skill in the art have not been described in detail to avoid obscuring the claimed subject matter. Therefore, the claimed subject matter is not limited to the specific examples disclosed, but rather includes all aspects falling within the scope of the appended claims and their equivalents.

Claims

1. A circuit comprising: A first transmitter circuit includes a first input terminal and a first node. The first input terminal is arranged to receive first input data, and the first node is arranged to transmit first intermediate data corresponding to the first input data. A first receiver circuit, comprising a second node and a first output terminal, wherein the second node is arranged to receive the first intermediate data and the first output terminal is arranged to generate first output data corresponding to the first input data; The second transmitter circuit includes a second input terminal and a second node, the second input terminal being arranged to receive second input data, and the second node being further arranged to transmit second intermediate data corresponding to the second input data; as well as The second receiver circuit includes the first node and the second output terminal, the first node being further arranged to receive the second intermediate data, and the second output terminal being arranged to generate second output data corresponding to the second input data.

2. The circuit of claim 1, wherein the first node comprises a first pair of differential isolation capacitors.

3. The circuit of claim 2, wherein the second node comprises a second pair of differential isolation capacitors.

4. The circuit of claim 3, wherein each of the first pair of differential isolation capacitors comprises a first top plate and a first bottom plate, each of the first top plates being coupled to the second node, and each of the first bottom plates being coupled to the first transmitter circuit.

5. The circuit of claim 4, wherein each of the first pair of differential isolation capacitors further comprises a second top plate attached to the first top plate and a second bottom plate separate from the first bottom plate.

6. The circuit of claim 5, wherein each of the second top plates is coupled to the second node, and each of the second bottom plates is coupled to the second receiver circuit.

7. The circuit of claim 6, wherein each of the second pair of differential isolation capacitors comprises a third top plate and a third bottom plate, each of the third top plates being coupled to a corresponding first top plate.

8. The circuit of claim 7, wherein each of the third base plates is coupled to the first receiver circuit.

9. The circuit of claim 8, wherein each of the second pair of differential isolation capacitors further comprises a fourth top plate attached to the third top plate and a fourth bottom plate separate from the third bottom plate.

10. The circuit of claim 9, wherein each of the fourth base plates is coupled to the second transmitter circuit.

11. The circuit of claim 1, wherein the first transmitter circuit and the second receiver circuit are arranged to operate relative to a first ground, and the first receiver circuit and the second transmitter circuit are arranged to operate relative to a second ground.

12. The circuit of claim 1, wherein the second input data includes fault data from the high side of the half-bridge circuit.

13. The circuit of claim 1, wherein the second input data includes over-temperature or over-current condition data from the high side of the half-bridge circuit.

14. A method of operating a circuit, the method comprising: A first transmitter circuit is provided, the first transmitter circuit including a first input terminal and a first node; A first receiver circuit is provided, the first receiver circuit including a second node and a first output terminal; A second transmitter circuit is provided, the second transmitter circuit including a second input terminal and a second node; A second receiver circuit is provided, the second receiver circuit including the first node and the second output terminal; The first input data is received by the first transmitter circuit; The first intermediate data corresponding to the first input data is transmitted by the first transmitter circuit; The first intermediate data is received by the second receiver circuit; as well as The first receiver circuit generates first output data corresponding to the first input data.

15. The method of claim 14, further comprising: The second input data is received by the second transmitter circuit; The second transmitter circuit transmits second intermediate data corresponding to the second input data; The second intermediate data is received by the second receiver circuit; as well as The second receiver circuit generates second output data corresponding to the second input data.

16. The method of claim 14, wherein the first transmitter circuit and the second receiver circuit are arranged to operate relative to a first ground, and the first receiver circuit and the second transmitter circuit are arranged to operate relative to a second ground.

17. A circuit comprising: A first transmitter circuit has a first input terminal and a first node, the first input terminal being arranged to receive first input data, and the first node being arranged to transmit first intermediate data corresponding to the first input data. A first receiver circuit has a second node and a first output terminal, the second node being arranged to receive the first intermediate data, and the first output terminal being arranged to generate first output data corresponding to the first input data. as well as The second transmitter circuit has a second input terminal and a second node, the second input terminal being arranged to receive second input data, and the second node being further arranged to transmit second intermediate data corresponding to the second input data.

18. The circuit of claim 17, further comprising a second receiver circuit including the first node and a second output terminal, the first node being further arranged to receive the second intermediate data, and the second output terminal being arranged to generate second output data corresponding to the second input data.

19. The circuit of claim 18, wherein the first transmitter circuit and the second receiver circuit are arranged to operate relative to a first ground, and the first receiver circuit and the second transmitter circuit are arranged to operate relative to a second ground.

20. The circuit of claim 17, wherein the second input data includes over-temperature or over-current condition data from the high side of the half-bridge circuit.

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