Signal transmission device and electronic equipment

Abstract

The embodiment of the invention provides a signal transmission device applied to the interior of a chip and electronic equipment, the signal transmission device comprises a signal sending unit, a signal receiving unit and a signal transmission line, and the signal sending unit and the signal receiving unit are directly and electrically connected through the signal transmission line; the signal sending unit is configured to send a target signal to the signal receiving unit through the signal transmission line; the signal receiving unit comprises a sensitive amplifier, and the target signal is received and processed by the sensitive amplifier to obtain an output signal. The signal transmission device can work under low-voltage swing, the power consumption is reduced, and the signal transmission speed is greatly improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a signal transmission device and an electronic device. BACKGROUND

[0002] Long line signal generally refers to the case that the geometric length of a transmission line is comparable to or longer than the wavelength of a signal transmitted by the transmission line. Inside a chip, there are many long line signals to be transmitted. Long line signal transmission has the characteristics of slow speed and high voltage drop. SUMMARY

[0003] At least some embodiments of the present disclosure provide a signal transmission device applied to a chip, which comprises a signal sending unit, a signal receiving unit and a signal transmission line, wherein the signal sending unit and the signal receiving unit are directly electrically connected through the signal transmission line; the signal sending unit is configured to send a target signal to the signal receiving unit through the signal transmission line; and the signal receiving unit comprises a sensitive amplifier, and the target signal is received and processed by the sensitive amplifier to obtain an output signal.

[0004] Some embodiments of the present disclosure further provide an electronic device comprising the signal transmission device provided by any of the embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0005] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some of the embodiments of the present disclosure, but not limit the present disclosure.

[0006] Figure 1 A schematic diagram of long line transmission inside a chip;

[0007] Figure 2 A structural schematic diagram of the signal transmission device provided by some embodiments of the present disclosure;

[0008] Figure 3 A structural schematic diagram of another signal transmission device provided by some embodiments of the present disclosure;

[0009] Figure 4 A circuit diagram of a voltage-type latch sensitive amplifier provided by some embodiments of the present disclosure;

[0010] Figure 5 A waveform diagram of an enable signal and an output signal during the working process of the voltage-type latch sensitive amplifier shown in Figure 4

[0011] Figure 6 A circuit diagram of a current-type latch sensitive amplifier provided by some embodiments of the present disclosure; and​

[0012] Figure 7 A structural schematic diagram of an electronic device provided for some embodiments of the present disclosure. DETAILED DESCRIPTION

[0013] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without any inventive effort fall within the protection scope of the present disclosure.

[0014] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as having the common meaning in the field of the present disclosure to which the present disclosure pertains. The terms “first”, “second” and similar terms used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. The terms “include” or “contain” and similar terms mean that the components or objects before the terms encompass the components or objects listed after the terms and their equivalents, without excluding other components or objects. The terms “connect” or “connected” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper”, “lower”, “left”, “right” and the like only represent relative positional relationships, which can change accordingly when the absolute positions of the described objects change.

[0015] The present disclosure will be described below through several specific embodiments. In order to keep the following description of the embodiments of the present disclosure clear and concise, the detailed description of known functions and known components can be omitted. When any component of the embodiments of the present disclosure appears in more than one drawing, the component is denoted by the same or similar reference numeral in each drawing.

[0016] In order to reduce the negative effects caused by slow speed and high voltage drop characteristics during long line signal transmission, the current solution is to insert a D flip-flop (DFF) in the transmission path of the long line signal, and to insert a certain number of inverters at equal intervals between two D flip-flops. The original long line is divided into shorter segments, and the capacitance and resistance of each transmission line segment are relatively reduced compared to the original long line, thereby achieving an increase in working frequency.

[0017] A D flip-flop is a circuit element capable of storing a one-bit binary data state, with a memory function. It updates its output state under the control of a clock signal, ensuring that the state of the input signal is captured and stored at a specific edge (usually the rising or falling edge) of the clock signal.

[0018] A D flip-flop can generally include the following four main ports: data input D, which receives the binary data to be stored; clock input CLK, which controls the source of the signal that updates the flip-flop state; data output Q, which outputs the current state of the flip-flop, synchronized with the value of the data input D at the clock edge; and inverted output Q': which outputs the inverted state of Q.

[0019] Without a clock signal, the D flip-flop remains unchanged in its current state. When the clock signal undergoes a valid edge transition (including a rising or falling edge), the D flip-flop samples the value of the data input D. If the input D is 1, the output Q will become 1; if the input D is 0, the output Q will become 0. This state update only occurs at a specific edge of the clock signal, ensuring the synchronization and stability of the data.

[0020] An inverter (also known as a phase inverter or level inverter) is capable of inverting the phase or level of an input signal by 180 degrees. An inverter typically includes an input and an output, and its core components usually include an amplifier (such as a transistor, operational amplifier, etc.) and a feedback network (such as a resistor).

[0021] When the input signal of the inverter is amplified by the amplifier, a portion of the output signal is fed back to the input of the amplifier through the feedback network, forming a stable negative feedback loop. Due to the effect of negative feedback, the output signal and the input signal exhibit opposite phase or level relationships.

[0022] Depending on the implementation and application scenario, inverters can be divided into various types, such as CMOS inverters, TTL inverters, normal inverters, exchange-type inverters, and differential inverters, etc. Each type of inverter has its unique features in structure, performance, and application.

[0023] As mentioned above, for example, when the distance of long-line transmission is 700 μm, a long-line transmission schematic diagram inside a chip as shown in FIG. 1 can be inserted with D flip-flops at both ends of the signal transmission, and 6 inverters can be inserted at equal intervals of 100 μm between the two D flip-flops. Figure 1

[0024] The working frequency f of the transmission line can be calculated according to the following formula:

[0025] f = 1 / τ = 1 / RC

[0026] ​Here, R and C represent the resistance and capacitance of the transmission line. Six inverters divide the long transmission line into six equal segments. For example, if the R and C values ​​of each segment are reduced to 1 / 6 of the original length (this may not actually be a 1 / 6 relationship; it's just an example for illustration), then the voltage drop (τ) of each segment decreases to 1 / 36 of the original length. The operating frequency f of the transmission line can increase exponentially, and the reduction in R also solves the high voltage drop problem. Thus, when the chip is operating, a single clock signal beat can achieve long-distance signal transmission, effectively increasing the operating frequency and addressing the voltage drop issue.

[0027] However, the inventors of this disclosure have noted that the above method still requires full voltage swing operation, resulting in very high dynamic power consumption.

[0028] The chip's total power consumption includes dynamic power consumption and static power consumption. Dynamic power consumption includes dynamic switching power consumption and short-circuit power consumption, as shown in the following formula:

[0029] P total =α T ·C load VDD 2 ·f CLK +VDD(I short +I leakage )

[0030] Among them, P total For the total power consumption of the chip, α T C is the node transition factor, representing the actual number of power consumption voltage transitions per clock cycle. load VDD is the load capacitor, f is the switching capacitor. CLK I is the clock toggle frequency. sho I is the average short-circuit current. leakage This is the leakage current. α T ·C load VDD 2 ·f CLK For dynamic switching power consumption, VDD·I short For short-circuit power consumption, VDD·I leakage This refers to static power consumption.

[0031] Dynamic switching power consumption accounts for a significant portion of dynamic power consumption and remains a major consideration in current circuit design. As shown in the above equation, dynamic switching power consumption is related to the node switching factor, load capacitance, switching voltage, and clock frequency.

[0032] In the aforementioned process of solving long-line signal transmission, full voltage swing (reaching and maintaining voltage VDD) is required, resulting in high dynamic power consumption. Furthermore, the multiple stages of inverters inserted into the long line to increase the operating frequency (mainly due to the MOSFETs in the inverters) further increase the device's switching power consumption.

[0033] Excessive dynamic power consumption can have numerous negative impacts, such as increased chip temperature, requiring more expensive packaging and cooling systems; reduced chip reliability and lifespan; shortened battery life in portable devices; and increased power supply costs and environmental burden for large-scale electronic devices. Therefore, low-power design is a key development direction for advanced chips.

[0034] This disclosure provides a signal transmission device applied within a chip. The device includes a signal transmitting unit, a signal receiving unit, and a signal transmission line, wherein the signal transmitting unit and the signal receiving unit are directly electrically connected via the signal transmission line. The signal transmitting unit is configured to transmit a target signal to the signal receiving unit via the signal transmission line. The signal receiving unit includes a sensitive amplifier, and the target signal is received and processed by the sensitive amplifier to obtain an output signal. This signal transmission device can operate with low voltage swing, requiring only a low voltage difference to obtain an output signal, thus significantly improving signal transmission speed.

[0035] Figure 2 This is a schematic diagram of the structure of a signal transmission device provided in some embodiments of this disclosure. For example... Figure 2 As shown, the signal transmission device 100 includes a signal transmitting unit 110, a signal receiving unit 120, and a signal transmission line 130.

[0036] The signal transmitting unit 110 is configured to transmit a target signal to the signal receiving unit via the signal transmission line 130. The signal transmitting unit 110 and the signal receiving unit 120 are directly electrically connected via the signal transmission line 130. The signal receiving unit 120 includes a sensitive amplifier 121, which receives and processes the target signal to obtain an output signal. Unlike technical solutions that insert D flip-flops and inverters into the transmission line, the signal transmitting unit and the signal receiving unit are electrically connected only via the signal transmission line. The sensitive amplifier in the signal receiving unit amplifies the target signal to obtain the output signal. This eliminates the need for additional components such as D flip-flops, inverters, or other parts in the signal transmission line, enabling the output signal to be obtained at a lower voltage difference, significantly improving signal transmission speed.

[0037] In the above embodiments, the transmission distance between the signal transmitting unit and the signal receiving unit is greater than or equal to 2μm, for example, 2.5μm, 3.0μm, 3.5μm, etc.

[0038] Since the characteristics of slow speed and high voltage drop become more pronounced with long-distance signal transmission, the implementation effect of the embodiments of this disclosure is also more obvious.

[0039] Figure 3This is a schematic diagram illustrating the structure of yet another signal transmission device provided in some embodiments of this disclosure. For example... Figure 3 As shown, the signal transmission device 200 includes a signal transmitting unit 210, a signal receiving unit 220, a signal transmission line 230, and an inverter 240. The signal transmitting unit 210 and the signal transmission line 230 can be referred to the aforementioned descriptions of the signal transmitting unit 110 and the signal transmission line 230, and will not be repeated here.

[0040] Inverter 240 is configured to receive the target signal, invert the target signal to obtain an inverted signal, and output an inverted signal; sensitive amplifier 221 is configured to obtain an output signal based on the target signal and the inverted signal. It should be noted that inverter 240 can be separately configured from signal transmitting unit 210 and signal receiving unit 220, or it can be integrated with signal transmitting unit 210 or signal receiving unit 220. The configuration of inverter 240 should not be considered a limitation of this disclosure.

[0041] The sensitive amplifier 221 includes a first input terminal 10 and a second input terminal 20. The first input terminal 10 receives the target signal, and the second input terminal 20 is electrically connected to the inverter 240 to receive the inverted signal.

[0042] For example, amplifiers leverage the nonlinear characteristics of electronic components (such as transistors and operational amplifiers) to amplify the amplitude (voltage or current) of an input signal to a certain level by adjusting the operating states of these components, making it easier for subsequent circuits or devices to process or identify. Sensitive amplifiers are a special type of amplifier specifically designed to amplify very weak signals. Sensitive amplifiers may employ more advanced electronic components, more sophisticated circuit designs, and more stringent manufacturing processes. They typically have higher amplification factors, lower noise, and better stability to ensure accurate amplification and detection of weak signals.

[0043] The operation of a sensitive amplifier can include the following steps:

[0044] (1) Signal reception: Receiving weak input signals, such as those from sensors or other signal sources.

[0045] (2) Amplification: The input signal is amplified, which usually includes adjusting the amplification factor and gain to ensure that the signal reaches a sufficient amplitude.

[0046] (3) Noise control: Minimize the introduction of noise during amplification to improve signal quality.

[0047] (4) Output signal: The amplified signal is output to the subsequent circuit for further processing or analysis.

[0048] The sensitive amplifier 221 used in this embodiment includes a first input terminal 10 and a second input terminal 20. Rated equal-amplitude inverted signals are input to the first input terminal 10 and the second input terminal 20 respectively, enabling the sensitive amplifier 221 to process the target signal and obtain the output signal. Alternatively, the first input terminal can directly receive the target signal, and the inverted signal obtained by the inverter 240 processing the target signal can be input to the second input terminal 20.

[0049] In one or more embodiments of this disclosure, the sensitive amplifier may include a voltage-type latching sensitive amplifier or a current-type latching sensitive amplifier.

[0050] A voltage-type latching sensitive amplifier primarily operates by comparing and amplifying the voltage difference between two bit lines. It typically includes an input stage, flip-flops, and a latch (e.g., an SR latch). When a voltage difference exists between the two bit lines, this difference is captured and amplified by the voltage-type sensitive amplifier, then converted into a digital high / low voltage difference by the flip-flop, and finally latched by the latch.

[0051] Current-mode latching amplifiers operate by detecting and amplifying the current difference between two bit lines. They typically offer higher sensitivity and lower noise sensitivity. Due to their design characteristics, current-mode amplifiers excel at suppressing common-mode noise, contributing to improved read stability.

[0052] The above embodiments use voltage-type latching sensitive amplifiers or current-type latching sensitive amplifiers to process the target signal, which can obtain the output signal at a lower voltage difference and improve the signal transmission speed.

[0053] Figure 4 This is a circuit diagram of a voltage-type latch-up sensitive amplifier provided for some embodiments of this disclosure. For example... Figure 4 As shown, the voltage latch-up sensitive amplifier 2211 includes a first field-effect transistor P1, a second field-effect transistor P2, a third field-effect transistor P3, a fourth field-effect transistor P4, a fifth field-effect transistor N5, a sixth field-effect transistor N6, and a seventh field-effect transistor N7.

[0054] A field-effect transistor (FET) is a voltage-controlled semiconductor device that uses the electric field effect of the input circuit to control the current in the output circuit. Classified by structure and operating principle, FETs include, for example, junction field-effect transistors (JFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), high electron mobility transistors, and insulated-gate bipolar transistors (IGBTs). This disclosure does not limit the type of FET.

[0055] A field-effect transistor (FET) consists of three terminals: a source, a gate, and a drain. The source and drain can usually be made of the same semiconductor material, while the gate can be made of an insulating material.

[0056] The operating principle of a field-effect transistor (FET) is based on the characteristic of voltage controlling current. When a voltage exceeding a threshold voltage is applied between the gate and source, a conductive channel is formed between the source and drain. Charge carriers flow between the source and drain, generating current. When the gate voltage changes, it alters the width of the conductive channel between the source and drain, thereby controlling the magnitude of the current flowing through the channel. For example, when the gate voltage increases, the conductive channel widens, and the current increases; when the gate voltage decreases, the conductive channel narrows, and the current decreases. Therefore, the output current of an FET is proportional to the input voltage.

[0057] In the above embodiments, the first field-effect transistor P1, the second field-effect transistor P2, the third field-effect transistor P3, and the fourth field-effect transistor P4 are P-type field-effect transistors. The fifth field-effect transistor N5, the sixth field-effect transistor N6, and the seventh field-effect transistor N7 are N-type field-effect transistors.

[0058] Based on the type of charge carriers in the conductive channel, field-effect transistors (FETs) can be classified into N-type FETs (N-FETs or NMOS) and P-type FETs (P-FETs or PMOS). In an N-type FET, the charge carriers in the channel are electrons. The substrate is doped with a small amount of donor impurities (e.g., phosphorus P, arsenic As), which provide additional free electrons. When a forward bias voltage is applied to the gate, a negative bias electric field is formed, attracting free electrons into the channel, allowing electrons to flow and thus forming a conductive path. In a P-type FET, the charge carriers in the channel are holes. The substrate is doped with a small amount of acceptor impurities (e.g., boron B, aluminum Al), which provide additional holes. When a negative bias voltage is applied to the gate, a positive bias electric field is formed, attracting holes into the channel, allowing holes to flow and thus forming a conductive path.

[0059] Figure 4 In the context of MOSFETs, those with a small circle on the gate are P-type MOSFETs, while those without a small circle on the gate are N-type MOSFETs.

[0060] like Figure 4 As shown, the source of the first field-effect transistor P1 and the source of the second field-effect transistor P2 are connected to the voltage source VDD. The drains of the first field-effect transistor P1, the third field-effect transistor P3, and the fifth field-effect transistor N5 are connected to the first node, and through the first node, are connected to the gates of the second field-effect transistor P2 and the sixth field-effect transistor N6. The drains of the second field-effect transistor P2, the fourth field-effect transistor P4, and the sixth field-effect transistor N6 are connected to the second node, and through the second node, are connected to the gates of the first field-effect transistor P1 and... The gate of the fifth field-effect transistor N5 is connected to the ground. The source of the fifth field-effect transistor N5, the source of the sixth field-effect transistor N6, and the drain of the seventh field-effect transistor N7 are connected to the ground. The source of the seventh field-effect transistor N7 is grounded to VSS. The gates of the third field-effect transistor P3, the fourth field-effect transistor P4, and the seventh field-effect transistor N7 are electrically connected to the enable signal. The sources of the third field-effect transistor P3 and the fourth field-effect transistor P4 serve as the first and second input terminals, respectively, to receive the input signal. The voltage difference between the first node and the second node is the output signal.

[0061] In the above embodiments, the signal receiving unit is further configured to receive a clock signal and use the clock signal to control an enable signal.

[0062] By making the enable signal controlled by the clock signal, when the clock signal is not turned on or not output, the enable signal is at a low level, and the above-mentioned voltage-type latching sensitive amplifier does not work.

[0063] In the above embodiments, the signal receiving unit may further include a pre-charging module, which is configured to pre-charge the first node and the second node to the target level for the voltage-type latch-sensitive amplifier when the signal receiving unit is not working.

[0064] The following is combined with Figure 4 The working process of a voltage latch-up sensitive amplifier is explained.

[0065] When the voltage-type latching sensitive amplifier 2211 is not working, the precharge module precharges the first and second nodes to the target level, such as a high level. The clock signal is not enabled or not output, and the enable signal is controlled by the clock signal. The enable signal is low, at which time the third field-effect transistor P3 and the fourth field-effect transistor P4 are turned on, and the sensitive amplifier is in a high-impedance state.

[0066] When the source of the third field-effect transistor P3, i.e., the first input terminal, receives a high-level signal, the signal received at the second input terminal is inverted compared to the first input terminal, and the signal received at the source of the fourth field-effect transistor P4, i.e., the second input terminal, is low-level. When there is a certain voltage difference between the signal received at the first input terminal and the signal received at the second input terminal, since the third field-effect transistor P3 and the fourth field-effect transistor P4 are conducting at this time, the voltage of the first node is higher than the voltage of the second node; for example, the first node is high-level and the second node is low-level.

[0067] When the clock signal starts outputting, an enable signal is generated, for example, a high level enable signal. The third MOSFET P3 and the fourth MOSFET P4 are turned off. At this time, because the voltage at the first node is high, the gates of the sixth MOSFET P6 and the second MOSFET P2 are also high, causing the sixth MOSFET P6 to conduct and the second MOSFET P2 to turn off. The gate of the seventh MOSFET N7 is electrically connected to the enable signal, therefore the seventh MOSFET N7 is turned on. Since the source of the seventh MOSFET N7 is grounded, the conduction of the sixth MOSFET N6 and the seventh MOSFET N7 accelerates the voltage drop at the second node. The second node is connected to the gate of the fifth MOSFET N5. The lower the voltage at the second node, the higher the degree to which the fifth MOSFET N5 is turned off, and simultaneously, the higher the degree to which the first MOSFET P1 is turned on. The source of the first MOSFET P1 is connected to the voltage source VDD, and the degree to which the first MOSFET P1 is turned on accelerates the voltage at the first node to reach the voltage value of the voltage source VDD. This positive feedback effect rapidly amplifies the voltage difference between the first and second nodes, thus generating the output signal.

[0068] Figure 5 forFigure 4 The diagram shows the waveforms of the enable and output signals during the operation of a voltage-type latching sensitive amplifier. When the enable signal is low, the sensitive amplifier is not working and no output signal is generated. When the first and second input terminals of the sensitive amplifier receive input signals, for example, when the first input terminal receives a high-level signal and the second input terminal receives a low-level signal as analyzed above, a voltage difference is generated between the first and second nodes. When the clock signal starts generating the enable signal, the sensitive amplifier starts working, rapidly amplifying the voltage difference between the first and second nodes to obtain the output signal.

[0069] For example, when the switching voltage is 750mV, Figure 5 The voltage difference corresponding to the dashed line is 150mV or less, which serves as the voltage swing. This voltage swing can be amplified by a sensitive amplifier to obtain the output signal. Not only is the output signal readout speed fast, but also, because the power consumption of the dynamic switch is determined by the square of the switching voltage, for example, when the voltage swing of the switching voltage is 150mV, the power consumption of the dynamic switch is only 20% of that when it is 750mV. This significantly reduces dynamic power consumption and enables fast signal transmission.

[0070] In the above embodiments, the voltage-type latching sensitive amplifier can also be replaced by a current-type latching sensitive amplifier.

[0071] Figure 6 A circuit diagram of a current-type latch-up sensitive amplifier is provided for some embodiments of this disclosure. For example... Figure 6 As shown, the current-mode latching sensitive amplifier 2212 includes an eighth field-effect transistor (FET) P8, a ninth field-effect transistor (FET) P9, a tenth field-effect transistor (FET) P10, an eleventh field-effect transistor (FET) P11, a twelfth field-effect transistor (FET) N12, a thirteenth field-effect transistor (FET) N13, a fourteenth field-effect transistor (FET) N14, a fifteenth field-effect transistor (FET) N15, and a sixteenth field-effect transistor (FET) N16. (The last sentence appears to be incomplete and possibly refers to a different topic.) Figure 4 The representation is the same. The eighth field-effect transistor P8, the ninth field-effect transistor P9, the tenth field-effect transistor P10 and the eleventh field-effect transistor P11 are P-type field-effect transistors, and the twelfth field-effect transistor N12, the thirteenth field-effect transistor N13, the fourteenth field-effect transistor N14, the fifteenth field-effect transistor N15 and the sixteenth field-effect transistor N16 are N-type field-effect transistors.

[0072] The sources of the eighth field-effect transistor P8, the ninth field-effect transistor P9, the tenth field-effect transistor P10, and the eleventh field-effect transistor P11 are connected to a voltage source. The drains of the eighth field-effect transistor P8, the tenth field-effect transistor P10, and the twelfth field-effect transistor N12 are connected at the third node, and through the third node, they are connected to the gates of the eleventh field-effect transistor P11 and the thirteenth field-effect transistor N13. The drains of the ninth field-effect transistor P9, the eleventh field-effect transistor P11, and the thirteenth field-effect transistor N13 are connected at the fourth node, and through the fourth node, they are connected to the gates of the tenth field-effect transistor P10 and the twelfth field-effect transistor N12. The source of field-effect transistor N12 is connected to the drain of the fourteenth field-effect transistor N14. The source of the thirteenth field-effect transistor N13 is connected to the drain of the fifteenth field-effect transistor N15. The sources of the fourteenth field-effect transistor N14, the fifteenth field-effect transistor N15, and the sixteenth field-effect transistor N16 are connected. The source of the sixteenth field-effect transistor N16 is grounded. The gates of the eighth field-effect transistor P8, the ninth field-effect transistor P9, and the sixteenth field-effect transistor N16 are electrically connected to the enable signal. The gates of the fifteenth field-effect transistor N15 and the fourteenth field-effect transistor N14 serve as the first and second input terminals, respectively, to receive input signals. The voltage difference between the third and fourth nodes is the output signal.

[0073] Similar to voltage-type latching sensitive amplifiers, the clock signal is received by the signal receiving unit, and the clock signal controls the enable signal.

[0074] The pre-charge module included in the signal receiving unit pre-charges the third and fourth nodes of the current-type latching sensitive amplifier to the target level.

[0075] The current-type latching sensitive amplifier 2212 amplifies the signal by detecting the current difference. Its working principle is similar to that of the voltage-type latching sensitive amplifier 2211, and will not be described in detail here.

[0076] In the signal transmission device provided in this disclosure, both voltage-type latching sensitive amplifiers and current-type latching sensitive amplifiers can be used, each with its own advantages and disadvantages. Voltage-type latching sensitive amplifiers have higher amplification gain and faster amplification speed; as long as the bit line voltage difference reaches a certain value (minimum 50mV), the amplifier can quickly amplify and read this voltage difference. However, since its input and output share a common pair of ports (e.g., ...), ... Figure 4In the voltage-type latching amplifier 2211, the first and second nodes are connected to the first and second input terminals respectively when the voltage-type latching amplifier 2211 is not working. Its amplified voltage difference is easily affected by interference; if the control circuit operates at the wrong time, it may produce incorrect data output. In contrast, the current-type latching amplifier has its input and output ports isolated (e.g., ...). Figure 6 The third and fourth nodes of the current-mode latching sensitive amplifier 2212 are disconnected from the first and second input terminals, so this problem does not exist. However, since its amplification process involves converting voltage difference to current difference and then back to voltage difference, its amplification speed is relatively slow.

[0077] Analysis of voltage-type latching sensitive amplifiers and current-type latching sensitive amplifiers reveals that the sensitive amplifier needs to operate under the control of an enable signal, thus requiring precise timing of its activation. The enable signal is controlled by a clock signal. The signal transmission device in the above embodiment may further include a tracking module, which controls the output signal of the signal processing device by adjusting the timing of the clock signal activation.

[0078] The tracking module in the above embodiments includes a delay chain or a detection data signal line. By checking the signal delay of the delay chain or the detection data signal line, the delay of the output signal is obtained. The tracking module adjusts the timing of the clock signal activation based on the delay.

[0079] In the above embodiments, for example, multiple inverters can be connected in series to form a delay chain, or a detection data signal line can be formed by copying a data signal line. The delay of the output signal can be determined by detecting the signal delay of the delay chain and the detection data signal line.

[0080] Based on the output signal delay, the tracking module can adjust, for example, the process offset between the field-effect transistors in the sensitive amplifier, the corresponding position of the rising edge and the signal voltage difference, or the offset of the resistor and capacitor, to control the jump point of the enable signal, so as to accurately identify the timing of the clock signal activation and read the data accurately and quickly.

[0081] Some embodiments of this disclosure also provide an electronic device that includes any of the signal transmission devices described above. The electronic device may be, for example, a chip that includes any of the signal transmission devices described above. Alternatively, the electronic device may be a terminal device, server device, etc., that includes the chip; the embodiments of this disclosure are not limited thereto.

[0082] For example, the chips involved in the embodiments of this disclosure may include logic chips, memory chips, etc. For example, logic chips may be central processing units, coprocessors, graphics processors, etc. The embodiments of this disclosure do not limit the specific types or structures of chips; the signals involved in the embodiments of this disclosure may include data signals, control signals, etc. The embodiments of this disclosure do not limit the types of signals.

[0083] Figure 7 This is a schematic diagram illustrating the structure of an electronic device provided in some embodiments of this disclosure. The electronic device of this disclosure may include any of the signal transmission devices described above. The electronic device may include at least one memory and at least one processor, wherein the memory non-transitory stores computer-executable instructions, and the processor is configured to execute the computer-executable instructions. For example, the processor or memory may include the aforementioned signal transmission device. For example, the electronic device of this disclosure may be implemented as, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. The above-described electronic device is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this disclosure.

[0084] like Figure 7 As shown, the electronic device 300 may include a processing device (e.g., one or more central processing units, one or more graphics processing units, etc.) 310, which includes a computing device capable of implementing the signal transmission method described above, capable of performing various appropriate actions and processes according to a program stored in a read-only memory (ROM) 320 or a program loaded from a storage device 380 into a random access memory (RAM) 330. The RAM 330 also stores various executable programs and data required for the operation of the electronic device 300. The processing device 310, ROM 320, and RAM 330 are interconnected via a bus 340. An input / output (I / O) interface 350 is also connected to the bus 340.

[0085] Typically, the following devices can be connected to I / O interface 350: input devices 360 including, for example, a touchscreen, touchpad, keyboard, mouse, camera, microphone, accelerometer, or gyroscope; output devices 370 including, for example, a liquid crystal display (LCD), speaker, or vibrator; storage devices 380 including, for example, magnetic tape, hard disk, etc.; and communication devices 390. Communication device 390 allows electronic device 300 to communicate wirelessly or wiredly with other electronic devices to exchange data. Although Figure 7 The electronic device 300 may alternatively implement or have more or fewer devices, incorporating all the devices shown.

[0086] In at least one embodiment of this disclosure, the computer program can be downloaded and installed from a network via communication device 390, or installed from storage device 380, or installed from ROM 320. When the computer program is executed by processing device 310, it can be used at least in part to perform the functions defined in the signal transmission device provided in the embodiments of this disclosure.

[0087] Although the present disclosure has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to the embodiments of the present disclosure, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the spirit of the present disclosure are within the scope of protection claimed by the present disclosure.

[0088] The following points should be noted regarding this disclosure:

[0089] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0090] (2) For clarity, the thickness of layers or regions in the drawings used to describe embodiments of the present disclosure is enlarged or reduced, i.e., these drawings are not drawn to actual scale.

[0091] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0092] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure shall be determined by the scope of the claims.

Claims

1. A signal transmission device applied inside a chip, comprising: The signal transmitting unit, the signal receiving unit, and the signal transmission line, among which, The signal transmitting unit and the signal receiving unit are directly electrically connected via the signal transmission line; The signal transmitting unit is configured to transmit a target signal to the signal receiving unit via the signal transmission line; The signal receiving unit includes a sensitive amplifier, and the target signal is received and processed by the sensitive amplifier to obtain an output signal.

2. The signal transmission device according to claim 1, wherein, The transmission distance between the signal transmitting unit and the signal receiving unit is greater than or equal to 2 μm.

3. The signal transmission device according to claim 1 further includes an inverter, wherein, The inverter is configured to receive the target signal, invert the target signal to obtain an inverted signal, and output the inverted signal. The sensitive amplifier includes a first input terminal and a second input terminal. The first input terminal receives the target signal, and the second input terminal is electrically connected to the inverter to receive the inverted signal. The sensitive amplifier is configured to obtain the output signal based on the target signal and the inverted signal.

4. The signal transmission device according to claim 3, wherein, The sensitive amplifier includes a voltage-type latching sensitive amplifier or a current-type latching sensitive amplifier.

5. The signal transmission device according to claim 4, wherein, The voltage-type latch-up sensitive amplifier includes a first field-effect transistor, a second field-effect transistor, a third field-effect transistor, a fourth field-effect transistor, a fifth field-effect transistor, a sixth field-effect transistor, and a seventh field-effect transistor. The source of the first field-effect transistor and the source of the second field-effect transistor are connected to a voltage source. The drains of the first, third, and fifth field-effect transistors are connected to a first node, and are also connected to the gates of the second and sixth field-effect transistors through the first node. The drains of the second, fourth, and sixth field-effect transistors are connected to a second node, and are also connected to the gates of the first and fifth field-effect transistors through the second node. The source of the fifth field-effect transistor, the source of the sixth field-effect transistor, and the drain of the seventh field-effect transistor are connected. The source of the seventh field-effect transistor is grounded. The gates of the third field-effect transistor, the fourth field-effect transistor, and the seventh field-effect transistor are electrically connected to the enable signal. The source of the third field-effect transistor and the source of the fourth field-effect transistor serve as the first input terminal and the second input terminal, respectively, to receive input signals. The voltage difference between the first node and the second node is the output signal.

6. The signal transmission device according to claim 4, wherein, The current-mode latching sensitive amplifier includes: an eighth field-effect transistor, a ninth field-effect transistor, a tenth field-effect transistor, an eleventh field-effect transistor, a twelfth field-effect transistor, a thirteenth field-effect transistor, a fourteenth field-effect transistor, a fifteenth field-effect transistor, and a sixteenth field-effect transistor. The sources of the eighth, ninth, tenth, and eleventh field-effect transistors are connected to a voltage source. The drains of the eighth, tenth, and twelfth field-effect transistors are connected at the third node, and are also connected to the gates of the eleventh and thirteenth field-effect transistors through the third node. The drains of the ninth, eleventh, and thirteenth field-effect transistors are connected at the fourth node, and are also connected to the gates of the tenth and twelfth field-effect transistors through the fourth node. The source of the twelfth field-effect transistor is connected to the drain of the fourteenth field-effect transistor. The source of the thirteenth field-effect transistor is connected to the drain of the fifteenth field-effect transistor. The source of the fourteenth field-effect transistor, the source of the fifteenth field-effect transistor, and the drain of the sixteenth field-effect transistor are connected. The source of the sixteenth field-effect transistor is grounded. The gates of the eighth field-effect transistor, the ninth field-effect transistor, and the sixteenth field-effect transistor are electrically connected to the enable signal. The gate of the fifteenth field-effect transistor and the gate of the fourteenth field-effect transistor serve as the first input terminal and the second input terminal, respectively, to receive input signals. The voltage difference between the third node and the fourth node is the output signal.

7. The signal transmission device according to claim 5 or 6, wherein, The signal receiving unit is also configured to receive a clock signal and use the clock signal to control the enable signal.

8. The signal transmission device according to claim 5 or 6, wherein, The signal receiving unit also includes a pre-charging module. The pre-charge module is configured to, when the signal receiving unit is not working, pre-charge the first node and the second node to the target level for the voltage-type latch-sensitive amplifier, or pre-charge the third node and the fourth node to the target level for the current-type latch-sensitive amplifier.

9. The signal transmission device according to any one of claims 1-6, wherein, The signal transmission device also includes a tracking module. The tracking module controls the signal processing device to output the output signal by adjusting the timing of the clock signal activation.

10. The signal transmission device according to claim 9, wherein, The tracking module includes a delay chain or a detection data signal line. The delay of the output signal is obtained by checking the signal delay of the delay chain or the detection data signal line. The tracking module adjusts the timing of the clock signal activation based on the delay.

11. An electronic device comprising a signal transmission device according to any one of claims 1-10.

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