Signal equalization apparatus, system and method

Abstract

The application discloses a signal equalization device, system and method, and belongs to the electronic information technical field. The signal equalization device comprises an adder and a controller. The first input end of the adder is connected with a signal source. The output end of the adder is connected with the input end of the controller. The output end of the controller is connected with the second input end of the adder. The adder receives a target signal generated by the signal source and a control signal output by the controller. The target current is determined according to the control signal. The target signal is equalized according to the target current, and an equalized signal is obtained. The control signal is determined by the controller according to characteristic information. The characteristic information indicates the signal rate of a first signal output by the adder to the controller. The first signal is obtained by equalizing a previous signal of the target signal by the adder according to an initial current. The application determines the current according to the signal rate, so that the adder can generate stable gain to the signal in the equalization process according to the current.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic information, in particular to a signal equalization device, system and method. BACKGROUND

[0002] In the process of signal transmission from a sending end to a receiving end, the signal is often interfered by a channel, resulting in that the signal received by the receiving end is different from the signal sent by the sending end. Therefore, the receiving end needs to perform equalization processing on the received signal to restore the received signal to the signal sent by the sending end. SUMMARY

[0003] Embodiments of the present application provide a signal equalization device, system and method, which can be used for equalization processing of a signal. The technical scheme provided by the embodiments of the present application includes the following aspects.

[0004] In one aspect, a signal equalization device is provided, which includes an adder and a controller. A first input end of the adder is connected with a signal source. An output end of the adder is connected with an input end of the controller. An output end of the controller is connected with a second input end of the adder.

[0005] The adder is configured to receive a target signal generated by the signal source.

[0006] The adder is further configured to receive a control signal output by the controller. The control signal is determined by the controller according to characteristic information. The characteristic information indicates a signal rate of a first signal output by the adder to the controller. The first signal is obtained by the adder performing equalization processing on a previous signal according to an initial current. The previous signal is a signal generated by the signal source before the target signal is generated.

[0007] The adder is further configured to determine a target current according to the control signal, and perform equalization processing on the target signal according to the target current to obtain an equalization-processed signal.

[0008] In an exemplary embodiment, the adder includes a plurality of first switches connected in parallel. First input ends of the plurality of first switches are connected with a second input end of the adder. Second input ends of the plurality of first switches are connected with a bias voltage source in the signal equalization device. Output ends of the plurality of first switches are connected with an output end of the adder. The control signal is used to indicate a first number of first switches that need to be closed in the plurality of first switches.

[0009] In an example embodiment, the adder further comprises a plurality of second switches corresponding to the plurality of first switches, input ends of the plurality of second switches being connected to a second input end of the adder, output ends of each second switch being connected to ground through output ends of corresponding first switches, the control signals of the plurality of second switches further being used to indicate a second number of second switches that need to be closed. Among them, the second number of second switches correspond to other switches, the other switches being first switches other than the first number of first switches that need to be closed in the plurality of first switches.

[0010] In an example embodiment, the controller comprises a filter, a first power detector, a second power detector, an error amplifier, a counter and a digital-to-analog converter, the filter being a low-pass filter or a high-pass filter. An input end of the filter and an input end of the second power detector are connected to an input end of the controller respectively, an output end of the filter is connected to an input end of the first power detector, output ends of the first power detector and the second power detector are connected to input ends of the error amplifier respectively, an output end of the error amplifier is connected to an input end of the counter, an output end of the counter is connected to an input end of the digital-to-analog converter, and an output end of the digital-to-analog converter is connected to an output end of the controller.

[0011] In an aspect, a signal equalization system is provided, comprising: a signal source and any of the example signal equalization devices described above, the signal source being connected to the signal equalization device.

[0012] In another aspect, a signal equalization method is provided, comprising: an adder receiving a target signal generated by a signal source; the adder receiving a control signal output by a controller, the control signal being determined by the controller according to characteristic information, the characteristic information indicating a signal rate of a first signal output by the adder to the controller, the first signal being obtained by the adder by equalizing a previous signal according to an initial current, the previous signal being a signal generated by the signal source before the target signal is generated; the adder determining a target current according to the control signal, and equalizing the target signal according to the target current to obtain an equalized signal.

[0013] In an example embodiment, when the signal rate indicated by the feature information is greater than a first threshold, the control signal is used to make the target current greater than the initial current; wherein the signal rate greater than the first threshold is used to indicate that the gain generated by the adder when performing the equalization processing is reduced, and the gain generated by the adder when performing the equalization processing according to the target current is greater than the gain generated by the adder when performing the equalization processing according to the initial current.

[0014] In an example embodiment, when the signal rate indicated by the feature information is less than or equal to a second threshold, the control signal is used to make the target current less than the initial current; wherein the signal rate less than or equal to the second threshold is used to indicate that the gain generated by the adder when performing the equalization processing is increased, and the gain generated by the adder when performing the equalization processing according to the target current is less than the gain generated by the adder when performing the equalization processing according to the initial current.

[0015] In an example embodiment, the feature information is a difference between a second power consumption and a first power consumption, the second power consumption is a power consumption corresponding to the first signal, and the first power consumption is a power consumption corresponding to a partial signal in the first signal with a frequency in a target range.

[0016] In an example embodiment, the partial signal with the frequency in the target range is a signal with a frequency greater than a third threshold, and the feature information is negatively correlated with the signal rate indicated by the feature information.

[0017] In an example embodiment, the partial signal with the frequency in the target range is a signal with a frequency less than or equal to a fourth threshold, and the feature information is positively correlated with the signal rate indicated by the feature information.

[0018] The technical scheme provided by the embodiments of the present application at least brings the following beneficial effects:

[0019] The current used in the process of performing the equalization processing according to the adaptability of the signal rate of the signal, so that the influence of the signal rate of the signal on the gain can be offset by the influence of the used current on the gain, thereby ensuring the stability of the gain generated by the adder on the signal. Thus, the influence of the signal rate on the gain generated by the adder on the signal can be avoided, so that the signal after the equalization processing by the adder can maintain a small jitter, which is embodied as the eye diagram corresponding to the signal has a small opening degree. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments description. Obviously, the drawings in the following description only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0021] Figure 1 is a structural schematic diagram of a signal equalization device provided by an embodiment of the present application;

[0022] Figure 2 is a structural schematic diagram of another signal equalization device provided by an embodiment of the present application;

[0023] Figure 3 is a structural schematic diagram of still another signal equalization device provided by an embodiment of the present application;

[0024] Figure 4 is a structural schematic diagram of an adder provided by an embodiment of the present application;

[0025] Figure 5 is a structural schematic diagram of another adder provided by an embodiment of the present application;

[0026] Figure 6 is a structural schematic diagram of a controller provided by an embodiment of the present application;

[0027] Figure 7 is a flow chart of a signal equalization method provided by an embodiment of the present application;

[0028] Figure 8 is a structural diagram of a signal equalization system provided by an embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solutions and advantages of the present application more clear, the following will further describe the embodiments of the present application in combination with the drawings.

[0030] In the process of signal transmission from a transmit (TX) end to a receive (RX) end, the signal is often interfered by the channel between the TX end and the RX end, so as to cause the signal received by the RX end to be different from the signal sent by the TX end. Therefore, the RX end needs to perform equalization processing on the received signal, so as to restore the received signal to the signal sent by the TX end, i.e. the signal after equalization processing. Thus, the signal after equalization processing can be used, such as obtaining information according to the signal after equalization processing, continuing other processing on the signal after equalization processing, etc. The RX end is for example a receive end of a serializer / deserializer (SerDes).

[0031] In the related art, the greater the signal rate of the signal to be equalized, the smaller the gain of the signal generated by the adder, and the greater the jitter of the signal obtained after equalization, which is manifested as a smaller opening degree of the eye diagram corresponding to the signal. The smaller the signal rate of the signal to be equalized, the greater the gain of the signal generated by the adder, and the smaller the jitter of the signal obtained after equalization, which is manifested as a larger opening degree of the eye diagram corresponding to the signal. As can be seen, the gain of the signal generated by the adder in the related art changes with the change of the signal rate of the signal, which not only has poor stability, but also can cause the jitter of the obtained signal to be large.

[0032] To this end, it is necessary to ensure the stability of the gain of the signal generated by the adder, or in other words, to make the gain of the signal generated by the adder not change with the change of the signal rate. As known from the foregoing description, the gain of the signal generated by the adder is related to the manufacturing process of the adder, the signal rate of the signal, and the current used in the equalization process. Considering that it is often difficult to change the manufacturing process after the adder is manufactured according to a certain manufacturing process, the current used in the equalization process is adjusted in the embodiments of the present application to make the gain of the signal generated by the adder not change with the change of the signal rate. In other words, the signal rate is not intervened in the embodiments of the present application, but the current is intervened according to the signal rate to offset the influence of the signal rate on the gain, thereby controlling the change of the gain. In other words, the current is determined according to the adaptability of the signal rate of the signal in the embodiments of the present application, and the current is used in the equalization process, so that the signal rate and the current have opposite influences on the gain, for example, the influence of the signal rate on the gain is offset by the influence of the current on the gain, thereby ensuring the stability of the gain of the signal generated by the adder, or realizing constant gain of the signal by the adder.

[0033] To this end, it is necessary to ensure the stability of the gain of the signal generated by the adder, or in other words, to make the gain of the signal generated by the adder not change with the change of the signal rate. As known from the foregoing description, the gain of the signal generated by the adder is related to the manufacturing process of the adder, the signal rate of the signal, and the current used in the equalization process. Considering that it is often difficult to change the manufacturing process after the adder is manufactured according to a certain manufacturing process, the current used in the equalization process is adjusted in the embodiments of the present application to make the gain of the signal generated by the adder not change with the change of the signal rate. In other words, the signal rate is not intervened in the embodiments of the present application, but the current is intervened according to the signal rate to offset the influence of the signal rate on the gain, thereby controlling the change of the gain. In other words, the current is determined according to the adaptability of the signal rate of the signal in the embodiments of the present application, and the current is used in the equalization process, so that the signal rate and the current have opposite influences on the gain, for example, the influence of the signal rate on the gain is offset by the influence of the current on the gain, thereby ensuring the stability of the gain of the signal generated by the adder, or realizing constant gain of the signal by the adder.

[0034] The embodiments of the present application provide a signal equalization device, as shown in Figure 1 The signal equalization device includes an adder and a controller. The adder includes a first input terminal, a second input terminal, and an output terminal. The controller includes an input terminal and an output terminal.

[0035] The first input end of the adder is connected with the signal source, so that the signal generated by the signal source can be input into the adder through the first input end of the adder after the signal source generates the signal, or in other words, the adder can receive the signal generated by the signal source through the first input end. Inside the adder, the signal generated by the signal source can be balanced according to a certain current to obtain a processed signal. The signal source belongs to the transmitting end in the above description, and the signal balancing device (including but not limited to the adder and the controller) belongs to the receiving end in the above description.

[0036] The output end of the adder is connected with the input end of the controller, so that the processed signal can be output through the output end of the adder and then input through the input end of the controller, and the controller can receive the processed signal through the input end. Inside the controller, characteristic information can be determined according to the processed signal, which is used to indicate the signal rate of the processed signal, and the signal rate of the processed signal is equal to the signal rate of the signal generated by the signal source. In addition, the controller can also determine a control signal according to the characteristic information, which is used for the adder to balance the signal received through the first input end subsequently.

[0037] The output end of the controller is connected with the second input end of the adder, so that the control signal can be output from the output end of the controller to the adder through the second input end of the adder, so that the adder can receive the control signal through the second input end. Inside the adder, the current can be determined according to the control signal, so that the signal generated by the signal source can be balanced according to the determined current after being received through the first input end subsequently, such as after the signal generated by the signal source is received through the first input end next time.

[0038] That is to say, in the signal balancing device, the adder is used to receive the target signal generated by the signal source (corresponding to the signal received by the adder through the first input end subsequently in the above description), and also used to receive the control signal output by the controller, to determine the target current according to the control signal (corresponding to the current determined according to the control signal in the above description), and to balance the target signal according to the target current to obtain the balanced signal.

[0039] The control signal is determined by the controller according to the characteristic information, and the characteristic information indicates the signal rate of the first signal (corresponding to the processed signal in the above description) output by the adder to the controller, and the first signal is obtained by balancing the previous signal by the adder according to the initial current (corresponding to the certain current in the above description), and the previous signal is the signal generated by the signal source before the target signal is generated.

[0040] It should be understood that, since the target current is obtained based on the previous signal generated by the signal source in the embodiments of the present application, and then the target signal generated by the signal source is equalized according to the target current, the previous signal and the target signal need to have sufficient similarity to avoid that the target current is not suitable for equalizing the target signal and affects the accuracy of equalization. In the exemplary embodiments, considering that the signal source continuously generates signals, the continuously generated signals often only have slight changes and the change trend conforms to a certain rule, the embodiments of the present application provide the following two implementation manners to ensure that the previous signal and the target signal have sufficient similarity.

[0041] In implementation manner one, the number of signals between the previous signal and the target signal is less than a number threshold. For example, the number threshold can be set to 1, and the number of signals between the previous signal and the target signal needs to be less than 1, that is, equal to 0. Therefore, the previous signal is the last signal of the target signal, or the previous signal and the target signal are two signals generated by the signal source in sequence. In implementation manner two, the difference between the generation time of the previous signal and the generation time of the target signal is less than a time threshold, which will not be described in detail here.

[0042] Of course, the number threshold or the time threshold can be flexibly adjusted. For example, when the stability of the signals generated by the signal source increases, the number threshold or the time threshold can be increased. For example, when the stability of the signals generated by the signal source decreases, the number threshold or the time threshold can be decreased.

[0043] It should also be understood that, in the initial state, that is, the case where the adder has not received the control signal, the initial current used by the adder in the process of equalization can be a default current set according to experience or actual demand. In the non-initial state, that is, the case where the adder has received the control signal, the initial current used by the adder in the process of equalization can be the target current determined according to the last received control signal. In addition, the initial current and the target current can be the same (that is, the initial current is equal to the target current), or different (for example, the initial current is greater than the target current, or the initial current is less than the target current). Whether the initial current and the target current are the same is related to the control signal determined by the controller.

[0044] Of course, the signal equalization device can include other elements in addition to the adder and the controller, which will be described below.

[0045] Exemplarily, the signal equalization device further includes an amplifier and a flip-flop. As Figure 2As shown in the figure, the first input end of the adder is connected with the signal source, comprising: the first input end of the adder is connected with the signal source through the amplifier. That is, the input end of the amplifier is connected with the signal source, and the output end of the amplifier is connected with the first input end of the adder. The amplifier is used for amplifying the signal generated by the signal source, so that the signal generated by the signal source is input into the amplifier through the input end of the amplifier, is amplified in the amplifier, and the amplified signal is output from the amplifier through the output end of the amplifier and is input into the adder through the first input end of the adder. Then, in the adder, the amplified signal can be equalized after being received to obtain a processed signal.

[0046] Exemplarily, when the amplifier amplifies the signal, the direct current offset problem existing in the signal can be eliminated through the correction circuit in the amplifier to ensure the accuracy of the signal. For example, the signal source sends two 1V (unit: volt) voltage signals, but after channel transmission, the two 1V voltage signals become 0.9V voltage signals and 1.1V voltage signals respectively, and the sizes of the two voltage signals are different, and there is a direct current offset problem. Correspondingly, after the amplifier receives the 0.9V voltage signal and the 1.1V voltage signal, the two voltage signals can be amplified to 2V voltage signals through the correction circuit and output, so that the sizes of the two voltage signals are the same, and the direct current offset problem is eliminated.

[0047] However, although the amplifier can eliminate the direct current offset problem existing in the signal through the correction circuit, the signal rate of the signal will not be changed. If the signal rates of the two voltage signals are different, the signal rates of the two amplified signals output by the amplifier are also different. If the two amplified signals are equalized by the adder in the related art, since the gain of the adder in the related art changes with the change of the signal rate, the gain of the adder to the two amplified signals is different. Then, the adder will amplify the two amplified signals by different multiples through the equalization process to obtain two processed voltage signals with different sizes, which recauses the direct current offset problem, or causes the direct current offset elimination effect realized by the amplifier through the correction circuit to be invalid. If the two amplified signals are equalized by the adder provided in the embodiment of the present application, since the gain of the adder to the signal is not affected by the signal rate, the adder can amplify the two amplified signals by the same multiple through the equalization process to obtain two processed voltage signals with the same size, which will not recause the direct current offset problem, nor will it cause the direct current offset elimination effect realized by the amplifier through the correction circuit to be invalid.

[0048] In addition, the output of the adder is connected to the input of the controller, including: the output of the adder is connected to the input of the controller through a flip-flop. That is, the output of the adder is connected to the input of the flip-flop, and the first output of the flip-flop is connected to the input of the controller. The adder further includes a third input, and the flip-flop further includes a second output, and the second output of the flip-flop is connected to the third input of the adder.

[0049] Correspondingly, in the process of one equalization processing, after the adder receives the signal through the first input, the adder sends the received signal to the flip-flop through the output of the adder and the input of the flip-flop. The flip-flop acts on the received signal to obtain an acted signal, and sends the acted signal to the adder through the second output of the flip-flop and the third input of the adder. The adder processes the acted signal and the signal received through the first input according to a certain weight to obtain a processed signal. Exemplarily, the adder calculates the acted signal according to a certain weight (i.e. Figure 2 The calculation result is added to the signal received through the first input to obtain the processed signal. Then, the adder sends the processed signal to the flip-flop again through the output of the adder and the input of the flip-flop. The flip-flop acts on the processed signal to obtain a re-acted signal, and then sends the re-acted signal to the controller through the first output of the flip-flop and the input of the controller.

[0050] Therefore, the controller can determine the characteristic information according to the re-acted signal, determine the control signal according to the characteristic information, and send the control signal to the adder through the output of the controller and the second input of the adder, so that the adder determines the current according to the control signal and uses the determined current in the next equalization processing.

[0051] In addition, the action of the flip-flop on the received signal can be determined according to the type of the signal equalization circuit, which is not limited in the embodiments of the present application.

[0052] For example, when the type of the signal equalization circuit is DFE (Decision Feedback Equalizer, Decision Feedback Equalizer), the action of the flip-flop can include but is not limited to: sampling decision and delay processing. When the flip-flop receives the signal, the flip-flop performs sampling decision on the signal to obtain a sampling decision result, and then delays the sampling decision result by one clock cycle to obtain an acted signal. For example, the flip-flop includes a slicer for performing the sampling decision process and a delay unit loop for performing the delay process.

[0053] In the DFE, the trigger includes, but is not limited to, a SAFF (Sensitive Amplification Flip-Flop) or a DFF (D Flip-Flop), where D in the DFF represents Data or Delay. The difference between the SAFF and the DFF is that the signal output by the SAFF is in the form of a digital signal, while the signal output by the DFF is in the form of an analog signal.

[0054] For example, when the type of the signal equalization circuit is an FFE (Feed-forward Equalizer), the action performed by the trigger can include, but is not limited to, a delay process. After the trigger receives the signal, the signal is delayed by one clock cycle to obtain the signal after the action. For example, the trigger includes a delay unit loop for performing the delay process.

[0055] In the embodiments of the present application, the signal is delayed by one clock cycle in the trigger because it is considered that, in the process of continuously receiving the signal, the signal received later (the latter signal) will affect the signal received earlier (the former signal), and thus the signal that needs to be equalized is taken as the former signal, which is actively delayed by the trigger by one time period to obtain the signal after the action, and the signal after the action is taken as the latter signal, and then the two signals are weighted by the adder, so that the effect of the latter signal on the former signal can be eliminated, so that the signal processed by the adder is the signal with the effect eliminated. The effect eliminated includes, but is not limited to, the larger post-ISI (Inter-symbol interference) in the ISI, and thus the processed signal is the signal with the post-ISI eliminated.

[0056] In some embodiments, because Figure 2 In the signal equalization device shown, the number of amplifiers, adders, and triggers is one, and thus the trigger outputs the signal after the action to the same adder after receiving the signal output by the adder and obtaining the signal after the action through the action, that is, the second output end of the trigger is connected to the third input end of the same adder (or the adder of the same path as the trigger itself). Alternatively, in other embodiments, the number of amplifiers, adders, and triggers included in the signal equalization device is multiple. After the trigger receives the signal output by an adder and obtains the signal after the action through the action, the trigger outputs the signal after the action to other adders other than the adder, that is, the second output end of the trigger is connected to the third input end of different adders (or the adders of different paths from the trigger itself).

[0057] Taking the number of amplifiers, adders and flip-flops as two as an example, referring to Figure 3 , the amplifier 1, the adder 1 and the flip-flop 1 belong to one path, and the amplifier 2, the adder 2 and the flip-flop 2 belong to another path. Vin represents a signal generated by a signal source, and the signal belongs to a full-rate signal. The full-rate signal is split into two half-rate signals, i.e., half-rate signal 1 and half-rate signal 2. The two half-rate signals correspond to different clock cycles, for example, the half-rate signal 1 corresponds to an even clock cycle, and the half-rate signal 2 corresponds to an odd clock cycle. The half-rate signal 1 enters the amplifier 1, and the half-rate signal 2 enters the amplifier 2. Thus, the signal that needs to be processed by each path is only the half-rate signal in the full-rate signal, which can reduce the process requirements for the elements included in each path.

[0058] The amplifier 1 sends the amplified signal 1 to the adder 1, the adder 1 sends the amplified signal 1 to the flip-flop 1, and the flip-flop 1 inputs the acted signal 1 to the adder 2 after the action. The amplifier 2 sends the amplified signal 2 to the adder 2, the adder 2 sends the amplified signal 2 to the flip-flop 2, and the flip-flop 2 inputs the acted signal 2 to the adder 1 after the action.

[0059] Thus, the adder 1 can perform weighted calculation on the acted signal 2 and the amplified signal 1 according to the weight C1 shown in Figure 3 , to obtain the processed signal 1, which will enter the flip-flop 1 to be acted, to obtain the re-acted signal 1 (Veven). The adder 2 can perform weighted calculation on the acted signal 1 and the amplified signal 2 according to the weight C1 shown in Figure 3 , to obtain the processed signal 2, which will enter the flip-flop 2 to be acted, to obtain the re-acted signal 2 (Vodd).

[0060] Referring to Figure 3 , the signal equalization device further includes a multiplexer (MUX), and for each flip-flop in the plurality of flip-flops, the first output end of the flip-flop is connected to the input end of the controller, including: the first output end of the flip-flop is connected to the input end of the controller through the MUX, that is, the first output end of the flip-flop is connected to the input end of the MUX, and the output end of the MUX is connected to the input end of the controller.

[0061] The re-acted signal 1 outputted by the flip-flop 1 and the re-acted signal 2 outputted by the flip-flop 2 are multiplexed into a full-rate signal (Vmux) without post-cursor ISI by the MUX. The MUX sends the multiplexed full-rate signal to the controller through the output of the MUX and the input of the controller, so that the controller determines the characteristic information and the control signal according to the above description, and sends the control signal to the adder (e.g. the adder 1 and the adder 2) of each channel respectively, so that each adder determines the current according to the control signal and uses the determined current in the next equalization process.

[0062] Exemplarily, the re-acted signal 1 and the re-acted signal 2 can be directly outputted for use by other elements in addition to being sent to the MUX. Of course, the full-rate signal multiplexed by the MUX can be directly outputted for use by other elements in addition to being sent to the controller. The embodiments of the present application do not limit other elements.

[0063] It should be understood that the way of achieving equalization by the re-acted signal sent by the flip-flop inside the adder is only an example and does not limit the way of achieving equalization by the adder. For example, the adder can also include other elements with equalization function inside, and the adder can achieve equalization of the signal by the other elements. In addition, the signal equalization devices shown in the above embodiments are only examples and do not limit the signal equalization devices provided by the embodiments of the present application. Figure 1 to Figure 3 The signal equalization devices shown in the above embodiments are only examples and do not limit the signal equalization devices provided by the embodiments of the present application.

[0064] Next, the internal structure of the adder and the controller will be further described.

[0065] In the exemplary embodiments, as shown in Figure 4 and Figure 5 , the adder includes a plurality of first switches (i.e. S1 shown in Figure 4 and Figure 5 ) connected in parallel, the first input ends of the plurality of first switches are connected to the second input end of the adder, the second input ends of the plurality of first switches are connected to the bias voltage source in the signal equalization device, the output ends of the plurality of first switches are connected to the output end of the adder, and the control signal is used to indicate the first number of the first switches needed to be closed in the plurality of first switches.

[0066] The bias voltage source can refer to Figure 4 and Figure 5Vbias, bias represents bias. Since multiple first switches are in parallel and are connected to the bias voltage source, the voltage in the signal equalization device will change accordingly when one first switch is closed or opened, and the current inside the adder will also change accordingly, i.e. the current used by the adder in the equalization process, also known as tail current (see Figure 4 and Figure 5 I2) as shown in FIGS. 1 and 2. Therefore, the control signal can be used to indicate the number of first switches that need to be closed or opened, and by changing the number of closed or opened first switches, the adder can determine the target current.

[0067] Exemplarily, the size of the tail current is positively correlated with the number of closed first switches. That is, the size of the tail current increases by 10 mA (unit: milliampere) when one first switch is closed. For example, when all first switches are opened, the voltage provided by the bias voltage source is only accessed from M7 (one switch inside the adder) to the circuit inside the adder, which makes the tail current 10 mA. When one more first switch is closed, the voltage accessed from M8 (one switch inside the adder) to the circuit inside the adder increases by 10 mA, thereby increasing the size of the tail current by 10 mA. Taking the total number of first switches as 64 for example, when all first switches are opened, the current provided by the 64 first switches is 0, so the size of the tail current is 10 mA. When all first switches are closed, each of the 64 first switches provides a current of 10 mA, and the total current provided by the 64 first switches is 640 mA, so the size of the tail current is 650 mA. That is, by using the 64 first switches, the size of the tail current can be adjusted to be between 10 mA and 650 mA.

[0068] It should be understood that the positive correlation between the size of the tail current and the number of closed first switches is only an example, and the circuit can also be designed according to actual needs so that the size of the tail current is negatively correlated with the number of closed first switches, as long as the adjustment of the size of the tail current can be realized. Moreover, the 64 first switches and 10 mA mentioned above are only examples, and the number of first switches and the size of the tail current affected by closing one first switch can be selected according to actual needs.

[0069] Exemplarily, the adder further includes a plurality of second switches (i.e. Figure 4 and Figure 5The second switches are one-to-one corresponding to the first switches, the input ends of the second switches are connected to the second input end of the adder, the output end of each second switch is grounded through the output end of the corresponding first switch, and the control signals of the second switches are also used to indicate the second number of the second switches that need to be closed.

[0070] The second number of the second switches corresponds to the other switches, and the other switches are the first switches except the first number of the first switches that need to be closed. That is, the first number of the first switches that need to be closed, the second number of the first switches that do not need to be closed (i.e. the other switches), the second number of the second switches that need to be closed correspond to the first switches that do not need to be closed, and the sum of the first number and the second number is the total number of the first switches. Therefore, in the corresponding first switch and the second switch, one switch is closed and the other switch is opened. For example, when the first switch is closed, the second switch is opened, and when the first switch is opened, the second switch is closed. When the first switch is closed, the tail current increases, and when the second switch is closed, the output end of the second switch is grounded through the output end of the corresponding first switch, so that the circuit in which the first switch and the second switch are located is grounded.

[0071] The reason for setting the first switch and the second switch in this way is as follows. After the first switch is closed, there is a voltage in the circuit in which the first switch and the second switch are located, which causes the tail current to increase. If the second switch is not closed after the first switch is opened, the circuit is grounded, and even if the first switch is opened, there is still a residual voltage in the circuit, which still causes the tail current to increase, resulting in the situation that the first switch is opened but the tail current does not decrease, causing the tail current to fail to be adjusted, thereby affecting the gain of the adder to the signal and causing errors. Therefore, after the first switch is opened, the second switch corresponding to the first switch can be closed to ground the circuit in which the first switch and the second switch are located, release the residual voltage, and ensure that the tail current is successfully adjusted.

[0072] In addition, in Figure 4 and Figure 5 , Vsign represents the third input end of the adder, which is used to be connected to the second output end of the flip-flop. I1 represents the weight C1 used by the adder when performing weighting processing, and the larger I1 is, the larger C1 is, and the smaller I1 is, the smaller C1 is. Vin represents the signal source connected to the first input end of the adder, and Vout represents the signal output by the adder. Exemplarily, the adder can also include other elements according to actual needs, and the other elements include but are not limited to Figure 4 and Figure 5 The elements shown in the figure, see the following description.

[0073] Similar to M7 and M8 mentioned above, M1, M2, M3, M4, M5, and M6 are all switches. Vdd represents the power supply, R represents the resistor, and C represents the capacitor, which includes the capacitor itself shown (i.e., the load capacitor) and the capacitor corresponding to the circuit (wire) inside the adder. Clkn represents the clock signal, which is connected to both M5 and M6, indicating that M5 and M6 are connected to the same clock signal.

[0074] Figure 4 Corresponding to the above text Figure 2 When the amplifier, adder, and flip-flop are all one, there is no need to control the charging and discharging of capacitor C through the clock signal Clkn. Therefore, Clkn, M5, M6, and part of R and C are not needed. Figure 5 This corresponds to the case where there are multiple amplifiers, adders, and flip-flops. Figure 3 Taking the example shown, in adder 1, when the clock signal is low, M5 and M6 are turned on and capacitor C is charged; when the clock signal is high, M5 and M6 are turned off and capacitor C is discharged. Similarly, in adder 2, when the clock signal is high, M5 and M6 are turned on and capacitor C is charged; when the clock signal is low, M5 and M6 are turned off and capacitor C is discharged. The high and low levels of the clock signal correspond to the parity of the clock signal as described above. Thus, adder 1 and adder 2 respectively perform equalization processing on half-rate signals within a full-rate signal.

[0075] In an exemplary embodiment, such as Figure 6 As shown, the controller includes a filter, a first power detector, a second power detector, an error amplifier, a counter, and a digital-to-analog converter (DAC). The filter can be a low-pass or high-pass filter. The DAC converts digital signals to analog signals. The inputs of the filter and the second power detector are connected to the input of the controller. The output of the filter is connected to the input of the first power detector. The outputs of the first and second power detectors are connected to the input of the error amplifier. The output of the error amplifier is connected to the input of the counter. The output of the counter is connected to the input of the DAC. The output of the DAC is connected to the output of the controller.

[0076] The reason for adopting Figure 6The shown design is because: when the signal rates of signals are different, the frequencies of the signals are also different, and the power consumptions of the signals are also different. Among them, the higher the signal rate is, the higher the frequency of the signal is, and the lower the signal rate is, the lower the frequency of the signal is. Therefore, by determining the differences in the power consumptions of the signals through the filter, the first power detector, the second power detector and the error amplifier, the characteristic information for indicating the signal rate can be determined. The error amplifier sends the characteristic information to the counter through the output end of the error amplifier and the input end of the counter. The counter counts according to the characteristic information to obtain a digital signal, and sends the digital signal to the DAC through the output end of the counter and the input end of the DAC. The DAC converts the digital signal into an analog signal, and the analog signal is the control signal needed to be sent to the adder. The DAC sends the control signal to the adder through the output end of the controller and the second input end of the adder, so that the adder determines the current according to the control signal, and uses the determined current in the next equalization process.

[0077] The above illustrates the signal equalization device provided by the embodiment of the present application. Next, the signal equalization method provided by the embodiment of the present application is described, which can be applied to the signal equalization device described above. As shown in the figure, Figure 7 The signal equalization method includes the following steps 701 to 703.

[0078] Step 701: The adder receives the target signal generated by the signal source.

[0079] Among them, since the adder is connected with the signal source, the adder can receive the target signal generated by the signal source. Illustratively, the adder directly receives the target signal generated by the signal source, or the amplifier directly receives the target signal generated by the signal source, and the adder receives the target signal amplified by the amplifier.

[0080] Illustratively, before step 701, the adder can also receive the previous level signal generated by the signal source, and equalize the previous level signal generated by the signal source according to the initial current to obtain the first signal.

[0081] For example, the adder directly receives the previous level signal generated by the signal source, or the amplifier directly receives the previous level signal generated by the signal source, and the adder receives the previous level signal amplified by the amplifier. No matter what kind of signal the adder receives, the adder can equalize the received signal according to the initial current to obtain the first signal.

[0082] At step 702, the adder receives a control signal output by the controller, the control signal being determined by the controller according to feature information indicative of a signal rate of a first signal output by the adder to the controller, the first signal being obtained by the adder from equalizing a previous signal according to an initial current, the previous signal being a signal generated by the signal source before the target signal is generated.

[0083] The control signal is determined by the controller and output to the adder, so that the adder can receive the control signal output by the controller and determine a target current for equalizing the target signal according to the control signal in a subsequent process.

[0084] For example, for the case that the adder equalizes to obtain the first signal and outputs the first signal to the controller, before step 702, the controller can perform steps 7021 and 7022 as follows.

[0085] At step 7021, the controller determines the feature information according to the first signal, the feature information being indicative of a signal rate of the first signal.

[0086] For example, the controller directly receives the first signal output by the adder and performs the step 7021. Alternatively, the controller receives a signal after the action of the flip-flop and performs the step 7021, the signal after the action of the flip-flop being obtained by the flip-flop acting on the first signal. Alternatively, the controller receives a signal after the multiplexing of the MUX and performs the step 7021, the signal after the multiplexing being obtained by the MUX multiplexing the signal after the action.

[0087] In an exemplary embodiment, the feature information is a difference between a second power consumption and a first power consumption, the second power consumption being a power consumption corresponding to the first signal, and the first power consumption being a power consumption corresponding to a partial signal in the first signal having a frequency within a target range. That is, the controller determines the feature information according to the first signal, including: obtaining the partial signal in the first signal having the frequency within the target range, determining the first power consumption corresponding to the partial signal; determining the second power consumption corresponding to the first signal; and determining the difference between the second power consumption and the first power consumption as the feature information.

[0088] In some embodiments, when the filter is a high-pass filter, the high-pass filter is configured to allow a signal having a higher frequency to pass, or in other words, the target range allowed to pass by the high-pass filter is a range greater than a third threshold value, and the partial signal having the frequency within the target range is a signal having a frequency greater than the third threshold value, i.e., a high-frequency signal. Then, the first power consumption corresponding to the partial signal is a high-frequency power consumption, and the second power consumption corresponding to the first signal is a full-frequency power consumption, and the feature information is a comparison result output by the error amplifier, i.e., a difference between the high-frequency power consumption and the full-frequency power consumption, or in other words, a difference between the full-frequency power consumption and the high-frequency power consumption.

[0089] The greater the difference is, the more the high frequency power consumption is smaller than the full frequency power consumption, and thus it is indicated that the low frequency power consumption accounts for a greater proportion in the full frequency power consumption, and thus it is indicated that the first signal is a lower frequency signal with a smaller signal rate. Or, the smaller the difference is, the less the high frequency power consumption is smaller than the full frequency power consumption, and thus it is indicated that the low frequency power consumption accounts for a smaller proportion in the full frequency power consumption, and thus it is indicated that the first signal is a higher frequency signal with a larger signal rate. Since the greater the difference is, the smaller the signal rate is, and the smaller the difference is, the larger the signal rate is, and the difference is taken as the characteristic information in the embodiment of the present application, it is known that the characteristic information is negatively related to the signal rate indicated by the characteristic information when the filter is a high-pass filter, and of course, the characteristic information is also negatively related to the signal frequency.

[0090] In some other embodiments, when the filter is a low-pass filter, the low-pass filter is used to obtain a signal with a lower frequency, or in other words, the target range allowed to pass through the low-pass filter is a range less than or equal to a fourth threshold value, and the part of the signal with a frequency in the target range is a signal with a frequency less than or equal to the fourth threshold value, i.e., a low frequency signal. Then, the first power consumption corresponding to the part of the signal is a low frequency power consumption, the second power consumption corresponding to the first signal is a full frequency power consumption, and the characteristic information is the comparison result output by the error amplifier, i.e., the difference between the low frequency power consumption and the full frequency power consumption, or the difference between the full frequency power consumption and the low frequency power consumption.

[0091] The greater the difference is, the more the low frequency power consumption is smaller than the full frequency power consumption, and thus it is indicated that the high frequency power consumption accounts for a greater proportion in the full frequency power consumption, and thus it is indicated that the first signal is a higher frequency signal with a larger signal rate. Or, the smaller the difference is, the less the low frequency power consumption is smaller than the full frequency power consumption, and thus it is indicated that the low frequency power consumption accounts for a smaller proportion in the full frequency power consumption, and thus it is indicated that the first signal is a lower frequency signal with a smaller signal rate. Since the greater the difference is, the larger the signal rate is, and the smaller the difference is, the smaller the signal rate is, and the difference is taken as the characteristic information in the embodiment of the present application, it is known that the characteristic information is positively related to the signal rate indicated by the characteristic information when the filter is a low-pass filter, and of course, the characteristic information is also positively related to the signal frequency.

[0092] In step 7022, the controller determines a control signal according to the characteristic information.

[0093] The controller includes a counter that counts the characteristic information output by the error amplifier to obtain a digital signal, and a DAC that performs digital-to-analog conversion on the digital signal to obtain an analog signal, and the analog signal is the control signal.

[0094] In some embodiments, the control signal is configured to make the target current greater than the initial current when the signal rate indicated by the characteristic information is greater than a first threshold. Since the signal rate indicated by the characteristic information is greater than the first threshold, it means that the signal rate is high, resulting in a small gain of the adder, i.e., the signal rate greater than the first threshold is used to indicate that the gain of the adder generated when the adder performs the equalization processing is small. Then, the embodiment of the present application needs to increase the initial current to obtain the target current, i.e., the target current is greater than the initial current, and the increase of the current in the adder can make the gain of the adder large, i.e., the gain of the adder generated when the adder performs the equalization processing according to the target current is greater than the gain of the adder generated when the adder performs the equalization processing according to the initial current, so that the target current and the signal rate have opposite effects (e.g., offset) on the gain of the adder, keeping the gain of the adder unchanged and ensuring that the eye opening of the eye diagram is large.

[0095] In some other embodiments, the control signal is configured to make the target current less than the initial current when the signal rate indicated by the characteristic information is less than or equal to a second threshold, and the second threshold is less than the first threshold. Since the signal rate indicated by the characteristic information is less than the first threshold, it means that the signal rate is low, resulting in a large gain of the adder, i.e., the signal rate less than or equal to the second threshold is used to indicate that the gain of the adder generated when the adder performs the equalization processing is large. Then, the embodiment of the present application needs to decrease the initial current to obtain the target current, i.e., the target current is less than the initial current, and the decrease of the current in the adder can make the gain of the adder small, i.e., the gain of the adder generated when the adder performs the equalization processing according to the target current is less than the gain of the adder generated when the adder performs the equalization processing according to the initial current, so that the target current and the signal rate have opposite effects (e.g., offset) on the gain of the adder, keeping the gain of the adder unchanged and ensuring that the eye opening of the eye diagram is large.

[0096] In step 703, the adder determines the target current according to the control signal, performs the equalization processing on the target signal according to the target current, and obtains the equalization-processed signal.

[0097] Since the control signal can be used to indicate the first number of the first switches that need to be closed in the plurality of first switches and the second number of the second switches that need to be closed in the plurality of second switches, the adder can adjust the number of the closed or opened first switches and the number of the second switches according to the control signal, so as to make the target current greater than, less than, or equal to the initial current according to the indication of the control signal. Thus, the adder can perform the equalization processing on the target signal according to the target current after receiving the target signal subsequently, and obtain the equalization-processed signal.

[0098] In summary, the current used in the equalization process of the embodiment of the present application is determined according to the signal rate adaptability of the signal, so that the influence of the signal rate on the gain can be offset by the influence of the current used on the gain, thereby ensuring the stability of the gain of the signal generated by the adder. Thus, the influence of the signal rate on the gain of the signal generated by the adder can be avoided, and the signal processed by the adder maintains a small jitter, which is embodied in that the eye diagram corresponding to the signal has a small opening degree. Moreover, in the case that the signal processed by the adder is the signal whose DC offset problem is eliminated by the correction circuit of the amplifier, since the adder generates stable gain for the signal, the DC offset elimination effect of the correction circuit of the amplifier can be avoided from being invalid.

[0099] The embodiment of the present application also provides a signal equalization system, as shown in the figure, the signal equalization system comprises a signal equalization device and a signal source. The signal equalization device is connected with the signal source, and the signal equalization device can be the signal equalization device shown in any of the figures. Figure 8 In the exemplary embodiment, the signal equalization device connected with the signal source comprises that the signal equalization device is connected with the signal source through an adder or an amplifier, which is not limited here. Figure 1 to Figure 3

[0100] All the optional technical solutions described above can be combined to form optional embodiments of the present application, which will not be described one by one here.

[0101] Those skilled in the art can understand that all or part of the steps of the above-mentioned embodiments can be completed by hardware, or by program instructing relevant hardware to complete, and the program can be stored in a computer readable storage medium, and the storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk.

[0102] The above only describes the embodiments of the present application, and does not limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.​

Claims

1. A signal equalization device, characterized in that, The signal equalization device includes an adder and a controller. The first input terminal of the adder is connected to a signal source, the output terminal of the adder is connected to the input terminal of the controller, and the output terminal of the controller is connected to the second input terminal of the adder. The adder is used to receive the target signal generated by the signal source; The adder is also used to receive a control signal output by the controller. The control signal is determined by the controller based on feature information. The feature information indicates the signal rate of a first signal output by the adder to the controller. The first signal is obtained by the adder equalizing the previous stage signal based on the initial current. The previous stage signal is a signal generated by the signal source before generating the target signal. The adder is also used to determine a target current based on the control signal, and to perform equalization processing on the target signal based on the target current to obtain an equalized signal.

2. The signal equalization device according to claim 1, characterized in that, The adder includes a plurality of first switches connected in parallel. The first input terminals of the plurality of first switches are connected to the second input terminal of the adder. The second input terminals of the plurality of first switches are connected to the bias voltage source in the signal equalization device. The output terminals of the plurality of first switches are connected to the output terminal of the adder. The control signal is used to indicate a first number of first switches that need to be closed among the plurality of first switches.

3. The signal equalization device according to claim 2, characterized in that, The adder also includes a plurality of second switches, which correspond one-to-one with the plurality of first switches. The input terminals of the plurality of second switches are connected to the second input terminal of the adder. The output terminal of each second switch is grounded through the output terminal of the corresponding first switch. The control signal of the plurality of second switches is also used to indicate a second number of second switches that need to be closed. The second number of second switches correspond to the other switches, which are the first switches among the plurality of first switches other than the first number of first switches that need to be closed.

4. The signal equalization device according to any one of claims 1-3, characterized in that, The controller includes a filter, a first power detector, a second power detector, an error amplifier, a counter, and a digital-to-analog converter, wherein the filter is a low-pass filter or a high-pass filter; The input terminals of the filter and the second power detector are respectively connected to the input terminal of the controller. The output terminal of the filter is connected to the input terminal of the first power detector. The output terminals of the first power detector and the second power detector are respectively connected to the input terminal of the error amplifier. The output terminal of the error amplifier is connected to the input terminal of the counter. The output terminal of the counter is connected to the input terminal of the digital-to-analog converter. The output terminal of the digital-to-analog converter is connected to the output terminal of the controller.

5. A signal equalization system, characterized in that, The signal equalization system includes: a signal source and a signal equalization device as described in any one of claims 1-4, wherein the signal source is connected to the signal equalization device.

6. A signal equalization method, characterized in that, The signal equalization method includes: The adder receives the target signal generated by the signal source; The adder receives a control signal output by the controller. The control signal is determined by the controller based on feature information. The feature information indicates the signal rate of a first signal output by the adder to the controller. The first signal is obtained by the adder equalizing the previous stage signal based on the initial current. The previous stage signal is a signal generated by the signal source before generating the target signal. The adder determines the target current based on the control signal, and performs equalization processing on the target signal based on the target current to obtain the equalized signal.

7. The signal equalization method according to claim 6, characterized in that, If the signal rate indicated by the feature information is greater than a first threshold, the control signal is used to make the target current greater than the initial current; Wherein, the signal rate being greater than a first threshold is used to indicate that the gain generated by the adder during equalization processing is reduced, and the gain generated by the adder during equalization processing based on the target current is greater than the gain generated by the adder during equalization processing based on the initial current.

8. The signal equalization method according to claim 6, characterized in that, If the signal rate indicated by the feature information is less than or equal to the second threshold, the control signal is used to make the target current less than the initial current; The signal rate being less than or equal to the second threshold is used to indicate that the gain generated by the adder during equalization processing is increased, and the gain generated by the adder during equalization processing based on the target current is less than the gain generated by the adder during equalization processing based on the initial current.

9. The signal equalization method according to any one of claims 6-8, characterized in that, The feature information is the difference between the second power consumption and the first power consumption. The second power consumption is the power consumption corresponding to the first signal, and the first power consumption is the power consumption corresponding to the portion of the first signal whose frequency is within the target range.

10. The signal equalization method according to claim 9, characterized in that, The portion of the signal whose frequency is within the target range is a signal whose frequency is greater than the third threshold, and the feature information is negatively correlated with the signal rate indicated by the feature information.

11. The signal equalization method according to claim 9, characterized in that, The portion of the signal whose frequency is within the target range is a signal whose frequency is less than or equal to the fourth threshold, and the feature information is positively correlated with the signal rate indicated by the feature information.

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