A clock radio frequency interference calibration method, device, medium

Abstract

The present disclosure provides a clock radio frequency interference calibration method, device and medium, the clock radio frequency interference calibration method comprising: setting a chip to work at a frequency with clock harmonic interference; optimizing the spatial radio frequency interference of the environment; obtaining the intermediate frequency value of the clock harmonic interference of the digital circuit at the receiver of the analog-to-digital converter based on the initial clock duty cycle, and determining the clock interference energy at the intermediate frequency value; determining whether the clock interference energy at the intermediate frequency value affects the radio frequency sensitivity; when it is determined that the clock interference energy at the intermediate frequency value affects the radio frequency sensitivity, adjusting the clock duty cycle so that the clock interference energy at the intermediate frequency value continues to decrease to no longer change; obtaining the calibrated clock duty cycle. The clock radio frequency interference calibration method provided in the embodiments of the present disclosure can effectively reduce the harmonics of the clock of the digital circuit and reduce the interference of the clock on the radio frequency signal.

Description

Technical Field

[0001] This disclosure relates to the field of radio frequency circuit technology, specifically to a clock radio frequency interference calibration method, device, and medium. Background Technology

[0002] In today's information age, people have come to regard the transmission and interaction of information as an essential part of social life. Among these, wireless communication is the most active part of the communication field, and it has been widely used in various aspects.

[0003] With the development of integrated circuit technology, integrating a complete communication system onto a single chip has become increasingly common. Typically, such a chip includes modules such as an RF transceiver, digital modem (e.g., digital circuitry), a physical layer, and a media layer. This is what we commonly refer to as a mixed-signal chip (MS / DC). A major challenge facing MS / DC chips is the interference of clock harmonics from the digital circuitry on the RF receiving circuitry. Taking a 2.4GHz Bluetooth receiver as an example, the chip clock is 40MHz, which generates harmonics at 2.44GHz and 2.48GHz. These harmonics are coupled to the chip's RF input terminal through chip substrate coupling, electromagnetic coupling, and other methods, interfering with the signal and reducing sensitivity.

[0004] Traditional methods typically involve separating the digital chip (digital circuit) and the radio frequency (RF) chip (RF circuit) into two separate chips, or adding isolation slots between the RF chip and the digital chip. These methods, firstly, fail to effectively solve the problem and secondly, increase chip costs. Interference in digital circuits is a constant problem, urgently requiring innovative solutions.

[0005] Therefore, existing technologies still need to be improved and enhanced.

[0006] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0007] To address at least one of the aforementioned problems, as well as one or more other potential problems, this disclosure proposes a clock radio frequency interference calibration method that effectively reduces the harmonics of the clock in digital circuits and reduces their interference with radio frequency signals.

[0008] In a first aspect of this disclosure, a clock radio frequency interference calibration method is provided, comprising: setting a chip to operate at a frequency subject to clock harmonic interference; optimizing the spatial radio frequency interference noise of the environment; obtaining the intermediate frequency value of the clock harmonic interference of the digital circuit at the output of the analog-to-digital converter of the receiver based on an initial clock duty cycle, and determining the clock interference energy at the intermediate frequency value; determining whether the clock interference energy at the intermediate frequency value affects the radio frequency sensitivity; when it is determined that the clock interference energy at the intermediate frequency value affects the radio frequency sensitivity, adjusting the clock duty cycle so that the clock interference energy at the intermediate frequency value continuously decreases until it no longer changes; and obtaining a calibrated clock duty cycle.

[0009] Furthermore, in some embodiments, optimizing the spatial radio frequency interference clutter of the environment includes: receiving a first spatial radio frequency interference signal; when the peak value of the clock harmonic of the digital circuit in the spectrum output by the analog-to-digital converter is greater than the highest peak value in the received first spatial radio frequency interference clutter, and the difference between the peak value of the clock harmonic and the highest peak value in the received first spatial radio frequency interference clutter is greater than or equal to a given threshold; performing subsequent calibration steps.

[0010] Furthermore, in some embodiments, the optimization of spatial radio frequency interference clutter in the surrounding environment further includes: when the peak value of the clock harmonic of the digital circuit in the spectrum output by the analog-to-digital converter is less than or equal to the highest peak value in the received first spatial radio frequency interference clutter, or the difference between the peak value of the clock harmonic and the highest peak value in the received first spatial radio frequency interference clutter is less than a given threshold; then receiving a second spatial radio frequency interference signal, and averaging the received first spatial radio frequency interference signal and the received second spatial radio frequency interference signal to obtain a second corrected spatial radio frequency interference signal; when the peak value of the clock harmonic of the digital circuit in the spectrum output by the analog-to-digital converter is greater than the highest peak value in the received second corrected spatial radio frequency interference clutter, and the difference between the peak value of the clock harmonic and the highest peak value in the received second corrected spatial radio frequency interference clutter is greater than or equal to a given threshold; performing subsequent calibration steps.

[0011] Furthermore, in some embodiments, the optimization of spatial radio frequency interference clutter in the environment further includes: when the peak value of the clock harmonic of the digital circuit in the spectrum output by the analog-to-digital converter is less than or equal to the highest peak value in the received first spatial radio frequency interference clutter, or the difference between the peak value of the clock harmonic and the highest peak value in the received first spatial radio frequency interference clutter is greater than or equal to a given threshold; then receiving a second spatial radio frequency interference signal to an Nth spatial radio frequency interference signal, and averaging the received first spatial radio frequency interference signal and the received second spatial radio frequency interference signal to the Nth spatial radio frequency interference signal to obtain an Nth corrected spatial radio frequency interference signal, where N is a positive integer; when the peak value of the clock harmonic of the digital circuit in the spectrum output by the analog-to-digital converter is greater than the highest peak value in the received Nth corrected spatial radio frequency interference clutter, and the difference between the peak value of the clock harmonic and the highest peak value in the received Nth corrected spatial radio frequency interference clutter is greater than or equal to a given threshold; performing subsequent calibration steps.

[0012] Furthermore, in some embodiments, the step of adjusting the clock duty cycle to continuously reduce the clock interference energy at the intermediate frequency value until it no longer changes when it is determined that the clock interference energy at the intermediate frequency value affects the radio frequency sensitivity includes: adjusting the clock duty cycle to a first clock duty cycle to reduce the clock interference energy at the intermediate frequency value, and then adjusting the clock duty cycle to a second clock duty cycle to further reduce the clock interference energy at the intermediate frequency value, until the clock duty cycle can no longer be reduced after adjusting it again.

[0013] Furthermore, in some embodiments, adjusting the clock duty cycle to continuously reduce the clock interference energy at the intermediate frequency value until it no longer changes when it is determined that the clock interference energy at the intermediate frequency value affects the radio frequency sensitivity includes: increasing the clock duty cycle to a first increased clock duty cycle to reduce the clock interference energy at the intermediate frequency value when it is determined that the clock interference energy at the intermediate frequency value affects the radio frequency sensitivity, then increasing the clock duty cycle to a second increased clock duty cycle to further reduce the clock interference energy at the intermediate frequency value, until increasing the clock duty cycle again can no longer reduce the clock interference energy at the intermediate frequency value.

[0014] Furthermore, in some embodiments, adjusting the clock duty cycle to continuously reduce the clock interference energy at the intermediate frequency value until it no longer changes when it is determined that the clock interference energy at the intermediate frequency value affects the radio frequency sensitivity includes: reducing the clock duty cycle to a first reduced clock duty cycle to reduce the clock interference energy at the intermediate frequency value, then reducing the clock duty cycle to a second reduced clock duty cycle to further reduce the clock interference energy at the intermediate frequency value, until reducing the clock duty cycle again can no longer reduce the clock interference energy at the intermediate frequency value.

[0015] Further, in some embodiments, the step of adjusting the clock duty cycle to continuously reduce the clock interference energy at the intermediate frequency (IF) value until it no longer changes when it is determined that the clock interference energy at the IF value affects the radio frequency (RF) sensitivity includes: increasing the clock duty cycle to a first increased clock duty cycle when it is determined that the clock interference energy at the IF value affects the RF sensitivity, and determining the change in clock interference energy at the IF value at the current moment; and further increasing the clock duty cycle to a second increased clock duty cycle when it is determined that the clock interference energy at the IF value decreases, so that the clock interference energy at the IF value continues to decrease until it no longer changes when it is determined that the clock interference energy at the IF value decreases. The clock interference energy at the intermediate frequency value is further reduced until the clock duty cycle is increased again, which no longer reduces the clock interference energy at the intermediate frequency value. When it is determined that the clock interference energy at the intermediate frequency value is increasing, the clock duty cycle is reduced from the first increased clock duty cycle to the first decreased clock duty cycle to reduce the clock interference energy at the intermediate frequency value, and then the clock duty cycle is reduced to the second decreased clock duty cycle to further reduce the clock interference energy at the intermediate frequency value, until the clock duty cycle is reduced again, which no longer reduces the clock interference energy at the intermediate frequency value.

[0016] Further, in some embodiments, the step of adjusting the clock duty cycle to continuously reduce the clock interference energy at the intermediate frequency (IF) value until it no longer changes when it is determined that the clock interference energy at the IF value affects the radio frequency (RF) sensitivity includes: when it is determined that the clock interference energy at the IF value affects the RF sensitivity, reducing the clock duty cycle to a first reduced clock duty cycle, and determining the change in clock interference energy at the IF value at the current moment; when it is determined that the clock interference energy at the IF value decreases, further reducing the clock duty cycle to a second reduced clock duty cycle to continuously reduce the clock interference energy at the IF value until it no longer changes. The clock interference energy at the intermediate frequency value is further reduced until the clock duty cycle is reduced again, which no longer reduces the clock interference energy at the intermediate frequency value. When it is determined that the clock interference energy at the intermediate frequency value is increased, the clock duty cycle is increased from the first reduced clock duty cycle to the first increased clock duty cycle to reduce the clock interference energy at the intermediate frequency value, and then the clock duty cycle is increased to the second increased clock duty cycle to further reduce the clock interference energy at the intermediate frequency value, until the clock duty cycle is increased again, which no longer reduces the clock interference energy at the intermediate frequency value.

[0017] In a second aspect of this disclosure, an electronic device is also provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that the processor executes the computer program to implement the steps of the above-described clock radio frequency interference calibration method.

[0018] In a third aspect of this disclosure, a computer-readable storage medium is provided, on which a computer program is stored, characterized in that the computer program, when executed by a processor, implements the steps of the above-described clock radio frequency interference calibration method.

[0019] This disclosure has the following advantages over the prior art:

[0020] In some embodiments, the clock harmonic calibration method adjusts the clock duty cycle based on the different harmonic frequencies at which the chip operates, thereby optimizing the clock's interference with radio frequency sensitivity. In other embodiments, an environmental interference judgment step is set before clock harmonic calibration to determine whether spatial radio frequency interference will affect harmonic calibration, and to gradually reduce the impact of spatial radio frequency interference on calibration by averaging once or multiple times. Attached Figure Description

[0021] The above and other features, advantages and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description, wherein:

[0022] Figure 1 A schematic diagram of a receiver system generating harmonic interference according to an embodiment of the present disclosure is shown;

[0023] Figure 2 A schematic diagram of the circuit connections for clock radio frequency interference of a receiver system according to an embodiment of the present disclosure is shown;

[0024] Figure 3 A schematic flowchart of a clock radio frequency interference calibration method according to an embodiment of the present disclosure is shown;

[0025] Figure 4 A schematic diagram illustrating the spatial radio frequency interference faced by a receiver system according to an embodiment of the present disclosure when it is to be calibrated;

[0026] Figure 5 Another schematic flowchart of a clock radio frequency interference calibration method according to an embodiment of the present disclosure is shown;

[0027] Figure 6 A schematic diagram of a pulse width adjustment circuit according to an embodiment of the present disclosure is shown; and

[0028] In the various figures, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation

[0029] Embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the accompanying drawings and embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of protection of the present disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0030] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "this embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below. It should also be understood that the term "and / or" as used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0031] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, a first state may also be referred to as a second state, and similarly, a second state may also be referred to as a first state. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0032] It should be understood that, as previously stated, this disclosure discusses a chip that includes an RF transceiver and a digital modem. Therefore, a major challenge for mixed-signal chips is the interference of clock harmonics from the digital circuits on the RF receiving circuit. Figure 1 The diagram schematically illustrates the impact of harmonic interference generated by a digital system on the receiver section above. It should be noted that the digital system in the diagram schematically represents a type of digital circuit that generates clock harmonics. Generally, taking a Bluetooth SoC chip with a 40MHz clock as an example, the chip's sensitivity at 2.44GHz and 2.48GHz is often degraded due to clock harmonic interference. Here, 2.44GHz is the 61st harmonic of the clock, and 2.48GHz is the 62nd harmonic. Furthermore, the inventors found that some chips are mainly interfered with by the 2.44GHz clock, while others are mainly interfered with by the 2.48GHz clock. This is determined by the clock's duty cycle, such as... Figure 1 As shown.

[0033] To address at least one of the aforementioned problems, and one or more other potential problems, this disclosure proposes a clock radio frequency interference calibration method. A detailed explanation is provided in conjunction with the accompanying drawings.

[0034] Furthermore, according to Fourier analysis, an ideal square wave, i.e., a clock with a 50% duty cycle, has only odd-order harmonics and no even-order harmonics. However, as the duty cycle shifts by 50%, even-order harmonics begin to appear and increase, while odd-order harmonics decrease. Utilizing this characteristic of the clock, the duty cycle can be adjusted according to the different harmonic frequencies at which the chip operates, thereby optimizing the clock's interference with RF sensitivity.

[0035] Furthermore, in some embodiments, when the Bluetooth chip operates at 2.44 GHz, i.e., odd-order harmonics, the clock duty cycle can be adjusted to deviate from 50% to reduce odd-order harmonics. When the single chip operates at 2.48 GHz, the clock duty cycle can be adjusted to be as close to 50% as possible to suppress interference from even-order harmonics.

[0036] To implement such a system-level clock interference mitigation scheme on a System on Chip (SoC), it is necessary to introduce a pulse width adjustment circuit (the pulse width refers to the clock duty cycle) and a system-level calibration method.

[0037] Further, see Figure 2 As shown, a pulse width adjustment circuit and a lookup table are introduced through the clock of the digital circuit. Still using a Bluetooth chip as an example, the receiver system uses a 0.75MHz low-IF scheme, meaning that when the chip operates at 2.44GHz, the local oscillator is 2.43925GHz; obviously, Figure 2 The upper section represents the receiver system. When the 61st harmonic of the 40MHz clock, or 2.44GHz, is coupled to the receiver's RF output, it is down-converted to an intermediate frequency (IF) of 0.75MHz. The energy of the interfering IF signal can be determined through conversion by an analog-to-digital converter (ADC). It should be understood that if the energy of the 2.44GHz clock harmonic is greater than, for example, -110dBm, it indicates that the interference energy will affect the sensitivity of Bluetooth transmission. When the interference energy is sufficiently large to affect RF sensitivity, the clock interference calibration system is activated to calibrate the 61st harmonic interference of the digital circuit's clock.

[0038] Furthermore, taking 2.44GHz clock harmonic interference as an example, the calibration procedure is as follows (and please refer to...). Figure 5 The process begins by setting the chip to operate at 2.44GHz and configuring the default values ​​for the pulse width adjustment (PWM) circuit. It then checks whether the 0.75MHz energy at the receiver's analog-to-digital converter (ADC) output affects sensitivity. If it does, the pulse width (clock duty cycle) is first increased. Further analysis is then performed to determine whether the 0.75MHz energy increases or decreases with this increase. If it decreases, the adjustment is correct; if it increases, the adjustment is incorrect, and the pulse width (clock duty cycle) should be decreased. This process is repeated after each adjustment step. The calibration ends when the 0.75MHz energy is optimized to the point where it no longer affects sensitivity. The PWM circuit register is then stored in a lookup table. When the receiver operates at 2.44GHz, the configuration corresponding to the lookup table is applied to the PWM circuit to eliminate the impact of clock harmonics on receiver sensitivity.

[0039] Alternatively, in some embodiments, the same calibration procedure can be extended to any clock circuit of other corresponding system-on-chips (SoCs). Alternatively, taking a Bluetooth SoC using a 26MHz clock as an example, the 93rd, 94th, and 95th harmonics of 26MHz need to be calibrated, i.e., 2.418GHz, 2.444GHz, and 2.470GHz. It should be understood that setting the chip to operate at 2.444GHz is an example; with a Bluetooth chip using a 26MHz clock frequency as an example, calibration at 2.418GHz and 2.470GHz is also required. It should also be understood that these three frequencies are chosen because, using a 26MHz reference clock as an example, these three frequencies are the harmonic frequencies of 26MHz in the 2.4-2.48GHz range, specifically its 93rd, 94th, and 95th harmonics. If the clock frequency is 40MHz, then only the 2.4GHz, 2.44GHz, and 2.48GHz frequencies are considered, which are the 60th, 61st, and 62nd harmonics of 40MHz. It should also be noted that the default value of the above-mentioned pulse width adjustment circuit configuration is the register value given by the logic circuit in the pulse width adjustment circuit to the multiplexer to select a clock with an intermediate delay. In addition, it can be determined whether the interference energy will affect the sensitivity based on whether it is greater than, for example, -105dBm. The interference energy is the magnitude of the 0.75MHz signal output by the ADC. If it increases, it means that the interference has increased.

[0040] Alternatively, in some embodiments, the above method can be used for clock harmonic interference calibration and optimization for any system that includes an RF receiver and digital circuitry.

[0041] The embodiments will be further explained below with reference to the accompanying drawings.

[0042] Figure 3 A schematic flowchart of a clock radio frequency interference calibration method according to an embodiment of the present disclosure is shown. In this illustrated embodiment, the clock radio frequency interference calibration method 100 includes: step 110, setting the chip to operate at a frequency with clock harmonic interference; step 120, optimizing the spatial radio frequency interference noise of the environment; step 130, obtaining the intermediate frequency value of the clock harmonic interference of the digital circuit at the output of the analog-to-digital converter of the receiver based on an initial clock duty cycle, and determining the clock interference energy at the intermediate frequency value; step 140, determining whether the clock interference energy at the intermediate frequency value affects the radio frequency sensitivity; when it is determined that the clock interference energy at the intermediate frequency value affects the radio frequency sensitivity, adjusting the clock duty cycle so that the clock interference energy at the intermediate frequency value continuously decreases until it no longer changes; step 150, obtaining the calibrated clock duty cycle. It should be understood that the physical quantity that changes after calibration is the magnitude of the intermediate frequency signal energy output by the analog-to-digital converter, which in this example is the magnitude of a 750kHz signal.

[0043] It should be understood that a crucial step in the clock radio frequency interference calibration method disclosed herein is the assessment and optimization of spatial radio frequency interference. It should be understood that, taking the 2.4 GHz band as an example, this is a band with a high level of interference, and various devices operate in this band. Therefore, before clock harmonic calibration, it is necessary to determine whether spatial radio frequency interference will affect harmonic calibration and how to reduce the impact of spatial radio frequency interference on calibration.

[0044] Further, see Figure 4 The spectrum output by the receiver's analog-to-digital converter (ADC) includes not only the 0.75MHz harmonic interference but also spatial radio frequency (RF) noise (the four vertical dashed lines in the diagram). It should be understood that spatial RF interference must be 6dB smaller than the clock harmonics (i.e., a given threshold) for effective calibration. However, spatial RF interference can sometimes be larger than the clock harmonics. Therefore, the calibration method in this embodiment optimizes the spatial RF noise of the environment, and is also an adaptive spatial RF interference judgment and optimization method. This method is based on the randomness and unsustainability of spatial RF interference, because in reality, RF signals are transmitted intermittently and continuously select operating frequency bands randomly.

[0045] In a further embodiment, for example, upon receiving the interference signal for the first time, it is determined whether the maximum spatial radio frequency interference is smaller than the 0.75MHz clock harmonic interference. If the difference is 6dB or greater, the calibration environment meets the requirements, and subsequent calibration steps can be performed. Obviously, if the requirements are not met—that is, if the maximum spatial radio frequency interference is greater than or equal to the 0.75MHz clock harmonic interference, or even if the maximum spatial radio frequency interference is less than the 0.75MHz clock harmonic interference, but the difference between them is less than 6dB—then generally, a second reception of the interference signal is required. The second received interference signal is then averaged with the first interference signal. Due to the randomness and intermittency of spatial radio frequency interference, the average value of multiple sums will inevitably decrease (as more received interference signals are summed and averaged, the average value will tend towards zero, meaning the spatial radio frequency interference will be reduced or even eliminated), while the clock harmonic interference is stable and will not decrease. Furthermore, through the above averaging process, the resulting signal is ultimately smaller, and the difference between it and the clock harmonic interference satisfies 6dB or greater, at which point subsequent calibration steps can be performed. It should also be understood that, generally, a maximum of ten spatial radio frequency interference signals should be received. This is because ten spatial radio frequency interference signals is a relatively suitable value selected based on practical experience, and calibration can be performed in most cases without taking too long. Pursuing extreme cases, such as more than ten times, will lead to excessively long calibration times.

[0046] Based on the above discussion, in some embodiments, the optimization of spatial radio frequency interference clutter in the environment includes: receiving a first spatial radio frequency interference signal (i.e., the first received interference signal mentioned above); when the peak value of the clock harmonic of the digital circuit in the spectrum output by the analog-to-digital converter is greater than the highest peak value in the received first spatial radio frequency interference clutter, and the difference between the peak value of the clock harmonic and the highest peak value in the received first spatial radio frequency interference clutter is greater than or equal to a given threshold; this indicates that the spatial radio frequency interference clutter in the environment meets the calibration requirements, and subsequent calibration steps can be performed.

[0047] Furthermore, in some embodiments, the above-mentioned optimization of spatial radio frequency interference noise in the environment further includes: when the peak value of the clock harmonic of the digital circuit in the spectrum output by the analog-to-digital converter is less than or equal to the highest peak value of the received first spatial radio frequency interference noise, or when the difference between the peak value of the clock harmonic and the highest peak value of the received first spatial radio frequency interference noise is less than a given threshold (for example, if the above-mentioned 6dB threshold is not met, it indicates that the spatial radio frequency interference noise in the environment is too strong, and forcibly performing subsequent calibration steps in this case will cause the calibration result to fail); therefore, it is necessary to receive a second spatial radio frequency interference signal (i.e., to receive the interference signal a second time as described above), and to... The first spatial radio frequency interference signal and the second spatial radio frequency interference signal (i.e., the two received spatial radio frequency interference signals) are added together and averaged to obtain the second corrected spatial radio frequency interference signal (i.e., the corrected spatial radio frequency interference signal received twice). Then, the corrected spatial radio frequency interference signal is further judged. If the peak value of the clock harmonic of the digital circuit in the spectrum output by the analog-to-digital converter is greater than the highest peak value of the received second corrected spatial radio frequency interference noise, and the difference between the peak value of the aforementioned clock harmonic and the highest peak value of the received second corrected spatial radio frequency interference noise is greater than or equal to a given threshold (i.e., the corrected signal meets a set threshold, such as 6dB), then the subsequent calibration steps are performed.

[0048] Furthermore, in some embodiments, the above-mentioned optimization of spatial radio frequency interference noise in the surrounding environment further includes: when the peak value of the clock harmonic of the digital circuit in the spectrum output by the analog-to-digital converter is less than or equal to the highest peak value in the received first spatial radio frequency interference noise, or when the difference between the peak value of the clock harmonic and the highest peak value in the received first spatial radio frequency interference noise is greater than a given threshold; then receiving a second spatial radio frequency interference signal to an Nth spatial radio frequency interference signal (i.e., multiple spatial radio frequency interference signals can be received), and converting the received first spatial radio frequency interference signal into a signal that is not explicitly stated in the original text. The interference signal and the received second to Nth spatial radio frequency interference signals are added together and averaged to obtain the Nth corrected spatial radio frequency interference signal (i.e., the spatial radio frequency interference signal after N corrections), where N is a positive integer; when the peak value of the clock harmonic of the digital circuit in the spectrum output by the analog-to-digital converter is greater than the highest peak value in the noise of the received Nth corrected spatial radio frequency interference, and the difference between the peak value of the aforementioned clock harmonic and the highest peak value in the noise of the received Nth corrected spatial radio frequency interference is greater than or equal to a given threshold; the subsequent calibration steps are performed.

[0049] Furthermore, in some embodiments, the above-mentioned adjustment of the pulse width to make the clock interference energy at the intermediate frequency value continuously decrease until it no longer changes when it is determined that the clock interference energy at the intermediate frequency value affects the radio frequency sensitivity includes: when it is determined that the clock interference energy at the intermediate frequency value affects the radio frequency sensitivity, adjusting the pulse width to a first pulse width to reduce the clock interference energy at the intermediate frequency value, and then adjusting the pulse width to a second pulse width to further reduce the clock interference energy at the intermediate frequency value, until the clock interference energy at the intermediate frequency value can no longer be reduced after adjusting the pulse width again.

[0050] Furthermore, in some embodiments, the above-mentioned adjustment of the pulse width to make the clock interference energy at the intermediate frequency value continuously decrease until it no longer changes when it is determined that the clock interference energy at the intermediate frequency value affects the radio frequency sensitivity includes: when it is determined that the clock interference energy at the intermediate frequency value affects the radio frequency sensitivity, increasing the pulse width to a first increased pulse width to reduce the clock interference energy at the intermediate frequency value, and then increasing the pulse width to a second increased pulse width to further reduce the clock interference energy at the intermediate frequency value, until the clock interference energy at the intermediate frequency value can no longer be reduced after increasing the pulse width again.

[0051] Furthermore, in some embodiments, the above-mentioned adjustment of the pulse width to continuously reduce the clock interference energy at the intermediate frequency value until it no longer changes when it is determined that the clock interference energy at the intermediate frequency value affects the radio frequency sensitivity includes: when it is determined that the clock interference energy at the intermediate frequency value affects the radio frequency sensitivity, reducing the pulse width to a first reduced pulse width to reduce the clock interference energy at the intermediate frequency value, then reducing the pulse width to a second reduced pulse width to further reduce the clock interference energy at the intermediate frequency value, until the pulse width is reduced again and it is no longer possible to reduce the clock interference energy at the intermediate frequency value.

[0052] Furthermore, in some embodiments, the above-mentioned adjustment of the pulse width to continuously reduce the clock interference energy at the intermediate frequency (IF) value until it no longer changes when it is determined that the clock interference energy at the IF value affects the RF sensitivity includes: when it is determined that the clock interference energy at the IF value affects the RF sensitivity, increasing the pulse width to a first increased pulse width and determining the change in clock interference energy at the IF value at the current moment; when it is determined that the clock interference energy at the IF value decreases, further increasing the pulse width to a second increased pulse width to further reduce the clock interference energy at the IF value, until increasing the pulse width again can no longer reduce the clock interference energy at the IF value; when it is determined that the clock interference energy at the IF value increases, decreasing the pulse width from the first increased pulse width to a first decreased pulse width to reduce the clock interference energy at the IF value, then decreasing the pulse width to a second decreased pulse width to further reduce the clock interference energy at the IF value, until decreasing the pulse width again can no longer reduce the clock interference energy at the IF value.

[0053] Furthermore, in some embodiments, the above-mentioned adjustment of the pulse width to continuously reduce the clock interference energy at the intermediate frequency (IF) value until it no longer changes when it is determined that the clock interference energy at the IF value affects the RF sensitivity includes: when it is determined that the clock interference energy at the IF value affects the RF sensitivity, reducing the pulse width to a first reduced pulse width and determining the change in clock interference energy at the IF value at the current moment; when it is determined that the clock interference energy at the IF value decreases, further reducing the pulse width to a second reduced pulse width to further reduce the clock interference energy at the IF value, until further reducing the pulse width can no longer reduce the clock interference energy at the IF value; when it is determined that the clock interference energy at the IF value increases, increasing the pulse width from the first reduced pulse width to a first increased pulse width to reduce the clock interference energy at the IF value, and then increasing the pulse width to a second increased pulse width to further reduce the clock interference energy at the IF value, until further increasing the pulse width can no longer reduce the clock interference energy at the IF value.

[0054] It should be understood that in the various embodiments of this disclosure, it is the harmonics generated by the clock circuit that need to be adjusted or eliminated. These harmonics are not generated by the pulse width adjustment circuit; the pulse width circuit is used to adjust these harmonics. It should also be understood that the clock pulse width (also known as the clock duty cycle) of this disclosure is defined as the time of the high level within one clock cycle. For the circuit setup of the pulse width adjustment circuit (i.e., the pulse width adjustment circuit), please refer to [link to relevant documentation]. Figure 6 In this circuit, the input clock and the delayed clock are simultaneously fed to an AND gate and an OR gate, respectively, to obtain clocks that decrease and increase the pulse width. The digital control circuit selects whether to increase or decrease the pulse width as needed. Furthermore, in... Figure 6 The timing diagram below shows the signal timing at each marked position. Clk_in is the clock signal at the input terminal, Clk_dly is the signal at the output terminal of the multiplexer, Clk_and is the signal at the output terminal of the AND gate, Clk_or is the signal at the output terminal of the OR gate, and Clk_out is the signal at the output terminal of the second-stage multiplexer.

[0055] In other embodiments, an electronic device is also provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the clock radio frequency interference calibration method described above.

[0056] In some other embodiments, a computer-readable storage medium is also provided, on which a computer program is stored, wherein the computer program, when executed by a processor, implements the steps of the clock radio frequency interference calibration method described above.

[0057] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0058] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A clock radio frequency interference calibration method, characterized in that, include: Set the chip to operate at a frequency subject to clock harmonic interference; Optimize the spatial radio frequency interference clutter in the surrounding environment; Based on the initial clock duty cycle, the intermediate frequency value of the clock harmonic interference of the digital circuit at the output of the analog-to-digital converter of the receiver is obtained, and the clock interference energy is calculated at the intermediate frequency value. Determine whether clock interference energy at the intermediate frequency value affects radio frequency sensitivity; When it is determined that the clock interference energy at the intermediate frequency value affects the radio frequency sensitivity, the clock duty cycle is adjusted so that the clock interference energy at the intermediate frequency value continues to decrease until it no longer changes. Obtain the calibrated clock duty cycle. The process of adjusting the clock duty cycle to continuously reduce the clock interference energy at the intermediate frequency value until it no longer changes includes: adjusting the clock duty cycle to increase or decrease to a first clock duty cycle to reduce the clock interference energy at the intermediate frequency value; further adjusting the clock duty cycle to increase or decrease to a second clock duty cycle to further reduce the clock interference energy at the intermediate frequency value; until the clock duty cycle is further increased or decreased again and can no longer reduce the clock interference energy at the intermediate frequency value.

2. The clock radio frequency interference calibration method according to claim 1, characterized in that, The optimization of spatial radio frequency interference clutter in the environment includes: Receives first-space radio frequency interference signals; When the peak value of the clock harmonic of the digital circuit in the spectrum output by the analog-to-digital converter is greater than the highest peak value of the received first spatial radio frequency interference noise, and the difference between the peak value of the clock harmonic and the highest peak value of the received first spatial radio frequency interference noise is greater than or equal to a given threshold, the subsequent calibration steps are performed.

3. The clock radio frequency interference calibration method according to claim 2, characterized in that, The optimization of spatial radio frequency interference clutter in the environment also includes: When the peak value of the clock harmonic of the digital circuit is less than or equal to the highest peak value of the clutter of the first spatial radio frequency interference received in the spectrum of the analog-to-digital converter output, or when the difference between the peak value of the clock harmonic and the highest peak value of the clutter of the first spatial radio frequency interference received is less than a given threshold. Then, the second spatial radio frequency interference signal is received, and the received first spatial radio frequency interference signal and the received second spatial radio frequency interference signal are added together and averaged to obtain the second corrected spatial radio frequency interference signal. When the peak value of the clock harmonic of the digital circuit in the spectrum output by the analog-to-digital converter is greater than the highest peak value in the received second-correction spatial radio frequency interference clutter, and the difference between the peak value of the clock harmonic and the highest peak value in the received second-correction spatial radio frequency interference clutter is greater than or equal to a given threshold, the subsequent calibration steps are performed.

4. The clock radio frequency interference calibration method according to claim 2, characterized in that, The optimization of spatial radio frequency interference clutter in the environment also includes: When the peak value of the clock harmonic of the digital circuit is less than or equal to the highest peak value of the clutter of the first spatial radio frequency interference received in the spectrum output by the analog-to-digital converter, or when the difference between the peak value of the clock harmonic and the highest peak value of the clutter of the first spatial radio frequency interference received is greater than or equal to a given threshold. Then, the second spatial radio frequency interference signal to the Nth spatial radio frequency interference signal is received, and the received first spatial radio frequency interference signal and the received second spatial radio frequency interference signal to the Nth spatial radio frequency interference signal are added together and averaged to obtain the Nth corrected spatial radio frequency interference signal, where N is a positive integer; When the peak value of the clock harmonic of the digital circuit in the frequency spectrum output by the analog-to-digital converter is greater than the highest peak value of the received noise of the Nth corrected space radio frequency interference, and the difference between the peak value of the clock harmonic and the highest peak value of the received noise of the Nth corrected space radio frequency interference is greater than or equal to a given threshold, the subsequent calibration steps are performed.

5. The clock radio frequency interference calibration method according to claim 1, characterized in that, When it is determined that the clock interference energy at the intermediate frequency value affects the radio frequency sensitivity, adjusting the clock duty cycle so that the clock interference energy at the intermediate frequency value continuously decreases until it no longer changes includes: When it is determined that clock interference energy at the intermediate frequency value affects RF sensitivity Increase the clock duty cycle to a first increased clock duty cycle, and determine the change in clock interference energy at the intermediate frequency value at the current moment; When it is determined that the clock interference energy at the intermediate frequency value increases, the clock duty cycle is reduced from a first increased clock duty cycle to a first decreased clock duty cycle to reduce the clock interference energy at the intermediate frequency value. Then, the clock duty cycle is reduced to a second decreased clock duty cycle to further reduce the clock interference energy at the intermediate frequency value, until the clock duty cycle is reduced again and the clock interference energy at the intermediate frequency value can no longer be reduced.

6. The clock radio frequency interference calibration method according to claim 1, characterized in that, When it is determined that the clock interference energy at the intermediate frequency value affects the radio frequency sensitivity, adjusting the clock duty cycle so that the clock interference energy at the intermediate frequency value continuously decreases until it no longer changes includes: When it is determined that clock interference energy at the intermediate frequency value affects RF sensitivity The clock duty cycle is reduced to a first reduced clock duty cycle, and the clock interference energy change at the intermediate frequency value at the current moment is determined. When it is determined that the clock interference energy at the intermediate frequency value increases, the clock duty cycle is increased from a first decreasing clock duty cycle to a first increasing clock duty cycle to reduce the clock interference energy at the intermediate frequency value. Then, the clock duty cycle is increased to a second increasing clock duty cycle to further reduce the clock interference energy at the intermediate frequency value, until the clock duty cycle is increased again and it is no longer possible to reduce the clock interference energy at the intermediate frequency value.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1-6.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1-6.

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