Protocol identification circuit, method, device and equipment and storage medium

Abstract

The invention relates to a protocol identification circuit, method and device, equipment and a storage medium. The circuit comprises an upstream circuit used for sending a first starting signal to a process control state machine after initialization; the flow control state machine is used for reading the configuration information in the configuration table and sending the configuration information and a second starting signal to the link protocol identification state machine; the link protocol identification state machine is used for configuring the physical layer matching function circuit according to the configuration information, acquiring the feature information extracted by the feature extraction circuit, and sending the feature information to the process control state machine; and the process control state machine is also used for reading the expected characteristics in the detection table under the condition that the characteristic information is received, matching the characteristic information with the expected characteristics, and taking the protocol type corresponding to the expected characteristics as a protocol identification result and sending the protocol identification result to the upstream circuit under the condition that the matching is passed. The protocol identification efficiency can be improved.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a protocol identification circuit, method, apparatus, device, and storage medium. Background Technology

[0002] As chip process nodes continue to evolve, the internal circuit density of chips has increased significantly, leading to a substantial increase in the demands on interface bandwidth and protocol support capabilities. The underlying logic of this trend is that enhanced interface bandwidth and expanded multi-protocol support not only directly broaden the application scenarios of chips but also effectively reduce potential tape-out costs and iteration risks. SerDes (Serializer / Deserializer) multiplexing technology provides the physical layer foundation for efficient transmission of multi-protocol data, while high-speed protocol interface identification circuits effectively support automatic multi-protocol detection and compatibility.

[0003] High-speed protocol interface identification circuits can distinguish different protocol types from the initial stage of communication, avoiding data transmission conflicts and errors, ensuring the reliability of multiplexed links, and helping devices expand application scenarios and reduce design and tape-out costs. For example, a certain company's RAID series chips can automatically identify SATA / SAS / NVMe protocols. This chip uses the operation logic of "switching the high-speed interface controller (communication protocol) and attempting to establish a connection." However, this method is a trial-and-error identification method, which suffers from slow identification speed, and the identification process becomes longer as the number of detected protocol types increases. Summary of the Invention

[0004] Therefore, it is necessary to provide a protocol identification circuit, method, apparatus, computer device, readable storage medium, and computer program product that can improve the efficiency of protocol identification in order to address the above-mentioned technical problems.

[0005] In a first aspect, this application provides a protocol identification circuit, comprising: an upstream circuit, a process control state machine, a link protocol identification state machine, a physical layer supporting functional circuit, and a physical layer transceiver connected in sequence; and further comprising a feature extraction circuit connected to the physical layer transceiver and the link protocol identification state machine.

[0006] The upstream circuit is used to send the first start signal to the process control state machine after initialization;

[0007] The process control state machine is used to read the configuration information in the configuration table upon receiving the first start signal, and to send the configuration information and the second start signal to the link protocol identification state machine.

[0008] The link protocol identification state machine is used to configure the physical layer supporting functional circuits according to the configuration information upon receiving the second start signal and configuration information, obtain the feature information extracted by the feature extraction circuit, and send the feature information to the process control state machine; the feature information is obtained by feature extraction of the link signals received by the physical layer transceiver through the feature extraction circuit.

[0009] The process control state machine is also used to read the expected features in the detection table when the feature information is received, match the feature information with the expected features, and if the match is successful, send the protocol type corresponding to the expected feature as the protocol identification result to the upstream circuit.

[0010] In one embodiment, the configuration table has multiple pages, each storing configuration information corresponding to a different protocol type; the process control state machine is also used to traverse the configuration table page by page, read the configuration information of the current page in the configuration table, and send the configuration information of the current page and the second start signal to the link protocol identification state machine.

[0011] The link protocol identification state machine is used to configure the physical layer supporting functional circuits according to the configuration information of the current page when the second start signal and the configuration information of the current page are received, obtain the feature information corresponding to the current page extracted by the feature extraction circuit, and fill the feature information corresponding to the current page into the result table until the configuration table is traversed.

[0012] The process control state machine is also used to read the feature information corresponding to each of the multiple pages in the result table, and to read the expected features of each of the multiple protocol types in the detection table. It matches the feature information corresponding to each of the multiple pages with the expected features. If the matching result indicates that the matching is successful, it sends the protocol type corresponding to the expected feature as the protocol identification result to the upstream circuit.

[0013] In one embodiment, the process control state machine is further configured to, when the similarity between the feature information corresponding to any page in the matching result indicates that the feature information is greater than a preset value than the expected feature of any protocol type in the detection table, send the protocol type corresponding to the expected feature as the protocol identification result to the upstream circuit.

[0014] In one embodiment, the process control state machine is further configured to send the matching result indicating that the matching failed to match to the upstream circuit if the matching result indicates that the matching failed.

[0015] The upstream circuit is also used to modify the configuration information in the configuration table when a matching result that fails to match is received, so as to obtain a modified configuration table.

[0016] The link protocol identification state machine is used to reconfigure the physical layer supporting functional circuits according to the configuration information in the modified configuration table when the second start signal and the configuration information in the modified configuration table are received, to obtain the updated feature information extracted by the feature extraction circuit, and to send the updated feature information to the process control state machine.

[0017] The process control state machine is also used to read the expected features in the detection table when updated feature information is received, match the updated feature information with the expected features, and if the match is successful, send the protocol type corresponding to the expected feature as the protocol identification result to the upstream circuit.

[0018] In one embodiment, the upstream circuit is further configured to determine a link anomaly when a preset number of failed matching results are received.

[0019] In one embodiment, the configuration information in the configuration table includes physical layer internal clock configuration information, physical layer transmit link simulation parameters, physical layer receive link simulation parameters, physical layer transmit link data path configuration information, physical layer receive link data path configuration information, and physical layer special signal configuration information; the link protocol identification state machine is also used to configure the physical layer supporting functional circuits according to the physical layer internal clock configuration information, physical layer transmit link simulation parameters, physical layer receive link simulation parameters, physical layer transmit link data path configuration information, physical layer receive link data path configuration information, and physical layer special signal configuration information in the configuration information when the second start signal and configuration information are received.

[0020] Secondly, this application provides a protocol identification method applied to the protocol identification circuit of the first aspect, comprising:

[0021] After initialization, a first start signal is sent to the process control state machine. The first start signal instructs the process control state machine to read the configuration information in the configuration table upon receiving the first start signal, and to send the configuration information and a second start signal to the link protocol identification state machine. The configuration information and the second start signal instruct the link protocol identification state machine to configure the physical layer supporting functional circuits according to the configuration information and to obtain the feature information extracted by the feature extraction circuit. The feature information is obtained by extracting features from the link signals received by the physical layer transceiver through the feature extraction circuit. The feature information instructs the process control state machine to read the expected features in the detection table upon receiving the feature information, match the feature information with the expected features, and if the match is successful, take the protocol type corresponding to the expected feature as the protocol identification result.

[0022] Receive the protocol identification result sent by the process control state machine.

[0023] Thirdly, this application also provides a protocol identification device, comprising:

[0024] The sending module is used to send a first start signal to the process control state machine after initialization. The first start signal instructs the process control state machine to read the configuration information in the configuration table and send the configuration information and a second start signal to the link protocol identification state machine upon receiving the first start signal. The configuration information and the second start signal instruct the link protocol identification state machine to configure the physical layer supporting functional circuits according to the configuration information and obtain the feature information extracted by the feature extraction circuit. The feature information is obtained by extracting features from the link signals received by the physical layer transceiver through the feature extraction circuit. The feature information instructs the process control state machine to read the expected features in the detection table upon receiving the feature information, match the feature information with the expected features, and if the match is successful, take the protocol type corresponding to the expected feature as the protocol identification result.

[0025] The receiving module is used to receive the protocol identification results sent by the process control state machine.

[0026] Fourthly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0027] After initialization, a first start signal is sent to the process control state machine. The first start signal instructs the process control state machine to read the configuration information in the configuration table upon receiving the first start signal, and to send the configuration information and a second start signal to the link protocol identification state machine. The configuration information and the second start signal instruct the link protocol identification state machine to configure the physical layer supporting functional circuits according to the configuration information and to obtain the feature information extracted by the feature extraction circuit. The feature information is obtained by extracting features from the link signals received by the physical layer transceiver through the feature extraction circuit. The feature information instructs the process control state machine to read the expected features in the detection table upon receiving the feature information, match the feature information with the expected features, and if the match is successful, take the protocol type corresponding to the expected feature as the protocol identification result.

[0028] Receive the protocol identification result sent by the process control state machine.

[0029] Fifthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, performs the following steps:

[0030] After initialization, a first start signal is sent to the process control state machine. The first start signal instructs the process control state machine to read the configuration information in the configuration table upon receiving the first start signal, and to send the configuration information and a second start signal to the link protocol identification state machine. The configuration information and the second start signal instruct the link protocol identification state machine to configure the physical layer supporting functional circuits according to the configuration information and to obtain the feature information extracted by the feature extraction circuit. The feature information is obtained by extracting features from the link signals received by the physical layer transceiver through the feature extraction circuit. The feature information instructs the process control state machine to read the expected features in the detection table upon receiving the feature information, match the feature information with the expected features, and if the match is successful, take the protocol type corresponding to the expected feature as the protocol identification result.

[0031] Receive the protocol identification result sent by the process control state machine.

[0032] Sixthly, this application also provides a computer program product, including a computer program that, when executed by a processor, performs the following steps:

[0033] After initialization, a first start signal is sent to the process control state machine. The first start signal instructs the process control state machine to read the configuration information in the configuration table upon receiving the first start signal, and to send the configuration information and a second start signal to the link protocol identification state machine. The configuration information and the second start signal instruct the link protocol identification state machine to configure the physical layer supporting functional circuits according to the configuration information and to obtain the feature information extracted by the feature extraction circuit. The feature information is obtained by extracting features from the link signals received by the physical layer transceiver through the feature extraction circuit. The feature information instructs the process control state machine to read the expected features in the detection table upon receiving the feature information, match the feature information with the expected features, and if the match is successful, take the protocol type corresponding to the expected feature as the protocol identification result.

[0034] Receive the protocol identification result sent by the process control state machine.

[0035] The aforementioned protocol identification circuit, method, apparatus, computer equipment, computer-readable storage medium, and computer program product, in which the upstream circuit starts a process control state machine and a link protocol identification state machine after initialization, the process control state machine reads the configuration information from the configuration table, the link protocol identification state machine configures the physical layer supporting functional circuits according to the configuration information, and uses a feature extraction circuit to extract features from the link signals, transmitting the feature information to the process control state machine, and the process control state machine matches the feature information with the expected features in the detection table, which can quickly determine the protocol identification result. The core process of protocol identification is completely completed autonomously by the hardware state machine, and the identification logic is solidified in the hardware. Compared with the traditional software trial-and-error identification method, it can improve the reliability of the protocol identification result. At the same time, the hardware-based state transition does not require software scheduling overhead, which greatly improves the protocol identification efficiency. The upstream circuit can directly switch to the corresponding protocol to establish the link according to the protocol identification result, which is simple and efficient, without the need for the upstream circuit to intervene in the complex initialization process and protocol polling operation, reducing the software load and system power consumption of the upstream circuit. In addition, the configuration table and detection table can be flexibly configured and expanded according to actual needs, compatible with multiple protocol types, and can quickly adapt to new protocol types, reducing the risk of technology iteration. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of the protocol identification circuit in one embodiment;

[0038] Figure 2 This is a flowchart illustrating a protocol identification method in one embodiment;

[0039] Figure 3 This is a schematic diagram of the data processing flow of upstream software in one embodiment;

[0040] Figure 4 This is a schematic diagram of the data processing flow of the process control state machine in one embodiment;

[0041] Figure 5 This is a schematic diagram of the data processing flow of the link protocol identification state machine in one embodiment;

[0042] Figure 6 This is a structural block diagram of a protocol identification device in one embodiment;

[0043] Figure 7 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0045] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0046] In one exemplary embodiment, such as Figure 1 As shown, a protocol identification circuit is provided. The circuit includes: an upstream circuit 101, a process control state machine 102, a link protocol identification state machine 103, a physical layer supporting functional circuit 104, and a physical layer transceiver 105 connected in sequence; it also includes a feature extraction circuit 106 connected to the physical layer transceiver 105 and the link protocol identification state machine 103; the upstream circuit 101 is used to send a first start signal to the process control state machine 102 after initialization; the process control state machine 102 is used to read configuration information from the configuration table and send configuration information and a second start signal to the link protocol identification state machine 103 upon receiving the first start signal; the link protocol identification state machine... The process control state machine 103 is used to configure the physical layer supporting functional circuit 104 according to the configuration information when it receives the second start signal and configuration information, obtain the feature information extracted by the feature extraction circuit 106, and send the feature information to the process control state machine 102. The feature information is obtained by feature extraction of the link signal received by the physical layer transceiver 105 through the feature extraction circuit 106. The process control state machine 102 is also used to read the expected feature in the detection table when it receives the feature information, match the feature information with the expected feature, and if the match is successful, send the protocol type corresponding to the expected feature as the protocol identification result to the upstream circuit 101.

[0047] The upstream circuit 101 is the top-level control module that triggers the protocol identification process. Upstream software runs within the upstream circuit 101, responsible for overall identification parameter configuration, link identification initiation, link identification result collection, status monitoring during the link identification process, and dynamic updates of the configuration and detection tables. This ensures the system's flexibility and scalability.

[0048] The process control state machine 102 is a logic circuit implemented based on a hardware finite state machine (FSM). It dominates the scheduling function and its core function is to coordinate the logical scheduling and data interaction of the entire protocol identification process. Based on the detection table, configuration table, and the status of each module in the hardware architecture, it achieves automated and highly reliable protocol identification and adaptation. It can associate the detection table, configuration table, and result table, coordinate the identification process, synchronize the results with the upstream circuit 101, and configure the clock source according to the configuration table.

[0049] The link protocol identification state machine 103 is a hardware state machine for physical layer configuration and feature acquisition. It dominates the protocol identification process. Its core functions are information configuration and feature extraction. It interacts with the process control state machine 102, receives feature and status information from the physical layer supporting function circuit 104, controls the physical layer supporting function circuit 104, and collects feature information extracted by the feature extraction circuit 106 until the protocol type identification is completed.

[0050] The Physical Layer Transceiver 105 (PHY) is a complete physical layer solution that includes TX (transmit link), RX (receive link), clock resources, and supporting signal processing modules, supporting the transmission and reception of link signals of multiple protocol types.

[0051] The feature extraction circuit 106 refers to the hardware circuit that extracts features from the link signals acquired by the physical layer transceiver 105. For example, the feature extraction circuit 106 comprises an OOB (Out of Band) feature detection module, an encoding detection module, a scrambling code detection module, a training sequence detection module, a specific sequence detection module, and auxiliary functional circuits. Feature information includes protocol frame headers, encoding rules, and loss of signal (LOS) information.

[0052] The detection table refers to a data table that stores protocol features for protocol type identification. For example, the detection table stores the mapping relationship between various protocol types and their corresponding expected features. After the link protocol identification state machine 103 starts, it acquires the feature information extracted by the feature extraction circuit 106 and sends it to the process control state machine 102. The process control state machine 102 matches the feature information with the expected features in the detection table according to the mapping relationship, determines the protocol type corresponding to the expected feature that matches successfully as the protocol identification result, and sends it to the upstream circuit 101.

[0053] The physical layer supporting functional circuit 104 refers to the set of peripheral hardware circuits that assist the PHY (physical layer transceiver 105) in its operation, including the physical layer clock resource management circuit 107, the physical layer transmit link path controller 108, the physical layer receive link path controller 109, the physical layer analog link control interface 110, and the physical layer configuration and status interface 111.

[0054] The configuration table refers to a data table storing SerDes adaptation parameters, which may include physical layer configuration information for at least one protocol. The configuration information in the configuration table includes at least physical layer internal clock configuration information, external clock resource configuration information, physical layer transmit link (TX) analog parameters, physical layer receive link (RX) analog parameters, physical layer transmit link (TX) data path configuration information, physical layer receive link (RX) data path configuration information, and physical layer special signal configuration information. The physical layer supporting functional circuit 104 can adjust its electrical characteristics according to the configuration information in the configuration table to ensure that the physical layer transceiver 105 can accurately receive and process link signals of different protocols.

[0055] In some embodiments, the feature extraction circuit 106 is also used to obtain the state information of the physical layer supporting functional circuit 104, and the process control state machine 102 determines the protocol identification result based on the feature information and the state information.

[0056] The physical layer clock resource management circuit 107 is used to configure the frequency and mode of the internal PLL (Phase Locked Loop) of the physical layer transceiver 105 to match protocol and clock requirements. The physical layer transmit link path controller 108 and the physical layer receive link path controller 109 are used to control the transmit path of the physical layer transceiver 105 and process received data, respectively, supporting protocol data transmission and reception. The physical layer analog link control interface 110 is used to adjust the physical layer analog link parameters to ensure signal transmission quality. The physical layer configuration and status interface 111 is used to configure the parameters of the physical layer transceiver 105 and feed back its operating status to the link protocol identification state machine 103.

[0057] The protocol identification circuit also includes an external clock management circuit 112 and an external or internal clock resource 113. The external or internal clock resource 113 is used to provide a physical layer reference clock and, in coordination with the external clock management circuit 112 and the upstream circuit 101, is responsible for clock allocation and synchronization for a specific protocol.

[0058] The first start signal is used to start the process control state machine 102, and the second start signal is used to start the link protocol identification state machine 103.

[0059] In some embodiments, the feature extraction circuit 106 extracts the signal features in the early stage of link establishment. Typically, it only needs to sample and identify the link establishment signal sent from the peer TX to the local physical layer transceiver 105 RX a few times. After receiving a valid link establishment RX signal, the local physical layer transceiver 105 sends a "link establishment handshake" signal from the TX to the peer RX to complete the link protocol identification. This process usually takes hundreds of microseconds to tens of milliseconds. This method is highly scalable, and the specific time depends on the number and types of protocols to be identified.

[0060] In the aforementioned protocol identification circuit, the upstream circuit initiates a process control state machine and a link protocol identification state machine after initialization. The process control state machine reads the configuration information from the configuration table, and the link protocol identification state machine configures the physical layer supporting functional circuits according to the configuration information. It also uses a feature extraction circuit to extract features from the link signals and transmits the feature information to the process control state machine. The process control state machine matches the feature information with the expected features in the detection table, which can quickly determine the protocol identification result. The core process of protocol identification is completely completed autonomously by the hardware state machine, and the identification logic is solidified in the hardware. Compared with the traditional software trial-and-error identification method, it can improve the reliability of the protocol identification result. At the same time, the hardware-based state transition does not require software scheduling overhead, which greatly improves the protocol identification efficiency. The upstream circuit can directly switch to the corresponding protocol to establish the link based on the protocol identification result, which is simple and efficient. It does not require the upstream circuit to intervene in the complex initialization process and protocol polling operation, reducing the software load and system power consumption of the upstream circuit. In addition, the configuration table and detection table can be flexibly configured and expanded according to actual needs, compatible with multiple protocol types, and can quickly adapt to new protocol types, reducing the risk of technology iteration.

[0061] In an exemplary embodiment, the configuration table has multiple pages, each storing configuration information corresponding to various protocol types. The process control state machine 102 is further configured to traverse the configuration table page by page, read the configuration information of the current page, and send the configuration information of the current page and a second start signal to the link protocol identification state machine 103. Upon receiving the second start signal and the configuration information of the current page, the link protocol identification state machine 103 configures the physical layer supporting function circuit 104 according to the configuration information of the current page, obtains the feature information corresponding to the current page extracted by the feature extraction circuit 106, and fills the feature information corresponding to the current page into the result table until the configuration table traversal is completed. The process control state machine 102 is further configured to read the feature information corresponding to each page in the result table, read the expected features of various protocol types in the detection table, match the feature information corresponding to each page with the expected features, and if the matching result indicates that the matching is successful, send the protocol type corresponding to the expected feature as the protocol identification result to the upstream circuit 101.

[0062] The configuration table can store configuration information for various protocol types. Multiple protocol types can be stored in pages in the configuration table so that the process control state machine 102 can read the configuration information corresponding to different protocol types in pages.

[0063] The process control state machine 102 traverses the configuration table page by page, and the link protocol identification state machine 103 configures the physical layer supporting functional circuit 104 according to the configuration information of each page. After the circuit is configured, the physical layer supporting functional circuit 104 can work in the corresponding protocol type state. In this way, the feature extraction circuit 106 extracts feature information. If the link signal belongs to the protocol type corresponding to the current page, the feature information corresponding to the current page should match the expected feature of the corresponding protocol type in the detection table. If the link signal does not belong to the protocol type corresponding to the current page, the feature information corresponding to the current page should not match the expected feature of the corresponding protocol type in the detection table.

[0064] The extracted feature information is filled into the result table. After all pages in the configuration table have been traversed, the link protocol identification state machine 103 sends a traversal completion signal to the process control state machine 102. The process control state machine 102 reads the result table, matches the feature information corresponding to each page with the expected features of each protocol type in the detection table, thereby determining the protocol identification result and sending it to the upstream circuit 101.

[0065] In some embodiments, the expected features of the detection table may include: OOB features, data encoding features, TS1 / TS2 features, K28.5 features, specific sequence matching features, scrambling features, etc.

[0066] In this embodiment, the configuration table is traversed page by page to configure various protocol types, thereby improving the recognition accuracy in multi-protocol scenarios. The protocol types in the configuration table and detection table can be flexibly expanded as needed, without the need to design a separate configuration and caching circuit for each protocol. The matching process is completed automatically by the hardware state machine, which improves the protocol recognition efficiency.

[0067] In an exemplary embodiment, the process control state machine 102 is further configured to send the protocol type corresponding to the expected feature as the protocol identification result to the upstream circuit 101 when the similarity between the feature information corresponding to any page in the matching result indicates that the feature information is more than a preset value than the expected feature of any protocol type in the detection table.

[0068] During the feature matching process, the flow control state machine 102 traverses the feature information of multiple pages and matches the feature information corresponding to the current page with the expected features of various protocol types in the detection table. If the similarity between more than a preset number of feature information in the current page and the expected feature of any protocol type exceeds a preset value, it is determined that the feature information and the expected feature have matched successfully, and the protocol type corresponding to the expected feature is taken as the protocol identification result.

[0069] For example, if all the feature information corresponding to the current page is consistent with the corresponding expected feature, or if more than a preset number of feature information on the current page is consistent with the corresponding expected feature, then it is determined that the feature information corresponding to the current page matches the corresponding expected feature.

[0070] For example, if physical layer transceiver 105 is connected to an unknown link, the protocol type needs to be identified. Possible protocol types include at least SATA / SAS / NVME. The configuration table can include the configuration information corresponding to each of the SATA / SAS / NVME protocols.

[0071] The configuration information corresponding to the SATA protocol may include: ① configuring the phase-locked loop to 6GHz; ② configuring the TX data link to 20bit; ③ configuring the RX data link to 20bit; ④ configuring the PHY analog parameters (this may include various control signals); ⑤ configuring the external reference clock to 100MHz, etc.

[0072] The configuration information corresponding to the SAS protocol may include: ① configuring the phase-locked loop to 12GHz; ② configuring the TX data link to 40bit; ③ configuring the RX data link to 40bit; ④ configuring the PHY analog parameters (this may include various control signals); ⑤ configuring the external reference clock to 100MHz, etc.

[0073] The configuration information corresponding to the NVME protocol may include: ① configuring the phase-locked loop to 12GHz; ② configuring the TX data link to 40bit; ③ configuring the RX data link to 40bit; ④ configuring the PHY analog parameters (this may include various control signals); ⑤ configuring the external reference clock source slot / local, with a frequency of 100MHz, etc.

[0074] The test table can include the expected characteristics corresponding to each of the SATA / SAS / NVME protocols.

[0075] The expected characteristics of the SATA protocol include: ① OOB detects the COM_RESET sequence; ② 1.5G link clock sequence is successfully recovered and CDR is locked; ③ No response to the returned COMSAS sequence.

[0076] The expected characteristics of the SAS protocol include: ① OOB detects the COM_RESET sequence; ② 3G link clock sequence is successfully restored and CDR is locked; ③ COMSAS sequence is returned in response.

[0077] The expected characteristics of the NVME protocol include: ① not sending any OOB sequences; ② detecting 8B / 10B encoding and symbols; ③ detecting TS1 / TS2 sequences.

[0078] In this embodiment, the expected feature with the highest similarity result is determined by matching the feature information with the expected feature, and the protocol type corresponding to the expected feature is used as the protocol identification result, thereby improving the reliability of protocol identification.

[0079] In an exemplary embodiment, the process control state machine 102 is further configured to send the matching result indicating a failed match to the upstream circuit 101 when the matching result indicates a failed match; the upstream circuit 101 is further configured to modify the configuration information in the configuration table upon receiving the matching result indicating a failed match, thereby obtaining a modified configuration table; the link protocol identification state machine 103 is configured to reconfigure the physical layer supporting function circuit 104 according to the configuration information in the modified configuration table upon receiving the second start signal and the configuration information in the modified configuration table, obtain the updated feature information extracted by the feature extraction circuit 106, and send the updated feature information to the process control state machine 102; the process control state machine 102 is further configured to read the expected feature in the detection table upon receiving the updated feature information, match the updated feature information with the expected feature, and, if the match is successful, send the protocol type corresponding to the expected feature as the protocol identification result to the upstream circuit 101.

[0080] The matching result indicating a failed match can be interpreted as the similarity between the feature information and the expected feature not exceeding a preset value, indicating that the flow control state machine 102 failed to identify the protocol type. Upon receiving a failed match result, the upstream circuit 101 modifies the configuration information in the configuration table. For example, it increases the burst period of the OOB sequence memory by a preset duration. For instance, if the OOB sequence memory has a burst period of 106.66ns, and the configuration table sets a burst period between 102ns and 110ns, it might miss the burst detection signal, leading to a failed match. Therefore, the burst period can be increased in the configuration table, configuring the burst detection to a burst period of 90ns to 130ns, which is more lenient and easier to detect.

[0081] After the configuration table is modified, the physical layer supporting functional circuit 104 is reconfigured using the configuration information in the modified configuration table. This causes the feature extraction circuit 106 to extract updated features. The updated features are then matched with the expected features to obtain the protocol recognition result.

[0082] In some embodiments, referring to the method described above, the feature information can also be matched with the modified expected features in the detection table to determine the protocol identification result.

[0083] In this embodiment, a proactive optimization solution is provided to address protocol identification failures caused by link interference, initial configuration deviations, etc. By modifying the configuration information in the configuration table to adapt to the actual link characteristics, the problem that fixed configurations cannot cope with complex environments is solved, thereby improving the accuracy and flexibility of protocol identification.

[0084] In one exemplary embodiment, the upstream circuit 101 is further configured to determine a link anomaly when a preset number of failed matching results are received.

[0085] In this process, when the upstream circuit 101 receives a failed match result, it counts the match result. If the count reaches a preset number, it determines that the link is abnormal. For example, physical link open circuit, short circuit, protocol incompatibility, signal attenuation exceeding the compensation range, etc.

[0086] In some embodiments, when the upstream circuit 101 determines that the link is abnormal, it triggers an alarm and logs to help maintenance personnel quickly locate the type of fault.

[0087] In this embodiment, a threshold is used to determine the matching results that fail to match. When the threshold is reached, the link is determined to be abnormal, the invalid operation is stopped, and system resources are saved.

[0088] In an exemplary embodiment, the configuration information in the configuration table includes physical layer internal clock configuration information, physical layer transmit link simulation parameters, physical layer receive link simulation parameters, physical layer transmit link data path configuration information, physical layer receive link data path configuration information, and physical layer special signal configuration information; the link protocol identification state machine 103 is further configured, upon receiving the second start signal and configuration information, to configure the physical layer supporting functional circuit 104 according to the physical layer internal clock configuration information, physical layer transmit link simulation parameters, physical layer receive link simulation parameters, physical layer transmit link data path configuration information, physical layer receive link data path configuration information, and physical layer special signal configuration information in the configuration information.

[0089] Among them, reference Figure 1The physical layer supporting functional circuit 104 includes a physical layer clock resource management circuit 107, a physical layer transmit link path controller 108, a physical layer receive link path controller 109, a physical layer analog link control interface 110, and a physical layer configuration and status interface 111.

[0090] For example, the link protocol identification state machine 103 can configure the physical layer internal clock configuration information for the physical layer clock resource management circuit 107, configure the physical layer transmit link data path configuration information for the physical layer transmit link path controller 108, configure the physical layer receive link data path configuration information for the physical layer receive link path controller 109, configure the physical layer transmit link simulation parameters and physical layer receive link simulation parameters for the physical layer analog link control interface 110, and configure the physical layer special signal configuration information for the physical layer configuration and status interface 111.

[0091] In this embodiment, by covering the configuration information such as clock, analog link, data path, and special signals of the physical layer operation through the configuration table, the link protocol identification state machine can complete the fine configuration of the hardware circuit according to the parameter requirements of different protocols, ensuring that the signal features collected by the feature extraction circuit truly reflect the protocol attributes, avoiding parameter conflicts when switching between multiple protocols, and improving the stability of multi-protocol identification.

[0092] In one exemplary embodiment, such as Figure 2 As shown, a protocol identification method is provided, which can be applied to... Figure 1 The protocol identification circuit in the example is used for illustration, including the following steps 202 to 206. Wherein:

[0093] Step 202: After initialization, a first start signal is sent to the process control state machine. The first start signal instructs the process control state machine to read the configuration information in the configuration table upon receiving the first start signal, and to send the configuration information and a second start signal to the link protocol identification state machine. The configuration information and the second start signal instruct the link protocol identification state machine to configure the physical layer supporting functional circuits according to the configuration information and obtain the feature information extracted by the feature extraction circuit. The feature information is obtained by extracting features from the link signals received by the physical layer transceiver through the feature extraction circuit. The feature information instructs the process control state machine to read the expected features in the detection table upon receiving the feature information, match the feature information with the expected features, and if the match is successful, take the protocol type corresponding to the expected feature as the protocol identification result.

[0094] Step 204: Receive the protocol identification result sent by the process control state machine.

[0095] The upstream circuit deploys upstream software. After initialization, the upstream software configures the physical layer's supporting functional circuits by starting the process control state machine and the link protocol identification state machine. It then extracts feature information through a feature extraction circuit and matches it with a detection table to determine the protocol identification result. For example... Figure 3 The diagram illustrates the data processing flow of upstream software in some embodiments. After completing system initialization, the upstream software starts the process control state machine. Through data processing in the process control state machine, it determines whether protocol identification is successful. If identification is successful, the protocol identification result is written to the result table. If identification fails, it indicates that there is no link at the other end or the link quality is extremely poor. After N failed identification attempts, the configuration table or detection table is modified, and the process control state machine is restarted for protocol identification. If identification still fails, it is determined that the link quality is too poor.

[0096] like Figure 4 The diagram illustrates the data processing flow of the process control state machine in some embodiments. Upon receiving a start signal from the upstream software, the process control state machine reads the configuration table and sends it to the link protocol identification state machine. It then configures clock resources, starts the link protocol identification state machine, and processes the data to read the protocol identification result. The process machine matches the protocol identification result with the expected features in the detection table. If the match is successful, the successful protocol identification result is written to the result table, including a success flag and feature information. If the match fails, the failed protocol identification result is written to the result table, including a failure flag and feature information. This process continues until all configurations in the configuration table are completed, at which point the upstream software is notified that protocol identification is complete.

[0097] like Figure 5 The diagram shows a data processing flow of the link protocol identification state machine in some embodiments. Upon receiving a start signal from the process control state machine, the link protocol identification state machine configures the physical layer clock resources, transmitter, receiver, and other parameters according to the configuration information, acquires the feature information extracted by the feature extraction circuit, and outputs the feature information to the process control state machine.

[0098] In the aforementioned protocol identification method, the upstream circuit starts a process control state machine and a link protocol identification state machine after initialization. The process control state machine reads the configuration information from the configuration table, and the link protocol identification state machine configures the physical layer supporting functional circuits according to the configuration information. It also uses a feature extraction circuit to extract features from the link signals and transmits the feature information to the process control state machine. The process control state machine matches the feature information with the expected features in the detection table, which can quickly determine the protocol identification result. The core process of protocol identification is completely completed autonomously by the hardware state machine, and the identification logic is solidified in the hardware. Compared with the traditional software trial-and-error identification method, it can improve the reliability of the protocol identification result. At the same time, the hardware-based state transition does not require software scheduling overhead, which greatly improves the protocol identification efficiency. The upstream circuit can directly switch to the corresponding protocol to establish the link based on the protocol identification result, which is simple and efficient. It does not require the upstream circuit to intervene in the complex initialization process and protocol polling operation, reducing the software load and system power consumption of the upstream circuit. In addition, the configuration table and detection table can be flexibly configured and expanded according to actual needs, compatible with multiple protocol types, and can quickly adapt to new protocol types, reducing the risk of technology iteration.

[0099] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0100] Based on the same inventive concept, this application also provides a protocol identification device for implementing the protocol identification method described above. The solution provided by this device is similar to the implementation described in the above method; therefore, the specific limitations in one or more protocol identification device embodiments provided below can be found in the limitations of the protocol identification method described above, and will not be repeated here.

[0101] In one exemplary embodiment, such as Figure 6 As shown, a protocol identification device 600 is provided, including: a transmitting module 620 and a receiving module 640, wherein:

[0102] The sending module 620 is used to send a first start signal to the process control state machine after initialization. The first start signal is used to instruct the process control state machine to read the configuration information in the configuration table and send the configuration information and a second start signal to the link protocol identification state machine upon receiving the first start signal. The configuration information and the second start signal are used to instruct the link protocol identification state machine to configure the physical layer supporting functional circuits according to the configuration information and obtain the feature information extracted by the feature extraction circuit. The feature information is obtained by extracting features from the link signals received by the physical layer transceiver through the feature extraction circuit. The feature information is used to instruct the process control state machine to read the expected features in the detection table upon receiving the feature information, match the feature information with the expected features, and if the match is successful, take the protocol type corresponding to the expected feature as the protocol identification result.

[0103] The receiving module 640 is used to receive the protocol identification results sent by the process control state machine.

[0104] The aforementioned protocol identification device, through its upstream circuit, initiates a process control state machine and a link protocol identification state machine after initialization. The process control state machine reads configuration information from the configuration table, while the link protocol identification state machine configures the physical layer supporting functional circuits based on the configuration information and uses a feature extraction circuit to extract features from the link signals. These feature information is then transmitted to the process control state machine, which matches the feature information with the expected features in the detection table, enabling rapid determination of the protocol identification result. The core process of protocol identification is entirely autonomously completed by the hardware state machine, with the identification logic embedded in the hardware. Compared to traditional software trial-and-error identification methods, this improves the reliability of the protocol identification results. Furthermore, the hardware-based state transitions eliminate software scheduling overhead, significantly enhancing protocol identification efficiency. The upstream circuit can directly switch to the corresponding protocol to establish a link based on the protocol identification result, simplifying and optimizing the process. This eliminates the need for complex initialization processes and protocol polling operations by the upstream circuit, reducing software load and system power consumption. Additionally, the configuration table and detection table can be flexibly configured and expanded according to actual needs, are compatible with multiple protocol types, and can quickly adapt to new protocol types, reducing the risk of technology iteration.

[0105] Each module in the aforementioned protocol identification device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0106] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 7As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements a protocol identification method. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0107] Those skilled in the art will understand that Figure 7 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0108] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.

[0109] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0110] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0111] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0112] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external buffer memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0113] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0114] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A protocol identification circuit, characterized in that, include: The system comprises, in sequence, an upstream circuit, a process control state machine, a link protocol identification state machine, a physical layer supporting functional circuit, and a physical layer transceiver; it also includes a feature extraction circuit connected to the physical layer transceiver and the link protocol identification state machine. The upstream circuit is used to send a first start signal to the process control state machine after initialization; The process control state machine is used to read the configuration information in the configuration table when the first start signal is received, and send the configuration information and the second start signal to the link protocol identification state machine. The link protocol identification state machine is used to configure the physical layer supporting functional circuit according to the configuration information when receiving the second start signal and the configuration information, obtain the feature information extracted by the feature extraction circuit, and send the feature information to the process control state machine; the feature information is obtained by feature extraction of the link signal received by the physical layer transceiver through the feature extraction circuit. The process control state machine is further configured to, upon receiving the feature information, read the expected feature in the detection table, match the feature information with the expected feature, and if the match is successful, send the protocol type corresponding to the expected feature as the protocol identification result to the upstream circuit.

2. The protocol identification circuit according to claim 1, characterized in that, The configuration table has multiple pages, each storing configuration information corresponding to various protocol types. The process control state machine is also used to traverse the configuration table page by page, read the configuration information of the current page in the configuration table, and send the configuration information of the current page and the second start signal to the link protocol identification state machine. The link protocol identification state machine is used to configure the physical layer supporting functional circuit according to the configuration information of the current page when it receives the second start signal and the configuration information of the current page, obtain the feature information corresponding to the current page extracted by the feature extraction circuit, and fill the feature information corresponding to the current page into the result table until the configuration table is traversed. The process control state machine is also used to read the feature information corresponding to each of the multiple pages in the result table, and to read the expected features of each of the multiple protocol types in the detection table. The feature information corresponding to each of the multiple pages is matched with the expected features. If the matching result indicates that the matching is successful, the protocol type corresponding to the expected feature is used as the protocol identification result and sent to the upstream circuit.

3. The protocol identification circuit according to claim 2, characterized in that, The process control state machine is also used to send the protocol type corresponding to the expected feature as the protocol identification result to the upstream circuit when the similarity between the feature information corresponding to any page in the matching result indicates that the feature information is more than a preset value than the expected feature of any protocol type in the detection table.

4. The protocol identification circuit according to claim 1, characterized in that, The process control state machine is also used to send the matching result of the failed match to the upstream circuit when the matching result indicates that the match failed. The upstream circuit is also used to modify the configuration information in the configuration table when a matching result that fails to match is received, so as to obtain a modified configuration table. The link protocol identification state machine is used to reconfigure the physical layer supporting functional circuit according to the configuration information in the modified configuration table when it receives the second start signal and the configuration information in the modified configuration table, obtain the updated feature information extracted by the feature extraction circuit, and send the updated feature information to the process control state machine. The process control state machine is further configured to, upon receiving the updated feature information, read the desired feature from the detection table, match the updated feature information with the desired feature, and if the match is successful, send the protocol type corresponding to the desired feature as the protocol identification result to the upstream circuit.

5. The protocol identification circuit according to claim 4, characterized in that, The upstream circuit is also used to determine a link anomaly when a preset number of failed matching results are received.

6. The protocol identification circuit according to claim 1, characterized in that, The configuration information in the configuration table includes physical layer internal clock configuration information, physical layer transmit link simulation parameters, physical layer receive link simulation parameters, physical layer transmit link data path configuration information, physical layer receive link data path configuration information, and physical layer special signal configuration information. The link protocol identification state machine is also used to configure the physical layer supporting functional circuits according to the physical layer internal clock configuration information, physical layer transmit link simulation parameters, physical layer receive link simulation parameters, physical layer transmit link data path configuration information, physical layer receive link data path configuration information, and physical layer special signal configuration information in the configuration information when the second start signal and the configuration information are received.

7. A protocol identification method, characterized in that, The method, applied to the protocol identification circuit according to any one of claims 1-6, comprises: After initialization, a first start signal is sent to the process control state machine. This first start signal instructs the process control state machine, upon receiving the first start signal, to read configuration information from the configuration table and send the configuration information and a second start signal to the link protocol identification state machine. The configuration information and the second start signal instruct the link protocol identification state machine to configure the physical layer supporting functional circuits according to the configuration information and obtain feature information extracted by the feature extraction circuit. The feature information is obtained by extracting features from the link signals received by the physical layer transceiver through the feature extraction circuit. The feature information instructs the process control state machine, upon receiving the feature information, to read the expected features from the detection table, match the feature information with the expected features, and if the match is successful, use the protocol type corresponding to the expected feature as the protocol identification result. Receive the protocol identification result sent by the process control state machine.

8. A protocol identification device, characterized in that, The device includes: The sending module is configured to send a first start signal to the process control state machine after initialization. The first start signal instructs the process control state machine, upon receiving the first start signal, to read configuration information from a configuration table and send the configuration information and a second start signal to the link protocol identification state machine. The configuration information and the second start signal instruct the link protocol identification state machine to configure the physical layer supporting functional circuits according to the configuration information and obtain feature information extracted by the feature extraction circuit. The feature information is obtained by extracting features from the link signals received by the physical layer transceiver through the feature extraction circuit. The feature information instructs the process control state machine, upon receiving the feature information, to read expected features from a detection table, match the feature information with the expected features, and, if the match is successful, use the protocol type corresponding to the expected feature as the protocol identification result. The receiving module is used to receive the protocol identification result sent by the process control state machine.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method of claim 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the method of claim 7.

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