A method for manufacturing a semiconductor structure and a semiconductor structure

Abstract

The application provides a semiconductor structure preparation method and a semiconductor structure. The preparation method comprises the following steps: providing an initial semiconductor structure, wherein the initial semiconductor structure comprises a substrate, a trench isolation structure, an oxide layer and a gate structure, the trench isolation structure is arranged in the substrate and protrudes from the substrate, the oxide layer is formed on the surface of the substrate, and the gate structure is formed on the surface of the oxide layer; depositing a heat-conducting layer on the surface of the oxide layer and the surface of the trench isolation structure; coating a photoresist layer on the surface of the heat-conducting layer and the surface of the gate structure, and performing a patterning process on the photoresist layer to expose an amorphization ion implantation area; and performing amorphization ion implantation on the amorphization ion implantation area. The preparation method can timely conduct heat in the photoresist layer during amorphization ion implantation, reduce heat accumulation of the photoresist layer, and reduce splashing or collapse of the photoresist layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and the semiconductor structure thereof. Background Technology

[0002] As semiconductor manufacturing technology continues to advance, device channel dimensions are gradually entering the nanometer scale, exacerbating the impact of short-channel effects and hot carrier injection effects on device characteristics. Existing technologies typically employ amorphizing ion implantation (PAI) to suppress the lateral diffusion of subsequent dopant ions, thereby mitigating the short-channel effect (SCE). However, this method can lead to photoresist layer melting and spattering or structural collapse, introducing particle contamination and causing systematic shifts in wafer acceptance test (WAT) electrical parameters, severely impacting process windows and product yield. Summary of the Invention

[0003] This invention provides a method for preparing a semiconductor structure and the semiconductor structure itself, in order to improve the yield of semiconductor structures.

[0004] The present invention provides a method for fabricating a semiconductor structure, comprising the following steps:

[0005] An initial semiconductor structure is provided, the initial semiconductor structure including a substrate, a trench isolation structure, an oxide layer and a gate structure, the trench isolation structure being disposed within the substrate and extending out of the substrate at its upper part, the oxide layer being formed on the surface of the substrate, and the gate structure being formed on the surface of the oxide layer;

[0006] A thermally conductive layer is deposited on the surface of the oxide layer and the surface of the trench isolation structure;

[0007] A photoresist layer is coated on the surface of the thermally conductive layer and the surface of the gate structure. The photoresist layer is patterned to expose the amorphous ion implantation region.

[0008] Amorphous ion implantation is performed on the amorphous ion implantation region.

[0009] In one embodiment of the present invention, before performing amorphous ion implantation on the amorphous ion implantation region, the preparation method further includes a process of decoupling plasma oxidation of the photoresist layer.

[0010] In one embodiment of the present invention, the duration of the decoupled plasma oxidation is 100~200s.

[0011] In one embodiment of the present invention, the amorphous ion implantation is performed in a stepwise implantation manner, with an implantation time interval of 2 to 5 seconds.

[0012] In one embodiment of the present invention, the concentration of the amorphous ion implantation is 4E15~6E15 ions / cm³. 2 .

[0013] In one embodiment of the present invention, the amorphous ions include any one of germanium ions, silicon ions, and xenon ions.

[0014] In one embodiment of the present invention, the thermally conductive layer is a silicon nitride layer.

[0015] In one embodiment of the present invention, after exposing the amorphous ion implantation region, before performing amorphous ion implantation on the amorphous ion implantation region, the preparation method further includes a process of removing the thermally conductive layer of the amorphous ion implantation region.

[0016] In one embodiment of the present invention, after performing amorphous ion implantation on the amorphous ion implantation region, the preparation method further includes the process of removing the photoresist layer and the thermally conductive layer below the photoresist layer.

[0017] The present invention also provides a semiconductor structure, which is made by the above-described semiconductor structure preparation method.

[0018] The beneficial effects of this invention are as follows: This invention proposes a method for fabricating a semiconductor structure and a semiconductor structure in which the initial semiconductor structure includes a trench isolation structure formed in a substrate, and an oxide layer and a gate structure sequentially formed on the substrate surface. After depositing a thermally conductive layer on the surface of the oxide layer and the trench isolation structure, a photoresist layer is coated on the surface of the thermally conductive layer and the surface of the gate structure. The photoresist layer is then patterned to expose an amorphous ion implantation region, which is subsequently subjected to amorphous ion implantation. An unexpected benefit of this application is that by providing a thermally conductive layer between the photoresist layer and the oxide layer of the initial semiconductor structure, heat from the photoresist layer during amorphous ion implantation can be promptly dissipated, reducing heat accumulation in the photoresist layer and minimizing spattering or collapse of the photoresist layer. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0020] In the attached diagram:

[0021] Figure 1 This is a flowchart illustrating the fabrication process of a semiconductor structure in one embodiment of the present invention;

[0022] Figure 2 This is a schematic diagram of an oxide layer formed on a substrate according to an embodiment of the present invention;

[0023] Figure 3 This is a schematic diagram of a nitride layer formed on a substrate in one embodiment of the present invention;

[0024] Figure 4 This is a schematic diagram of the formation of the second photoresist layer in one embodiment of the present invention;

[0025] Figure 5 This is a schematic diagram of the formation of a trench in one embodiment of the present invention;

[0026] Figure 6 This is a schematic diagram of removing the second photoresist layer in one embodiment of the present invention;

[0027] Figure 7 This is a schematic diagram of a trench isolation structure formed in one embodiment of the present invention;

[0028] Figure 8 This is a schematic diagram of removing the nitride layer in one embodiment of the present invention;

[0029] Figure 9 This is a schematic diagram of an etched trench isolation structure in one embodiment of the present invention;

[0030] Figure 10 This is a schematic diagram of forming a gate structure in one embodiment of the present invention;

[0031] Figure 11 This is a schematic diagram of a sidewall structure formed in one embodiment of the present invention;

[0032] Figure 12 This is a schematic diagram of the formation of a heat-conducting layer in one embodiment of the present invention;

[0033] Figure 13 This is a schematic diagram of the formation of the first photoresist layer in one embodiment of the present invention;

[0034] Figure 14 This is a schematic diagram of decoupling plasma oxidation of the first photoresist layer in one embodiment of the present invention;

[0035] Figure 15 This is a schematic diagram of the removal of the thermally conductive layer from the amorphous ion implantation region in one embodiment of the present invention;

[0036] Figure 16 This is a schematic diagram of amorphous ion implantation in an amorphous ion implantation region according to an embodiment of the present invention;

[0037] Figure 17 This is a schematic diagram of removing the first photoresist layer and the thermally conductive layer below the first photoresist layer in one embodiment of the present invention.

[0038] The attached figures are labeled as follows:

[0039] 10. Initial semiconductor structure; 100. Substrate; 110. First well region; 120. Second well region; 200. Oxide layer; 300. Nitride layer; 400. Second photoresist layer; 410. Trench region; 420. Trench; 500. Trench isolation structure; 600. Gate structure; 610. Gate oxide layer; 620. Gate material layer; 630. Sidewall structure; 700. Thermally conductive layer; 800. First photoresist layer; 900. Amorphous region. Detailed Implementation

[0040] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0041] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0042] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0043] When numerical ranges are given in the embodiments, it should be understood that, unless otherwise stated in the present invention, both endpoints of each numerical range and any value between the two endpoints may be selected. Unless otherwise defined, all technical and scientific terms used in this invention, as well as the prior art known to those skilled in the art and the description of the invention, may be implemented using any prior art methods, devices, and materials similar to or equivalent to the methods, devices, and materials in the embodiments of the present invention.

[0044] Research has shown that before amorphous ion implantation, an oxide layer is typically deposited on the substrate surface, with a photoresist layer placed on top of this oxide layer. During amorphous ion implantation, the amorphous ions collide with the photoresist layer, converting their kinetic energy into heat. When the local temperature exceeds the glass transition temperature (Tg) of the photoresist, it can cause the photoresist layer to melt and sputter or collapse. The oxide layer material is, for example, silicon dioxide (SiO2), which has a thermal conductivity of approximately 0.27 W / (m²). The heat dissipation effect is poor, and the heat generated by the collision between the photoresist layer and amorphous ions is not easily dissipated, leading to heat accumulation within the photoresist layer. This damages the photoresist layer and affects subsequent processes and semiconductor yield. The impact is particularly pronounced when the implantation concentration of amorphous ions is high. Therefore, this application provides a method for fabricating a semiconductor structure to enhance the stability of the photoresist layer during amorphous ion implantation and improve the yield of the semiconductor structure.

[0045] Please see Figures 1 to 16 The method for preparing a semiconductor structure provided by the present invention includes the following steps:

[0046] S1, providing such Figure 10 The initial semiconductor structure 10 shown includes a substrate 100, a trench isolation structure 500, an oxide layer 200, and a gate structure 600. The trench isolation structure 500 is disposed within the substrate 100 and extends out of the substrate 100. The oxide layer 200 is formed on the surface of the substrate 100, and the gate structure 600 is formed on the surface of the oxide layer 200.

[0047] S2, such as Figure 12 As shown, a thermally conductive layer 700 is deposited on the surface of the oxide layer 200 and the surface of the trench isolation structure 500;

[0048] S3, such as Figure 13 As shown, a photoresist layer is coated on the surface of the thermally conductive layer 700 and the surface of the gate structure 600. The photoresist layer is patterned to expose the amorphous ion implantation region. Figure 13 (The area not covered by the first photoresist layer 800).

[0049] S4, such as Figure 16 As shown, amorphous ion implantation is performed on the amorphous ion implantation region.

[0050] Please see Figure 10 As shown, in step S1 of the present invention, the initial semiconductor structure 10 can be a purchased semi-finished product or can be prepared by oneself. In one embodiment, the initial semiconductor structure 10 is prepared by oneself.

[0051] Please see Figure 12As shown, in step S2 of the present invention, a thermally conductive layer 700 is deposited on the surface of the oxide layer 200 and the surface of the trench isolation structure 500, exposing the gate structure 600. The thermally conductive layer 700 can be deposited using any one of the following processes: low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or high-density plasma chemical vapor deposition. In this embodiment, the thermally conductive layer 700 is deposited using atmospheric pressure chemical vapor deposition. In one embodiment, the thermally conductive layer 700 is, for example, a silicon nitride (SiN) layer. SiN has excellent thermal conductivity, with a thermal conductivity of up to 140~180 W / (m²). K) can promptly dissipate heat from the first photoresist layer 800 during subsequent amorphous ion implantation, reducing heat accumulation in the first photoresist layer 800 and minimizing spattering or collapse of the first photoresist layer 800. The thickness of the thermally conductive layer 700 is, for example, 200~1000 Å, such as any value in the range of 200 Å, 500 Å, 800 Å, or 1000 Å. In other embodiments, the thermally conductive layer 700 can also be other thermally conductive materials with good thermal conductivity.

[0052] Please see Figure 13 As shown, in step S3 of this invention, after depositing the thermally conductive layer 700, a photoresist layer is coated on the surface of the thermally conductive layer 700 and the surface of the gate structure 600. This photoresist layer is referred to as the first photoresist layer 800. The material type of the first photoresist layer 800 is not limited; it can be a common positive photoresist material or a negative photoresist material. After coating the photoresist, the first photoresist layer 800 is patterned by photolithography processes such as mask exposure and development to expose the amorphous ion implantation region (…). Figure 13 (The area not covered by the first photoresist layer 800).

[0053] Please see Figure 14 As shown, in one embodiment of the present invention, the patterned first photoresist layer 800 undergoes decoupled plasma oxidation (DPO). The decoupled plasma oxidation of the first photoresist layer 800 is performed at room temperature, and the duration of the decoupled plasma oxidation is 100-200 s, for example, any value within the range of 100-200 s, such as 100 s, 150 s, or 200 s. In some embodiments, the formation process of the initial semiconductor structure 10 includes ion implantation on the substrate 100, for example, forming a well region on the substrate 100. Since the decoupled plasma oxidation of the first photoresist layer 800 is performed at room temperature, it does not affect the diffusion of the preceding ion implantation process of the initial semiconductor structure 10. The main components of the material of the first photoresist layer 800 are polymer resin and photosensitive compound, and the structural formula of the polymer resin is shown in Structural Formula 1:

[0054]

[0055] Structural Formula 1

[0056] The structural formula of the photosensitive compound is shown in structural formula 2:

[0057]

[0058] Structural Form 2

[0059] The following reaction occurs during the plasma oxidation of polymer resins:

[0060]

[0061] The photosensitive compound undergoes the following reaction during plasma oxidation:

[0062]

[0063] The polymer resin and photosensitive compound in the first photoresist layer 800 are oxidized by oxygen plasma in the DPO process to form more -COOH polar functional groups, which improves the intermolecular forces (the relative molecular mass increases and hydrogen bonds are formed). At the same time, the functional groups become more complex, which enhances the crosslinking density between molecules and can improve the thermal stability of the first photoresist layer 800.

[0064] Please see Figures 14 to 15 As shown, in one embodiment of the present invention, after decoupling plasma oxidation of the first photoresist layer 800, before performing amorphous ion implantation on the amorphous ion implantation region, the semiconductor structure fabrication method further includes a process of removing the thermally conductive layer 700 of the amorphous ion implantation region. The present invention does not limit the method for removing the thermally conductive layer 700; for example, it can be removed using dry etching, wet etching, or a combination of dry and wet etching. In this embodiment, wet etching is used to remove the thermally conductive layer 700. For example, phosphoric acid is used to remove the thermally conductive layer 700 of the amorphous ion implantation region.

[0065] Please see Figure 16As shown, in one embodiment of the present invention, after removing the thermally conductive layer 700 of the amorphous ion implantation region, amorphous ion implantation is performed on the amorphous ion implantation region to form an amorphous region 900 within the substrate 100. The amorphous ions are ions that can be implanted within the substrate 100 to form the amorphous region 900. The amorphous ions selected are ions with a high atomic mass, which refers to ions relative to conventional implanted ions such as B and P in the prior art. For example, amorphous ions include any one of germanium (Ge) ions, silicon (Si) ions, and xenon (Xe) ions. Those skilled in the art can select appropriate amorphous ions for the amorphous ion implantation process according to the actual process requirements to form the amorphous region 900. The concentration of amorphous ion implantation is 4E15~6E15 ions / cm³. 2 That is, the ion concentration in the amorphous region 900 is 4E15~6E15 ions / cm³. 2 For example, 4E15 ions / cm 2 5E15 ions / cm 2 Or 6E15 ions / cm 2 4E15~6E15 ions / cm 2 Any value in the range. In other embodiments of this application, amorphous ion implantation is performed using a step-by-step implantation method, where amorphous ions are implanted through multiple implantation processes to form the amorphous region 900. The time interval between two adjacent implantations is 2 to 5 seconds, such as any value in the range of 2 seconds, 3 seconds, or 5 seconds. This application does not limit the energy and angle of amorphous ion implantation and can adjust them according to the type of semiconductor structure. Exemplarily, in this embodiment, amorphous ion implantation is performed along a direction perpendicular to the substrate 100.

[0066] Please see Figure 17 As shown, in one embodiment of the present invention, after forming the amorphous region 900, the preparation method further includes the process of removing the first photoresist layer 800 and the thermally conductive layer 700 below the first photoresist layer 800. For example, the first photoresist layer 800 is removed by wet cleaning or ashing treatment, and the thermally conductive layer 700 below the first photoresist layer 800 is removed by wet etching.

[0067] Please see Figures 2 to 10 As shown, the fabrication process of the initial semiconductor structure 10 of the present invention is as follows:

[0068] Please see Figure 2As shown, a substrate 100 is first provided. The substrate 100 can be any material suitable for forming a semiconductor structure, such as undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). This invention does not limit the specific material and thickness of the substrate 100, and the substrate 100 can be a P-doped semiconductor substrate or an N-doped semiconductor substrate. The doping type of the impurities can be flexibly set according to the desired semiconductor structure. In this embodiment, the substrate 100 is, for example, a silicon substrate.

[0069] Please see Figure 2 As shown, in one embodiment of the present invention, an oxide layer 200 is formed on a substrate 100. The oxide layer 200 not only serves as a protective layer for the substrate 100, but also protects the substrate 100 it covers in subsequent processes, preventing unnecessary damage to the substrate 100. Furthermore, since the subsequently formed nitride layer 300 experiences high stress, dislocations are easily generated on the surface of the substrate 100 during its formation. The oxide layer 200 can also provide a buffer during the formation of the nitride layer 300, preventing dislocations from being generated on the substrate 100. The oxide layer 200 can be made of materials such as silicon dioxide, and can be formed by any one of the following methods: dry oxidation, wet oxidation, or in-situ steam generation (ISSG). In this embodiment, for example, the oxide layer 200 is formed by dry oxygen oxidation. Exemplarily, the substrate 100 is placed in a furnace tube, oxygen is introduced, and the surface of the substrate 100 reacts with the oxygen at high temperature to generate a dense oxide layer 200. The fabrication process of the initial semiconductor structure 10 may also include cleaning the substrate 100 before forming the oxide layer 200. Cleaning the substrate 100 removes impurities present on its surface, preventing these impurities from affecting subsequent processes and thus ensuring device performance. Exemplarily, a cleaning solution can be used to clean the substrate 100, or a gas such as nitrogen can be used to purge the substrate 100 to achieve cleaning.

[0070] Please see Figure 3As shown, in one embodiment of the present invention, after forming the oxide layer 200, a nitride layer 300 is formed on the surface of the oxide layer 200. The material of the nitride layer 300 can be silicon nitride or oxynitride; in this embodiment, the material of the nitride layer 300 is, for example, silicon nitride. The nitride layer 300 can be prepared by any one of the following processes: low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or high-density plasma chemical vapor deposition. Exemplarily, when preparing the nitride layer 300 using a low-pressure chemical vapor deposition process, silicon nitride can be generated by reacting ammonia and dichlorosilane. By setting the nitride layer 300, it can not only serve as a mask during the subsequent formation of the trench 420, protecting the substrate 100 from damage during etching, but also protect the substrate 100 from planarization processes such as chemical mechanical polishing (CMP) involved in the fabrication of the trench isolation structure 500.

[0071] Please see Figures 4 to 6 As shown, in one embodiment of the present invention, after forming the nitride layer 300, photoresist is coated on the nitride layer 300 to form a photoresist layer, which is referred to as the second photoresist layer 400. The material type of the second photoresist layer 400 is not limited; it can be a common positive photoresist material or a negative photoresist material. After coating the photoresist, photolithography processes such as mask exposure and development are used to pattern the coated photoresist, exposing the trench region 410. Using the patterned second photoresist layer 400 as a mask layer, the nitride layer 300, the oxide layer 200, and the substrate 100 are etched sequentially to form trenches 420. The number, location, depth, and width of the trenches 420 are set according to actual needs and are not limited here. Exemplarily, in this embodiment, the trenches 420 are shallow trenches. In this embodiment, the trenches 420 extend from the nitride layer 300 into the substrate 100. Exemplarily, the trench 420 has an inverted trapezoidal cross-section that is wider at the top and narrower at the bottom, meaning the width of the top of the trench 420 is greater than the width of the bottom. In some embodiments, the trench 420 may also be rectangular. In this embodiment, the trench 420 is formed by sequentially removing the nitride layer 300, the oxide layer 200, and a portion of the substrate 100 by dry etching. The etching gas includes, for example, one or a mixture of several of chlorine (Cl2), trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), or hydrogen bromide (HBr), or a combination thereof with oxygen (O2). After etching, the second photoresist layer 400 is removed by wet cleaning or ashing.

[0072] Please see Figure 7As shown, in one embodiment of the present invention, after forming the trench 420, an insulating medium is deposited within the trench 420 until the insulating medium covers the surface of the nitride layer 300. Before depositing the insulating medium, the trench 420 can be thermally oxidized to round the corners at the bottom of the trench 420, reducing tip leakage. The present invention does not limit the deposition method of the insulating medium; for example, high-density plasma chemical vapor deposition (HDP-CVD) or high-aspect-ratio process chemical vapor deposition (HARP-CVD) can be used to form a high-quality insulating medium. After depositing the insulating medium, a high-temperature tempering process can be performed to increase the density and stress characteristics of the insulating medium. In this embodiment, the insulating medium is, for example, silicon oxide; in other embodiments, the insulating medium can also be other insulating materials suitable for isolation. After depositing the insulating medium within the trench 420, the insulating medium is planarized. For example, a trench isolation structure 500 is obtained by planarizing the insulating medium using chemical mechanical polishing, with at least a portion of the trench isolation structure 500 exposed above the substrate 100. For example, the trench isolation structure 500 is obtained by polishing away a portion of the insulating medium. This invention does not limit the planarization of the insulating medium to a specific location; it can be placed at any location according to the semiconductor device design requirements. For example, the insulating medium within the trench 420 can be planarized to be flush with the nitride layer 300.

[0073] Please see Figure 8 As shown, in one embodiment of the present invention, after forming the trench isolation structure 500, the nitride layer 300 is removed. The present invention does not limit the method for removing the nitride layer 300; for example, it can be removed using dry etching, wet etching, or a combination of both. In this embodiment, wet etching is used to remove the nitride layer 300, for example, phosphoric acid is used to remove the nitride layer 300.

[0074] Please see Figure 9As shown, in one embodiment of the present invention, after removing the nitride layer 300, the insulating medium can be etched to adjust the height of the trench isolation structure 500. Exemplarily, wet etching or dry etching is used to adjust the height of the trench isolation structure 500, for example, making the trench isolation structure 500 flush with the oxide layer 200. Using the oxide layer 200 as an ion implantation buffer layer, a first ion implantation is performed on the substrate 100 to form a first well region 110 on the substrate 100. Exemplarily, the doped ions in the first well region 110 are, for example, P-type ions, or boron (B) or gallium (Ga). The doped ions in the first well region 110 are, for example, N-type ions, or phosphorus (P) or arsenic (As). Using the oxide layer 200 as an ion implantation buffer layer, a second ion implantation is performed on the substrate 100 to form a second well region 120 on the substrate 100. For example, the dopant ions in the second well region 120 are, for example, p-type ions, or boron (B) or gallium (Ga). The dopant ions in the first well region 110 are, for example, n-type ions, or phosphorus (P) or arsenic (As). The first well region 110 and the second well region 120 are isolated by a trench isolation structure 500, and the types of dopant ions in the first well region 110 and the second well region 120 are opposite. For example, if the type of dopant ions in the first well region 110 is p-type, then the type of dopant ions in the second well region 120 is n-type; or if the type of dopant ions in the first well region 110 is n-type, then the type of dopant ions in the second well region 120 is p-type. In this embodiment, the type of dopant ions in the first well region 110 is p-type, and the type of dopant ions in the second well region 120 is n-type. After the second ion implantation, the first well region 110 and the second well region 120 are subjected to a rapid thermal annealing (RTA) process to allow the ion implantation to diffuse to a suitable depth. The present invention does not limit the ion implantation concentration and depth of the first well region 110 and the second well region 120, and sets the ion implantation concentration and depth according to the specific semiconductor type.

[0075] Please see Figure 10As shown, in one embodiment of the present invention, after forming the first well region 110 and the second well region 120, a gate structure 600 is formed on the surface of the oxide layer 200. Specifically, a gate oxide layer 610 is first formed on the surface of the substrate 100, and then a gate material layer 620 is formed on the surface of the gate oxide layer 610. In this embodiment, the material of the gate oxide layer 610 is, for example, silicon oxide. The gate oxide layer 610 is formed by methods such as thermal oxidation, chemical vapor deposition, or physical vapor deposition. The gate material layer 620 is, for example, a polysilicon layer, and the polysilicon layer can be P-type doped or N-type doped to ensure that the doping type of the polysilicon layer is different from the doping type of the well region, so as to improve the performance of the semiconductor device. For example, if the doping type of the first well region 110 is P-type doped, then the polysilicon layer of the gate structure 600 corresponding to the first well region 110 is N-type doped; if the doping type of the second well region 120 is N-type doped, then the polysilicon layer of the gate structure 600 corresponding to the first well region 110 is P-type doped. In other embodiments, the material and thickness of the gate material layer 620 can be set according to actual needs. The gate material layer 620 and the gate oxide layer 610 are then etched using, for example, a dry etching process, a wet etching process, or a combination of dry and wet etching processes to form the gate structure 600. In other embodiments, the gate material layer 620 may also be, for example, a metal gate layer.

[0076] Please see Figure 11 As shown, in one embodiment of the present invention, after forming the gate structure 600, sidewall structures 630 are formed on both sides of the gate structure 600. Specifically, a dielectric layer (not shown in the figure) is formed on the gate structure 600 and the oxide layer 200, and the dielectric layer includes, for example, a silicon oxide layer. The dielectric layer is formed, for example, by high-temperature thermal oxidation, including, for example, dry thermal oxidation, wet thermal oxidation, or in-situ water vapor oxidation (In... The sidewall structure 630 is formed using methods such as Situ Steam Generation (ISSG). The dielectric layer is then nitrided, for example, by one or a combination of methods such as decoupled plasma nitriding (DPN), rapid thermal nitriding (RTN), or ammonia immersion, to improve the stability of the sidewall structure 630. The dielectric layers on both sides of the gate structure 600 are preserved using wet etching, dry etching, or a combination of wet and dry etching methods, thereby forming single-layer or multi-layer sidewall structures 630 on both sides of the gate, effectively controlling the effects of parasitic capacitance and improving the performance of the semiconductor device.

[0077] The present invention also provides a semiconductor structure, which is fabricated using the above-described semiconductor structure preparation method.

[0078] This invention proposes a method for fabricating a semiconductor structure and the semiconductor structure itself. The initial semiconductor structure includes a trench isolation structure formed in a substrate, and an oxide layer and a gate structure sequentially formed on the substrate surface. After depositing a thermally conductive layer on the surface of the oxide layer and the trench isolation structure, a photoresist layer is coated on the surface of the thermally conductive layer and the surface of the gate structure. The photoresist layer is then patterned to expose an amorphous ion implantation region, which is subsequently subjected to amorphous ion implantation. An unexpected benefit of this invention is that by placing a thermally conductive layer between the photoresist layer and the oxide layer of the initial semiconductor structure, heat from the photoresist layer during amorphous ion implantation can be promptly dissipated, reducing heat accumulation in the photoresist layer and minimizing spattering or collapse of the photoresist layer.

[0079] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: An initial semiconductor structure is provided, the initial semiconductor structure including a substrate, a trench isolation structure, an oxide layer and a gate structure, the trench isolation structure being disposed within the substrate and extending out of the substrate at its upper part, the oxide layer being formed on the surface of the substrate, and the gate structure being formed on the surface of the oxide layer; A thermally conductive layer is deposited on the surface of the oxide layer and the surface of the trench isolation structure, wherein the thermally conductive layer is a silicon nitride layer; A photoresist layer is coated on the surface of the thermally conductive layer and the surface of the gate structure. The photoresist layer is patterned to expose the amorphous ion implantation region. Remove the thermally conductive layer from the amorphous ion implantation region; Amorphous ion implantation is performed on the amorphous ion implantation region; Remove the photoresist layer and the thermally conductive layer beneath the photoresist layer; Prior to performing amorphous ion implantation on the amorphous ion implantation region, the preparation method further includes a process of decoupling plasma oxidation of the photoresist layer, wherein the decoupling plasma oxidation is performed at room temperature.

2. The preparation method according to claim 1, characterized in that, The duration of the decoupled plasma oxidation is 100~200s.

3. The preparation method according to claim 1, characterized in that, The amorphous ion implantation is performed in a stepwise implantation manner, with an implantation time interval of 2 to 5 seconds.

4. The preparation method according to claim 1, characterized in that, The concentration of the amorphous ion implantation is 4E15~6E15 ions / cm³. 2 .

5. The preparation method according to claim 1, characterized in that, The amorphous ions include any one of germanium ions, silicon ions, and xenon ions.

6. A semiconductor structure, characterized in that, It is prepared according to any one of claims 1 to 5.

Images