A semiconductor structure and a method of fabricating the same

Abstract

This invention proposes a semiconductor structure and its fabrication method, belonging to the field of semiconductor technology. The semiconductor structure includes at least: a substrate; a groove recessed from the surface of the substrate into the substrate; a barrier layer disposed on the surface of the substrate and within the groove; a first doped layer disposed on the barrier layer; a second doped layer disposed on the first doped layer; and a conductive layer disposed on the second doped layer. The semiconductor structure and its fabrication method proposed in this invention can effectively reduce void defects in copper interconnect structures while effectively preventing electromigration, thereby improving the reliability and yield of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor structure and its fabrication method. Background Technology

[0002] Copper interconnect metalworking is widely used in mature chip manufacturing processes to reduce the resistance-capacitance delay of interconnects and improve device performance. However, as integrated circuit process nodes advance to more advanced processes, the aspect ratio of interconnect structures continues to increase. During copper filling, the grooves cannot be completely filled, leading to void defects. Furthermore, due to the inherent susceptibility of copper to migration, copper interconnect structures are prone to failure due to electromigration, severely impacting device reliability. Therefore, how to improve the electromigration reliability of copper interconnect processes while simultaneously addressing void defects has become a pressing technical challenge. Summary of the Invention

[0003] This invention proposes a semiconductor structure and its fabrication method. The semiconductor structure and its fabrication method provided by this invention can effectively reduce the void defects in the copper interconnect structure, while effectively avoiding electromigration, thereby improving the reliability and yield of the semiconductor structure.

[0004] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising at least:

[0005] Base;

[0006] A groove, which is recessed from the surface of the substrate into the substrate;

[0007] A barrier layer is disposed on the surface of the substrate and within the groove;

[0008] A first doped layer is disposed on the barrier layer;

[0009] A second doped layer is disposed on the first doped layer; and

[0010] A conductive layer is disposed on the second doped layer.

[0011] In one embodiment of the present invention, the material of the first doped layer includes a transition metal, nitrogen, and boron.

[0012] In one embodiment of the present invention, the material of the second doped layer includes a transition metal, nitrogen, boron, and silicon.

[0013] In one embodiment of the present invention, the thickness of the first doped layer is 5 Å-20 Å, and the thickness of the second doped layer is 5 Å-20 Å.

[0014] In one embodiment of the present invention, the semiconductor structure further includes an auxiliary layer disposed between the second doped layer and the conductive layer.

[0015] In one embodiment of the present invention, the material of the auxiliary layer includes tantalum.

[0016] This invention also proposes a method for fabricating a semiconductor structure, comprising at least the following steps:

[0017] Provide a base;

[0018] A groove is formed within the substrate, the groove being recessed from the surface of the substrate into the substrate;

[0019] A barrier layer is formed on the surface of the substrate and within the groove;

[0020] A first doped layer is formed on the barrier layer;

[0021] A second doped layer is formed on the first doped layer; and

[0022] A conductive layer is formed on the second doped layer.

[0023] In one embodiment of the present invention, forming the barrier layer includes at least the following steps:

[0024] A barrier material layer is deposited on the surface of the substrate and within the groove;

[0025] Boronize a portion of the barrier material layer on the side facing away from the substrate into a first doped material layer; and

[0026] The unbored barrier material layer is defined as the barrier layer.

[0027] In one embodiment of the present invention, forming the first doped layer and the second doped layer includes at least the following steps:

[0028] The portion of the first doped material layer facing away from the barrier layer is siliconized into a second doped layer; and

[0029] The first doped material layer that is not siliconized is defined as the first doped layer.

[0030] In one embodiment of the present invention, the first doped material layer is silanized by a plasma processing process.

[0031] In summary, this invention proposes a semiconductor structure and its fabrication method. Through improvements to the semiconductor structure and its fabrication method, the unexpected technical effect of this application is the enhanced barrier capability against materials in the conductive layer, preventing the diffusion of materials from the conductive layer into the substrate, ensuring the electrical properties of the semiconductor structure, and improving the yield and reliability of the semiconductor structure. Furthermore, the semiconductor structure and its fabrication method proposed in this invention can further enhance the barrier capability against materials in the conductive layer and avoid the generation of void defects during copper deposition, thereby improving the quality of the semiconductor structure. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of the formation of the groove.

[0034] Figure 2 A schematic diagram of the formation of the barrier material layer.

[0035] Figure 3 This is a schematic diagram of the formation of the first doped material layer.

[0036] Figure 4 This is a schematic diagram of the formation of the second doped layer.

[0037] Figure 5 This is a schematic diagram of the formation of the auxiliary layer.

[0038] Figure 6 This is a schematic diagram of the formation of a conductive layer.

[0039] Figure 7 To observe using a transmission electron microscope Figure 3 A representation diagram of the structure.

[0040] Figure 8 To observe using a transmission electron microscope Figure 4 A representation diagram of the structure.

[0041] Label Explanation:

[0042] 10. Dielectric layer; 101. First surface; 102. Second surface; 11. Groove; 12. Barrier layer; 121. Barrier material layer; 13. First doped layer; 131. First doped material layer; 14. Second doped layer; 15. Auxiliary layer; 16. Conductive layer. Detailed Implementation

[0043] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0044] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0045] The technical solution of the present invention will be further described in detail below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0046] Please see Figure 6 As shown, the present invention provides a semiconductor structure, which includes a substrate, a groove 11, a barrier layer 12, a first doped layer 13, a second doped layer 14, an auxiliary layer 15, and a conductive layer 16. The groove 11 is recessed from the surface of the substrate into the substrate. The barrier layer 12 is disposed on the surface of the substrate and in the groove 11. The first doped layer 13 is disposed on the barrier layer 12 and extends from the barrier layer 12 in the groove 11 to the barrier layer 12 on the substrate surface. The second doped layer 14 is disposed on the first doped layer 13 and extends from the first doped layer 13 in the groove 11 to the first doped layer 13 on the substrate surface. The auxiliary layer 15 is disposed on the second doped layer 14 and extends from the second doped layer 14 in the groove 11 to the second doped layer 14 on the substrate surface. The conductive layer 16 is disposed on the auxiliary layer 15 and fills the groove 11 to the auxiliary layer 15 on the substrate surface. The barrier layer 12 is made of materials such as transition metal nitrides, the first doped layer 13 is made of materials such as transition metals, nitrogen, and boron, the second doped layer 14 is made of materials such as transition metals, nitrogen, boron, and silicon, and the conductive layer 16 is made of a conductive metal layer. In the semiconductor structure provided by this invention, by providing the first doped layer 13, the barrier capability against the material in the conductive layer 16 can be enhanced, preventing the material in the conductive layer 16 from diffusing into the substrate, ensuring the electrical properties of the semiconductor structure, and improving the yield and reliability of the semiconductor structure. Moreover, by providing the second doped layer 14, the barrier capability against the material in the conductive layer 16 can be further enhanced, and by utilizing the adhesion of the second doped layer 14, it is easy for the subsequent conductive layer 16 to be uniformly formed on the second doped layer 14, avoiding void defects.

[0047] Please see Figure 1 As shown, the present invention also provides a method for fabricating a semiconductor structure, used to fabricate the aforementioned semiconductor structure. First, a substrate is provided. The substrate structure includes, for example, a substrate (not shown) and a dielectric layer 10. The substrate can be any material suitable for forming a semiconductor device, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, silicon wafers, or other semiconductor materials formed from III / V compounds. The dielectric layer 10 is formed on the substrate, for example, by a method such as chemical vapor deposition. The material of the dielectric layer 10 includes at least one of silicon oxide or silicon nitride. Further, the dielectric layer 10 includes a first surface 101 and a second surface 102 disposed opposite to each other. The first surface 101 is disposed away from the substrate, and the second surface 102 is disposed in contact with the substrate.

[0048] Please see Figure 1 As shown, in one embodiment of the present invention, a photoresist layer (not shown in the figure) is formed on the first surface 101 by, for example, spin coating or spray coating. After exposure and development processes, the photoresist layer is patterned to form a photoresist layer (not shown in the figure). The photoresist layer exposes part of the first surface 101. Then, using the photoresist layer as a mask, the exposed dielectric layer 10 is etched to form a groove 11. After that, the photoresist layer is removed. The groove 11 is recessed from the first surface 101 into the dielectric layer 10. The present invention does not limit the depth of the groove 11, that is, the distance between the bottom of the groove 11 and the first surface 101, and can be selected according to actual needs.

[0049] Please see Figures 1 to 2As shown, in one embodiment of the present invention, after the groove 11 is formed, a barrier material layer 121 is formed on the first surface 101 and within the groove 11. The material of the barrier material layer 121 includes, for example, transition metal nitrides, specifically tantalum nitride. The thickness of the barrier material layer 121 is, for example, less than the depth of the groove 11. The method for forming the barrier material layer 121 is, for example, physical vapor deposition or chemical vapor deposition. In this embodiment, the barrier material layer 121 is formed, for example, by physical vapor deposition. Specifically, tantalum metal is used as the target material, nitrogen is used as the reactant gas, and argon is used as the sputtering gas. A DC electric field and an AC electric field are applied between the target material and the first surface 101. Argon in the argon gas ionizes to generate argon ions. The argon ions bombard the target material, sputtering tantalum in the target material, which reacts with nitrogen ions generated by the decomposition of nitrogen, forming the barrier material layer 121 on the first surface 101 and within the groove 11. The power of the DC electric field is, for example, 1000W-8000W, and the power of the AC electric field is, for example, 0-800W. By setting the barrier material layer 121, the conductive metal in the subsequently formed conductive layer 16 can be prevented from diffusing into the dielectric layer 10, effectively avoiding electromigration and leakage problems, and improving the reliability and yield of the semiconductor structure.

[0050] Please see Figures 2 to 3 As shown, in one embodiment of the present invention, after forming the barrier material layer 121, the dielectric layer 10 with the barrier material layer 121 is placed in the reaction chamber, and a boron-containing gas is introduced. The mixture is maintained at a preset temperature and pressure for a preset time. A portion of the barrier material layer 121 on the side opposite to the first surface 101 is boronized to become a first doped material layer 131. The unboronized barrier material layer 121 is defined as the barrier layer 12, and the thickness of the barrier layer 12 is, for example, 20 Å-50 Å. The material of the first doped material layer 131 includes, for example, transition metals, nitrogen, and boron, specifically, TaNB. x x is, for example, 0.1-0.5, the thickness of the first doped material layer 131 is, for example, less than the thickness of the barrier material layer 121 before boration, the boron-containing gas includes, for example, diborane (B2H6), and the reaction formula of the boration process is, for example, TaN + B2H6 → TaNB. x +H2, the flow rate of boron-containing gas is, for example, 100 sccm-1000 sccm, the preset temperature is, for example, 300℃-400℃, the preset pressure is, for example, 5 torr-20 torr, and the preset time is, for example, 5s-60s. By setting the first doped material layer 131, the barrier capability against the material in the conductive layer 16 can be enhanced, preventing the material in the conductive layer 16 from diffusing into the dielectric layer 10, effectively avoiding electromigration, ensuring the electrical characteristics of the semiconductor structure, and improving the reliability and yield of the semiconductor structure. However, please refer to... Figure 7As shown, although boronizing can improve the blocking ability, it has little effect on improving the overhang phenomenon of the opening of the groove 11. Specifically, the opening width of the groove 11 is small. In this embodiment, the opening width is, for example, 8.19 nm.

[0051] Please see Figures 3 to 4 As shown, in one embodiment of the present invention, after forming the first doped material layer 131, a portion of the first doped material layer 131 facing away from the barrier layer 12 is silicided to form a second doped layer 14. The thickness of the second doped layer 14 is, for example, 5 Å-20 Å. The unsilicided first doped material layer 131 is defined as the first doped layer 13, and the thickness of the first doped layer 13 is, for example, 5 Å-20 Å. The material of the second doped layer 14 includes, for example, transition metals, nitrogen, boron, and silicon, specifically, TaNB. x Si y The value of y is, for example, 0.1-0.5. The thickness of the second doped layer 14 is, for example, less than the thickness of the first doped material layer 131 before borosilicated treatment. The first doped material layer 131 is silanized, for example, by plasma treatment. Specifically, the dielectric layer 10 with the first doped material layer 131 is placed in the reaction chamber, and a silicon source gas is introduced. The high-frequency power supply and the low-frequency power supply are started to ionize the silicon source gas to form plasma, and then the surface of the first doped material layer 131 is silanized. The silicon source gas includes, for example, at least one of tetramethylsilane, silane, and trimethylsilane. The flow rate of the silicon source gas is, for example, 100 sccm-1000 sccm. The power of the high-frequency power supply is, for example, 400W-1000W. The power of the low-frequency power supply is, for example, 100W-300W. The temperature of the silanization treatment is, for example, 300℃-350℃. The time of the silanization treatment is, for example, 10s-100s. In this embodiment, the silicon source gas is, for example, tetramethylsilane, and the silanization reaction formula is, for example, TaNB. x +Si(CH3)4→TaNB x Si y +CH4. By setting a second doped layer 14, the barrier effect on the material in the conductive layer 16 can be further enhanced, thereby improving the reliability and yield of the semiconductor structure. Furthermore, the adhesion of the second doped layer 14 is superior to that of the barrier layer 12. Utilizing the adhesion of the second doped layer 14, it is easier for the subsequent auxiliary layer 15 to be uniformly deposited on the second doped layer 14, which in turn facilitates the uniform deposition of the subsequent conductive layer 16 on the auxiliary layer 15, avoiding void defects and improving the quality of the semiconductor structure. Moreover, compared to... Figure 7 and Figure 8It can be seen that the siliconization process can increase the opening width of the groove 11 to 15.39 nm. Compared with the original siliconization process, the opening depth of the groove 11 is increased by 87.9%. This shows that the siliconization process can etch the opening overhang of the groove 11, which is more conducive to the uniform and sufficient deposition of the subsequent auxiliary layer 15 and conductive layer 16, and reduces the number of hole defects in the conductive layer 16. Specifically, the improvement of hole defects can reach more than 80%, thereby improving the quality of the semiconductor structure.

[0052] Please see Figures 4 to 5 As shown, in one embodiment of the present invention, after forming the second doped layer 14, an auxiliary layer 15 is formed on the second doped layer 14. The material of the auxiliary layer 15 includes, for example, tantalum, and the thickness of the auxiliary layer 15 is, for example, 50 Å-150 Å. The auxiliary layer 15 is formed, for example, by physical vapor deposition. Specifically, using tantalum metal as the target, a DC electric field and an AC electric field are applied between the target and the second doped layer 14, and the tantalum in the target is sputtered and deposited on the second doped layer 14. The power of the DC electric field is, for example, 4000W-12000W, and the power of the AC electric field is, for example, 0-1200W. By setting the auxiliary layer 15, the adhesion of the conductive metal of the subsequent conductive layer 16 to the auxiliary layer 15 can be significantly improved, preventing the conductive layer 16 from detaching and improving the quality of the semiconductor structure.

[0053] Please see Figures 5 to 6 As shown, in one embodiment of the present invention, after forming the auxiliary layer 15, conductive metal is deposited on the auxiliary layer 15 and in the groove 11 until the conductive metal in the groove 11 protrudes from the auxiliary layer 15. Then, the conductive metal is planarized, for example, by chemical mechanical polishing, thereby forming a conductive layer 16 on the auxiliary layer 15. The material of the conductive layer 16 includes, for example, copper. The thickness of the conductive layer 16 on the first surface 101 is, for example, 200 Å-500 Å. The conductive layer 16 is formed, for example, by physical vapor deposition. Specifically, using metallic copper as the target, a DC electric field and an AC electric field are applied between the target and the auxiliary layer 15, and copper in the target is sputtered and deposited on the auxiliary layer 15. The power of the DC electric field is, for example, 20000W-50000W, and the power of the AC electric field is, for example, 0-1200W.

[0054] In summary, this invention proposes a semiconductor structure and its fabrication method. By setting a first doped layer between the barrier layer and the conductive layer, the unexpected technical effect of this application is that it enhances the barrier capability against materials in the conductive layer, prevents the diffusion of materials in the conductive layer into the substrate, avoids electromigration, ensures the electrical properties of the semiconductor structure, and improves the yield and reliability of the semiconductor structure. Moreover, in the semiconductor structure proposed in this invention, by setting a second doped layer between the first doped layer and the conductive layer, the barrier capability against materials in the conductive layer can be further enhanced. Furthermore, the adhesion of the second doped layer facilitates the uniform deposition of the subsequent conductive layer, avoids void defects, and improves the quality of the semiconductor structure.

[0055] The above description is merely a preferred embodiment of this application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to the technical solutions formed by a specific combination of the above-mentioned technical features, but should also cover other technical solutions formed by any combination of the above-mentioned technical features or their equivalent features without departing from the inventive concept. For example, technical solutions formed by replacing the above-mentioned features with technical features with similar functions disclosed in this application (but not limited to) each other.

[0056] Apart from the technical features described in the specification, the other technical features are known to those skilled in the art. To highlight the innovative features of this invention, the other technical features will not be described in detail here.

Claims

1. A semiconductor structure, characterized in that, At least including: Base; A groove, which is recessed from the surface of the substrate into the substrate; A barrier layer is disposed on the surface of the substrate and within the groove; A first doped layer is disposed on the barrier layer, and the material of the first doped layer is ZNB. x ; A second doped layer is disposed on the first doped layer, and the material of the second doped layer is ZNB. x Si y Where x ranges from 0.1 to 0.5, y ranges from 0.1 to 0.5, and Z represents a transition metal; and A conductive layer is disposed on the second doped layer.

2. The semiconductor structure according to claim 1, characterized in that, The thickness of the first doped layer is 5 Å-20 Å, and the thickness of the second doped layer is 5 Å-20 Å.

3. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes an auxiliary layer disposed between the second doped layer and the conductive layer, the auxiliary layer being made of tantalum.

4. A method for fabricating a semiconductor structure, characterized in that, At least the following steps are included: Provide a base; A groove is formed within the substrate, the groove being recessed from the surface of the substrate into the substrate; A barrier layer is formed on the surface of the substrate and within the groove. Forming the barrier layer includes at least the following steps: forming a barrier material layer on the surface of the substrate and within the groove; boronizing a portion of the barrier material layer on the side facing away from the substrate as a first doped material layer; defining the unboronized barrier material layer as the barrier layer; and silicideizing a portion of the first doped material layer on the side facing away from the barrier layer as a second doped layer, wherein the material of the second doped layer is ZNB. x Si y Where x ranges from 0.1 to 0.5, y ranges from 0.1 to 0.5, and Z represents a transition metal; The first doped material layer that is not siliconized is defined as the first doped layer, and the material of the first doped layer is ZNB. x ;as well as A conductive layer is formed on the second doped layer.

5. The preparation method according to claim 4, characterized in that, Forming the barrier layer includes at least the following steps: The barrier material layer is deposited on the surface of the substrate and within the groove.

6. The preparation method according to claim 4, characterized in that, The first doped material layer is siliconized using a plasma processing technique.

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