Nitrogen plasma treatment to improve the interface between an etch stop layer and a copper interconnect

Abstract

Interconnect structure of a multilayer interconnect feature of an integrated circuit device, wherein the interconnect structure comprises the following: a first interlayer dielectric layer, ILD layer (210); a second ILD layer (270) arranged above the first ILD layer (210); a first copper interconnect (230) located in the first ILD layer (210); a second copper interconnect (290) arranged in the second ILD layer (270); and an aluminum nitride contact etch stop layer, aluminum nitride-CESL (250), arranged between a section of the first copper interconnect (230) and the second ILD layer (270) and between the first ILD layer (210) and the second ILD layer (270), wherein the second copper interconnect (290) extends through the aluminum nitride-CESL (250) to physically contact the first copper interconnect (230), and wherein a surface nitrogen concentration at an interface between the aluminum nitride-CESL (250) and the first copper interconnect (230) is approximately 20 at% or higher, which further exhibits the following: an oxygen-doped silicon carbide CESL (260) arranged above the aluminum nitride CESL (250); and an aluminum oxide CESL (262) arranged above the oxygen-doped silicon carbide CESL (260), wherein the second copper interconnect (290) extends through the oxygen-doped silicon carbide CESL (260) and the aluminum oxide CESL (262).

Description

GENERAL STATE OF THE ART

[0001] The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuitry than the previous one. Throughout IC development, functional density (i.e., the number of interconnected IC devices per chip area) has generally increased, while geometric size (i.e., the dimensions and / or sizes of IC features and / or the spacing between these features) has decreased. Typically, downward scaling has been limited only by the ability to define IC features at steadily decreasing geometric sizes.However, resistance-capacitance delay (RC delay) has emerged as a significant challenge in implementing reduced geometric sizes to achieve faster operating speeds in ICs (e.g., by reducing the distances traveled by electrical signals), thus negating some of the benefits gained by downscaling and limiting further downscaling of ICs. RC delay generally indicates a delay in the speed of an electrical signal through an IC, resulting from the product of resistance (R) (i.e., the resistance of a material to the flow of an electric current) and capacitance (C) (i.e., the ability of a material to store an electric charge).Reducing both resistance and capacitance is therefore desirable to decrease RC delay and optimize the performance of downscaled ICs. Interconnects between ICs, which physically and / or electrically connect IC components and / or features, are particularly problematic with regard to their contribution to RC delay. Solutions for interconnects that have been observed to reduce the contribution of interconnects to RC delay have introduced new challenges. For example, improved interconnect structures sometimes fail to adequately prevent metal diffusion from interconnects into surrounding dielectric materials, leading to undesirable gaps in the interconnects that degrade IC performance.Therefore, there is a need for improvements regarding IC interconnects and / or methods for manufacturing the interconnects. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The present disclosure is best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale and are used for illustrative purposes only. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 is a flowchart of a process for manufacturing a section of a multilayer interconnect feature according to various aspects of the present disclosure. Fig. Figures 2A-2I are fragmentary diagrammatic views of a section of a multilayer interconnect feature at different stages of manufacturing, such as those produced using the process of Fig. 1 are linked, according to various aspects of the present revelation. Fig. Figure 3 is a fragmentary diagrammatic view of a section of a multi-layer interconnect feature according to various aspects of the present disclosure. Fig. Figure 4 is a flowchart of a deposition process for forming an etch stop layer of a multilayer interconnect structure according to various aspects of the present disclosure. Fig. Figure 5 is a flowchart of a nitrogen plasma treatment process for an interface region between an etch stop layer and an interconnect of a multilayer interconnect structure according to various aspects of the present disclosure. Fig. 6 is a Fourier transform infrared spectrum (FTIR spectrum) obtained by performing FTIR spectroscopy on an AlN bulk film before and after nitrogen plasma treatment, according to various aspects of the present disclosure. Fig. 7A and Fig. 7B are fragmentary, diagrammatic top views of the sections of the multilayer interconnect features of Fig. 2I and Fig. 3 in part or wholly according to various aspects of the present revelation. Fig. Figure 8 is a fragmentary diagrammatic view of an integrated circuit device in part or all according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0003] The invention is defined by the subject matter of the independent claims. Specific embodiments are given by the additional features of the dependent claims. The present disclosure relates generally to integrated circuit devices (IC devices) and more specifically to interconnect structures for IC devices.

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, forming a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also embodiments in which additional features may be formed between the first and second features, so that the first and second features may not be in direct contact.In addition, spatially related terms, for example, "lower," "upper," "horizontal," "vertical," "above," "over," "below," "underneath," "top," "bottom," "top," "bottom," etc., and derivatives thereof (e.g., "horizontal," "downward," "upward," etc.), are used herein for a more convenient description of the relationship of one feature to another in the present disclosure. The spatially related terms are intended to cover various orientations of the device, including the features. Furthermore, when a number or range of numbers is described by "approximately," "about," and the like, the term is intended to include numbers that lie within a reasonable range that takes into account variations that generally occur during manufacturing, as a person skilled in the art would understand.For example, the number or range of numbers encompasses a reasonable range that exhibits the described number, such as within ±10% of the described number, based on known manufacturing tolerances associated with the production of a feature that has a property linked to the number. For example, a material layer having a thickness of "approximately 5 nm" may encompass a dimensional range of 4.5 nm to 5.5 nm, where a person skilled in the art knows that manufacturing tolerances associated with the deposition of the material layer are ±10%. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the sake of simplicity and clarity and does not in itself imply any relationship between the various embodiments and / or configurations described.

[0005] Typically, downscaling has been limited only by the ability to lithographically define IC features at steadily decreasing geometric sizes. However, a resistance-capacitance delay (RC delay) has emerged as a significant challenge in implementing reduced geometric sizes to achieve faster operating speeds in ICs (e.g., by reducing distances traveled by electrical signals), thereby negating some of the benefits gained from downscaling and limiting further scaling. For example, as IC technology nodes have been extended to 20 nm and below, decreasing critical dimensions (CDs) at IC device layers (e.g., gate lengths, gate spacing, fin spacing, etc.) have become a significant challenge.This has led to a corresponding reduction in the interconnect dimensions (e.g., device-level contact dimensions, via dimensions, metal conductor dimensions, device-level contact spacing, via spacing, metal conductor spacing, etc.) of multi-layer interconnect features (MLI features) of ICs. Smaller interconnects become increasingly problematic when their contribution to RC delay is considered. Solutions to reduce both the resistance and capacitance associated with interconnects are therefore desirable to decrease RC delay and optimize the performance of scaled-down ICs.

[0006] RC delay generally indicates a delay in the speed of an electrical signal through an integrated circuit (IC), resulting from the product of resistance (R), the resistance of a material to the flow of an electric current, and capacitance (C), the ability of a material to store an electric charge. For any two adjacent interconnects, capacitance is a function of the dielectric constant of the dielectric material surrounding the two interconnects and the distance between them. Since reduced distances (spacing) between interconnects result from downscaling ICs (and thus lead to increased capacitance), capacitance reduction techniques have focused on decreasing the dielectric constant of the insulating material of the interconnects.For example, low-k dielectric materials, such as dielectric materials with dielectric constants lower than those of silicon dioxide (e.g., SiO2), have been developed to reduce parasitic capacitance and / or capacitive coupling between interconnects and adjacent conductive features, such as neighboring interconnects or adjacent device features (e.g., gates). Reducing resistance associated with interconnects has been achieved by implementing interconnect materials and / or interconnect configurations that exhibit a desired resistance and allow for increased current flow.For example, since copper interconnects have lower electrical resistance, higher conductivity, and greater resistance to electromigration than aluminum interconnects, aluminum interconnects are often replaced by copper interconnects to reduce RC delay and increase IC speed. However, because copper ions / atoms from copper interconnects readily diffuse into low-k dielectric material (which is implemented to reduce capacitance), diffusion / barrier layers are often incorporated into copper interconnects to separate the copper layers from the surrounding low-k dielectric material and reduce (or prevent) the diffusion of copper atoms / ions from the copper layers into the surrounding low-k dielectric material.

[0007] Undesired copper diffusion has also been observed at interfaces between copper interconnects and overlying layers during processing, such as contact etch stop layers (CESLs). CESLs are often implemented in copper interconnect fabrication to prevent unintended etching and / or over-etching of an underlying interconnect.Consequently, interconnect fabrication can involve a two-step etching process to form an interconnect opening, such as a first etching process that etches a dielectric layer until a CESL is reached, formed between the dielectric layer and the underlying interconnect (in other words, the CESL acts as a stop feature for the first etching process), and a second etching process that etches the CESL until the underlying interconnect is reached (exposed), with parameters of the first etching process being tuned to selectively etch the dielectric layer (for example, with respect to the CESL), and parameters of the second etching process being tuned to selectively remove the CESL (for example, with respect to the dielectric layer and the underlying interconnect).The interconnect opening is then filled with one or more conductive materials, such as a copper bulk layer placed over a diffusion barrier layer (including, for example, tantalum and nitrogen), to form a copper interconnect with the underlying interconnect.

[0008] Stress-induced voiding (also known as stress migration) at the interface between the CESL and the copper interconnect (hereafter referred to as a CESL / copper interface) has become a major factor in IC device reliability. For example, mechanical stress in an MLI feature can cause copper ions / atoms and copper vacancies to migrate along grain boundaries in the copper interconnect to the CESL / copper interface. As the copper atoms / ions diffuse into the MLI feature (for example, into the CESL and / or the surrounding dielectric layers) and the copper vacancies accumulate at the CESL / copper interface, voids form at the CESL / copper interface, increasing the resistance of the copper interconnect and degrading IC performance.These gaps can cause an open circuit to be location- and / or size-dependent, and in some cases lead to interconnect failure and / or IC device failure. These mechanical stresses often arise during MLI feature manufacturing (referred to as back-end-of-line (BEOL) processing) due to differing coefficients of thermal expansion between the copper interconnect and its surrounding dielectric materials. For example, because the copper interconnect and surrounding dielectric materials have different coefficients of thermal expansion, the copper interconnect and surrounding dielectric materials will expand and contract at different rates during various BEOL thermal cycles, creating stress differentials in the MLI feature that cause copper ions / atoms and / or copper vacancies to migrate to the CESL / copper interface.The prior art relevant to the present invention is given by DE 10 2015 107 271 A1 and US 2019 / 0 043 804 A1. Furthermore, the following review article by Gaskins et al. also forms part of the prior art: “Review - Investigation and Review of the Thermal, Mechanical, Electrical, Optical, and Structural Properties of Atomic Layer Deposited High-k Dielectrics: Beryllium Oxide, Aluminum Oxide, Hafnium Oxide, and Aluminum Nitride”, published in: ECS Journal of Solid State Science and Technology, Vol. 6, 2017, pp. N189-N208.

[0009] To address these challenges, the present disclosure proposes interconnect fabrication methods for suppressing copper diffusion at the CESL / copper interface, thereby preventing the accumulation of copper vacancies at the CESL / copper interface and reducing (and even eliminating) gap formation in the copper interconnect at the CESL / copper interface. For example, the present disclosure proposes performing a nitrogen plasma treatment on the CESL prior to forming an overlying ILD layer, wherein the nitrogen plasma treatment is configured to increase the nitrogen concentration and / or enhance nitrogen binding at the CESL / copper interface.Increasing the nitrogen concentration and / or nitrogen binding at the CESL / copper interface prevents (or limits) the diffusion of copper ions / atoms and reduces copper vacancies along the CESL / copper interface, thereby preventing the accumulation of copper vacancies at the CESL / copper interface and limiting stress-induced voiding in copper interconnects. It has been observed that the proposed nitrogen plasma treatment not only increases the nitrogen concentration of the CESL but also, in some embodiments, increases the dielectric constant, refractive index, and / or density of the CESL. Methods for fabricating interconnect structures incorporating the proposed nitrogen plasma treatment process, along with the resulting interconnect structures, are described in detail below.Different embodiments may have different advantages, and no specific advantage is required of any particular embodiment.

[0010] With reference to Fig. 1 is Fig. Figure 1 shows a flowchart of a method 100 for producing a section of an MLI feature according to various aspects of the present disclosure. In blocks 110 and 120, the method 100 comprises forming a first dielectric layer over a device substrate and forming a first interconnect opening in the first dielectric layer to expose an underlying conductive feature, such as an interconnect of the MLI feature, or a conductive feature of the device substrate (for example, a gate or a source / drain feature). In some embodiments, the dielectric layer includes an intermediate dielectric layer arranged over an etch stop layer. In block 130, a first interconnect is formed in the first interconnect opening.For example, in block 132, a diffusion barrier layer is formed over sidewall surfaces (defined, for example, by the dielectric layer) and a bottom surface (defined, for example, by the underlying conductive feature) that define the interconnect opening. In block 134, a bulk layer is formed over the diffusion barrier layer, so that the diffusion barrier layer and the bulk layer fill the interconnect opening. In block 136, a cover layer is formed over the bulk layer and, in some embodiments, over the diffusion barrier layer. In some embodiments, the bulk layer contains copper, the cover layer contains metal, such as cobalt, and nitrogen, and the first interconnect is a copper interconnect. In block 140, an etch stop layer is deposited over the first interconnect. The etch stop layer contains metal, such as aluminum, and nitrogen.A region near an interface between the etch stop layer and the first interconnect is referred to as an interface region, which has an interface between the etch stop layer and the cover layer and an interface between the cover layer and the bulk layer. In some embodiments, the cover layer of the first interconnect is omitted, and the interface region has an interface between the etch stop layer and the bulk layer. In Block 150, a nitrogen plasma treatment is performed on the etch stop layer to increase the nitrogen concentration and / or nitrogen binding at the interface region, as described herein.Increasing the nitrogen concentration and / or nitrogen binding at the interface region improves the metal diffusion barrier capacity of the interface region, thus preventing metal ions / atoms and / or metal vacancies from diffusing from the bulk layer of the first interconnect to surrounding layers via the interface region during subsequent processing of the MLI feature, such as that associated with blocks 160-180. It has been observed that improving the diffusion barrier capacity of the interface region minimizes (and even eliminates) gap formation at the interface region.Method 100 then proceeds with forming a second dielectric layer over the etch stop layer at block 160, forming a second interconnect opening in the second dielectric layer to expose the first interconnect at block 170, and forming a second interconnect (which may be similar to the first interconnect) in the second interconnect opening at block 180. Additional steps may be provided before, during, and after Method 100, and some of the described steps may be deferred, replaced, or omitted by additional embodiments of Method 100.

[0011] Fig. 2A-2I are fragmentary diagrammatic views of section 200 of a multilayer interconnect feature (MLI feature), such as an MLI feature 400, as shown in Fig. 4 is shown, in various manufacturing phases (such as those using process 100 of Fig. 1 linked) according to various aspects of the present disclosure. MLI feature 400 electrically couples different devices (for example, transistors, resistors, capacitors, and / or inductors) and / or components (for example, gates and / or source / drain features) of an IC device so that the different devices and / or components can function as specified by design requirements. MLI feature 400 has a combination of dielectric layers and metal layers configured to form various interconnects. The metal layers are configured to form vertical interconnects, such as device-layer contacts and / or vias, and horizontal interconnects, such as conductive traces. Vertical interconnects typically connect horizontal interconnects in different layers (or different levels) of MLI feature 400.During operation of the IC device, the interconnects conduct signals between the devices and / or components of the IC device and / or distribute signals (for example, clock signals, voltage signals, and / or ground signals) to the devices and / or components, along with conducting and distributing signals between the devices and / or components of the IC device and devices and / or components that are external to the IC device. It is understood that, although MLI feature 400 will be represented with a given number of dielectric and metal layers, the present disclosure provides that MLI feature 400 may have more or fewer dielectric and / or metal layers. Fig. Sections 2A-2I have been simplified for clarity to better understand the inventive concepts of the present disclosure. Additional features may be added to section 200 of the MLI feature and / or MLI feature 400, and some of the features described below may be replaced, modified, or removed in other embodiments of section 200 of the MLI feature and / or MLI feature 400.

[0012] With reference to Fig. 2A A dielectric layer 202 is formed over a device substrate 206. In the illustrated embodiment, the dielectric layer 202 has an interlayer dielectric layer (ILD layer, interlayer dielectric layer) 210 arranged over a contact etch stop layer (CESL) 212. In some embodiments, the thickness of the ILD layer 210 is approximately 20 nm to approximately 30 nm, and the thickness of the CESL 212 is approximately 1 nm to approximately 3 nm.The ILD layer 210 and / or the CESL 212 are formed over the device substrate 206 by a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), metal-organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma-enhanced CVD (PECVD), low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), plasma-enhanced ALD (PEALD), other suitable deposition methods or combinations thereof.In some embodiments, the ILD layer 210 is formed by a high aspect ratio process (HARP), such as HDPCVD, which generally refers to a deposition process having parameters configured to achieve adequate filling in high aspect ratio structures. In some embodiments, the ILD layer 210 is formed by a flowable CVD process (FCVD process), which, for example, includes depositing a flowable material (such as a liquid compound) over the device substrate 206 and converting the flowable material into a solid material by a suitable technique, such as thermal annealing and / or treatment of the flowable material with ultraviolet radiation.Following the deposition of the ILD layer 210 and / or the CESL 212, a CMP process and / or another planarization process can be carried out, so that the ILD layer 210 and / or the CESL 212 have essentially planar surfaces.

[0013] The ILD layer 210 features a dielectric material that includes, for example, silicon dioxide, carbon-doped silicon dioxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), Black Diamond® (Applied Materials, Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene-based (BCB-based) dielectric material, SiLK (Dow Chemical, Midland, Michigan), polyimide, any other suitable dielectric material, or combinations thereof. In some embodiments, the ILD layer 210 incorporates a dielectric low-k material, which generally refers to a dielectric material having a low dielectric constant relative to the dielectric constant of silicon dioxide (k ≈ 3.9).For example, the dielectric low-k material has a dielectric constant less than approximately 3.9. In some embodiments, the dielectric low-k material has a dielectric constant less than approximately 2.5, which can be described as an extremely low k-value dielectric material. In the illustrated embodiment, the ILD layer 210 comprises a dielectric ELK material (and can thus be described as an ELK dielectric layer), such as silicon dioxide (SiO2) (for example, porous silicon dioxide), silicon carbide (SiC), and / or carbon-doped oxide (for example, a SiCOH-based material (which, for example, has Si-CH3 bonds)), each of which is tuned / configured to have a dielectric constant less than approximately 2.5.CESL 212 has a material that differs from ILD layer 210, such as a dielectric material that differs from the dielectric material of ILD layer 210. For example, if ILD layer 210 contains silicon and oxygen (e.g., SiCOH, SiO). x , or any other silicon and oxygen-containing material having a dielectric constant less than approximately 2.5), the CESL 212 may contain silicon and nitrogen and / or carbon (for example, SiN, SiCN, SiCON, SiON, SiC and / or SiCO) (and may thus be referred to as a silicon nitride layer). In some embodiments, the CESL 212 is configured similarly to other CESLs described herein, such as a metal nitride layer. The ILD layer 210 and / or the CESL 212 may have a multilayer structure containing several dielectric materials.

[0014] With reference to Fig. In 2B, an interconnect opening 220 is formed in the dielectric layer 202 by a structuring process. The interconnect opening 220 extends vertically through the ILD layer 210 and the CESL 212 to expose an underlying MLI feature (for example, a device-plane contact, a via, or a conductive trace of the MLI feature 400) and / or an underlying feature of the device substrate 206 (for example, a gate or a source / drain feature). The interconnect opening 220 has a side wall 222 (defined by the dielectric layer 202), a side wall 224 (defined by the dielectric layer 202), and a bottom surface 226 (defined by the underlying feature) extending between the side wall 222 and the side wall 224. Fig. 2B the interconnect opening 220 has a trapezoidal shape, although the present disclosure provides that the interconnect opening 220 has other shapes, such as a rectangular shape. The side walls 222, 224 of the interconnect opening 220 are tapered such that the width of the interconnect opening 220 decreases along the thickness of the dielectric layer 202, and the width of the interconnect opening 220 that exposes the underlying feature is less than the width of the interconnect opening 220 at an upper surface of the ILD layer 210. In some embodiments, the structuring process includes performing a lithography process to form a structured mask layer 228, which has an opening 229 therein, over the dielectric layer 202, and performing an etching process to transfer a structure defined in the structured mask layer 228 onto the dielectric layer 202.The lithography process can include forming a resist layer on the dielectric layer 202 (for example, by spin coating), performing a pre-exposure firing process, performing an exposure process using a mask, performing a post-exposure firing process, and performing a development process. During the exposure process, the resist layer is exposed to radiant energy (such as ultraviolet (UV) light, deep UV light (DUV light), or extreme UV light (EUV light)), with the mask blocking, transmitting, and / or reflecting radiation to the resist layer depending on the mask structure and / or mask type (for example, binary mask, phase-shift mask, or EUV mask), so that an image corresponding to the mask structure is projected onto the resist layer.Since the resist layer is sensitive to radiation energy, exposed sections of the resist layer undergo chemical changes, and exposed (or non-exposed) sections of the resist layer are dissolved during the development process, depending on the characteristics of the resist layer and the characteristics of the developing solution used. After development, the structured resist layer exhibits a resist structure corresponding to the mask. Alternatively, the exposure process can be implemented or replaced by other methods, such as maskless lithography, electron beam writing, and / or ion beam writing.

[0015] In some embodiments, the structured resist layer is the structured mask layer 228. In such embodiments, the structured resist layer is used as an etching mask to remove sections of the dielectric layer 202 exposed through the opening 229. In some embodiments, the structured resist layer is formed over a mask layer formed over the dielectric layer 202 before the resist layer is formed, and the structured resist layer is used as an etching mask to remove sections of the mask layer formed over the dielectric layer 202, thereby forming the structured mask layer 228. In such embodiments, the structured mask layer is used as an etching mask to remove sections of the dielectric layer 202 exposed through the opening 229.The etching process can include a dry etching process (for example, a reactive ion etching (RIE) process), a wet etching process, any other suitable etching process, or combinations thereof. Various selective etching processes can be performed to form the interconnect opening 220. For example, the etching process can include a first etch that selectively etches the ILD layer 210 with respect to the structured mask layer 228 and the CESL 212, such that the first etch stops after reaching the CESL 212, and a second etch that selectively etches the CESL 212 with respect to the ILD layer 210 and the underlying feature, such that the second etch stops after reaching the underlying feature.In some embodiments, the first etching and / or the second etching may be configured to slightly over-etch, so that the first etching can partially etch the CESL 212 and / or the second etching can partially etch the underlying feature. In some embodiments, the first and second etching are similar to the etching processes described herein for etching the ILDs and the CESLs. In some embodiments, the etching process may include multiple steps (stages) for etching the CESL 212. In some embodiments, the structured mask layer 228 is removed from the ILD layer 210 after the etching process (in some embodiments by a resist stripping process). In some embodiments, the structured mask layer 228 is removed during the etching of the ILD layer 210 and / or the CESL 212.

[0016] With reference to Fig. 2C is a copper interconnect 230 formed in the interconnect opening 220. The copper interconnect 230 has a diffusion barrier layer 232 (which has a first barrier layer 234A and a second barrier layer 234B) and a copper bulk layer 236 arranged above the diffusion barrier layer 232. The diffusion barrier layer 232 is arranged on side walls 222, 224 and the bottom 226 of the interconnect opening 220, which are defined by the ILD layer 210, the CESL 212 and the underlying feature.For example, the first barrier layer 234A physically contacts the side walls 222, 224 and the bottom 226 of the interconnect opening 220, which are defined by the ILD layer 210, the CESL 212 and the underlying feature, and the second barrier layer 234B is arranged on top of the first barrier layer 234A and physically contacts it, such that the second barrier layer 234B extends along the side walls 222, 224 and the bottom 226 of the interconnect opening 220, which are defined by the ILD layer 210, the CESL 212 and the underlying feature. In some embodiments, the thickness of the diffusion barrier layer 232 (a sum of the thickness t1 of the first barrier layer 234A and the thickness t2 of the second barrier layer 234B) is approximately 9 nm or less. For example, in some embodiments the thickness t1 is approximately 2 nm to approximately 5 nm and the thickness t2 is approximately 2 nm to approximately 4 nm.In some embodiments, the copper interconnect 230 is formed by performing a first deposition process to form a first barrier material over the ILD layer 210, which partially fills the interconnect opening 220; performing a second deposition process to form a second barrier material over the first barrier material, wherein the second barrier material partially fills the interconnect opening 220; and performing a third deposition process to form a copper bulk material over the second barrier material, wherein the copper bulk material fills the remainder of the interconnect opening 220. In such embodiments, the first barrier material, the second barrier material, and the copper bulk material are arranged in the interconnect opening 220 and over the upper surface of the ILD layer 210.The first, second, and third deposition processes may include CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, electroplating, electroless plating, other suitable deposition methods, or combinations thereof. In some embodiments, the first barrier layer 234A and the second barrier layer 234B have substantially uniform thicknesses along the side walls 222, 224 and the bottom surface 226 of the interconnect opening 220. The first barrier layer 234A and the second barrier layer 234B can thus be formed by a conformal deposition process.A CMP process and / or another planarization process is performed to remove excess copper bulk material, second barrier material, and first barrier material, for example, from above the top surface of the ILD layer 210, resulting in the copper interconnect 230 (in other words, the diffusion barrier layer 232 and the copper bulk layer 236, which fill the interconnect opening 220). The CMP process planarizes a top surface of the copper interconnect 230, so that in some embodiments, the top surface of the ILD layer 210 and a top surface of the copper interconnect 230 form a substantially planar surface.

[0017] The diffusion barrier layer 232 is configured to facilitate adhesion between the dielectric layer 202 (here the dielectric surfaces defining the interconnect opening 220) and the copper bulk layer 236 and to prevent the diffusion of the copper components (for example, copper atoms / ions) from the copper interconnect 230 into the dielectric layer 202. For example, the first barrier layer 234A has a material that prevents copper diffusion from the copper bulk layer 236 into the dielectric layer 202 and promotes adhesion between the copper bulk layer 236 and the dielectric layer 202, and the second barrier layer 234B has a material that promotes adhesion between the first barrier layer 234A and the copper bulk layer 236 (acting as an adhesive layer between the first barrier layer 234A and the copper bulk layer 236).The materials of the first barrier layer 234A and the second barrier layer 234B also exhibit low electrical resistivity to maximize the electrical conductivity of the copper interconnect 230. In some embodiments, the first barrier layer 234A comprises tantalum, a tantalum alloy, titanium, a titanium alloy, tungsten, a tungsten alloy, cobalt, a cobalt alloy, molybdenum, a molybdenum alloy, another suitable component configured to prevent copper from diffusing from a copper-based material into a dielectric material and to promote adhesion between the copper-based material and the dielectric material, or combinations thereof. For example, the first barrier layer 234A comprises tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, tantalum silicon nitride, titanium silicon nitride, tantalum carbide, titanium carbide, tungsten carbide, molybdenum nitride, or combinations thereof.In the illustrated embodiment, the first barrier layer 234A comprises tantalum and nitrogen and can be referred to as a tantalum nitride barrier layer (TaN barrier layer). Tantalum exhibits low resistance to electric current and adheres well to dielectric materials, such as those of the ILD layer 210 and / or the CESL 212, thereby improving the electrical conductivity of the copper interconnect 230 and minimizing (or eliminating) gaps formed between the copper interconnect 230 and the dielectric layer 202. Tantalum in combination with nitrogen also exhibits desirable copper diffusion barrier properties. In some embodiments, the TaN barrier layer has a tantalum concentration of approximately 55 atomic percent (at%) to approximately 60 at% and a nitrogen concentration of approximately 35 at% to approximately 40 at%.In some embodiments, the second barrier layer 234B comprises tantalum, a tantalum alloy, titanium, a titanium alloy, tungsten, a tungsten alloy, cobalt, a cobalt alloy, ruthenium, a ruthenium alloy, palladium, a palladium alloy, molybdenum, a molybdenum alloy, another suitable component configured to promote adhesion between a copper diffusion barrier material, such as tantalum nitride, and a copper-based material, or combinations thereof. For example, the second barrier layer 234B comprises cobalt, cobalt nitride, ruthenium, palladium, tantalum, titanium, tungsten, tantalum silicon nitride, titanium silicon nitride, tantalum aluminum nitride, titanium aluminum nitride, or combinations thereof. In the embodiment shown, the second barrier layer 234B comprises cobalt and may be referred to as a cobalt layer (Co layer).Cobalt exhibits low resistance to electric current and adheres well to tantalum nitride and copper-based materials, which improves the electrical conductivity of the copper interconnect 230 and minimizes (or eliminates) gaps formed between the copper bulk layer 236 and the first barrier layer 234A. In some embodiments, the second barrier layer 234B has a cobalt concentration of approximately 99 at% or more.

[0018] The copper bulk layer 236 contains copper or a copper alloy. In some embodiments, the copper bulk layer 236 has a copper concentration of approximately 99 at% or more, for example, approximately 99 at% to approximately 99.5 at%. The copper bulk layer 236 has grain boundaries 238, which generally define interfaces between copper grains (or crystallites) of copper (or a copper alloy), for example, in polycrystalline form. The grain boundaries 238 provide pathways for copper ions / atoms and copper vacancies to move within the copper bulk layer 236, enabling the copper ions / atoms and copper vacancies to migrate to interfaces between the copper interconnect 230 and its surrounding layers.Such migration can lead to diffusion of copper ions / atoms from the copper bulk layer 236 to interfaces of the copper interconnect 230 with surrounding dielectric materials and / or an accumulation of copper vacancies at the interfaces, which can result in gap formation in the copper interconnect 230. As further described below, the present disclosure proposes solutions to address these challenges in ICs that are miniaturized to IC technology nodes with a size of 20 nm and above. The copper bulk layer 236 has a thickness t3, which in some embodiments is approximately 20 nm to approximately 40 nm. In some embodiments, the copper bulk layer 236 has a copper-containing seed layer (or liner layer) that is arranged between the second barrier layer 234B and a copper-containing bulk layer.In such embodiments, the copper-containing nucleation layer is arranged on the second barrier layer 234B, such that the copper-containing nucleation layer extends along the side walls 222, 224 and the bottom 226 of the interconnect opening 220, which are defined by the ILD layer 210, the CESL 212 and the underlying feature. In some implementations, the copper-containing nucleation layer has a thickness of approximately 30 nm to approximately 40 nm, and the copper-containing bulk layer also has a thickness of approximately 30 nm to approximately 40 nm. In some embodiments, the copper-containing nucleation layer is formed by an ALD process, and the copper-containing bulk layer is formed by a CVD or PVD process.

[0019] With reference to Fig. 2D continues the processing by forming a cover layer 240 of the copper interconnect 230. The cover layer 240 covers the first barrier layer 234A, the second barrier layer 234B, and the copper bulk layer 236. In some embodiments, the cover layer 240 may cover only the copper bulk layer 236. The cover layer 240 has a thickness t4. In the illustrated embodiment, the thickness t4 is approximately 4 nm or less. In some embodiments, the thickness t4 is approximately 2 nm to approximately 4 nm. The cover layer 240 comprises a material that promotes adhesion between the copper interconnect 230 and a subsequently formed dielectric layer, such as a CESL. For example, the cover layer 240 comprises metal (e.g., cobalt) and nitrogen and can thus be described as a metal nitride cover layer. Fig. 2D features the cover layer 240 containing cobalt and nitrogen and can therefore be described as a cobalt nitride cover layer (CoN cover layer). In some embodiments, the CoN cover layer has a cobalt concentration of approximately 80 at% to approximately 90 at% and a nitrogen concentration of approximately 10 at% to approximately 20 at%. In some embodiments, the CoN layer is formed by depositing a cobalt layer over the copper interconnect 230, for example by an ALD process, and performing a nitrogen plasma treatment on the cobalt layer to introduce (drive) nitrogen into the cobalt layer, thereby forming the CoN layer.In some embodiments, the ALD process or other suitable deposition process implements a cobalt-containing precursor, such as biscyclopentadienyl cobalt (CoCp2), cyclopentadienyl cobalt dicarbonyl (CpCo(CO)2), bis(η-methylcyclopentadienyl) cobalt (Co(MeCp)2), dicobalt hexacarbonyl tertbutylacetylene (CCTBA), cobalt tricarbonyl nitrosyl (Co(CO)3NO), cyclopentadienyl isopropyl acetamidinate cobalt (Co(CpAMD)), bis(cyclopentadienyl) cobalt (Co(C5H5)2,CpCo(CO)2), bis(ethylcyclopentadienyl) cobalt (C. 14 H 18 Co), cobalt-tris(2,2,6,6-tetramethyl-3,5-heptanedionate), bis(pentamethylcyclopentadienyl)-cobalt (C 20 H 30Co), another suitable cobalt-containing precursor, or combinations thereof. In some embodiments, the nitrogen plasma treatment generates nitrogen-containing plasma from a suitable nitrogen-containing precursor gas. The nitrogen-containing precursor may be nitrogen (N2), ammonia (NH3), hydrazine (N2H4), dimethylhydrazine, tert-butylhydrazine, tert-butylamine, another suitable nitrogen-containing precursor, or combinations thereof. In some embodiments, the nitrogen plasma treatment implements a flow rate of the nitrogen-containing precursor (e.g., NH3) of approximately 300 sccm to approximately 5,000 sccm. In some embodiments, the power used to generate the nitrogen-containing plasma is approximately 200 W to approximately 700 W. In some embodiments, the nitrogen plasma treatment is performed for approximately 3 seconds to approximately 100 seconds.In some embodiments, the pressure maintained in the process chamber during nitrogen plasma treatment is approximately 133 Pa to approximately 2000 Pa. In some embodiments, the temperature maintained in the process chamber during nitrogen plasma treatment is approximately 150 °C to approximately 450 °C. In some embodiments, the cover layer 240 can be formed by CVD, PVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, electroplating, electroless plating, other suitable deposition processes, or combinations thereof.The present disclosure further provides embodiments in which the cover layer 240 comprises other materials and / or combinations of materials that promote the adhesion between the copper interconnect 230 and the dielectric layer subsequently formed, together with embodiments in which the copper interconnect 230 does not have the cover layer 240 (in which case such a processing step is omitted from the manufacture of section 200).

[0020] With reference to Fig. In the illustrated embodiment, a CESL 250 is formed over the dielectric layer 202 and the copper interconnect 230 by a suitable deposition process, such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, electroplating, electroless plating, other suitable deposition processes, or combinations thereof. In the illustrated embodiment, the CESL 250 is deposited on the ILD layer 210 and the cover layer 240 of the copper interconnect 230, such that the CESL 250 physically contacts the ILD layer 210 and the cover layer 240. The thickness t5 of the CESL 250 is greater than the thickness t4. In the illustrated embodiment, the thickness t5 is approximately 3 nm or less. In some embodiments, the thickness t5 is approximately 1 nm to approximately 2.5 nm.In embodiments where the cover layer 240 is omitted from the copper interconnect 230, the CESL 250 physically contacts the copper bulk layer 236, the second barrier layer 234A, and the first barrier layer 234B. The CESL 250 comprises a material different from that of the copper interconnect 230 (for example, a material of the cover layer 240) and any subsequently formed ILD layer, in order to achieve etch selectivity during subsequent etching processes, such as those used to create an interconnect opening that exposes the copper interconnect 230. In other words, the CESL 250 and its surrounding layers will comprise materials exhibiting different etch sensitivities to a given etchant.For example, CESL 250 comprises a material that has an etch rate with respect to an etchant that is lower than the etch rate of a material in an ILD layer with respect to the etchant, so that the CESL 250 material acts as an etch stop during the etching of an overlying ILD layer (including, for example, a dielectric low-k material). The CESL 250 material is also selected to prevent copper diffusion from the copper bulk layer 236 into surrounding layers, such as the subsequently formed ILD layer. In some embodiments, CESL 250 comprises metal and nitrogen and can thus be described as a metal nitride CESL. The metal can include aluminum, hafnium, titanium, copper, manganese, vanadium, another suitable metal, or combinations thereof. In the illustrated embodiment, the metal is aluminum, and CESL 250 is an aluminum nitride CESL (AlN-CESL).Aluminum in combination with nitrogen exhibits desirable copper diffusion barrier properties. CESL 250 has a nitrogen concentration higher than that of cover layer 240. For example, CESL 250 has an aluminum concentration of approximately 52 at% to approximately 58 at% and a nitrogen concentration of approximately 42 at% to approximately 48 at%. As described below, a nitrogen concentration at an interface between CESL 250 and cover layer 240 may not sufficiently block copper diffusion at smaller IC technology nodes, particularly copper diffusion associated with BEOL processing, such as the fabrication of section 200.The present disclosure thus provides an interconnect manufacturing process that increases the nitrogen concentration at the interface between the CESL 250 and the cover layer 240, and in particular increases a surface nitrogen concentration of the CESL 250 at the interface between the CESL 250 and the cover layer 240.

[0021] In some embodiments, an ALD is performed to form the AlN-CESL. Fig. Figure 4 is a flowchart of an ALD process 300, which starts at block 140 in Fig. 1 can be implemented according to various aspects of the present disclosure. In Block 302, a workpiece is loaded into a process chamber, the process chamber being prepared for an ALD process to form a contact etch stop layer, such as CESL 250, over a dielectric layer in which an interconnect is arranged. In Block 304, the workpiece is exposed to an aluminum-containing precursor (which may be referred to as an aluminum-containing pulse). In Block 306, a cleaning process is carried out to remove any remaining aluminum-containing precursor and any by-products from the process chamber. In Block 308, the workpiece is exposed to a nitrogen-containing precursor (which may be referred to as a nitrogen-containing pulse). In Block 310, a cleaning process is carried out,to remove any remaining nitrogenous precursor and any byproducts from the process chamber. Blocks 304-310 form an ALD cycle, which has two deposition phases (block 304 and block 308) and two cleanup phases (block 306 and block 310). Each ALD cycle is a self-limiting process, where approximately one aluminum-nitrogen monolayer or less is deposited during each ALD cycle. The ALD cycle is repeated until a contact etch stop layer, such as CESL 250, reaches a desired thickness (target thickness). For example, if the thickness of the CESL 250 at block 312 corresponds to a target thickness (or is within a given target thickness threshold), then the ALD process 300 ends at block 314. If the thickness of the CESL 250 does not correspond to the target thickness (or is not within the given target thickness threshold), then the ALD process 300 returns to block 304.to begin another ALD cycle. In some embodiments, the ALD cycle (blocks 304-310) is repeated until the CESL 250 has a thickness of approximately 1 nm to approximately 2.5 nm. Various parameters of the ALD process 300 can be adjusted to achieve desired growth characteristics, such as a flow rate of a deposition gas (including the aluminum-containing precursor gas, the nitrogen-containing precursor gas, and / or a carrier gas), a concentration (or dosage) of the aluminum-containing precursor gas, a concentration (or dosage) of the nitrogen-containing precursor gas, a concentration (or dosage) of the carrier gas, a ratio of the concentration of the aluminum-containing precursor gas to the concentration of the carrier gas, and a ratio of the concentration of the nitrogen-containing precursor gas to the concentration of the carrier gas.to achieve a specific power output from a high-frequency (HF) source (used, for example, to generate a plasma during the deposition process), a bias voltage (applied, for example, to excite the plasma during the deposition process), a process chamber pressure, a deposition process duration, other suitable deposition parameters, or combinations thereof. Additional steps can be provided before, during, and after the ALD process 300, and some of the steps can be shifted, replaced, or removed by additional embodiments of the ALD process 300.

[0022] The aluminum-containing precursor at block 304 may comprise trimethylaluminium (TMA), triethylaluminium (TEA), trimethylaminalane, aluminum chloride, dimethylaluminium hydride (DMAH), dithylaluminium ethoxide (DEAL), any other aluminum-containing precursor, or combinations thereof. In such embodiments, during the aluminum-containing pulse, aluminum and / or any other aluminum-containing precursor and / or reaction components are adsorbed onto exposed areas of the ILD layer 210 and / or the cover layer 240 to form a layer containing aluminum and / or any other aluminum-containing precursor and / or reaction components. In some embodiments, the flow rate of the aluminum-containing precursor is approximately 6,000 sccm to approximately 8,000 sccm. In some embodiments, the aluminum-containing pulse duration is approximately 20 seconds to approximately 30 seconds.In some embodiments, the pressure maintained in the process chamber during the aluminum-containing pulse is approximately 267 Pa to approximately 400 Pa. In some embodiments, the temperature maintained in the process chamber during the aluminum-containing pulse is approximately 300 °C to approximately 350 °C. In some embodiments, a carrier gas is used to supply the aluminum-containing precursor to the process chamber. In some embodiments, the carrier gas is an inert gas, such as an argon-containing gas, a helium-containing gas, another suitable inert gas, or a combination thereof. In some embodiments, the purification process at block 306 implements an inert gas, such as an argon-containing gas, a helium-containing gas, another suitable inert gas, or a combination thereof. In some embodiments, the flow rate of the inert gas is approximately 4,000 sccm to approximately 5,000 sccm.In some embodiments, the cleaning process takes approximately 20 to 30 seconds. In some embodiments, the pressure maintained in the process chamber during the cleaning process is approximately 267 Pa to 400 Pa.

[0023] The nitrogenous precursor in block 308 may comprise nitrogen (N₂), ammonia (NH₃), hydrazine (N₂H₄), dimethylhydrazine, tert-butylhydrazine, tert-butylamine, any other suitable nitrogenous precursor, or combinations thereof. In such embodiments, nitrogen and / or any other nitrogenous precursor and / or reaction components interact with the layer containing aluminum and / or any other aluminum-containing precursor and / or reaction components, forming approximately a monolayer or less containing aluminum and nitrogen, such as an AlN layer (for example, nitrogen is adsorbed onto the layer containing aluminum). In some embodiments, the flow rate of the nitrogenous precursor (e.g., NH₃) is approximately 5,000 sccm to approximately 10,000 sccm. In some embodiments, the duration of the nitrogenous pulse is approximately 1 second to approximately 20 seconds.In some embodiments, the pressure maintained in the process chamber during the nitrogen pulse is approximately 133 Pa to approximately 400 Pa. In some embodiments, the temperature maintained in the process chamber during the nitrogen pulse is approximately 300 °C to approximately 400 °C. In some embodiments, a carrier gas is used to supply the nitrogen precursor to the process chamber. In some embodiments, the carrier gas is an inert gas, such as an argon-containing gas, a helium-containing gas, another suitable inert gas, or a combination thereof. In some embodiments, the cleaning process at Block 310 implements an inert gas, such as an argon-containing gas, a helium-containing gas, another suitable inert gas, or a combination thereof. In some embodiments, the flow rate of the inert gas is approximately 2,000 sccm to approximately 7,000 sccm.In some embodiments, the cleaning process lasts approximately 1 second to approximately 10 seconds. In some embodiments, the pressure maintained in the process chamber during the cleaning process is approximately 133 Pa to approximately 400 Pa.

[0024] In some embodiments, CVD is performed to form the AlN-CESL. For example, a workpiece is loaded into a process chamber, the chamber being prepared for a CVD process to form a contact etch stop layer, such as CESL 250, over a dielectric layer containing an interconnect. In the process chamber, the workpiece is exposed to an aluminum-containing precursor and a nitrogen-containing precursor, both of which react with exposed surfaces of the dielectric layer and the interconnect to form an aluminum-nitrogen layer. The workpiece is exposed to the aluminum-containing and nitrogen-containing precursors until a contact etch stop layer reaches a desired thickness (target thickness), such as approximately 1 nm to approximately 2.5 nm. A cleaning process is then performed to remove any remaining aluminum-containing precursor.to remove nitrogenous precursors and any byproducts from the process chamber. The aluminum-containing precursor may comprise TMA, TEA, trimethylaminal aluminum chloride, DMAH, DEAL, any other aluminum-containing precursor, or combinations thereof. The nitrogenous precursor may comprise N₂, NH₃, N₂H₄, dimethylhydrazine, tert-butylhydrazine, tert-butylamine, any other suitable nitrogenous precursor, or combinations thereof. Various parameters of the CVD process can be adjusted to achieve desired growth characteristics (for example, the thickness, aluminum concentration, and / or nitrogen concentration of the AlN layer), such as a deposition gas flow rate (including the aluminum-containing precursor gas, the nitrogenous precursor gas, and / or a carrier gas), an aluminum-containing precursor gas concentration, a nitrogenous precursor gas concentration, or a carrier gas concentration.a ratio of the concentration of the aluminum-containing precursor gas to the concentration of the nitrogen-containing precursor gas, a ratio of the concentration of the aluminum-containing precursor gas and / or the nitrogen-containing precursor gas to the concentration of the carrier gas, a power of an RF source, a bias voltage, a process chamber pressure, a duration of the deposition process, other suitable deposition parameters, or combinations thereof. In some embodiments, the flow rate of the aluminum-containing precursor is approximately 6,000 sccm to approximately 8,000 sccm, and the flow rate of the nitrogen-containing precursor is approximately 4,000 sccm to approximately 5,000 sccm. In some embodiments, the workpiece is exposed to the aluminum-containing precursor and a nitrogen-containing precursor for approximately 20 seconds to approximately 40 seconds. In some embodiments, a pressureThe pressure maintained in the process chamber during the CVD process is approximately 267 Pa to approximately 400 Pa. In some embodiments, the nitrogen-containing precursor is used to generate a nitrogen-containing plasma (for example, if the CVD process is a PEALD process) that interacts with the aluminum-containing precursor and / or exposed surfaces of the workpiece. In some embodiments, the nitrogen-containing plasma has a nitrogen concentration of approximately 70% to approximately 90%. In some embodiments, the power used to generate a low-frequency nitrogen-containing plasma is approximately 80 W to approximately 100 W. In some embodiments, the power used to generate a high-frequency nitrogen-containing plasma is 500 W to approximately 650 W. It is understood that ALD is a type of CVD, with the exception that...that the ALD exposes the workpiece separately to the aluminum-containing precursor (or another metal-containing precursor depending on the desired composition of the CESL 250) and the nitrogen-containing precursor.

[0025] An interface region A between the CESL 250 and the copper interconnect 230 (hereinafter generally referred to as CESL / copper interface A) has an interface B between the CESL 250 and the cover layer 240 and an interface C between the cover layer 240 and the copper bulk layer 236. The present disclosure recognizes that stress-induced voiding (stress migration) at the CESL / copper interface A has become a major factor in IC device reliability. For example, mechanical stresses in the MLI feature comprising section 200 can cause copper ions / atoms and copper vacancies to migrate along the grain boundaries 238 in the copper interconnect 230 to the CESL / copper interface A.As copper vacancies accumulate and copper atoms / ions diffuse into the MLI feature (for example, the dielectric layers of the MLI feature), gaps form at the CESL / copper interface A. These gaps can increase the resistance of the copper interconnect 230 and degrade IC performance. They can cause an open circuit to be location- and / or size-dependent and, in some cases, lead to copper interconnect failure and / or IC device failure. These mechanical stresses arise during MLI feature processing (in other words, during BEOL processing) due to differing coefficients of thermal expansion between the copper interconnect 230 and its surrounding dielectric materials.For example, because the copper interconnect 230 and surrounding dielectric materials (for example, the ILD layer 210, the CESL 212 and subsequently formed ILD layers and / or CESLs) have different coefficients of thermal expansion, the copper interconnect 230 and the surrounding dielectric materials will expand and contract at different rates during BEOL thermal cycles (for example, heating cycles and / or cooling cycles), causing stress differences in section 200 of the MLI feature that cause the copper ions / atoms and / or copper vacancies to migrate to the CESL / copper interface A.Accordingly, the present disclosure proposes performing a nitrogen plasma treatment on the CESL 250 prior to the formation of an overlying ILD layer, wherein the nitrogen plasma treatment is configured to increase the nitrogen concentration and / or enhance nitrogen binding at the CESL / copper interface A. Increasing the nitrogen concentration and / or nitrogen binding at the CESL / copper interface A limits (and in some embodiments eliminates) the diffusion of copper ions / atoms and copper vacancies along the CESL / copper interface A, thereby preventing the accumulation of copper vacancies at the CESL / copper interface A and limiting stress-induced gap formation in the copper interconnect 230, as further detailed below.In some embodiments, the CESL 250 may have a surface nitrogen concentration (for example, at interface B) of approximately 10 at% to approximately 15 at% before nitrogen plasma treatment. It has been observed that this results in insufficient copper diffusion barrier capabilities for the CESL 250 at smaller IC technology nodes, particularly for copper diffusion in conjunction with BEOL processing, such as the fabrication of section 200. In such embodiments, implementing the nitrogen plasma treatment described herein increases the surface nitrogen concentration to approximately 20 at% to approximately 30 at% after the nitrogen plasma treatment. It has been observed that such increased surface nitrogen concentrations improve the copper diffusion barrier capabilities of the CESL 250 and reduce gap formation.

[0026] With reference to Fig. In 2F, a nitrogen plasma treatment 255 is performed on the CESL 250, resulting in a nitrogen-treated CESL 250'. The nitrogen-treated CESL 250' has a nitrogen concentration that is higher than the nitrogen concentration of the cover layer 240. For example, the nitrogen concentration is approximately 40 at%. In some embodiments, the ratio of the nitrogen concentration of the nitrogen-treated CESL 250' to the nitrogen concentration of the cover layer 240 is approximately 2:1 to approximately 5:1. In some embodiments, the nitrogen-treated CESL 250' has an aluminum concentration of approximately 52 at% to approximately 58 at% and a nitrogen concentration of approximately 42 at% to approximately 48 at%. It is understood that in the illustrated embodiment, the nitrogen concentration of the first barrier layer 234A (e.g.,a TaN barrier layer) is lower than the nitrogen concentration of the nitrogen-treated CESL 250' and higher than the nitrogen concentration of the cover layer 240. In some embodiments, the ratio of the nitrogen concentration of the nitrogen-treated CESL 250' to the nitrogen concentration of the first barrier layer 234A is approximately 1:1 to approximately 1.5:1. Fig. 5 is a flow diagram of a nitrogen plasma treatment process 350, which is referred to as nitrogen plasma treatment 255 in Fig. 2F and / or at block 150 in Fig. 1 can be implemented according to various aspects of the present disclosure. In Block 352, a workpiece (including, for example, the CESL 250 arranged above the copper interconnect 230) is loaded into a process chamber, where the process chamber is prepared for a nitrogen plasma treatment process. In some embodiments, the CESL 250 is deposited above the copper interconnect 250 in the same process chamber, so that the CESL deposition and the nitrogen plasma treatment are performed in place. In Block 354, the workpiece is exposed to nitrogen-containing plasma (which is referred to as a nitrogen-containing plasma pulse). The nitrogen-containing plasma bombards the CESL 250 with plasma-excited nitrogenous species to drive nitrogen into the CESL 250, in particular to the CESL / copper interface A.Bombarding the CESL 250 with plasma-excited nitrogenous species also creates, repairs, and / or enhances nitrogen bonding, such as NN bonds, Al-N bonds, Co-N bonds, and / or Co-N-Al bonds. In some embodiments, the nitrogen-treated CESL 250' exhibits more NN bonds, Al-N bonds, Co-N bonds, and / or Co-N-Al bonds than the CESL 250. For example, . Fig. 6. A Fourier transform infrared spectrum (FTIR spectrum) is provided, obtained by performing FTIR spectroscopy on an AlN bulk film before and after nitrogen plasma treatment, such as nitrogen plasma treatment 255. In the FTIR spectrum, the intensity of the absorbed frequencies / wavenumbers corresponding to the Al-N bonds after treatment (≈ 0.95) is greater than the intensity of the absorbed frequencies / wavenumbers corresponding to the Al-N bonds before treatment (≈ 0.75), indicating that the nitrogen plasma treatment increases the Al-N bonds in the AlN bulk film. Thus, nitrogen plasma treatment 255 can be implemented to increase the Al-N bonds in CESL 250.Various parameters of the nitrogen plasma treatment process 350 are adjusted to achieve a desired nitrogen concentration and / or nitrogen binding in the CESL 250, such as the flow rate of a nitrogenous precursor gas, the flow rate of a carrier gas, the concentration of the nitrogenous precursor gas, the concentration of the carrier gas, the ratio of the nitrogenous precursor gas concentration to the carrier gas concentration, the power of an RF source, the bias voltage, the pressure of the process chamber, the duration of the nitrogen plasma treatment process, other suitable parameters, or combinations thereof. In block 356, a cleaning process is carried out, if necessary, to remove any remaining nitrogenous plasma and any byproducts from the process chamber.In some embodiments, if the nitrogen-treated CESL 250' exhibits target nitrogen concentration and / or target nitrogen binding characteristics at block 358, then the nitrogen plasma treatment process 350 ends at block 360. If this is not the case, in some embodiments, blocks 354 and 356 (i.e., one cycle) can be repeated until the desired target nitrogen concentration and / or target nitrogen binding characteristics are achieved.

[0027] The nitrogen-containing plasma is generated from a nitrogen-containing precursor gas comprising diatomic nitrogen (N2) alone or in combination with NH3, another suitable nitrogen-containing precursor gas, or combinations thereof. The nitrogen plasma treatment 255 can thus, in some embodiments, be described as an N2 plasma treatment process. In such embodiments, the nitrogen-containing plasma comprises nitrogen-containing excited neutral molecules (for example, N2*), nitrogen-containing ionized molecules (for example, N2+), nitrogen-containing atoms (for example, N), ionized atoms (N+), or combinations thereof (all of which are generally referred to as plasma-excited nitrogenous species). The nitrogen-containing plasma is “nitrogen-rich,” which generally refers to a nitrogen-containing plasma having a nitrogen (N2) concentration greater than approximately 50%.In some embodiments, the nitrogen-containing plasma has a nitrogen concentration (N2) of approximately 70% to approximately 90% to effectively drive nitrogen into the CESL 250 towards interface B and / or into the cover layer 240 towards interface B and / or interface C, thereby increasing the nitrogen concentration and / or nitrogen binding at the CESL / copper interface A. Nitrogen concentrations in the nitrogen-containing plasma of approximately 30% or less are not suitable for increasing the nitrogen concentration and / or nitrogen binding at the CESL / copper interface A. In some embodiments, the power used to generate a low-frequency nitrogen-containing plasma is approximately 50 W to approximately 200 W. In some embodiments, the power used to generate a high-frequency nitrogen-containing plasma is approximately 500 W to approximately 650 W.In some embodiments, an RF bias and / or a DC bias is applied to the workpiece to accelerate the nitrogen-containing plasma to the workpiece. In some embodiments, the CESL 250 is exposed to the nitrogen-containing plasma for approximately 20 to 30 seconds. In some embodiments, the pressure maintained in the process chamber during the nitrogen plasma treatment is approximately 133 Pa to 267 Pa. In some embodiments, the temperature maintained in the process chamber during the nitrogen plasma treatment is approximately 350 °C to 450 °C. In some embodiments, the workpiece is heated to a temperature of approximately 350 °C to 450 °C during the nitrogen plasma treatment.

[0028] The nitrogen plasma treatment 255 drives nitrogen into the CESL 250, thereby increasing a surface nitrogen concentration and / or nitrogen binding at the CESL / copper interface A, particularly along interface B. In some embodiments, after the nitrogen plasma treatment 255, the surface nitrogen concentration at interface B of the nitrogen-treated CESL 250' is higher than the surface nitrogen concentration at interface B of the CESL 250. For example, the nitrogen-treated CESL 250' has a surface nitrogen concentration at interface B of approximately 20 at% or more (for example, approximately 20 at% to approximately 30 at%), and the CESL 250 has a surface nitrogen concentration at interface B of less than approximately 20 at% (for example, approximately 10 at% to approximately 15 at%), as shown in Fig. Figure 2F illustrates this. Surface nitrogen concentrations at interface B that are less than approximately 20 at% are insufficient to sufficiently inhibit copper diffusion, which has been observed to lead to gap formation within the copper interconnect 230 during subsequent processing. In contrast, surface nitrogen concentrations at interface B that are approximately 20 at% or higher can sufficiently reduce copper diffusion and have been observed to reduce, and in some cases eliminate, gap formation in the copper interconnect 230 during subsequent processing.In some embodiments, the surface nitrogen concentration of the CESL 250 at interface B before nitrogen plasma treatment 255 is approximately 10 at% to approximately 15 at%, and the surface nitrogen concentration of the nitrogen-treated CESL 250' at interface B after nitrogen plasma treatment 255 is approximately 20 at% to approximately 25 at%. In some embodiments, the nitrogen concentration of the nitrogen-treated CESL 250' has a stepped profile, with the nitrogen concentration increasing from an upper surface of the nitrogen-treated CESL 250' along its thickness to interface B, such that the nitrogen-treated CESL 250' has a maximum nitrogen concentration along interface B.In some embodiments, the nitrogen-treated CESL 250' exhibits other nitrogen concentration profiles, such as a step profile, a linear continuous profile, a non-linear continuous profile, a bell curve profile, a sawtooth profile, or any other suitable profile. In some embodiments, the nitrogen plasma treatment 255 increases the NN bonding and / or the Al-N bonding, such that the number of NN bonds and / or Al-N bonds in the nitrogen-treated CESL 250' (particularly along interface B) is approximately 20% greater than the number of NN bonds and / or Al-N bonds in the CESL 250. The nitrogen-treated CESL 250' also exhibits different material characteristics than the CESL 250 (which have a lower nitrogen concentration). For example, the dielectric constant and density of nitrogen-treated CESL 250' are greater than the dielectric constant and density of CESL 250.In some embodiments, the nitrogen plasma treatment 255 increases the dielectric constant by approximately 0.2. For example, the nitrogen-treated CESL 250' has a dielectric constant of approximately 7.2 to approximately 7.6 (for example, approximately 7.4) compared to the CESL 250, which has a dielectric constant of approximately 7 or less. In some embodiments, the nitrogen plasma treatment 255 increases the density by approximately 0.10. For example, the nitrogen-treated CESL 250' has a density of approximately 2.70 to approximately 2.80 (for example, approximately 2.75) compared to the CESL 250, which has a density of approximately 2.60 to approximately 2.70 (for example, approximately 2.65).

[0029] The nitrogen plasma treatment 255 can also drive nitrogen into the cover layer 240, thereby increasing the nitrogen concentration along interface C. For example, in some embodiments, after the nitrogen plasma treatment 255, the cover layer 240 has a cobalt concentration of approximately 80 at% to approximately 90 at% and a nitrogen concentration of approximately 10 at% to approximately 20 at%. In some embodiments, the nitrogen concentration of the cover layer 240 after the nitrogen plasma treatment 255 has a stepped profile, with the nitrogen concentration decreasing from interface B along its thickness to interface C, such that the cover layer 240 has a maximum nitrogen concentration along interface B.In some embodiments, the cover layer 240 exhibits other nitrogen concentration profiles, such as a stepped profile, a linear continuous profile, a non-linear continuous profile, a bell curve profile, a sawtooth profile, or any other suitable profile. In some embodiments, a nitrogen concentration profile of the nitrogen-treated CESL 250' and the cover layer 240 combined increases from the upper surface of the nitrogen-treated CESL 250' along a thickness of the CESL / copper interface A to a peak region near interface B and then decreases from the peak region along the thickness of the CESL / copper interface A to a lower surface of the cover layer 240 at interface C, as shown in [Figure]. Fig. 2F is represented by a diagram of the nitrogen concentration in atomic percent in the CESL 250' and the cover layer 240. In such embodiments, the nitrogen concentration of the CESL / copper interface A can be described as having a bell curve profile, with one peak of the bell curve located near the interface B. In some embodiments, the nitrogen plasma treatment 255 increases the NN bond and / or the Co-N bond, such that the number of NN bonds and / or Co-N bonds in the cover layer 240 after the nitrogen plasma treatment 255 (particularly along the interface B) is greater than the number of NN bonds and / or Co-N bonds in the cover layer 240 before the nitrogen plasma treatment 255.In some embodiments, the nitrogen plasma treatment 255 creates, repairs and / or improves the Co-N-Al bond between the cover layer 240 and the nitrogen-treated CESL 250', for example by increasing the number of Co-N-Al bonds at interface B in the nitrogen-treated CESL 250' compared with the number of Co-N-Al bonds at interface B in the CESL 250.

[0030] It is understood that the material of CESL 250 is selected to minimize metal diffusion while also providing sufficient etch-stop functionality during the formation of an interconnect opening to expose the copper interconnect 230 during subsequent processing. The material of CESL 250 is also selected to minimize its contribution to the parasitic capacitance resulting from section 200 of the MLI feature, which cannot be ignored in smaller IC technology nodes. The present disclosure recognizes that metal nitride (aluminum nitride in the illustrated embodiment) acts well as an etch-stop layer after undergoing nitrogen plasma treatment, such as nitrogen plasma treatment 255, when etching a dielectric low-k material, while also providing excellent copper diffusion-stop properties at thicknesses desirable for smaller IC technology nodes.While silicon nitride can satisfactorily restrict (or prevent) metal diffusion, such as copper diffusion, the thicknesses required for silicon nitride to achieve desired metal diffusion barrier properties (e.g., approximately 10 nm to approximately 20 nm) and thus avoid gapping at CESL / interconnect interfaces are too large for IC technology nodes of 20 nm and below. In contrast, metal nitride, after nitrogen plasma treatment, can reliably provide desired metal diffusion barrier and etch stop properties with a thickness of approximately 3 nm or less. These thicknesses also fit seamlessly into IC technology nodes of 20 nm and below, minimizing the contribution of parasitic capacitance from ESLs to MLI characteristics.

[0031] With reference to Fig. 2G continues the processing by forming a CESL 260 over the CESL 250 and a CESL 262 over the CESL 260, forming a multilayer CESL 265 comprising the CESL 250, the CESL 260, and the CESL 262. An ILD layer 270 is then formed over the CESL 265, particularly on the CESL 262. In some embodiments, the CESL 260 has a thickness t6 of approximately 3 nm to approximately 9 nm, and the CESL 262 has a thickness t7 of approximately 2 nm to approximately 5 nm. CESL 260 and CESL 262 feature materials different from the ILD layer 270 to achieve etch selectivity during subsequent etching processes, such as those used to create an interconnect opening that exposes the copper interconnect 230. In other words, CESL 260 and CESL 262 and their surrounding layers will feature materials exhibiting varying etch sensitivities to a given etchant.For example, CESL 260 and CESL 262 comprise a material exhibiting an etch rate with respect to an etchant that is lower than the etch rate of an ILD layer material with respect to the etchant, so that the material of CESL 260 and / or CESL 262 acts as an etch stop during the etching of an overlying ILD layer (including, for example, a dielectric low-k material). CESL 260 and CESL 262 also comprise materials that promote adhesion between CESL 250 and the ILD layer 270. In some embodiments, CESL 260 and CESL 262 comprise materials that are substantially nitrogen-free. For example, CESL 260 and CESL 262 comprise materials that have a nitrogen concentration of less than approximately 1 at%. The CESL 260 contains oxygen and / or carbon and, in some embodiments, silicon.For example, CESL 260 comprises SiO₂, SiC, SiCO₃, other oxygen- and / or carbon-containing material, or combinations thereof. In the illustrated embodiment, CESL 260 comprises oxygen-doped silicon carbide (SiCO₃, also referred to as ODC). CESL 262 comprises metal and oxygen and can thus be described as a metal oxide layer. The metal may comprise aluminum, hafnium, titanium, copper, manganese, vanadium, any other suitable metal, or combinations thereof. In the illustrated embodiment, the metal is aluminum, and CESL 262 is an aluminum oxide CESL (AlO-CESL). In some embodiments, CESL 262 has an aluminum concentration of approximately 55 at% to approximately 65 at% and an oxygen concentration of approximately 35 at% to approximately 45 at%.CESL 260 and CESL 262 are formed by CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, FCVD, other suitable deposition processes, or combinations thereof. Following the deposition of CESL 260 and / or CESL 262, a CMP process and / or another planarization process may be performed so that CESL 260 and / or CESL 262 have a substantially planar surface.

[0032] ILD layer 270 is similar to ILD layer 210. For example, ILD layer 270 is formed by a deposition process such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, FCVD, other suitable deposition processes, or combinations thereof. ILD layer 270 incorporates a dielectric material that includes, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, TEOS, PSG, BSG, BPSG, FSG, Black Diamond® (Applied Materials, Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB-based dielectric material, SiLK (Dow Chemical, Midland, Michigan), polyimide, other suitable dielectric material, or combinations thereof. In some embodiments, the ILD layer 270 features a dielectric low-k material.In the illustrated embodiment, for example, the ILD layer 270 comprises a dielectric ELK material, such as silicon dioxide (SiO2) (e.g., porous silicon dioxide), silicon carbide (SiC), and / or carbon-doped oxide (e.g., a SiCOH-based material (e.g., having Si-CH3 bonds)), each of which is tuned / configured to have a dielectric constant less than approximately 2.5. In some embodiments, the ILD layer 270 may have a multilayer structure comprising several dielectric materials. In some embodiments, the ILD layer 270 has a thickness t8 of approximately 60 nm to approximately 90 nm. Following the deposition of the ILD layer 270, a CMP process and / or another planarization process may be performed, such that the ILD layer 270 has a substantially planar surface.

[0033] With reference to Fig. 2H is an interconnect opening 280 formed in the ILD layer 270 and the CESL 265 (which together can be referred to as a dielectric layer) by a structuring process. In the illustrated embodiment, the interconnect opening 280 extends vertically through the ILD layer 270 and the CESL 265 to expose the copper interconnect 230, in particular the cover layer 240 of the copper interconnect 230. The interconnect opening 280 has a side wall 282 (defined by the ILD layer 270 and the CESL 265), a side wall 284 (defined by the ILD layer 270 and the CESL 265), and a bottom surface 286 (defined by the copper interconnect 230) extending between the side wall 282 and the side wall 284. Fig. In 2H, the interconnect opening 280 has a trapezoidal shape, although the present disclosure provides that the interconnect opening 280 can have other shapes, such as a rectangular shape. The sidewalls of the interconnect opening 280 are tapered, such that the width of the interconnect opening 280 decreases along the thickness of the dielectric layer, and the width of the interconnect opening 280 that exposes the copper interconnect 230 is less than the width of the interconnect opening 280 at a top surface of the ILD layer 270. The structuring process for forming the interconnect opening 280 can be similar to the structuring process used to form the interconnect opening 220.For example, the structuring process includes performing a lithography process to form a structured mask layer 288 (containing an opening 289) over the ILD layer 270 and performing an etching process to transfer a structure defined in the structured mask layer 288 to the ILD layer 270 and the CESL 265. The lithography process may include forming a resist layer on the ILD layer 270 (for example, by spin coating), performing a pre-exposure firing process, performing an exposure process using a mask, performing a post-exposure firing process, and performing a development process.During the exposure process, the resist layer is exposed to radiation energy. The mask blocks, transmits, and / or reflects radiation to the resist layer depending on the mask structure and / or type, projecting an image onto the resist layer that corresponds to the mask structure. Because the resist layer is sensitive to radiation energy, exposed portions of the resist layer undergo chemical changes. During the development process, exposed (or non-exposed) portions of the resist layer are dissolved, depending on the characteristics of the resist layer and the developing solution used. After development, the structured resist layer exhibits a resist structure that corresponds to the mask. Alternatively, the exposure process can be implemented or replaced by other methods, such as maskless lithography, electron beam writing, and / or ion beam writing.In some embodiments, the structured resist layer is the structured mask layer 288. In such embodiments, the structured resist layer is used as an etching mask to remove sections of the ILD layer 270 and / or the CESL 265 exposed through the opening 289, thereby exposing the copper interconnect 230. In some embodiments, the structured resist layer is formed over a mask layer formed over the ILD layer 270 prior to the formation of the resist layer, and the structured resist layer is used as an etching mask to remove sections of the mask layer formed over the ILD layer 270, thereby forming the structured mask layer 288.In such embodiments, the structured mask layer is used as an etching mask to remove sections of the ILD layer 270 and / or the CESL 265 exposed through the opening 289, thereby exposing the copper interconnect 230. In some embodiments, the structured mask layer 288 is removed from the ILD layer 270 after the etching process (in some embodiments by a resist stripping process). In some embodiments, the structured mask layer 288 is removed during the etching of the ILD layer 270, the CESL 262, the CESL 260, and / or the nitrogen-treated CESL 250'.

[0034] In some embodiments, the etching process is a multi-step etching process comprising a first etching step that selectively etches the ILD 270 and a second etching step that selectively etches the CESL 265. For example, the first etching step is configured to remove the ILD layer 270 but not, or not substantially, remove the CESL 265, so that the first etching stops after reaching the CESL 265, while the second etching step is configured to remove the CESL 265 but not, or not substantially, remove the ILD 270 and the copper interconnect 230, so that the second etching stops after reaching the copper interconnect 230 (specifically, the cover layer 240).Various etching parameters can be adjusted to achieve selective etching of the ILD layer 270 and the CESL 265, such as the etchant composition, etching temperature, etching solution concentration, etching time, etching pressure, source power, RF bias, RF bias power, etchant flow rate, other suitable etching parameters, or combinations thereof. For example, for the first etching step, an etchant is selected that etches the ILD layer 270 material (in the illustrated embodiment, an ELK material comprising silicon and oxygen) at a higher rate than the CESL 265 material (in the illustrated embodiment, metal oxide, oxygen-doped silicon carbide, and metal nitride) (i.e., the etchant exhibits high etch selectivity with respect to the ILD layer 270 material).For the second etching step, an etchant is selected that etches the CESL 265 material at a higher rate than the ILD layer 270 material (i.e., the etchant exhibits high etch selectivity with respect to the CESL 265 material). In some embodiments, the first and / or second etching step may be configured to slightly over-etch. In such embodiments, the first etching step may partially etch the CESL 265 and / or the second etching step may partially etch the cover layer 240. In some embodiments, the second etching step may comprise several steps for the selective etching of each layer of the CESL 265, such as the CESL 262, the CESL 260, and the nitrogen-containing CESL 250, with each step configured to selectively etch one of the respective layers of the CESL 265. The etching process is a dry etching process, a wet etching process, another suitable etching process, or combinations thereof.A dry etching process may employ a hydrogen-containing etching gas, an oxygen-containing etching gas, a fluorine-containing etching gas (for example, CF4, SF6, CH2F2, CHF3 and / or C2F6), a chlorine-containing etching gas (for example, Cl2, CHCl3, CCl4 and / or BCl3), a bromine-containing etching gas (for example, HBr and / or CHBr3), an iodine-containing etching gas, other suitable etching gases and / or etching plasmas, or combinations thereof. A wet etching process may implement a wet etching solution containing DHF, KOH, NH4OH, NH3, HF, HNO3, CH3COOH, H2O, other suitable wet etching solution components, or combinations thereof. In some embodiments, the first etching step is a dry etching process that uses an etching gas containing C4F8 and Ar to selectively etch the ILD layer 270. In such embodiments, a ratio of C4F8 to Ar, an etching temperature and / or an RF power can be adjusted to achieve a desired etch selectivity.In some embodiments, the first etching step is a wet etching process using a wet etching solution containing HF to selectively etch the ILD layer 270. In such embodiments, an etching temperature and / or etching time can be adjusted to achieve a desired etch selectivity. In some embodiments, the second etching step is a dry etching process using an etching gas containing Cl₂, CHCl₂, and / or N₂ to selectively etch the CESL 265. In such embodiments, a ratio of Cl₂ to CHCl₂ and / or N₂, an etching temperature, and / or an HF power can be adjusted to achieve a desired etch selectivity.

[0035] With reference to Fig. In 2J, an interconnect 290 is formed in the interconnect opening 280. Since the nitrogen-treated CESL 250' of the CESL / copper interface A of section 200 has a higher surface nitrogen concentration and a higher (stronger) nitrogen binding than a CESL that is not nitrogen-treated, such as the CESL 250 in section 200', which is in Fig. As shown in Figure 3, the CESL / copper interface A of section 200 limits (or prevents) the occurrence of copper diffusion during BEOL processing, which typically leads to an accumulation of copper vacancies at the CESL / copper interface A, thereby preventing gaps 298, such as those shown in Figure 3, from forming. Fig. Figure 3 shows that the CESL / copper interface A is formed at this interface. Such a phenomenon is further characterized by... Fig. 7A and Fig. 7B illustrates where Fig. 7A is a fragmentary diagrammatic top view of the copper bulk layer 236 of the copper interconnect 230 when the nitrogen-treated CESL 250' is formed over the copper interconnect 230, and Fig. Figure 7B shows a fragmentary schematic top view of the copper bulk layer 236 of the copper interconnect 230 when the CESL 250 (which is not subjected to nitrogen plasma treatment) is formed above the copper interconnect 230. Without nitrogen treatment of the CESL above the copper interconnect 230, copper diffusion occurring during BEOL processing can lead to an accumulation of copper vacancies and create gaps in the copper bulk layer 236, as shown in Figure 7B. Fig. Figure 7B illustrates this. In the illustrated embodiment, the copper interconnect 230 is a via of the MLI feature (in other words, an interconnect that connects two different layers of the MLI feature), and the interconnect 290 is a conductive trace of the MLI feature. For example, the copper interconnect 230 is a via that connects a conductive trace of a first metal layer of the MLI feature (e.g., a metal one layer (M1 layer) below the copper interconnect 230) to the interconnect 290 of a second metal layer of the MLI feature (e.g., a metal two layer (M2 layer) above the copper interconnect 230). In another example, the copper interconnect 230 is a via that connects a source / drain contact or gate of a first metal layer of the MLI feature (e.g.,The device contact connects the metal zero layer (M0 layer) below the copper interconnect 230 to the interconnect 290 of a second metal layer of the MLI feature (e.g., the metal one layer (M1 layer) above the copper interconnect 230). In some embodiments, the interconnect 290 is similar to the copper interconnect 230. For example, the interconnect 290 may have a diffusion barrier layer 292 (which has a first barrier layer 294A and a second barrier layer 294B) and a copper bulk layer 296 arranged above the diffusion barrier layer 292. The diffusion barrier layer 292 is arranged on the side walls 282, 284 and the bottom 286 of the interconnect opening 280, which are defined by the ILD layer 270, the CESL 265 and the copper interconnect 230.The diffusion barrier layer 292, the first barrier layer 294A, the second barrier layer 294B, and the copper bulk layer 296 are each similar to the diffusion barrier layer 232, the first barrier layer 234A, the second barrier layer 234B, and the copper bulk layer 236, all of which have been previously described. Alternatively, the interconnect 290 is configured differently from the copper interconnect 230 and has different layers and / or materials. The present disclosure thus provides for various material configurations and / or compositions of the interconnect 290. The manufacturing process can then proceed with the fabrication of additional sections of the MLI feature.

[0036] With reference to Fig. 8 is Fig. 8 A fragmentary diagrammatic view of an IC device 500, in part or in whole, according to various aspects of the present disclosure. The IC device 500 may be contained in a microprocessor, a memory, and / or another integrated circuit device.In some implementations, the IC device 500 is part of an IC chip, a system-on-chip (SoC), or a part thereof, which incorporates various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor transistors (CMOS transistors), bipolar junction transistors (BJTs), laterally diffused MOS transistors (LDMOS transistors), high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. The transistors can be planar transistors or multi-gate transistors, such as fin-like FETs (FinFETs). Fig. For the sake of clarity, paragraph 8 has been simplified to better illustrate the inventive concepts of the present disclosure. Additional features may be added to the IC device 500, and some of the features described below may be replaced, modified, or removed in other embodiments of the IC device 500.

[0037] The IC device 500 comprises the device substrate 206, which has a substrate (wafer) 510. In the illustrated embodiment, the substrate 510 comprises silicon. Alternatively or additionally, the substrate 510 comprises another elemental semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. Alternatively, substrate 510 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator substrate (SOI substrate), a silicon germanium-on-insulator substrate (SGOI substrate), or a germanium-on-insulator substrate (GOI substrate).Semiconductor-on-insulator substrates can be fabricated using separation by oxygen implementation (SIMOX), wafer bonding, and / or other suitable methods. The substrate 510 can have doped regions formed by an ion implantation process, a diffusion process, and / or another suitable doping process, depending on the design requirements of the IC device 500. In some embodiments, the substrate 510 has p-doped regions (for example, p-wells) doped with p-dopants such as boron, indium, another p-dopant, or combinations thereof. In some embodiments, the substrate 510 has n-doped regions (for example, n-wells) doped with n-dopants such as phosphorus, arsenic, another n-dopant, or combinations thereof.In some embodiments, the substrate 510 has doped regions formed with a combination of p-type and n-type dopants. The various doped regions can be formed directly on and / or in the substrate 510, for example by providing a p-well structure, an n-well structure, a double-well structure, a raised structure, or combinations thereof.

[0038] Insulation features can be formed on and / or within the substrate 510 to isolate various regions, such as device regions, of the IC device 500. For example, insulation features define active device regions and / or passive device regions and electrically isolate them from one another. The insulation features comprise silicon oxide, silicon nitride, silicon oxynitride, another suitable insulating material (for example, including silicon, oxygen, nitrogen, carbon, or another suitable insulating component), or combinations thereof. The insulation features can have different structures, such as shallow trench isolation structures (STI structures), deep trench isolation structures (DTI structures), and / or local oxidation of silicon structures (LOCOS structures).In some embodiments, the insulation features are formed by etching a trench (or trenches) in the substrate 510 and filling the trench with insulating material (for example, using a CVD process or a spin-on-glass process). A CMP process can be performed to remove excess insulating material and / or to planarize an upper surface of the insulation features. In some embodiments, the insulation features can be formed by depositing an insulating material over the substrate 510 after forming fin structures (in some embodiments such that the insulating material layer fills gaps (trenches) between the fin structures) and back-etching the insulating material layer.In some embodiments, the insulating features have a multilayer structure that fills the grooves, such as a bulk dielectric layer arranged over a liner dielectric layer, wherein the bulk dielectric layer and the liner dielectric layer have materials depending on the design requirements (for example, a bulk dielectric layer having silicon nitride arranged over a liner dielectric layer having thermal oxide). In some embodiments, the insulating features have a dielectric layer arranged over a doped liner layer (which has, for example, BSG or PSG).

[0039] The device substrate 206 further comprises various gate structures arranged over the substrate 510, such as gate structure 520A, gate structure 520B, and gate structure 520C. Gate structures 520A-520C each engage a respective channel region defined between a respective source region and a respective drain region, allowing current to flow between the respective source / drain regions during operation. In some embodiments, gate structures 520A-520C are formed over a fin structure, such that each gate structure 520A-520C wraps around a section of the fin structure and incorporates a respective source region and a respective drain region (collectively referred to as source / drain regions) of the fin structure. The gate structures 520A-520C each feature a metal gate stack (MG stack), such as a metal gate stack 522.The metal gate stacks 522 are formed by deposition processes, lithography processes, etching processes, other suitable processes, or combinations thereof. The metal gate stacks 522 are manufactured according to a gate-last process, a gate-first process, or a hybrid gate-last / gate-first process. In gate-last process embodiments, the gate structures 520A-520C have dummy gate stacks that are subsequently replaced by the metal gate stacks 522. The dummy gate stacks have, for example, an interface layer (comprising, for example, silicon oxide) and a dummy gate electrode layer (comprising, for example, polysilicon). In such embodiments, the dummy gate electrode layer is removed, forming openings (trenches) that are subsequently filled with the metal gate stacks 522.

[0040] The metal gate stacks 522 are configured to achieve desired functionality according to the design requirements of the IC device 500. In some embodiments, the metal gate stacks 522 comprise a gate dielectric (for example, a gate dielectric layer) and a gate electrode (for example, an exit layer and a conductive bulk layer). The metal gate stacks 522 can have numerous other layers, for example, cover layers, interface layers, diffusion layers, barrier layers, hard mask layers, or combinations thereof. In some embodiments, the gate dielectric layer is arranged over an interface layer (which, for example, comprises a dielectric material such as silicon oxide), and the gate electrode is arranged over the gate dielectric layer.The gate dielectric layer comprises a dielectric material, such as silicon dioxide, a high-k dielectric material, another suitable dielectric material, or a combination thereof. Examples of high-k dielectric materials include hafnium dioxide (HfO₂), HfSiO₂, HfSiON₄, HfTaO₂, HfTiO₂, HfZrO₂, zirconium oxide, aluminum oxide, a hafnium dioxide-aluminum oxide alloy (HfO₂-Al₂O₃ alloy), other suitable high-k dielectric materials, or combinations thereof. High-k dielectric material generally refers to dielectric materials that have a high dielectric constant (k-value) relative to the dielectric constant of silicon dioxide (k ≈ 3.9). For example, a high-k dielectric material has a dielectric constant greater than approximately 3.9. In some embodiments, the gate dielectric layer is a high-k dielectric layer.The gate electrode comprises a conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, molybdenum, cobalt, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, another conductive material, or combinations thereof. In some embodiments, the exit work layer is a conductive layer tuned to exhibit a desired work function (such as an n-work function or a p-work function), and the conductive bulk layer is a conductive layer formed above the exit work layer. In some embodiments, the exit work layer comprises n-work function materials, such as Ti, silver, manganese, zirconium, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, other suitable n-work function materials, or combinations thereof.In some embodiments, the exit layer comprises a p-exit material, such as ruthenium, molybdenum (Mo), aluminum (Al), titanium nitride (TiN), tantalum (TaN), tungsten nitride (WN), zirconia (ZrSi2), molybdenum nitride (MoSi2), tungsten nitride (TaSi2), tungsten nitride (NiSi2), tungsten nitride (WN), other suitable p-exit materials, or combinations thereof. The conductive bulk layer (or filler layer) comprises a suitable conductive material, such as aluminum (Al), tungsten (W), and / or copper (Cu). The conductive bulk layer may additionally or concurrently comprise polysilicon, titanium (Ti), tungsten nitride (Ta), metal alloys, other suitable materials, or combinations thereof.

[0041] The gate structures 520A-520C further comprise gate spacers 236, which are arranged adjacent to the metal gate stacks 522 (for example, along their sidewalls). The gate spacers 236 are formed by any suitable process and comprise a dielectric material. The dielectric material can be silicon, oxygen, carbon, nitrogen, any other suitable material, or combinations thereof (for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide). For example, in the illustrated embodiment, a dielectric layer comprising silicon and nitrogen, such as a silicon nitride layer, can be deposited over the substrate 510 and subsequently anisotropically etched to form the gate spacers 236.In some embodiments, the gate spacers 236 have a multilayer structure, such as a first dielectric layer comprising silicon nitride and a second dielectric layer comprising silicon oxide. In some embodiments, more than one group of spacers, such as gasket spacers, offset spacers, sacrificial spacers, dummy spacers, and / or principal spacers, are formed adjacent to the metal gate stacks 522. In such embodiments, the different groups of spacers may comprise materials exhibiting different etch rates.For example, a first dielectric layer comprising silicon and oxygen (e.g., silicon oxide) can be deposited over the substrate 510 and subsequently anisotropically etched to form a first spacer group adjacent to the metal gate stacks 522 (or the dummy metal gate stacks in some embodiments). A second dielectric layer comprising silicon and nitrogen (e.g., silicon nitride) can then be deposited over the substrate 510 and subsequently anisotropically etched to form a second spacer group adjacent to the first spacer group. Implantation, diffusion, and / or annealing processes can be performed to form lightly doped source and drain features (LDD features) and / or heavily doped source and drain features (HDD features) in the substrate 510 before and / or after the formation of the gate spacers 236, depending on the design requirements of the IC device 500.

[0042] Epitaxial source features and epitaxial drain features (referred to as epitaxial source / drain features), such as epitaxial source / drain features 530, are arranged in the source / drain regions of the substrate 510. The gate structure 520B is located between the epitaxial source / drain features 530, thus defining a channel region between the epitaxial source / drain features 530. In some embodiments, the gate structure 520B and the epitaxial source / drain features 530 form a section of a transistor of the IC device 500. In some embodiments, a semiconductor material is grown epitaxially onto and / or from the substrate 510 to form the epitaxial source / drain features 530 over the source / drain regions of the substrate 510.In some embodiments, an etching process is performed on the source / drain regions of the substrate 510 to form source / drain recesses, with the epitaxial source / drain features 530 being grown to fill the source / drain recesses. In some embodiments where the substrate 510 represents a section of a fin structure, the epitaxial source / drain features 530 wrap around source / drain regions of the fin structure and / or are arranged in source / drain recesses of the fin structure, depending on the design requirements of the IC device 500. An epitaxy process can implement CVD deposition techniques (for example, vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), low-pressure carbon dioxide (LPCVD), and / or peroxide electron beam ionization (PECVD)), molecular beam epitaxy, or suitable SEG processes, or combinations thereof. The epitaxy process can utilize gaseous and / or liquid precursors that interact with the composition of substrate 510.The epitaxial source / drain features 530 are doped with n-type and / or p-type dopants. In some embodiments, the epitaxial source / drain features 530 are epitaxial layers comprising silicon and / or carbon, wherein the silicon-containing epitaxial layers or the silicon-carbon-containing epitaxial layers are doped with phosphorus, another n-type dopant, or combinations thereof. In some embodiments, the epitaxial source / drain features 530 are epitaxial layers comprising silicon and germanium, wherein the silicon-germanium-containing epitaxial layers are doped with boron, another p-type dopant, or combinations thereof. In some embodiments, the epitaxial source / drain features 530 comprise materials and / or dopants that achieve a desired tensile and / or compressive stress in the channel regions.In some embodiments, the epitaxial source / drain features 530 are doped during deposition by adding impurities to a source material of the epitaxial process. In some embodiments, the epitaxial source / drain features 530 are doped by an ion implantation process following a deposition process. In some embodiments, annealing processes are performed to activate dopants in the epitaxial source / drain features 530 and / or other source / drain regions of the IC device 500 (for example, the HDD regions and / or the LDD regions).

[0043] The MLI feature 400 is arranged above the device substrate 206 and comprises one or more ILD layers and / or CESLs. In Fig.Figure 8 of MLI feature 400 includes an ILD layer 552 (ILD-0) arranged above substrate 510, an ILD layer 554 (ILD-1) arranged above ILD layer 552, an ILD layer 556 (ILD-2) arranged above ILD layer 554, and an ILD layer 558 (ILD-3) arranged above ILD layer 556. MLI feature 400 further includes a CESL 562 arranged between ILD layer 552 and ILD layer 554, a CESL 564 arranged between ILD layer 554 and ILD layer 556, and a CESL 566 arranged between ILD layer 556 and ILD layer 558.A device-level contact 570, a device-level contact 572, a device-level contact 574, a via 580, a via 582, a via 584, a conductive trace 590, a conductive trace 592, and a conductive trace 594 are arranged in the ILD layers 552–558 and the CESLs 562–566 to form interconnect structures. One or more of the ILD layers 552–558 are configured and fabricated similarly to the ILD layer 210 and / or the ILD layer 270, which were previously described in detail. One or more of the CESLs 562-566 are configured and manufactured similarly to the CESL 265, the nitrogen-treated CESL 250, the CESL 260, the CESL 262 and / or the CESL 212, which were previously described in detail.One or more of the device-level contacts 570-574, vias 580-584, and conductive lines 590-594 are configured and manufactured similarly to the copper interconnect 230 and / or the interconnect 290. For example, in some embodiments, the vias 580-584 are copper interconnects, such as the copper interconnect 230, and the CESL 566 is configured similarly to the CESL 265 and features the nitrogen-treated CESL 250. Accordingly, gap formation at interfaces between the vias 580-584 and the CESL 566 and / or respective conductive lines 590-594 is limited and / or prevented during the fabrication of the MLI feature 400. The IC device 500, such as a transistor of the IC device 500, exhibits improved performance.

[0044] The device-level contacts 570-574 (also referred to as local interconnects or local contacts) couple IC device features electrically and / or physically to other conductive features of the MLI feature 400. For example, device-level contact 570 is a metal-poly contact (MP contact), which generally refers to a contact with a gate structure, such as a poly-gate structure or a metal-gate structure. In the illustrated embodiment, device-level contact 570 is arranged on the gate structure 520B (in particular, the metal-gate stack 522), such that device-level contact 570 connects the gate structure 520B to the via 580.Continuing the example, device-level contact 572 and device-level contact 574 are metal-to-device contacts (MD contacts), which generally relate to contacts with a conductive region of the IC device 500, such as source / drain regions. For example, device-level contact 572 and device-level contact 574 are arranged on respective epitaxial source / drain features 530, such that device-level contact 572 and device-level contact 574 connect the epitaxial source / drain features 530 to vias 582 and 584, respectively. Vias 580-584 couple conductive features of the MLI feature 400 electrically and / or physically.For example, the via 580 is arranged on the device-level contact 570, such that the via 580 connects the device-level contact 570 to the conductive line 590; the via 582 is arranged on the device-level contact 572, such that the via 582 connects the device-level contact 572 to the conductive line 592; and the via 584 is arranged on the device-level contact 574, such that the via 584 connects the device-level contact 574 to the conductive line 594.

[0045] The present disclosure provides for many different embodiments. Interconnect structures featuring a reduced accumulation of copper vacancies along interfaces between CESLs and interconnects, together with methods for fabricating such interconnect structures, are disclosed herein. An exemplary interconnect structure of a multilayer interconnect feature of an integrated circuit device comprises a first interlayer dielectric layer (ILD layer), a second ILD layer arranged above the first ILD layer, a first copper interconnect arranged within the first ILD layer, and a second copper interconnect arranged within the second ILD layer. An aluminum nitride contact etch stop layer (aluminum nitride CESL) is arranged between a portion of the first copper interconnect and the second ILD layer, and between the first ILD layer and the second ILD layer.The surface nitrogen concentration at an interface between the aluminum nitride CESL and the first copper interconnect is approximately 20 at% or more. The second copper interconnect extends through the aluminum nitride CESL to physically contact the first copper interconnect. In some embodiments, the density of the aluminum nitride CESL is approximately 2.70 g / cm³. 3 up to approximately 2.80 g / cm³ 3 In some embodiments, the dielectric constant of the aluminum nitride CESL is approximately 7.2 to approximately 7.4. In some embodiments, the aluminum nitride CESL has a thickness of approximately 3 nm or less. In some embodiments, the nitrogen concentration of the aluminum nitride CESL is approximately 42 atomic percent (at%) to approximately 48 at%.

[0046] In some embodiments, the first copper interconnect comprises a copper bulk layer and a cobalt nitride cover layer positioned between the aluminum nitride CESL and the copper bulk layer. A first nitrogen concentration in the aluminum nitride CESL is higher than a second nitrogen concentration in the cobalt nitride cover layer. In some embodiments, the first copper interconnect further comprises a tantalum nitride diffusion barrier layer positioned between the copper bulk layer and the first ILD layer. A third nitrogen concentration in the tantalum nitride diffusion barrier layer is higher than the second nitrogen concentration in the cobalt nitride cover layer. The interconnect structure further comprises an oxygen-doped silicon carbide CESL positioned above the aluminum nitride CESL and an aluminum oxide CESL positioned above the oxygen-doped silicon carbide CESL.The second copper interconnect extends through the oxygen-doped silicon carbide CESL and the aluminum oxide CESL.

[0047] Another interconnect structure of a multilayer interconnect feature of an integrated circuit device has a first interconnect arranged within a dielectric layer. The first interconnect comprises a copper bulk layer, a first metal nitride layer arranged along the sidewalls of the copper bulk layer, and a second metal nitride layer arranged along a top surface of the copper bulk layer. The first metal nitride layer is located between the copper bulk layer and the dielectric layer. The first metal nitride layer contains a first metal, and the second metal nitride layer contains a second metal. The interconnect structure further includes a third metal nitride layer arranged above the second metal nitride layer. The third metal nitride layer contains a third metal. The third metal, the second metal, and the first metal are different.The interconnect structure further comprises a second interconnect located in the dielectric layer and extending through the third metal nitride layer to the first interconnect. In some embodiments, the first metal is tantalum, the second metal is cobalt, and the third metal is aluminum. In some embodiments, the first metal nitride layer has a first nitrogen concentration, the second metal nitride layer has a second nitrogen concentration, and the third metal nitride layer has a third nitrogen concentration. The first, second, and third nitrogen concentrations are different. In some embodiments, the third nitrogen concentration is higher than both the first and second nitrogen concentrations. In some embodiments, the first nitrogen concentration is higher than the second nitrogen concentration.In some embodiments, the density of the third metal nitride layer is approximately 2.70 g / cm³. 3 up to approximately 2.80 g / cm³ 3 In some embodiments, the dielectric constant of the third metal nitride layer is approximately 7.2 to approximately 7.4. In some embodiments, the interconnect structure further comprises a metal oxide layer arranged above the third metal nitride layer. The metal oxide layer comprises the third metal, and the second interconnect further extends through the metal oxide layer. The first interconnect further comprises a metal layer arranged between the first metal nitride layer and the dielectric layer, the metal layer comprising the second metal.

[0048] An exemplary method for fabricating an interconnect structure involves forming a copper interconnect within an interlayer dielectric (ILD) layer and depositing a metal nitride CESL over the copper interconnect and the ILD layer. An interface region between the metal nitride CESL and the copper interconnect exhibits an initial nitrogen concentration and / or an initial number of nitrogen-nitrogen bonds. The method further includes performing a nitrogen plasma treatment to modify the interface region between the metal nitride CESL and the copper interconnect. The nitrogen plasma treatment increases the initial nitrogen concentration to a second nitrogen concentration and / or the initial number of nitrogen-nitrogen bonds to a second number of nitrogen-nitrogen bonds, both of which minimize the accumulation of copper vacancies in the interface region.

[0049] An exemplary method comprises forming an interconnect opening in a first dielectric layer to expose an underlying conductive feature. The interconnect opening has first sidewalls defined by the first dielectric layer and a first bottom surface defined by the underlying conductive feature. The method further comprises forming a first metal interconnect in the interconnect opening, which involves forming a diffusion barrier layer along the first sidewalls defined by the first dielectric layer and the first bottom surface defined by the underlying conductive feature, forming a metal bulk layer over the diffusion barrier layer, and forming a metal nitride cover layer over the metal bulk layer. The diffusion barrier layer partially fills the interconnect opening, and the metal bulk layer fills the remainder of the interconnect opening.The method further comprises performing a deposition process to form a metal nitride etch stop layer (metal nitride ESL) over the first metal interconnect and the first dielectric layer. An interface is defined between the metal nitride ESL and the metal nitride cover layer of the first metal interconnect. The method further comprises performing a nitrogen plasma treatment on the metal nitride ESL to increase the nitrogen-nitrogen bond along the interface defined between the metal nitride ESL and the metal nitride cover layer of the first metal interconnect. The method further comprises forming a second dielectric layer over the metal nitride ESL and forming a second interconnect opening in the second dielectric layer to expose the first metal interconnect.The second interconnect opening has second sidewalls defined by the second dielectric layer and the metal nitride ESL, and a second bottom surface defined by the first metal interconnect. The method further includes forming a second metal interconnect in the second interconnect opening.

[0050] In some embodiments, the metal nitride ESL comprises aluminum, and the method further comprises tuning the parameters of the nitrogen plasma treatment to increase the number of Al-N bonds in the metal nitride ESL along the interface. In some embodiments, the metal nitride cover layer comprises cobalt, and the method further comprises tuning the parameters of the nitrogen plasma treatment to increase the number of Co-N bonds in the metal nitride cover layer along the interface. In some embodiments, performing the nitrogen plasma treatment includes generating an N₂ plasma. In some embodiments, the metal bulk layer comprises a first metal, the metal nitride cover layer comprises a second metal, and the metal nitride ESL comprises a third metal, wherein the first metal, the second metal, and the third metal are different.In some embodiments, the diffusion barrier layer comprises a metal nitride diffusion barrier layer containing a fourth metal. In some embodiments, the fourth metal differs from the first, second, and third metals.

Claims

[1] Interconnect structure of a multilayer interconnect feature of an integrated circuit device, wherein the interconnect structure comprises: a first interlayer dielectric layer, ILD layer (210); a second ILD layer (270) arranged above the first ILD layer (210); a first copper interconnect (230) located in the first ILD layer (210); a second copper interconnect (290) arranged in the second ILD layer (270); and an aluminum nitride contact etch stop layer, aluminum nitride-CESL (250), arranged between a section of the first copper interconnect (230) and the second ILD layer (270) and between the first ILD layer (210) and the second ILD layer (270), wherein the second copper interconnect (290) extends through the aluminum nitride-CESL (250) to physically contact the first copper interconnect (230), and wherein a surface nitrogen concentration at an interface between the aluminum nitride-CESL (250) and the first copper interconnect (230) is approximately 20 at% or higher, which further exhibits the following: an oxygen-doped silicon carbide CESL (260) arranged above the aluminum nitride CESL (250); and an aluminum oxide CESL (262) arranged above the oxygen-doped silicon carbide CESL (260), wherein the second copper interconnect (290) extends through the oxygen-doped silicon carbide CESL (260) and the aluminum oxide CESL (262). [2] Interconnect structure according to claim 1, wherein the density of the aluminium nitride CESL (250) is approximately 2.70 g / cm³ 3 up to approximately 2.80 g / cm³ 3 amounts. [3] Interconnect structure according to claim 1 or 2, wherein the dielectric constant of the aluminium nitride CESL (250) is approximately 7.2 to approximately 7.

4. [4] Interconnect structure according to any of the preceding claims, wherein the aluminium nitride CESL (250) has a thickness of approximately 3 nm or less. [5] Interconnect structure according to one of the preceding claims, wherein the nitrogen concentration of the aluminium nitride CESL (250) is approximately 42 atomic percent, at%, to approximately 48 at%. [6] Interconnect structure according to one of the preceding claims, wherein the first copper interconnect (230) comprises a copper bulk layer (236) and a cobalt nitride cover layer (240) arranged between the aluminum nitride CESL (250) and the copper bulk layer (236), wherein a first nitrogen concentration of the aluminum nitride CESL (250) is higher than a second nitrogen concentration of the cobalt nitride cover layer (240). [7] Interconnect structure according to claim 6, wherein the first copper interconnect further comprises a tantalum nitride diffusion barrier layer (234A) arranged between the copper bulk layer (236) and the first ILD layer (210), wherein a third nitrogen concentration of the tantalum nitride diffusion barrier layer (234A) is higher than the second nitrogen concentration of the cobalt nitride cover layer (240). [8] Interconnect structure of a multilayer interconnect feature of an integrated circuit device, wherein the interconnect structure comprises: a first interconnect arranged in a two-part dielectric layer (210, 270), wherein the first interconnect has the following: a copper bulk layer (236), a first metal nitride layer (234A) arranged along side walls of the copper bulk layer (236), wherein the first metal nitride layer (234A) is arranged between the copper bulk layer (236) and the two-part dielectric layer (210), a second metal nitride layer (240) arranged along a top side of the copper bulk layer (236), wherein the first metal nitride layer (234A) comprises a first metal and the second metal nitride layer (240) comprises a second metal, and a third metal nitride layer arranged above the second metal nitride layer (240), wherein the third metal nitride layer comprises a third metal, the third metal being different from the second metal and the first metal; and a metal layer (234B) arranged between the first metal nitride layer (234A) and the two-part dielectric layer (210, 270), wherein the metal layer (234B) comprises the second metal; a second interconnect (290) which is arranged in the two-part dielectric layer (210, 270) and extends through the third metal nitride layer to the first interconnect (230). [9] Interconnect structure according to claim 8, wherein the first metal is tantalum, the second metal is cobalt and the third metal is aluminium. [10] Interconnect structure according to claim 8 or 9, wherein: the first metal nitride layer (234A) has a first nitrogen concentration, the second metal nitride layer (240) has a second nitrogen concentration, and the third metal nitride layer (250) has a third nitrogen concentration; and The first nitrogen concentration, the second nitrogen concentration, and the third nitrogen concentration are different. [11] Interconnect structure according to claim 10, wherein the third nitrogen concentration is higher than the first nitrogen concentration and the second nitrogen concentration. [12] Interconnect structure according to claim 11, wherein the first nitrogen concentration is higher than the second nitrogen concentration. [13] Interconnect structure according to any one of the preceding claims 8 to 12, further comprising a metal oxide layer (260) arranged over the third metal nitride layer (250), wherein the metal oxide layer (260) comprises the third metal and the second interconnect (290) further extends through the metal oxide layer (260). [14] Interconnect structure according to any one of the preceding claims 8 to 13, wherein: a density of the third metal nitride layer (250) approximately 2.70 g / cm³ 3 up to approximately 2.80 g / cm³ 3 is; and a dielectric constant of the third metal nitride layer (250) is approximately 7.2 to approximately 7.

4. [15] Procedure (100) comprising: Forming a copper interconnect (230) in an interlayer dielectric layer, ILD layer (210); Deposition of a metal nitride contact etch stop layer, metal nitride CESL (250), over the copper interconnect (230) and the ILD layer (210), wherein an interface region between the metal nitride CESL (250) and the copper interconnect (230) has a first surface nitrogen concentration; and Performing a nitrogen plasma treatment to modify the interface region between the metal nitride CESL (250) and the copper interconnect (230), wherein the nitrogen plasma treatment increases the first surface nitrogen concentration to a second surface nitrogen concentration that minimizes the accumulation of copper vacancies in the interface region, wherein, after performing the nitrogen plasma treatment, the procedure (100) further comprises the following: Formation of an oxide-based CESL (260) over the metal nitride CESL (250); Forming a metal oxide CESL (262) over the oxide-based CESL (260), wherein the metal oxide CESL (262) and the metal nitride CESL (250) contain the same metal; Forming a second ILD layer (270) over the metal oxide CESL (262); and Forming a metal interconnect (290) in the second ILD layer (270), wherein the metal interconnect (290) extends through the second ILD layer (270), the metal oxide CESL (262), the oxide-based CESL (260) and the metal nitride CESL (250) to the copper interconnect. [16] Method (100) according to claim 15, wherein performing the nitrogen plasma treatment comprises exposing the metal nitride CESL (250) to a nitrogen-containing plasma having a nitrogen concentration of approximately 70% to approximately 90%. [17] Method (100) according to claim 15 or 16, wherein performing the nitrogen plasma treatment comprises exposing the metal nitride CESL (250) to a nitrogen-containing plasma for approximately 20 seconds to approximately 30 seconds.

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