LDO circuit

Abstract

The LDO circuit comprises a first operational amplifier, a first transistor, a current mirroring unit, a sampling feedback unit, a first adjusting unit and a second adjusting unit, the first transistor generates a first current based on driving of the first operational amplifier, the current mirroring unit performs mirroring on the first current to generate a second current, and the sampling feedback unit performs sampling feedback on the second current; the sampling feedback unit generates feedback voltage based on the second current; the first adjusting unit samples the first current and the second current and adjusts the voltage of the control end of the first transistor based on the sampled current, and the second adjusting unit adjusts the voltage of the current control end based on the second reference voltage and the feedback voltage. According to the LDO circuit, the voltage of the output end of the first operational amplifier in the dropout region is limited through the first adjusting unit, and overshoot is optimized; a second adjusting unit is introduced, one-stage drive stage pull-down current is increased, and under the condition that the pull-down current of a first transistor is limited, the pull-down current of a current control end is ensured, and undershoot is optimized.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to an LDO circuit. Background Technology

[0002] like Figure 1 The diagram shows a typical P-type LDO circuit. When the LDO circuit operates in the dropout region, due to its abnormal operating point, the main loop cannot be established, and the main loop is in an open-loop state. The voltage at node EA_OUT is very high. When a linetran occurs (a rapid, step change in the input voltage VIN), if the input voltage VIN jumps from a very low voltage to a higher value, the |VGS| of the power transistor M3 increases, and the output voltage VOUT increases. This will result in a large overshoot. The output voltage VOUT will only decrease after the LDO circuit loop is established and the voltage at node EA_OUT is pulled down. Conversely, if the input voltage VIN jumps from a very high voltage to a lower value, the |VGS| of the power transistor M3 decreases, and the output voltage VOUT decreases. This will result in a large undershoot.

[0003] To optimize linetran during dropout and reduce overshoot or undershoot, many circuit designers introduce new loops or disable the main loop when the LDO circuit is operating in dropout mode. The downside is that the dropout voltage is sacrificed, and the power transistor size needs to be increased to compensate for it.

[0004] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide an LDO circuit that can reduce overshoot and undershoot during step changes in input voltage, without increasing the size of the power transistor and without sacrificing the dropout voltage.

[0006] In order to achieve the above object, a technical solution of one embodiment of the present application is provided as follows: A LDO circuit, comprising: a first operational amplifier, a first transistor, a current mirror unit and a sampling feedback unit, the output end of the first operational amplifier is connected with the control end of the first transistor, the first transistor generates a first current based on the driving of the first operational amplifier, the current mirror unit forms a current control end with the second end of the first transistor, the current mirror unit is connected with an input voltage at the same time to mirror the first current to generate a second current, the sampling feedback unit is connected with the current mirror unit to form a voltage output end and generates a feedback voltage based on the second current, the first input end of the first operational amplifier is used to receive a first reference voltage, and the second input end of the first operational amplifier is used to receive the feedback voltage.

[0007] The LDO circuit further comprises a first adjusting unit and a second adjusting unit, the first adjusting unit is connected with the current control end, the input voltage, the voltage output end and the control end of the first transistor to sample the first current and the second current respectively and adjust the voltage of the control end of the first transistor based on the corresponding current obtained by sampling, and the second adjusting unit is connected with the second reference voltage, the feedback voltage and the current control end to adjust the voltage of the current control end based on the second reference voltage and the feedback voltage.

[0008] In one or more embodiments of the present application, the current mirror unit comprises a second transistor and a third transistor, the first end of the second transistor and the first end of the third transistor are connected with the input voltage, the control end of the second transistor is connected with the second end of the second transistor, the second end of the first transistor, the second adjusting unit and the control end of the third transistor to form the current control end, and the second end of the third transistor is connected with the sampling feedback unit to form the voltage output end.

[0009] In one or more embodiments of the present application, the first adjusting unit comprises a first adjusting tube, a first sampling unit and a second sampling unit, the first sampling unit is connected with the current control end and the input voltage to sample the first current to obtain a first sampling current, the second sampling unit is connected with the current control end, the input voltage and the voltage output end to sample the second current to obtain a second sampling current, the control end of the first adjusting tube is connected with the first sampling unit and the second sampling unit, the second end of the first adjusting tube is connected with the control end of the first transistor, the first end of the first adjusting tube is connected with a reference voltage, and the first adjusting tube adjusts the voltage of the control end of the first transistor based on the size between the first sampling current and the second sampling current.

[0010] In one or more embodiments of the present application, the first sampling unit comprises a fourth transistor and a first clamping unit, a first end of the fourth transistor is configured to receive the input voltage, a control end of the fourth transistor is connected to the current control end, a second end of the fourth transistor is connected to the first clamping unit, the first clamping unit is connected to the current control end and the control end of the first regulating tube at the same time, and the first clamping unit is configured to clamp the voltage of the second end of the fourth transistor based on the voltage of the current control end to generate the first sampling current on the fourth transistor and inject the first sampling current into the control end of the first regulating tube.

[0011] In one or more embodiments of the present application, the second sampling unit comprises a fifth transistor, a second clamping unit and a current mirror module, a first end of the fifth transistor is configured to receive the input voltage, a control end of the fifth transistor is connected to the current control end, a second end of the fifth transistor is connected to the second clamping unit, the second clamping unit is connected to the voltage output end and the current mirror module at the same time, and the second clamping unit is configured to clamp the voltage of the second end of the fifth transistor based on the output voltage of the voltage output end to generate the second sampling current on the fifth transistor and deliver the second sampling current to the current mirror module, and the current mirror module is connected to the control end of the first regulating tube at the same time to adjust the voltage of the control end of the first regulating tube.

[0012] In one or more embodiments of the present application, the first clamping unit comprises a first current mirror and a second current source, a first end of the first current mirror is connected to the second end of the fourth transistor, a second end of the first current mirror is connected to the control end of the first regulating tube, a third end of the first current mirror is connected to the current control end, a fourth end of the first current mirror is connected to a first end of the second current source, and a second end of the second current source is connected to the reference voltage.

[0013] In one or more embodiments of the present application, the second clamping unit comprises a second current mirror and a third current source, a first end of the second current mirror is connected to the second end of the fifth transistor, a second end of the second current mirror is connected to the current mirror module, a third end of the second current mirror is connected to the voltage output end, a fourth end of the second current mirror is connected to a first end of the third current source, and a second end of the third current source is connected to the reference voltage.

[0014] In one or more embodiments of the present application, the first regulating unit further comprises a first current source, a first end of the first current source is connected to the control end of the first regulating tube, and a second end of the first current source is connected to the reference voltage.

[0015] In one or more embodiments of the present application, the second regulating unit comprises a second regulating transistor and a second operational amplifier, a first input end of the second operational amplifier is configured to receive a second reference voltage, a second input end of the second operational amplifier is configured to receive a feedback voltage, an output end of the second operational amplifier is connected to a control end of the second regulating transistor, a second end of the second regulating transistor is connected to the current control end, a first end of the second regulating transistor is connected to the reference voltage, and the second regulating transistor adjusts the voltage of the current control end based on the driving of the second operational amplifier.

[0016] In one or more embodiments of the present application, the LDO circuit further comprises an RC filter circuit connected to the control end of the first transistor; and / or

[0017] The LDO circuit further comprises a resistance unit connected to the input voltage and the current control end.

[0018] Compared with the prior art, the LDO circuit of the present application limits the voltage of the output end of the first operational amplifier when the LDO circuit works in the dropout region by introducing the first regulating unit, accelerates the establishment speed when the input voltage occurs from low to high, and optimizes the overshoot; meanwhile, the second regulating unit is introduced to increase the pull-down current of the first driving stage, in the case that the pull-down current of the first transistor is limited when the LDO circuit works in the dropout region, the pull-down current of the current control end is ensured, the dropout voltage is not sacrificed, and the undershoot when the input voltage occurs from high to low is optimized. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments described in the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0020] Figure 1 It is a circuit schematic diagram of a LDO circuit in the prior art.

[0021] Figure 2 It is a circuit schematic diagram of a LDO circuit in an embodiment of the present application.

[0022] Figure 3 It is a circuit schematic diagram of a second regulating unit in an embodiment of the present application.

[0023] Figure 4 It is a voltage waveform diagram of a LDO circuit in the prior art.

[0024] Figure 5A voltage waveform diagram for another LDO circuit in the prior art.

[0025] Figure 6 A voltage waveform diagram for an LDO circuit in an embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to make the technical solutions in the present disclosure better understood by the person skilled in the art, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by the person skilled in the art without creative labor should fall within the scope of protection of the present disclosure.

[0027] In the specification, “coupling” or “connection” or “connection” includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium, which can have a parasitic inductance or a parasitic capacitance; indirect connection can also include a connection through other active devices or passive devices on the basis of achieving the same or similar functional purposes, such as a connection through circuits or components such as switches, follower circuits, etc. In addition, in the invention, words such as “first”, “second” and the like are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply a certain actual relationship, quantity or order between the technical features.

[0028] In the detailed description of the specification, reference is made to the drawings forming a part thereof, in which the same reference numerals refer to the same parts throughout, and in which an exemplary embodiment can be shown by way of example. It should be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be regarded as limiting.

[0029] Various operations in the specification can be described in sequential order in a manner that can most conveniently be related to the order of explanation of the subject matter. However, the order of description does not imply that these operations must be performed in the order they are presented. Specifically, these operations can be performed in an order other than the order presented. The described operations can be performed in a different order than the order described. Various additional operations can be performed and / or described operations can be omitted in additional embodiments.

[0030] For the purposes of the present disclosure, the phrase “A and / or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0031] Various components and devices may be referred to or shown in the singular (e.g., “transistor”, “transistor”, “switch”, etc.) in this document, but only for the convenience of discussion, and any element referred to in the singular may include multiple such elements as taught herein.

[0032] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used with respect to embodiments of this disclosure are synonymous.

[0033] like Figure 2 As shown, an LDO circuit in one embodiment of the present invention includes: a first operational amplifier op1, a first transistor M1, a current mirror unit, a sampling feedback unit 10, a first adjustment unit 20, and a second adjustment unit 30.

[0034] The output terminal EA_OUT of the first operational amplifier op1 is connected to the control terminal of the first transistor M1. The first transistor M1 generates a first current I1 based on the drive of the first operational amplifier op1. A current mirror unit forms a current control terminal VG with the second terminal of the first transistor M1. The current mirror unit is also connected to the input voltage VIN to mirror the first current I1 to generate a second current I2. The sampling feedback unit 10 is connected to the current mirror unit to form a voltage output terminal for generating an output voltage VOUT and generates a feedback voltage VFB based on the second current I2. The first input terminal of the first operational amplifier op1 is used to receive a first reference voltage VREF1, and the second input terminal of the first operational amplifier op1 is used to receive the feedback voltage VFB. In one embodiment, the first input terminal of the first operational amplifier op1 is a positive input terminal, and the second input terminal of the first operational amplifier op1 is a negative input terminal. In other embodiments, the first input terminal of the first operational amplifier op1 is a negative input terminal, and the second input terminal of the first operational amplifier op1 is a positive input terminal.

[0035] like Figure 2 As shown, the first adjustment unit 20 is connected to the current control terminal VG, the input voltage VIN, the voltage output terminal, and the control terminal of the first transistor M1 to sample the first current I1 and the second current I2 respectively, and adjust the voltage of the control terminal of the first transistor M1 based on the corresponding current obtained by sampling. The second adjustment unit 30 is connected to the second reference voltage VREF2, the feedback voltage VFB, and the current control terminal VG to adjust the voltage of the current control terminal VG based on the second reference voltage VREF2 and the feedback voltage VFB.

[0036] In one embodiment, the current mirror unit includes a second transistor M2 and a third transistor M3. The first terminal of the second transistor M2 and the first terminal of the third transistor M3 are connected to the input voltage VIN. The control terminal of the second transistor M2 is connected to the second terminal of the second transistor M2, the second terminal of the first transistor M1, the second adjustment unit 30, and the control terminal of the third transistor M3 to form a current control terminal VG. The second terminal of the third transistor M3 is connected to the sampling feedback unit 10 to form a voltage output terminal.

[0037] In one embodiment, the sampling feedback unit 10 includes a first feedback resistor Ra and a second feedback resistor Rb. The first end of the first feedback resistor Ra is connected to the second end of the third transistor M3 to form a voltage output terminal. The second end of the first feedback resistor Ra is connected to the first end of the second feedback resistor Rb to generate a feedback voltage VFB. The second end of the second feedback resistor Rb is connected to a reference voltage, which is ground voltage.

[0038] like Figure 3 As shown, the first adjustment unit 20 includes a first adjustment transistor MT1, a first current source A1, a first sampling unit, and a second sampling unit. The first sampling unit is connected to the current control terminal VG and the input voltage VIN to sample the first current I1 to obtain the first sampled current I1a. The second sampling unit is connected to the current control terminal VG, the input voltage VIN, and the voltage output terminal (output voltage VOUT) to sample the second current I2 to obtain the second sampled current I2a. The control terminal of the first adjustment transistor MT1 is connected to the first sampling unit and the second sampling unit. The second terminal of the first adjustment transistor MT1 is connected to the control terminal of the first transistor M1 (the output terminal EA_OUT of the first operational amplifier op1). The first terminal of the first adjustment transistor MT1 is connected to the reference voltage. The first terminal of the first current source A1 is connected to the control terminal of the first adjustment transistor MT1, and the second terminal of the first current source A1 is connected to the reference voltage. The first adjustment transistor MT1 adjusts the voltage at the control terminal of the first transistor M1 based on the magnitude of the first sampled current I1a, the second sampled current I2a, and the current generated by the first current source A1.

[0039] In one embodiment, the sum of the second sampling current I2a and the current generated by the first current source A1 is compared with the first sampling current I1a. If the sum of the second sampling current I2a and the current generated by the first current source A1 is greater than the first sampling current I1a, the voltage at the control terminal of the first regulating transistor MT1 is pulled down; if the sum of the second sampling current I2a and the current generated by the first current source A1 is less than the first sampling current I1a, the voltage at the control terminal of the first regulating transistor MT1 is pulled up. In other embodiments, the first current source A1 may not be provided.

[0040] like Figure 3As shown, the first sampling unit comprises a fourth transistor M4 and a first clamping unit 211. The first end of the fourth transistor M4 is configured to receive the input voltage VIN, the control end of the fourth transistor M4 is connected with the current control end VG, the second end of the fourth transistor M4 is connected with the first clamping unit 211, the first clamping unit 211 is connected with the current control end VG and the control end of the first regulating tube MT1 at the same time, and the first clamping unit 211 is configured to clamp the voltage of the second end of the fourth transistor M4 based on the voltage of the current control end VG to generate the first sampling current I1a on the fourth transistor M4 and inject the first sampling current I1a into the control end of the first regulating tube MT1.

[0041] In an embodiment, the first clamping unit 211 comprises a first current mirror and a second current source A2, the first end of the first current mirror is connected with the second end of the fourth transistor M4, the second end of the first current mirror is connected with the control end of the first regulating tube MT1, the third end of the first current mirror is connected with the current control end VG, the fourth end of the first current mirror is connected with the first end of the second current source A2, and the second end of the second current source A2 is connected with the reference voltage.

[0042] In an embodiment, the first current mirror comprises a sixth transistor M6 and a seventh transistor M7, the first end of the sixth transistor M6 is the first end of the first current mirror and is connected with the second end of the fourth transistor M4, the second end of the sixth transistor M6 is the second end of the first current mirror and is connected with the control end of the first regulating tube MT1, the first end of the seventh transistor M7 is the third end of the first current mirror and is connected with the current control end VG, the control end of the seventh transistor M7 is connected with the control end of the sixth transistor M6, the second end of the seventh transistor M7 is the fourth end of the first current mirror and is connected with the first end of the second current source A2. The width-length ratio of the sixth transistor M6 and the seventh transistor M7 is equal.

[0043] The first end of the fourth transistor M4 receives the input voltage VIN, the control end of the fourth transistor M4 is connected with the current control end VG, so that the current equal to the current on the second transistor M2 can be obtained on the fourth transistor M4, and at the same time, based on the characteristics of the first current mirror, the voltage equal to the voltage on the current control end VG can also be obtained on the first end of the sixth transistor M6, at this time, the current on the second transistor M2 can be more accurately collected through the fourth transistor M4.

[0044] As Figure 3As shown, the second sampling unit comprises a fifth transistor M5, a second clamping unit 221 and a current mirror module 222. The first end of the fifth transistor M5 is configured to receive the input voltage VIN, the control end of the fifth transistor M5 is connected with the current control end VG, the second end of the fifth transistor M5 is connected with the second clamping unit 221, the second clamping unit 221 is connected with the voltage output end and the current mirror module 222 at the same time, the second clamping unit 221 is configured to clamp the voltage at the second end of the fifth transistor M5 based on the output voltage of the voltage output end to generate the second sampling current I2a on the fifth transistor M5 and deliver the second sampling current I2a to the current mirror module 222, and the current mirror module 222 is connected with the control end of the first regulating tube MT1 at the same time to adjust the voltage at the control end of the first regulating tube MT1 based on the mirror current of the second sampling current I2a.

[0045] The second clamping unit 221 comprises a second current mirror and a third current source A3, the first end of the second current mirror is connected with the second end of the fifth transistor M5, the second end of the second current mirror is connected with the current mirror module 222, the third end of the second current mirror is connected with the voltage output end, the fourth end of the second current mirror is connected with the first end of the third current source A3, and the second end of the third current source A3 is connected with the reference voltage.

[0046] In an embodiment, the second current mirror comprises an eighth transistor M8 and a ninth transistor M9, the first end of the eighth transistor M8 is the first end of the second current mirror and is connected with the second end of the fifth transistor M5, the second end of the eighth transistor M8 is the second end of the second current mirror and is connected with the current mirror module 222, the first end of the ninth transistor M9 is the third end of the second current mirror and is connected with the voltage output end (the output voltage VOUT), the control end of the ninth transistor M9 is connected with the control end of the eighth transistor M8 and the second end of the ninth transistor M9, which is the fourth end of the second current mirror and is connected with the first end of the third current source A3.

[0047] The first end of the fifth transistor M5 is configured to receive the input voltage VIN, the control end of the fifth transistor M5 is connected with the current control end VG, so that the current equal to the current on the third transistor M3 can be obtained on the fifth transistor M5, and at the same time, since the first end of the ninth transistor M9 is connected with the voltage output end (the output voltage VOUT), based on the characteristics of the second current mirror, the voltage equal to the voltage on the voltage output end can also be obtained on the first end of the eighth transistor M8, at this time, the current on the third transistor M3 can be more accurately collected through the fifth transistor M5.

[0048] The current mirror module 222 includes a tenth transistor M10 and an eleventh transistor M11. The first terminal of the tenth transistor M10 and the first terminal of the eleventh transistor M11 are connected to a reference voltage. The second terminal of the tenth transistor M10 is connected to the control terminal of the first regulating transistor MT1. The control terminal of the tenth transistor M10 is connected to the control terminal of the eleventh transistor M11, the second terminal of the eleventh transistor M11, and the second terminal of the eighth transistor M8 of the second clamping unit 221.

[0049] like Figure 2 As shown, the second adjustment unit 30 includes a second adjustment transistor MT2 and a second operational amplifier op2. The first input terminal of the second operational amplifier op2 receives a second reference voltage VREF2, and the second input terminal receives a feedback voltage VFB. The output terminal EA_OUT_FAST of the second operational amplifier op2 is connected to the control terminal of the second adjustment transistor MT2. The second terminal of the second adjustment transistor MT2 is connected to the current control terminal VG, and the first terminal of the second adjustment transistor MT2 is connected to a reference voltage. The second adjustment transistor MT2 adjusts the voltage of the current control terminal VG based on the drive of the second operational amplifier op2. In one embodiment, the first input terminal of the second operational amplifier op2 is a positive input terminal, and the second input terminal is a negative input terminal. In other embodiments, the first input terminal of the second operational amplifier op2 is a negative input terminal, and the second input terminal is a positive input terminal.

[0050] like Figure 2 As shown, the LDO circuit also includes a filter circuit RC connected to the control terminal of the first transistor M1, and a resistor unit R1 connected to the input voltage VIN and the current control terminal VG. The filter circuit RC is used for frequency compensation to ensure the stability of the entire circuit loop and prevent oscillation. The resistor unit R1 is used to limit the voltage difference between the input voltage VIN and the voltage at the current control terminal VG.

[0051] The first transistor M1, the first regulating transistor MT1, the second regulating transistor MT2, the tenth transistor M10, and the eleventh transistor M11 are N-channel MOSFETs. The second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are P-channel MOSFETs. In other embodiments, the first transistor M1, the first regulating transistor MT1, the second regulating transistor MT2, the tenth transistor M10, and the eleventh transistor M11 are P-channel MOSFETs. The second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are N-channel MOSFETs.

[0052] The first end of the first transistor M1, the first end of the second transistor M2, the first end of the third transistor M3, the first end of the first regulating tube MT1, the first end of the second regulating tube MT2, the first end of the fourth transistor M4, the first end of the fifth transistor M5, the first end of the sixth transistor M6, the first end of the seventh transistor M7, the first end of the eighth transistor M8, the first end of the ninth transistor M9, the first end of the tenth transistor M10 and the first end of the eleventh transistor M11 are source electrodes; the second end of the first transistor M1, the second end of the second transistor M2, the second end of the third transistor M3, the second end of the first regulating tube MT1, the second end of the second regulating tube MT2, the second end of the fourth transistor M4, the second end of the fifth transistor M5, the second end of the sixth transistor M6, the second end of the seventh transistor M7, the second end of the eighth transistor M8, the second end of the ninth transistor M9, the second end of the tenth transistor M10 and the second end of the eleventh transistor M11 are drain electrodes; the control end of the first transistor M1, the control end of the second transistor M2, the control end of the third transistor M3, the control end of the first regulating tube MT1, the control end of the second regulating tube MT2, the control end of the fourth transistor M4, the control end of the fifth transistor M5, the control end of the sixth transistor M6, the control end of the seventh transistor M7, the control end of the eighth transistor M8, the control end of the ninth transistor M9, the control end of the tenth transistor M10 and the control end of the eleventh transistor M11 are gate electrodes.

[0053] In an embodiment, the second reference voltage VREF2 is less than the first reference voltage VREF1, and the second reference voltage VREF2 can be 25mV or other voltage values less than the first reference voltage VREF1 to satisfy the sequence of the second regulating tube MT2 and the first transistor M1 when turned on and turned off. The first current source A1 can select a current source generating a bias current of 100nA or other current values.

[0054] When the LDO circuit works in the dropout region, the voltage of the output end EA_OUT of the first operational amplifier op1 is limited to be not too large by introducing the loop composed of the first regulating unit 20, thereby limiting the opening degree of the first transistor M1; at this time, since the current on the first transistor M1 is limited by the loop, in order to ensure sufficient driving stage current, the fast loop circuit composed of the second regulating unit 30 is introduced, at this time, the fast loop circuit is in an open loop state, the current on the second regulating tube MT2 is large, which compensates for the current on the limited first transistor M1, thereby ensuring the dropout voltage.

[0055] When the input voltage VIN is stepped from a low voltage to a high voltage, the main loop establishes a faster pull-down of the voltage at the output terminal EA_OUT of the first operational amplifier op1 due to the voltage at the output terminal EA_OUT of the first operational amplifier op1 being clamped during the dropout region, and the overshoot is optimized; when the LDO circuit is in a non-dropout region, the first regulating circuit 20 and the second regulating circuit 30 are not in operation.

[0056] Figure 4 For the existing LDO circuit, when the LDO circuit is in a dropout region, the third transistor M3 operates in a linear region, when the input voltage VIN is stepped from a high voltage (5V) to a low voltage (3.3V), the voltage at the output terminal EA_OUT of the first operational amplifier op1 is still very high, and although the voltage at the current control terminal VG has been pulled very low, the control function has been lost, and there is a dropout voltage between the output voltage VOUT and the input voltage VIN. In addition, when the input voltage VIN is stepped from a high voltage (5V) to a low voltage (3.3V), the output voltage VOUT is prone to undershoot with the input voltage VIN.

[0057] Figure 5 For the LDO circuit in a dropout region, when the input voltage VIN is stepped from a high voltage (5V) to a low voltage (3.3V), a new loop is introduced to make the main loop composed of the first operational amplifier op1 not operate in an open-loop state, so that the voltage at the output terminal EA_OUT of the first operational amplifier op1 is not too high, and the voltage at the current control terminal VG is not too low, resulting in that the output voltage VOUT is not too high, and the dropout voltage is large, thereby sacrificing the dropout voltage between the output voltage VOUT and the input voltage VIN.

[0058] Figure 6 For the LDO circuit in a dropout region in the present application, when the input voltage VIN is stepped from a high voltage (5V) to a low voltage (3.3V), the first regulating unit 20 operates to make the voltage at the output terminal EA_OUT of the first operational amplifier op1 not too high, so that the first operational amplifier op1 does not operate at an extreme operating point, and the second regulating unit 30 operates to pull down the voltage at the current control terminal VG, so that the output voltage VOUT maintains a maximum output, ensuring a small enough dropout voltage between the output voltage VOUT and the input voltage VIN, and compared with Figure 4 , the voltage between the first end of the third transistor M3 and the control terminal of the third transistor M3 is reduced, i.e. the opening degree of the third transistor M3 is reduced, so that when the input voltage VIN is stepped from a high voltage to a low voltage, the output voltage VOUT does not produce a large undershoot, and the undershoot is optimized.

[0059] It will be apparent to those skilled in the art that the disclosure is not limited to the details of the above-exemplified embodiments as such, and that the disclosure can be implemented in other particular forms without departing from the spirit or essential characteristics of the disclosure. The embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the disclosure being indicated by the appended claims rather than by the above description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. No reference signs in the claims should be considered as limiting the scope of the claims to the features to which the reference signs correspond.

[0060] Furthermore, it should be understood that although the description is made on the basis of the embodiments, not every embodiment contains only one independent technical solution, and the description manner of the specification is only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be properly combined to form other embodiments which can be understood by those skilled in the art.

Claims

1. An LDO circuit, characterized in that, include: The system comprises a first operational amplifier, a first transistor, a current mirror unit, and a sampling feedback unit. The output terminal of the first operational amplifier is connected to the control terminal of the first transistor. The first transistor generates a first current based on the drive of the first operational amplifier. The current mirror unit forms a current control terminal with the second terminal of the first transistor. The current mirror unit is also connected to an input voltage to mirror the first current and generate a second current. The sampling feedback unit is connected to the current mirror unit to form a voltage output terminal and generates a feedback voltage based on the second current. The first input terminal of the first operational amplifier is used to receive a first reference voltage, and the second input terminal of the first operational amplifier is used to receive the feedback voltage. The LDO circuit further includes a first adjustment unit and a second adjustment unit. The first adjustment unit is connected to a current control terminal, an input voltage, a voltage output terminal, and a control terminal of a first transistor to sample the first current and the second current respectively and adjust the voltage of the control terminal of the first transistor based on the corresponding current obtained from the sampling. The second adjustment unit is connected to a second reference voltage, a feedback voltage, and a current control terminal to adjust the voltage of the current control terminal based on the second reference voltage and the feedback voltage.

2. The LDO circuit according to claim 1, characterized in that, The current mirror unit includes a second transistor and a third transistor. The first terminals of the second transistor and the third transistor are connected to the input voltage. The control terminal of the second transistor is connected to the second terminal of the second transistor, the second terminal of the first transistor, the second adjustment unit, and the control terminal of the third transistor to form a current control terminal. The second terminal of the third transistor is connected to the sampling feedback unit to form a voltage output terminal.

3. The LDO circuit according to claim 1, characterized in that, The first adjustment unit includes a first adjustment transistor, a first sampling unit, and a second sampling unit. The first sampling unit is connected to a current control terminal and an input voltage to sample a first current to obtain a first sampling current. The second sampling unit is connected to a current control terminal, an input voltage, and a voltage output terminal to sample a second current to obtain a second sampling current. The control terminal of the first adjustment transistor is connected to the first sampling unit and the second sampling unit. The second terminal of the first adjustment transistor is connected to the control terminal of the first transistor. The first terminal of the first adjustment transistor is connected to a reference voltage. The first adjustment transistor adjusts the voltage at the control terminal of the first transistor based on the magnitude between the first sampling current and the second sampling current.

4. The LDO circuit according to claim 3, characterized in that, The first sampling unit includes a fourth transistor and a first clamping unit. The first terminal of the fourth transistor is used to receive the input voltage. The control terminal of the fourth transistor is connected to the current control terminal. The second terminal of the fourth transistor is connected to the first clamping unit. The first clamping unit is simultaneously connected to the current control terminal and the control terminal of the first regulating transistor. The first clamping unit is used to clamp the voltage at the second terminal of the fourth transistor based on the voltage at the current control terminal to generate a first sampling current on the fourth transistor and inject the first sampling current into the control terminal of the first regulating transistor.

5. The LDO circuit according to claim 3, characterized in that, The second sampling unit includes a fifth transistor, a second clamping unit, and a current mirror module. The first terminal of the fifth transistor is used to receive the input voltage. The control terminal of the fifth transistor is connected to the current control terminal. The second terminal of the fifth transistor is connected to the second clamping unit. The second clamping unit is connected to both the voltage output terminal and the current mirror module. The second clamping unit is used to clamp the voltage at the second terminal of the fifth transistor based on the output voltage of the voltage output terminal to generate a second sampling current on the fifth transistor and to send the second sampling current to the current mirror module. The current mirror module is also connected to the control terminal of the first regulating transistor to adjust the voltage at the control terminal of the first regulating transistor.

6. The LDO circuit according to claim 4, characterized in that, The first clamping unit includes a first current mirror and a second current source. The first end of the first current mirror is connected to the second end of the fourth transistor. The second end of the first current mirror is connected to the control terminal of the first regulating transistor. The third end of the first current mirror is connected to the current control terminal. The fourth end of the first current mirror is connected to the first end of the second current source. The second end of the second current source is connected to the reference voltage.

7. The LDO circuit according to claim 5, characterized in that, The second clamping unit includes a second current mirror and a third current source. The first end of the second current mirror is connected to the second end of the fifth transistor. The second end of the second current mirror is connected to the current mirror module. The third end of the second current mirror is connected to the voltage output terminal. The fourth end of the second current mirror is connected to the first end of the third current source. The second end of the third current source is connected to the reference voltage.

8. The LDO circuit according to claim 3, characterized in that, The first regulating unit further includes a first current source, the first end of which is connected to the control terminal of the first regulating tube, and the second end of which is connected to a reference voltage.

9. The LDO circuit according to claim 1, characterized in that, The second adjustment unit includes a second adjustment transistor and a second operational amplifier. The first input terminal of the second operational amplifier is used to receive a second reference voltage, and the second input terminal of the second operational amplifier is used to receive a feedback voltage. The output terminal of the second operational amplifier is connected to the control terminal of the second adjustment transistor. The second terminal of the second adjustment transistor is connected to the current control terminal, and the first terminal of the second adjustment transistor is connected to the reference voltage. The second adjustment transistor adjusts the voltage of the current control terminal based on the drive of the second operational amplifier.

10. The LDO circuit according to claim 1, characterized in that, The LDO circuit further includes an RC filter circuit connected to the control terminal of the first transistor; and / or The LDO circuit also includes a resistor unit connected to the input voltage and current control terminals.

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