System on chip and update data configuration method
By introducing a monitoring module and interrupt handling mechanism into the chip, the problem that software patches cannot update data during the chip startup phase is solved, enabling data updates at any address at any time and expanding the scope of data updates.
Patent Information
- Application Number
- CN202511642152.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-11
- Publication Date
- 2026-02-13
AI Technical Summary
In the existing technology, software patches cannot update the data of some registers during the chip startup phase, and cannot configure and update data in real time under specific conditions.
The monitoring module in the system-on-a-chip monitors the data read and write requests transmitted on the system bus. When the address or data matches, the program execution of the central processing unit is paused through the interrupt request mechanism, and the interrupt handler is executed to update the data.
It enables the configuration of arbitrary updated data at any address at any time after the chip starts up, expanding the scope of data updates and surpassing the limitations of software patches.
Smart Images
Figure CN121523707A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the chip field, and in particular to a system on chip and a method for updating data configuration. BACKGROUND
[0002] The register is a high-speed storage component in the chip. During the operation of the chip, various devices on the chip usually use the register to store temporary data. In some special cases such as program optimization, firmware repair, and real-time task scheduling, there may be a need to replace the data stored in the register by the updated data.
[0003] In the related art, the data update is usually realized by a software patch. However, the software patch can only be loaded after the completion of the system startup of the chip, and cannot realize the function of updating the data of some registers in the system startup stage. Moreover, in some scenarios, the update requirement may be to configure the updated data immediately after the triggering of some specific conditions (such as the writing of a specific value to a specific address by the processor), and the software patch may not be able to capture the specific conditions or may not be able to realize the requirement of updating the data immediately after the specific conditions are met.
[0004] In summary, the data update by the software patch has the problem of limited scope of application. SUMMARY
[0005] Therefore, it is necessary to provide a system on chip and a method for updating data configuration in view of the above technical problems.
[0006] In a first aspect, the present application provides a system on chip, comprising a monitoring module, a system bus, and a central processing unit, wherein:
[0007] The central processing unit is configured to execute a program and initiate a data read / write request through the system bus during the execution of the program.
[0008] The monitoring module is configured to monitor the data read / write request transmitted on the system bus, and send an interrupt request to the central processing unit when at least one of the following conditions is met: the indicated address matches the preconfigured monitoring address, and the indicated data matches the preconfigured monitoring data.
[0009] The central processing unit is configured to pause the execution of the program and execute an interrupt processing program in response to the interrupt request, wherein the interrupt processing program is preconfigured with updated data and a target address to which the updated data needs to be configured, and the interrupt processing program is configured to write the updated data into the target address.
[0010] In one of the embodiments, the monitoring module comprises a monitoring control register, in which an address monitoring enable bit and a data monitoring enable bit are set;
[0011] When the address monitoring enable bit is enabled, the monitoring module sends an interrupt request to the central processor when the address indicated by the data read / write request matches the preconfigured monitoring address;
[0012] When the data monitoring enable bit is enabled, the monitoring module sends an interrupt request to the central processor when the data indicated by the data read / write request matches the preconfigured monitoring data.
[0013] In one of the embodiments, the monitoring module further comprises an interrupt output unit, a monitoring address comparator and a monitoring data comparator;
[0014] The monitoring address comparator is configured to output a first signal to the interrupt output unit when the address indicated by the data read / write request matches the preconfigured monitoring address;
[0015] The monitoring data comparator is configured to output a second signal to the interrupt output unit when the data indicated by the data read / write request matches the preconfigured monitoring data;
[0016] The interrupt output unit is configured to read the values of the address monitoring enable bit and the data monitoring enable bit in the monitoring control register, and send an interrupt request to the central processor when the address monitoring enable bit is enabled and the first signal is received, or send an interrupt request to the central processor when the data monitoring enable bit is enabled and the second signal is received.
[0017] In one of the embodiments, the monitoring control register further comprises a read enable bit and a write enable bit;
[0018] When the read enable bit is enabled, the monitoring module performs the step of sending an interrupt request to the central processor when the data read / write request is a read request and at least one of the following conditions is met: the address indicated by the data read / write request matches the preconfigured monitoring address, and the data indicated by the data read / write request matches the preconfigured monitoring data;
[0019] When the write enable bit is enabled, the monitoring module performs the step of sending an interrupt request to the central processor when the data read / write request is a write request and at least one of the following conditions is met: the address indicated by the data read / write request matches the preconfigured monitoring address, and the data indicated by the data read / write request matches the preconfigured monitoring data.
[0020] In one of the embodiments, the monitoring control register further has an interrupt enable bit, and the monitoring module is further configured to determine to monitor the data read / write request transmitted on the system bus when the interrupt enable bit is enabled.
[0021] In one of the embodiments, the system further comprises a target memory, which is an on-chip memory or an off-chip memory.
[0022] The central processing unit is further configured to read the update data of the interrupt handling program configuration and the target address to which the update data needs to be configured from the target memory when executing the interrupt handling program.
[0023] In a second aspect, the application further provides an update data configuration method. The method comprises:
[0024] monitoring a data read / write request transmitted on a system bus, and sending an interrupt request to the central processing unit when the data read / write request meets at least one of the following conditions: an indicated address matches a preconfigured monitoring address, and an indicated data matches preconfigured monitoring data;
[0025] The interrupt request is used to instruct the central processing unit to suspend the currently executed program and execute an interrupt handling program, the interrupt handling program is preconfigured with update data and a target address to which the update data needs to be configured, and the interrupt handling program is used to write the update data into the target address.
[0026] The sending of the interrupt request to the central processing unit when the data read / write request meets at least one of the following conditions: an indicated address matches a preconfigured monitoring address, and an indicated data matches preconfigured monitoring data, comprises:
[0027] determining the enable states of an address monitoring enable bit and a data monitoring enable bit in a monitoring control register;
[0028] sending an interrupt request to the central processing unit when the data read / write request meets the condition that an indicated address matches a preconfigured monitoring address, when the address monitoring enable bit is enabled;
[0029] sending an interrupt request to the central processing unit when the data read / write request meets the condition that an indicated data matches preconfigured monitoring data, when the data monitoring enable bit is enabled.
[0030] In one of the embodiments, the sending of the interrupt request to the central processing unit when the data read / write request meets at least one of the following conditions: an indicated address matches a preconfigured monitoring address, and an indicated data matches preconfigured monitoring data, comprises:
[0031] determining the enable states of a read enable bit and a write enable bit in a monitoring control register;
[0032] when the data read-write request is a write request, performing a step of sending an interrupt request to the central processor when the data read-write request satisfies at least one of an indicated address matching a preconfigured monitoring address and indicated data matching preconfigured monitoring data.
[0033] when the data read-write request is a write request, performing a step of sending an interrupt request to the central processor when the data read-write request satisfies at least one of an indicated address matching a preconfigured monitoring address and indicated data matching preconfigured monitoring data.
[0034] In one of the embodiments, the monitoring of the data read-write request transmitted on the system bus comprises:
[0035] determining an enabling state of an interrupt enabling bit in a monitoring control register;
[0036] when the interrupt enabling bit is enabled, determining to monitor the data read-write request transmitted on the system bus.
[0037] In a third aspect, the present application further provides a computer device. The computer device comprises a memory and a processor, the memory stores a computer program, and the processor implements any of the above methods when executing the computer program.
[0038] In a fourth aspect, the present application further provides a computer readable storage medium. The computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement any of the above methods.
[0039] In a fifth aspect, the present application further provides a computer program product. The computer program product comprises a computer program, and the computer program is executed by a processor to implement any of the above methods.
[0040] The on-chip system and the updating data configuration method, in the process that the central processing unit executes the program, utilize the monitoring module to monitor the data read / write request transmitted on the system bus. When the address or data indicated by the data read / write request matches the monitoring address or monitoring data, an interrupt is initiated to the central processing unit, and the updating data that needs to be updated is written into the target address where the updating data needs to be configured by using the interrupt processing flow of the central processing unit. Since the interrupt processing flow of the central processing unit has the characteristics of high priority and can interrupt the program currently processed by the central processing unit, the embodiment of the present application can realize the requirement of configuring the data that needs to be updated in any target address immediately after the address matching or data matching is monitored by triggering the interrupt to configure the updating data. Moreover, since the monitoring module belongs to the hardware module inside the chip, the monitoring module can also normally run and monitor the request in the chip startup stage. Therefore, the on-chip system is used to configure the updating data, which has the characteristics of configuring any updating data in any address at any time after the chip is started, and the application range is wider than the software patch. BRIEF DESCRIPTION OF DRAWINGS
[0041] Figure 1 It is a schematic diagram of the on-chip system in one embodiment;
[0042] Figure 2 It is a schematic diagram of the monitoring module in one embodiment;
[0043] Figure 3 It is a flowchart of the updating data configuration method in one embodiment;
[0044] Figure 4 It is an internal structure diagram of the chip in one embodiment;
[0045] Figure 5 It is a flowchart of the soft / hardware debugging task executed by the off-chip controller in one embodiment;
[0046] Figure 6 It is an internal structure diagram of the chip containing the off-chip controller in one embodiment. DETAILED DESCRIPTION
[0047] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.
[0048] In one embodiment, as shown in Figure 1As shown, a system on chip is provided. The system comprises a monitoring module, a system bus, and a central processing unit. The central processing unit is configured to execute a program and initiate a data read / write request through the system bus during execution of the program; the monitoring module is configured to monitor the data read / write request transmitted on the system bus, and send an interrupt request to the central processing unit when the data read / write request satisfies at least one of the following conditions: an indicated address matches a preconfigured monitoring address, and an indicated data matches a preconfigured monitoring data; the central processing unit is configured to suspend execution of the program and execute an interrupt processing program in response to the interrupt request; the interrupt processing program is preconfigured with update data and a target address to which the update data needs to be configured, and the interrupt processing program is configured to write the update data into the target address.
[0049] In the embodiments of the present application, the monitoring module is arranged in the chip, connected with the system bus, and configured to monitor the data read / write request transmitted on the system bus. The monitoring module can be arranged as one or more. The registers in each monitoring module can be configured with the address to be monitored (i.e. the preconfigured monitoring address) and / or the data to be monitored (i.e. the preconfigured monitoring data). The preconfigured monitoring address and the preconfigured monitoring data of each monitoring module can exist as one or more, respectively. In one example, the preconfigured monitoring address can also be set as an address range, and the preconfigured monitoring data can be set as a data range.
[0050] When the central processing unit in the chip executes any program and needs to read data from the register in the chip or write data into the register, the central processing unit initiates a data read / write request to the register through the system bus. The data read / write request is configured to indicate the address of the data to be read or written, and the data to be read or written.
[0051] At each clock rising edge, the monitoring module can sample the signal transmitted on the system bus. If the monitoring module monitors the read signal or the write signal in the control line, the monitoring module matches the address sampled from the address line with the preconfigured monitoring address, and / or matches the data sampled from the data line with the preconfigured monitoring data. If at least one of the address and the data matches, the monitoring module outputs an interrupt signal to the system bus to initiate an interrupt request to the central processing unit, so that the central processing unit suspends execution of the current program and executes the interrupt processing program preconfigured for the monitoring module.
[0052] In one example, whether the monitoring module specifically performs address matching or data matching is determined according to whether the preconfigured monitoring address and the preconfigured monitoring data exist, i.e. if the valid preconfigured monitoring address is set in the register of the monitoring module, the monitoring module performs address matching; if the valid preconfigured monitoring data is set in the register of the monitoring module, the monitoring module performs data matching; if the valid preconfigured monitoring address and the valid preconfigured monitoring data are both set in the register, the monitoring module performs both address matching and data matching.
[0053] In one example, whether the monitoring module specifically initiates an interrupt when performing address matching or data matching is also determined according to whether the preconfigured monitoring address and the preconfigured monitoring data exist, i.e. if the valid preconfigured monitoring address is set in the register of the monitoring module, the monitoring module initiates an interrupt when address matching is determined; if the valid preconfigured monitoring data is set in the register of the monitoring module, the monitoring module initiates an interrupt when data matching is determined; if the valid preconfigured monitoring address and the valid preconfigured monitoring data are both set in the register, the monitoring module initiates an interrupt when both address matching and data matching are determined.
[0054] In another example, the monitoring module is provided with a monitoring control register, and the monitoring control register is provided with an address monitoring enable bit and a data monitoring enable bit. When the address monitoring enable bit is enabled, the monitoring module sends an interrupt request to the central processor when the address indicated by the data read / write request matches the preconfigured monitoring address; when the data monitoring enable bit is enabled, the monitoring module sends an interrupt request to the central processor when the data indicated by the data read / write request matches the preconfigured monitoring data.
[0055] In one example, a configuration interface can be provided in the monitoring module to enable the central processor to configure the monitoring control register and the register storing the preconfigured monitoring address or the preconfigured monitoring data through the configuration interface. For example, when the central processor needs to configure the monitoring control register, the central processor can initiate a data write request to the monitoring module, the address indicated by the data write request being the address of the enable bit in the monitoring control register that needs to be modified, and the data being the value to which the enable bit needs to be modified. This allows the address to be monitored by the monitoring module, the data to be monitored by the monitoring module, and the condition under which an interrupt is initiated to be configured through software.
[0056] The central processor starts an interrupt processing procedure after receiving the interrupt request from the monitoring module: suspending the program currently executed by the central processor, and executing the interrupt processing program pre-configured for the monitoring module. In the embodiment of the present application, the interrupt processing program is used to configure the data to be updated into a specific target address. The update data and the target address can be pre-written into the interrupt processing program, or can also be configured on the register inside or outside the chip, and read by the central processor when executing the interrupt processing program.
[0057] After the central processor finishes executing the interrupt processing program, the program being executed before the interrupt is resumed. At this time, since the data in the target address has been updated by the interrupt processing program, the central processor can use the updated data when continuing to execute the program, realizing real-time configuration of the update data.
[0058] The on-chip system provided by the embodiment of the present application uses the monitoring module to monitor the data read / write request transmitted on the system bus during the execution of the program by the central processor. When the address or data indicated by the data read / write request matches the monitoring address or monitoring data, an interrupt is initiated to the central processor, and the interrupt processing procedure of the central processor is used to write the update data to be updated into the target address where the update data needs to be configured. Since the interrupt processing procedure of the central processor has the characteristics of high priority and can interrupt the program currently being processed by the central processor, the embodiment of the present application can meet the requirement of configuring the update data in any target address immediately after the address match or data match is monitored. Moreover, since the monitoring module is a hardware module inside the chip, the monitoring module can also normally operate and monitor the request during the start-up stage of the chip. Therefore, the above-mentioned on-chip system for configuring the update data has the characteristics of being able to configure any update data in any address at any time after the chip is started, and has a wider application range than software patches.
[0059] In one embodiment, the monitoring module further comprises an interrupt output unit, a monitoring address comparator and a monitoring data comparator;
[0060] The monitoring address comparator is configured to output a first signal to the interrupt output unit when the address indicated by the data read / write request matches the pre-configured monitoring address;
[0061] The monitoring data comparator is configured to output a second signal to the interrupt output unit when the data indicated by the data read / write request matches the pre-configured monitoring data;
[0062] The interrupt output unit is configured to read the values of the address monitoring enable bit and the data monitoring enable bit in the monitoring control register, and send an interrupt request to the central processing unit if the first signal is received when the address monitoring enable bit is enabled, or send an interrupt request to the central processing unit if the second signal is received when the data monitoring enable bit is enabled.
[0063] In the embodiment of the present application, referring to FIG. 1, Figure 2 The monitoring module includes a monitoring address comparator, a monitoring data comparator, a monitoring control register and an interrupt output unit. The interrupt output unit is connected to the monitoring address comparator, the monitoring data comparator and the monitoring control register. The monitoring address comparator and the monitoring data comparator are connected to a register storing preconfigured monitoring addresses and preconfigured monitoring data. Figure 2 It is shown in FIG. 1 that two different registers store the preconfigured monitoring addresses and the preconfigured monitoring data respectively. However, in fact, the preconfigured monitoring addresses and the preconfigured monitoring data can be stored in the same register, which is not limited in the embodiment of the present application.
[0064] The monitoring address comparator is configured to read the preconfigured monitoring addresses from the register, and compare the preconfigured monitoring addresses with an address indicated by a data read / write request. If the preconfigured monitoring addresses are the same as the address indicated by the data read / write request, the monitoring address comparator outputs a first signal to the interrupt output unit. If the preconfigured monitoring addresses are different from the address indicated by the data read / write request, the monitoring address comparator does not output the first signal to the interrupt output unit.
[0065] The monitoring data comparator is configured to read the preconfigured monitoring data from the register, and compare the preconfigured monitoring data with data indicated by the data read / write request. If the preconfigured monitoring data are the same as the data indicated by the data read / write request, the monitoring address comparator outputs a second signal to the interrupt output unit. If the preconfigured monitoring data are different from the data indicated by the data read / write request, the monitoring data comparator does not output the second signal to the interrupt output unit.
[0066] The interrupt output unit determines whether to initiate an interrupt when the first signal is received or to initiate an interrupt when the second signal is received based on whether the address monitoring enable bit and the data monitoring enable bit in the monitoring control register are enabled. If the address monitoring enable bit and the data monitoring enable bit are both enabled, it means that the interrupt output unit initiates an interrupt only when the first signal and the second signal are both received, or the interrupt output unit initiates an interrupt when any one of the first signal and the second signal is received. The specific strategy can be preconfigured by a person skilled in the art according to actual requirements.
[0067] In one embodiment, the monitoring control register is further configured with a read enable bit and a write enable bit;
[0068] When the read enable bit is enabled, the monitoring module, when the data read / write request is a read request, performs the step of sending an interrupt request to the central processor when the data read / write request satisfies at least one of the indicated address matching a preconfigured monitoring address and the indicated data matching preconfigured monitoring data.
[0069] When the write enable bit is enabled, the monitoring module, when the data read / write request is a write request, performs the step of sending an interrupt request to the central processor when the data read / write request satisfies at least one of the indicated address matching a preconfigured monitoring address and the indicated data matching preconfigured monitoring data.
[0070] In the embodiments of the present application, the read enable bit and the write enable bit are configured to control the monitoring module to initiate an interrupt when reading a data read request or a data write request.
[0071] If the read enable bit is enabled and the write enable bit is not enabled, the monitoring module, when sampling a read signal from the control line, performs the step of comparing the address monitored from the address line with a preconfigured monitoring address and / or comparing the data monitored from the data line with preconfigured monitoring data. If the monitoring module samples a write signal from the control line, the monitoring module does not perform the above comparison.
[0072] If the write enable bit is enabled and the read enable bit is not enabled, the monitoring module, when sampling a write signal from the control line, performs the step of comparing the address monitored from the address line with a preconfigured monitoring address and / or comparing the data monitored from the data line with preconfigured monitoring data. If the monitoring module samples a read signal from the control line, the monitoring module does not perform the above comparison.
[0073] If the read enable bit and the write enable bit are both enabled, the monitoring module, when sampling a read signal or a write signal, performs the above comparison step.
[0074] In one specific example, the conditions for initiating an interrupt represented by different enable bits can be seen from Table 1:
[0075] Table 1
[0076]
[0077] In one embodiment, the monitoring control register is further configured with an interrupt enable bit, and the monitoring module is further configured to determine to monitor the data read / write request transmitted on the system bus when the interrupt enable bit is enabled.
[0078] In this embodiment, the operation of the monitoring module can be controlled by an interrupt enable bit. The interrupt enable bit can be configured by the central processing unit through the aforementioned configuration interface. When the interrupt enable bit is enabled, the monitoring module performs listening to the system bus. When the interrupt enable bit is disabled, the monitoring module does not perform listening to the system bus.
[0079] In one embodiment, the system further includes a target memory, which is an on-chip memory or an off-chip memory;
[0080] The central processing unit is also configured to, when executing the interrupt handler, read from the target memory the update data configured by the interrupt handler and the target address to which the update data needs to be configured.
[0081] In this embodiment, the data to be updated and the target address to which the data should be updated can be stored in on-chip memory or off-chip memory. The update data and target address can be pre-configured or calculated and stored in real time by the central processing unit (CPU) during operation. When the CPU executes an interrupt handler, it can read the update data and target address from the memory and configure the update data into the target address.
[0082] In one embodiment, a method for updating data configuration is provided, applied to Figure 1 The monitoring module includes:
[0083] When a data read / write request transmitted on the monitoring system bus satisfies at least one of the following conditions: the indicated address matches the pre-configured monitoring address, and the indicated data matches the pre-configured monitoring data, an interrupt request is sent to the central processing unit.
[0084] The interrupt request is used to instruct the central processing unit to pause the currently executing program and execute an interrupt handler. The interrupt handler is pre-configured with update data and a target address to which the update data needs to be configured. The interrupt handler is used to write the update data into the target address.
[0085] In this embodiment, the configuration methods for pre-configured monitoring data, pre-configured monitoring address, update data, and target address can be found in [reference needed]. Figure 3 As shown. Technicians can pre-assess the data and addresses to be monitored, as well as the data that needs to be updated and the target addresses to which the updated data needs to be configured, and then write the pre-configured monitoring data, pre-configured monitoring addresses, updated data, and target addresses into on-chip memory or off-chip memory.
[0086] See further Figure 3As shown, during the initialization phase after startup, the chip first loads and runs the on-chip firmware. While running the on-chip firmware, the central processing unit (CPU) may need to read and write to registers via the system bus. During the initialization phase, the monitoring module reads pre-configured monitoring data and a pre-configured monitoring address from the storage device, stores these data and addresses in registers within the monitoring module, and begins monitoring the system bus when the interrupt enable bit is enabled. If the monitoring module detects a target request on the system bus that matches the monitoring target (i.e., address or data matching), it initiates an interrupt to the CPU. After entering the interrupt handling process, the CPU can obtain the target address and update data (and execute the interrupt handler, writing the update data to the target address, thus completing the register update during the chip startup phase).
[0087] After the chip boots up, it will continue loading external firmware for operation. The monitoring module can also continue monitoring the system bus during the chip's external firmware execution phase.
[0088] In one embodiment, sending an interrupt request to the central processing unit when the data read / write request satisfies at least one of the following: the indicated address matches a pre-configured monitoring address, and the indicated data matches pre-configured monitoring data, includes:
[0089] Determine the enable status of the address monitoring enable bit and the data monitoring enable bit in the monitoring control register;
[0090] When the address monitoring enable bit is enabled, an interrupt request is sent to the central processing unit when the address indicated by the data read / write request matches the pre-configured monitoring address.
[0091] When the data monitoring enable bit is enabled, an interrupt request is sent to the central processing unit when the data read / write request satisfies the indication and matches the pre-configured monitoring data.
[0092] In one embodiment, sending an interrupt request to the central processing unit when the data read / write request satisfies at least one of the following: the indicated address matches a pre-configured monitoring address, and the indicated data matches pre-configured monitoring data, includes:
[0093] Determine the enable status of the read enable bit and write enable bit in the monitoring control register;
[0094] When the read enable bit is enabled, when the data read / write request is a write request, the step of sending an interrupt request to the central processing unit is performed when at least one of the data read / write request satisfies that the indicated address matches the pre-configured monitoring address and the indicated data matches the pre-configured monitoring data.
[0095] When the write enable bit is enabled, and when the data read / write request is a write request, the step of sending an interrupt request to the central processing unit is performed when the data read / write request satisfies at least one of the following: the indicated address matches the pre-configured monitoring address, and the indicated data matches the pre-configured monitoring data.
[0096] In one embodiment, monitoring data read / write requests transmitted on the system bus includes:
[0097] Determine the enable status of the interrupt enable bit in the monitoring control register;
[0098] When the interrupt enable bit is enabled, data read / write requests transmitted on the system bus are identified and monitored.
[0099] The specific execution method of each step can be found in the description of the foregoing embodiments, and will not be repeated here.
[0100] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.
[0101] In one embodiment, a chip is provided, the internal structure of which can be shown as follows: Figure 4 As shown. The chip includes a central processing unit (CPU), on-chip or off-chip storage devices, and a memory connected via a system bus. Figure 4 It includes ROM (Read-Only Memory) and RAM (Random Access Memory) and a monitoring module. The chip's central processing unit provides computing and control capabilities. The chip's storage devices can be located on-chip or off-chip. Figure 4 Located off-chip, the ROM stores at least one of monitoring information, target address, and target data. The ROM stores the operating system and computer program. The RAM stores the data and variables of the computer program. When executed by the processor, the computer program implements a method for updating data configuration.
[0102] Those skilled in the art will understand that Figure 4 The structure shown is merely a block diagram of a portion of the structure related to the solution of this application and does not constitute a limitation on the chip to which the solution of this application is applied. The specific chip may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.
[0103] In one embodiment, a system-on-a-chip (SoC) is provided, including a monitoring module and a central processing unit (CPU). The monitoring module is configured to respond to a target request transmitted on a target task monitoring system bus, and when the target request satisfies a preset condition corresponding to the target task, send an interrupt request to the CPU. The CPU is configured to, in response to the interrupt request, suspend the current task of the target master device and execute an interrupt handler corresponding to the interrupt request. The interrupt handler is pre-configured based on the target task.
[0104] In this embodiment, the monitoring module can also be used to execute any type of target task. The target task can be the update task in the foregoing embodiments, or other tasks configured according to actual needs. For example, the target task may include: software and hardware debugging task. Software and hardware debugging task refers to determining the state of each module in the chip before and after the error occurs (such as data stored at a certain memory address, status flags, etc.) when an error occurs during the operation of software or hardware, and determining the cause of the error based on the state of each module.
[0105] In software and hardware debugging tasks, preset conditions, monitoring addresses, or monitoring data can be configured according to actual needs. Based on the above information and referring to the configuration methods mentioned in the previous embodiments, the monitoring information register and monitoring control register in the monitoring module can be configured. Specifically, the monitoring address can be set to an address that will not be accessed during normal software or hardware operation (such as a non-existent address) or an address that is known in advance to cause errors (such as an address that is read or written when the software executes a certain line of code and then reports an error). The monitoring data can be set to data that is known in advance to cause errors (such as data that is read or written when the software executes a certain line of code and then reports an error).
[0106] After the monitoring module captures a target request that matches preset conditions and triggers an interrupt, the central processing unit (CPU) can execute an interrupt handler, which is configured according to the specific requirements of the target task. For example, in software and hardware debugging tasks, the interrupt handler can read the data currently stored in various registers in the chip and identify which register's data does not conform to the expected program. Technicians can then infer the cause of the error based on the register identified by the interrupt handler to further debug the software and hardware.
[0107] The specific hardware structure of the monitoring module, the preset conditions, and how to configure the monitoring module can be found in the aforementioned embodiments, and will not be repeated in the embodiments of this application.
[0108] In one embodiment, the system further includes an off-chip controller, and the interrupt handler is used to trigger the debugging process of the off-chip controller.
[0109] In this embodiment, the aforementioned hardware and software debugging tasks can be performed without using an interrupt handler. Instead, an interrupt handler can be used to call an external controller for debugging. The external controller can be a JTAG (Joint Test Action Group) testing tool or any testing tool; this embodiment does not specifically limit its use.
[0110] In one embodiment, the off-chip controller is used to set preset conditions based on software and hardware debugging tasks.
[0111] In this embodiment, preset conditions for the monitoring module can be configured via an off-chip controller based on the debugging requirements of the software and hardware debugging task. For details, please refer to [link to relevant documentation]. Figure 5 As shown. After assessing the monitoring address or data that needs to be monitored, the technicians use the corresponding instructions in the software tool used to control the external controller to write the monitoring address or data into the monitoring module through the external controller. They also configure the monitoring control register to set preset conditions so that the monitoring module can initiate an interrupt to the central controller when it detects a request on the bus that meets the preset conditions.
[0112] It should be noted that if there is a need to update the target data to the target address as in the aforementioned embodiment during the debugging process, technicians can also configure the external controller to set the target address and target data.
[0113] Technicians can further configure the interrupt handler to call the external controller's test flow, and configure the external controller to execute test flows when an interrupt is triggered by writing test programs. After the central controller receives an interrupt request, it enters the interrupt handling flow and executes the interrupt handler. The external controller can then execute test programs, such as checking the status of various on-chip registers, checking for physical connection problems of on-chip devices, etc.
[0114] Technicians can further configure the interrupt handler and test program to achieve the following functions: After completing all tests, the test program returns an interrupt end flag to the interrupt handler, causing the interrupt handler to terminate upon receiving the interrupt end flag. At this point, the central processing unit completes the interrupt handling process and resumes the current task being executed by the target master device before the interrupt began.
[0115] In one embodiment, the target request monitored by the monitoring module is initiated by the off-chip controller or the on-chip processor.
[0116] In this embodiment, a monitoring module can be configured to monitor target requests initiated by an external controller or by an on-chip processor. For example, the monitoring module can be configured to monitor target requests initiated by an external controller when a specific test process needs to be implemented (e.g., after writing data to a specific register, immediately triggering an interrupt to check the state of that register), and can be configured to monitor target requests initiated by an on-chip controller when it is necessary to monitor whether the process of the on-chip processor executing the software program is correct.
[0117] In one embodiment, a chip is provided, the internal structure of which can be shown as follows: Figure 6 As shown. The chip includes a central processing unit (CPU), an off-chip controller, and memory, all connected via a system bus. Figure 6 The chip includes RAM (Random Access Memory) and a monitoring module. Optionally, the chip may also include other microprocessors (CPUs) and intellectual property cores (IPs). The uses of the central processing unit, monitoring module, and off-chip controller are described in the foregoing embodiments, and will not be repeated in the embodiments of this application.
[0118] Those skilled in the art will understand that Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the solution of this application and does not constitute a limitation on the chip to which the solution of this application is applied. The specific chip may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.
[0119] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.
[0120] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0121] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.
Claims
1. A system-on-a-chip, characterized in that, include: Monitoring module, system bus, central processing unit, including: The central processing unit is used to execute programs and, during the execution of the programs, initiate data read / write requests through the system bus. The monitoring module is used to monitor data read and write requests transmitted on the system bus, and when the data read and write request satisfies at least one of the following: the indicated address matches the pre-configured monitoring address, and the indicated data matches the pre-configured monitoring data, the module sends an interrupt request to the central processing unit. The central processing unit is configured to, in response to the interrupt request, suspend the execution of the program and execute an interrupt handler; wherein, the interrupt handler is pre-configured with update data and a target address to which the update data needs to be configured, and the interrupt handler is configured to write the update data into the target address.
2. The system according to claim 1, characterized in that, The monitoring module includes a monitoring control register, which is configured with an address monitoring enable bit and a data monitoring enable bit. When the address monitoring enable bit is enabled, the monitoring module sends an interrupt request to the central processing unit when the address indicated by the data read / write request matches the pre-configured monitoring address. When the data monitoring enable bit is enabled, the monitoring module sends an interrupt request to the central processing unit when the data indicated by the data read / write request matches the pre-configured monitoring data.
3. The system according to claim 2, characterized in that, The monitoring module also includes an interrupt output unit, a monitoring address comparator, and a monitoring data comparator; The monitoring address comparator is used to output a first signal to the interrupt output unit when the address indicated by the data read / write request matches the pre-configured monitoring address; The monitoring data comparator is used to output a second signal to the interrupt output unit when the data indicated by the data read / write request matches the pre-configured monitoring data; The interrupt output unit is used to read the values of the address monitoring enable bit and the data monitoring enable bit in the monitoring control register, and when the address monitoring enable bit is enabled, if the first signal is received, an interrupt request is sent to the central processing unit; when the data monitoring enable bit is enabled, if the second signal is received, an interrupt request is sent to the central processing unit.
4. The system according to claim 2 or 3, characterized in that, The monitoring and control register is also equipped with a read enable bit and a write enable bit; When the read enable bit is enabled, the monitoring module, when the data read / write request is a read request, performs the step of sending an interrupt request to the central processing unit when at least one of the data read / write request satisfies the condition that the indicated address matches the pre-configured monitoring address and the indicated data matches the pre-configured monitoring data. When the write enable bit is enabled, the monitoring module, when the data read / write request is a write request, performs the step of sending an interrupt request to the central processing unit when the data read / write request satisfies at least one of the following: the indicated address matches the pre-configured monitoring address, and the indicated data matches the pre-configured monitoring data.
5. The system according to claim 2 or 3, characterized in that, The monitoring and control register is also equipped with an interrupt enable bit. The monitoring module is also used to determine the data read / write requests transmitted on the system bus when the interrupt enable bit is enabled.
6. The system according to claim 1, characterized in that, The system also includes a target memory, which is either on-chip memory or off-chip memory. The central processing unit is also configured to, when executing the interrupt handler, read from the target memory the update data configured by the interrupt handler and the target address to which the update data needs to be configured.
7. A method for updating data configuration, characterized in that, Applied to a monitoring module, the method includes: When a data read / write request transmitted on the monitoring system bus satisfies at least one of the following conditions: the indicated address matches the pre-configured monitoring address, and the indicated data matches the pre-configured monitoring data, an interrupt request is sent to the central processing unit. The interrupt request is used to instruct the central processing unit to pause the currently executing program and execute an interrupt handler. The interrupt handler is pre-configured with update data and a target address to which the update data needs to be configured. The interrupt handler is used to write the update data into the target address.
8. The method according to claim 7, characterized in that, When the data read / write request satisfies at least one of the following: the indicated address matches the pre-configured monitoring address, and the indicated data matches the pre-configured monitoring data, an interrupt request is sent to the central processing unit, including: Determine the enable status of the address monitoring enable bit and the data monitoring enable bit in the monitoring control register; When the address monitoring enable bit is enabled, an interrupt request is sent to the central processing unit when the address indicated by the data read / write request matches the pre-configured monitoring address. When the data monitoring enable bit is enabled, an interrupt request is sent to the central processing unit when the data read / write request satisfies the indication and matches the pre-configured monitoring data.
9. The method according to claim 7, characterized in that, When the data read / write request satisfies at least one of the following: the indicated address matches the pre-configured monitoring address, and the indicated data matches the pre-configured monitoring data, an interrupt request is sent to the central processing unit, including: Determine the enable status of the read enable bit and write enable bit in the monitoring control register; When the read enable bit is enabled, when the data read / write request is a write request, the step of sending an interrupt request to the central processing unit is performed when at least one of the data read / write request satisfies that the indicated address matches the pre-configured monitoring address and the indicated data matches the pre-configured monitoring data. When the write enable bit is enabled, and when the data read / write request is a write request, the step of sending an interrupt request to the central processing unit is performed when the data read / write request satisfies at least one of the following: the indicated address matches the pre-configured monitoring address, and the indicated data matches the pre-configured monitoring data.
10. The method according to claim 7, characterized in that, The monitoring of data read / write requests transmitted on the system bus includes: Determine the enable status of the interrupt enable bit in the monitoring control register; When the interrupt enable bit is enabled, data read / write requests transmitted on the system bus are identified and monitored.