Instruction processing method, processor, chip and electronic equipment

Abstract

The invention discloses an instruction processing method, a processor, a chip and electronic equipment, and relates to the field of computers. The instruction distribution unit reads an instruction sequence, the instruction sequence is obtained by inserting a check instruction in front of a target function instruction when the compiler determines the target function instruction with the data risk in the compiling process, and the scheduler executes the check instruction; and under the condition that the valid data volume in the first storage area reaches the valid data volume required by the execution of the target function instruction and / or the spare space in the second storage area is enough to accommodate the data output by the target function instruction, releasing the sub-calculation engine to execute the target function instruction. According to the method, the compiler defines that the check instruction is inserted into the function instruction with the data risk, so that the processor executes the function instruction according to the instruction of the check instruction, and the data dependency relationship between the instructions is detected and solved in a mode of combining software definition with hardware execution; the processing efficiency can be improved on the basis of simplifying hardware design.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to an instruction processing method, processor, chip, and electronic device. Background Technology

[0002] In current microprocessor architectures, concurrent and out-of-order instruction execution are common practices to improve overall performance. One problem arising from concurrent and out-of-order instruction execution is the need to resolve data dependencies between instructions. However, current methods for resolving these data dependencies are not very effective. Summary of the Invention

[0003] In view of the above problems, this application proposes an instruction processing method, processor, chip, and electronic device to solve the above problems.

[0004] In a first aspect, embodiments of this application provide an instruction processing method, the method comprising: a compiler compiling a plurality of functional instructions; if, during the compilation process, it is determined that a target functional instruction containing a data hazard exists among the plurality of functional instructions, a check instruction is inserted before the target functional instruction to obtain an instruction sequence, wherein the check instruction is used to instruct that the target functional instruction be executed only if the amount of valid data in a first storage area corresponding to the target functional instruction reaches the amount of valid data required for the execution of the target functional instruction, and / or the free space in a second storage area corresponding to the target functional instruction is sufficient to accommodate the data output by the target functional instruction; and storing the instruction sequence for a processor to read the instruction sequence and execute the target functional instruction according to the instructions of the check instruction.

[0005] Secondly, embodiments of this application provide an instruction processing method applied to a processor, the processor including an instruction dispatch unit, a scheduler, and a sub-computing engine. The method includes the instruction dispatch unit reading an instruction sequence, wherein the instruction sequence is obtained by the compiler inserting a check instruction before the target function instruction when it determines that there is a data hazard among the multiple function instructions during the compilation process of multiple function instructions. The check instruction is used to instruct that the target function instruction will only be executed if the parameter information corresponding to the target function instruction meets the specified parameter information. The specified parameter information includes that the effective data amount in the first storage area corresponding to the target function instruction reaches the effective data amount required for the execution of the target function instruction, and / or that the free space in the second storage area corresponding to the target function instruction is sufficient to accommodate the data output by the target function instruction; the scheduler executes the check instruction and, if it is determined that the parameter information corresponding to the target function instruction meets the specified parameter information, allows the target function instruction to proceed; the sub-computing engine executes the target function instruction.

[0006] Thirdly, embodiments of this application provide a processor, including an instruction dispatch unit, a scheduler, and a sub-computing engine, wherein: the instruction dispatch unit is used to read an instruction sequence, wherein the instruction sequence is obtained by the compiler inserting a check instruction before the target function instruction when it determines that there is a data hazard among the multiple function instructions during the compilation of multiple function instructions; the check instruction is used to instruct that the target function instruction be executed only if the parameter information corresponding to the target function instruction satisfies specified parameter information; the specified parameter information includes that the effective data amount in the first storage area corresponding to the target function instruction reaches the effective data amount required for the execution of the target function instruction, and / or that the free space in the second storage area corresponding to the target function instruction is sufficient to accommodate the data output by the target function instruction; the scheduler is used to execute the check instruction and, if it is determined that the parameter information corresponding to the target function instruction satisfies the specified parameter information, allow the target function instruction to proceed; the sub-computing engine is used to execute the target function instruction.

[0007] Fourthly, embodiments of this application provide an electronic device including the processor described above.

[0008] Fifthly, embodiments of this application provide a chip including the aforementioned processor.

[0009] The instruction processing method, processor, chip, and electronic device provided in this application embodiment involve a compiler (a software component) inserting a check instruction before a target function instruction containing data hazards during the compilation of multiple function instructions. The check instruction specifies that the target function instruction is executed only if the amount of valid data in the first storage area corresponding to the target function instruction reaches the amount of valid data required for its execution, and / or if the free space in the second storage area corresponding to the target function instruction is sufficient to accommodate the data output by the target function instruction. Subsequently, an instruction dispatch unit (a hardware component) reads the instruction, and a scheduler (a hardware component) determines whether to allow the target function instruction based on the check instruction's indication. If permission is granted, a sub-computing engine (a hardware component) executes the target function instruction. This achieves the detection and resolution of data dependencies between instructions through a combination of software definition and hardware execution, improving processing efficiency while simplifying hardware design. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A schematic diagram of the application environment that can be used for the instruction processing method provided in the embodiments of this application is shown;

[0012] Figure 2 A flowchart illustrating an embodiment of the instruction processing method provided in this application is shown.

[0013] Figure 3 A flowchart illustrating an embodiment of the instruction processing method provided in this application is shown.

[0014] Figure 4 A flowchart illustrating an embodiment of the instruction processing method provided in this application is shown.

[0015] Figure 5 A hardware design scheme for implementing instruction synchronization and scheduling using check instructions / data reservation instructions / update instructions is demonstrated;

[0016] Figure 6 A flowchart illustrating an embodiment of the instruction processing method provided in this application is shown.

[0017] Figure 7 A flowchart illustrating the execution of the inspection instructions provided in an embodiment of this application is shown;

[0018] Figure 8A flowchart illustrating an embodiment of the instruction processing method provided in this application is shown.

[0019] Figure 9 A flowchart illustrating an embodiment of the instruction processing method provided in this application is shown.

[0020] Figure 10 A flowchart illustrating an embodiment of the instruction processing method provided in this application is shown. Detailed Implementation

[0021] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0022] Out-of-order processor architecture improves instruction execution efficiency and performance by allowing independent instructions to be executed out of order. However, there are often data dependencies between instructions. Therefore, a key issue that out-of-order processor architecture needs to address is instruction scheduling and distribution, requiring that the execution order of instructions strictly adhere to their corresponding data dependencies.

[0023] Currently, artificial intelligence (AI) processors often employ multiple sub-computation engines to implement different computational processing functions, such as DMA sub-engines, vector quantum computing engines, and matrix sub-computation engines. These sub-engines often have data dependencies on each other. Before executing their respective instructions, each sub-engine needs to ensure the validity of the relevant input data and output space.

[0024] To resolve data dependencies between instructions, the inventors discovered two possible approaches:

[0025] First, the hardware is dynamically scheduled.

[0026] Hardware can rearrange the execution order of instructions based on actual conditions. This is typically achieved using techniques such as SchedulerWindow, Renaming, and Reservation Station. Hardware often needs to detect structural and data hazards during the instruction decoding stage. Simultaneously, the hardware needs to record corresponding data dependencies to dynamically schedule instruction issuance and operand retrieval. Finally, after instruction execution is complete, the hardware needs to write the results and update the data dependency graph.

[0027] Second, resolve data dependencies during the compilation phase.

[0028] Generally, compilers minimize instruction bubbles by unrolling cycles and rearranging instructions. However, when there are unavoidable data dependencies between instructions, the compiler still needs to insert cycle-level, estimated-number bubbles to ensure that the execution order of related instructions does not result in data conflicts.

[0029] However, while the first approach, using hardware for dynamic scheduling, is highly efficient, it suffers from poor adaptability. It often requires dedicated hardware solutions for different algorithms, resulting in a narrow range of support. Furthermore, this approach leads to higher system complexity and greater hardware resource consumption. It typically necessitates designing dedicated hardware circuits for logical judgments and allocating corresponding hardware resources to store and continuously update the overall program's data flow graph and data dependency graph. These approaches significantly increase hardware design complexity, making verification difficult, substantially increasing chip area, and introducing additional power consumption issues.

[0030] The second approach, resolving data dependencies during the compilation phase, introduces additional synchronization wait times between instructions, resulting in poor overall execution efficiency. Furthermore, the compiler cannot anticipate unforeseen delays during instruction execution, such as those caused by unpredictable external factors like bus behavior. Therefore, a corresponding hardware adaptation solution is still required, making the overall hardware solution equally complex and inefficient.

[0031] To address the aforementioned issues, the inventors, through long-term research, discovered that due to the diversity of upper-level algorithm types or the changing requirements brought about by rapid algorithm version iterations, differentiated hardware requirements can be proposed at the software level. Compared to purely hardware-based dynamic scheduling schemes, a software-defined approach combined with hardware implementation can significantly extend the lifecycle, expand the adaptability range, and reduce hardware verification costs.

[0032] Therefore, the inventors have proposed the instruction processing method, processor, chip, and electronic device provided in the embodiments of this application. By having a compiler (software) define and insert check instructions before functional instructions containing data hazards, the processor (hardware) executes the functional instructions according to the instructions of the check instructions. This software-defined approach combined with hardware execution detects and resolves data dependencies between instructions and sub-computing engines, improving processing efficiency while simplifying hardware design. The specific instruction processing method will be described in detail in the following embodiments.

[0033] The following will describe the application environment in which the instruction processing method provided in the embodiments of this application can be used.

[0034] Please see Figure 1 , Figure 1A schematic diagram illustrating an application environment that can be used for the instruction processing method provided in the embodiments of this application is shown. For example... Figure 1 As shown, it may include a processor 100 and a driver 200. The processor 100 may include an instruction dispatch unit 110, a scheduler 120, and a sub-computing engine 130. The driver 200 may embed a compiler 210. The processor 100 and the driver 200 can run on servers, personal computers, the cloud, etc. It is understood that the processor 100 and the driver 200 can run on the same platform, for example, both on a server; or they can run on different platforms, for example, the processor 100 on a personal computer and the driver 200 on a server. No specific limitation is made here. In a specific implementation, the compiler 210 can be used to compile relevant instructions, the instruction dispatch unit 110 can be used to read the relevant instructions, the scheduler 120 can be used to schedule and control the relevant instructions, and the sub-computing engine 130 can be used to execute the relevant instructions.

[0035] Please see Figure 2 , Figure 2 A flowchart illustrating an embodiment of the instruction processing method provided in this application is shown. This method involves a compiler-defined check instruction inserted before a function instruction containing a data hazard, allowing the processor to execute the function instruction according to the check instruction's directive. This software-defined approach combined with hardware execution detects and resolves data dependencies between instructions, improving processing efficiency while simplifying hardware design. The following will focus on... Figure 2 The process shown will be described in detail. In this embodiment, the instruction processing method is applied to the compiler, and the instruction processing method may specifically include the following steps:

[0036] Step S110: Compile multiple function instructions.

[0037] A compiler is a software tool that converts source code written in high-level programming languages ​​(such as C, C++, Java, etc.) into low-level code (such as machine language or bytecode) that a computer can directly execute. In this embodiment, the compiler mainly generates instructions that the hardware (such as the processor in this embodiment) can execute. Optionally, the compiler can work offline, that is, it can be independent of the hardware. It can compile the relevant instructions in advance on other hardware platforms (such as servers or computers) to form a file, usually a .bin file. Subsequently, the .bin file can be downloaded to the hardware used to execute the instructions, and the hardware will then parse it to execute these pre-compiled instructions.

[0038] Optionally, the multiple function instructions may include execution instructions and configuration instructions, abbreviated as EXEC and CFG instructions, used by the sub-computation engine to perform configuration and computation operations. The CFG and EXEC instructions can be defined according to actual functions, and will not be elaborated further here.

[0039] In this embodiment, the compiler compiles multiple functional instructions, which may include lexical analysis, syntax analysis, semantic analysis, intermediate code generation, optimization, final code generation, linking, etc., and will not be elaborated here.

[0040] Step S120: If a target function instruction with a data hazard is determined to exist among the plurality of function instructions during the compilation process, a check instruction is inserted before the target function instruction to obtain an instruction sequence. The check instruction is used to indicate that the target function instruction will be executed only if the amount of valid data in the first storage area corresponding to the target function instruction reaches the amount of valid data required for the execution of the target function instruction, and / or the free space in the second storage area corresponding to the target function instruction is sufficient to accommodate the data output by the target function instruction.

[0041] During the compilation phase of multiple functional instructions, the compiler can fully visualize the overall program's data flow graph and data dependency diagram. Therefore, for each set of functional instructions being compiled, the compiler can determine whether any data hazards exist based on these graphs. If a data hazard is identified, it means that among several concurrent functional instructions, one instruction depends on data from a preceding instruction but cannot obtain that data. Thus, the functional instructions containing data hazards can be identified as target functional instructions, and subsequent processing can be performed on these target instructions to resolve the problems caused by the data dependencies.

[0042] In this embodiment, when a target function instruction is determined, the compiler can generate a corresponding check command, abbreviated as CHK instruction, based on the target function instruction. Furthermore, the compiler can define the check command; specifically, it can be defined as an instruction to execute the target function instruction only if the amount of valid data in the first storage area corresponding to the target function instruction reaches the valid amount required for the execution of the target function instruction, and / or if the free space in the second storage area corresponding to the target function instruction is sufficient to accommodate the data output by the target function instruction. Optionally, the first storage area can be a region in the memory of the hardware used to execute the target function instruction that is bound to the target function instruction and used to provide input data, and the second storage area can be another region in the memory of the hardware used to execute the target function instruction that is bound to the target function instruction and used to provide data storage space.

[0043] It is understandable that for a target function instruction, if its execution depends on input data, then the prerequisite for its execution includes that the input data it depends on is ready and can be obtained. As an example, suppose the execution of the target function instruction requires 32 bits of valid data in the first storage area; then, this input data threshold can be defined as 32 bits. That is, the amount of valid data in the first storage area corresponding to the target function instruction can be defined to be at least 32 bits.

[0044] It is understandable that for a target function instruction, if it corresponds to output data, a prerequisite for its execution is that the corresponding data output storage space has sufficient free space to accommodate the generated data. For example, assuming the execution of the target function instruction will produce 64 bits of output data, then the threshold for the storage space of this output data can be defined as 64 bits. That is, it can be defined that the free space in the second storage area corresponding to the target function instruction must be at least 64 bits.

[0045] In this context, it's understandable that for a target function instruction, if its execution depends on input data, the prerequisites for its execution include that the input data is ready and available, and that the corresponding data output storage space has sufficient free space to accommodate the generated data. For example, assuming the target function instruction requires 32 bits of valid data and produces 64 bits of output data, then this input data threshold can be defined as 32 bits, and the output data storage space threshold can be defined as 64 bits. That is, it can be defined that the amount of valid data in the first storage area corresponding to the target function instruction must be at least 32 bits, and that the free space in the second storage area corresponding to the target function instruction must be at least 64 bits.

[0046] Therefore, in this embodiment, when a target function instruction is determined, the compiler can determine whether the target function instruction corresponds to input data and whether it corresponds to output data. Specifically, if it is determined that the target function instruction only corresponds to input data and not output data, a check instruction can be defined to instruct that the target function instruction is executed only if the amount of valid data in the first storage area corresponding to the target function instruction reaches the amount of valid data required for its execution. If it is determined that the target function instruction only corresponds to output data and not input data, a check instruction can be defined to instruct that the target function instruction is executed only if the available space in the second storage area corresponding to the target function instruction is sufficient to accommodate the output data of the target function instruction. If it is determined that the target function instruction corresponds to both input data and output data, a check instruction can be defined to instruct that the target function instruction is executed only if the amount of valid data in the first storage area corresponding to the target function instruction reaches the amount of valid data required for its execution, and the available space in the second storage area corresponding to the target function instruction is sufficient to accommodate the output data of the target function instruction.

[0047] In this process, the compiler, after determining the target function instruction and generating the check instruction, can insert a check instruction before the target function instruction to obtain the instruction sequence. By inserting the check instruction before the target function instruction, the hardware can execute the check instruction before executing the target function instruction. This allows the target function instruction to be executed based on the check instruction's indication; specifically, the target function instruction is executed only if the amount of valid data in the first memory area corresponding to the target function instruction meets the required quantity for execution, and / or if the available space in the second memory area corresponding to the target function instruction is sufficient to accommodate the data output by the target function instruction.

[0048] In one approach, multiple function instructions can form an initial instruction sequence based on the execution order of their actual functions. The compiler then determines the target function instructions from these instructions and inserts corresponding check instructions before them to form the final instruction sequence based on the initial instruction sequence. For example, assuming three target function instructions are determined from the multiple function instructions, check instructions corresponding to each of the three target function instructions can be generated and inserted before the respective target function instructions to form the final instruction sequence.

[0049] In some implementations, if it is determined that the target function instruction corresponds to input data, the compiler may define the check instruction to include the input buffer ID for determining the first storage area and the amount of valid data required for the execution of the target function instruction when generating the check instruction.

[0050] The input cache identifier can be used to determine the first storage area corresponding to the input data of the target function instruction, and the amount of valid data required for the execution of the target function instruction can be used to determine the amount of valid data that must be satisfied in the first storage area. If there are multiple first storage areas, the input cache identifier and the amount of valid data that must be satisfied are defined for each of the multiple first storage areas.

[0051] In some implementations, if it is determined that the target function instruction corresponds to output data, the compiler can define the check instruction to include the free space required to determine the output buffer ID of the second storage area and the data output by the target function instruction when generating the check instruction.

[0052] The output buffer identifier is used to determine the second storage area corresponding to the output data of the target function instruction. The free space required for the output data of the target function instruction is used to determine the completion of the target function instruction. The second storage area needs to ensure that there is corresponding free space to support the writing of output data. If there are multiple second storage areas, the output buffer identifier and the free space required for each second storage area are defined separately.

[0053] Of course, if it is determined that the target function instruction corresponds to input data and output data, the compiler can define the check instruction to include, when generating the check instruction, the input buffer identifier of the first storage area and the amount of valid data required for the execution of the target function instruction, as well as the free space required to determine the output buffer identifier of the second storage area and the data output by the target function instruction. This will not be elaborated further here.

[0054] In some implementations, when generating inspection instructions, the compiler can define the inspection instructions to include a bitmask. The bitmask can be used to control which data elements need to be processed or inspected. In this embodiment, each bit in the bitmask can correspond to a first storage region or a second storage region. The bitmask is used to indicate whether to inspect the valid data amount in the corresponding first storage region and whether to inspect the empty space in the corresponding second storage region, based on the value of each bit. It is understood that if it is determined that the target function instruction does not correspond to input data, the bitmask can indicate not to inspect the valid data amount in the corresponding first storage region; similarly, if it is determined that the target function instruction does not correspond to output data, the bitmask can indicate not to inspect the empty space in the corresponding second storage region.

[0055] In this implementation, the bitmask is represented by the symbol "mask," and each bit in the bitmask is represented by the symbol "bit." Each bit in the mask corresponds to a specific input buffer or output buffer (in this embodiment, corresponding to the first storage area or the second storage area). Optionally, it can be defined that when the corresponding bit is 1, it indicates that the corresponding input buffer or output buffer needs to be checked; if the corresponding bit is 0, then the corresponding input buffer or output buffer does not need to be checked. It is understood that the mask is not mandatory. If the thresholds or reserved values ​​of multiple inputs or outputs are recorded in a separately defined manner, then the mask does not need to be set. However, when multiple input or output parameters share the same storage resource, it needs to be defined to indicate which input or output the corresponding value belongs to.

[0056] It should be noted that while the instruction format is fixed, the number of input and output buffers for each instruction may differ. Suppose that in the current subgraph, instruction A has 1 input buffer and 1 output buffer, and instruction B has 2 input buffers and 2 output buffers. For consistency, this embodiment uses the maximum number, defining the mask in the check instruction as 4 bits: 2 bits for the input buffer and 2 bits for the output buffer. Therefore, the mask in the check instruction preceding instruction A will be set to 'b0101', while the mask in the check instruction preceding instruction B will be set to 'b1111'.

[0057] In this context, it's understandable that for a mask in the form of bxxxx, the first two bits (xx) from right to left represent the input buffer, and the last two bits (xx) from right to left also represent the input buffer. Therefore, in b0101, the first two bits from right to left are "01", indicating that one input buffer is needed, and the last two bits from right to left are "01", indicating that one output buffer is needed. This means that instruction A has one input buffer and one output buffer. In b1111, the first two bits from right to left are "11", indicating that two input buffers are needed, and the last two bits from right to left are "11", indicating that two output buffers are needed. This means that instruction B has two input buffers and two output buffers.

[0058] To achieve higher pipeline utilization efficiency, the AI ​​processor may allow another function instruction to be issued before the previous one has been completed, thus enabling out-of-order execution of instructions. In this embodiment, to ensure that corresponding resources (valid data or spare space) are not repeatedly allocated to multiple function instructions, in addition to checking whether the resource quantity reaches a preset threshold, a mechanism for reserving and recording resources can be implemented to ensure that the same data or space is not allocated to multiple function instructions (this error is referred to as data or space over-allocation).

[0059] In some implementations, the reservation mechanism can be implemented by configuring corresponding data reservation information in the inspection instructions. Specifically, when generating inspection instructions, the compiler can define the inspection instructions to include data reservation information, wherein the data reservation information is used to indicate the amount of valid data that needs to be reserved in the first storage area, and / or the amount of free space that needs to be reserved in the second storage area.

[0060] The first storage area needs to retain a certain amount of valid data, which is used to represent the data that will be used as input data for subsequent target function instructions. This data cannot be used as input data by other function instructions at the same time. Of course, if there are multiple first storage areas, the amount of valid data to be retained is defined for each of the multiple first storage areas.

[0061] The second storage area needs to reserve some free space to represent the output data of the target function instruction after it is allowed to be executed but before it is completed. Of course, if there are multiple second storage areas, the free space to be reserved is defined for each of the multiple second storage areas.

[0062] Optionally, when determining the target function instruction, the compiler can determine whether the target function instruction corresponds to input data and whether it corresponds to output data. Specifically, if it is determined that the target function instruction only corresponds to input data and not output data, data reservation information can be defined to indicate the amount of valid data that needs to be reserved in the first storage area. If it is determined that the target function instruction only corresponds to output data and not input data, data reservation information can be defined to indicate the amount of free space that needs to be reserved in the second storage area. If it is determined that the target function instruction corresponds to both input data and output data, data reservation information can be defined to indicate the amount of valid data that needs to be reserved in the first storage area and the amount of free space that needs to be reserved in the second storage area.

[0063] Step S130: Store the instruction sequence so that the processor can read the instruction sequence and execute the target function instruction according to the instructions of the check instruction.

[0064] In this embodiment, the compiler can store the instruction sequence upon obtaining it. It is understood that after storing the instruction sequence, the hardware (processor) used to execute the function instruction can read the instruction sequence and execute the target function instruction according to the instructions of the check instruction.

[0065] In some implementations, when the compiler obtains the instruction sequence, it can generate a .bin file based on the instruction sequence and store the .bin file so that the processor can read the .bin file, parse it to obtain the instruction sequence, and execute the target function instruction according to the instructions of the checked instructions.

[0066] Optionally, upon obtaining the instruction sequence, the compiler may store it in the target address space of the other hardware platform on which it runs. For example, if the compiler runs on a server, it may store the instruction in the server's target address space; if the compiler runs on a computer, it may store the instruction in the computer's target address space. Alternatively, upon obtaining the instruction sequence, the compiler may store it in the target address space of a server connected to the other hardware platform on which it runs. For example, if the compiler runs on a computer, it may store the instruction in the target address space of a server connected to the computer, and so on. This is not a limitation.

[0067] It is understandable that the checking instructions are generated by the compiler during the compilation phase, and the compiler determines the corresponding insertion order. These instructions are used to check the data dependencies between functional instructions. Furthermore, when generating the checking instructions, the compiler defines relevant data thresholds (such as the effective data volume in the first storage area and the free space in the second storage area). Subsequently, the processor performs the data dependency checks and instruction synchronization. Therefore, by ensuring that the instruction execution order strictly follows data dependencies, and by supporting out-of-order and concurrent execution of instructions as much as possible, overall execution efficiency can be improved. Moreover, the hardware does not need to concern itself with the overall program's computational flow graph and data dependency graph. The input and output requirements of each functional instruction are defined and set by the software, and whether checks are needed is also determined by the software. Therefore, the hardware does not need to maintain a complete computational order framework and computational logic flow graph in real time, resulting in low hardware implementation complexity, ease of verification, and high scalability.

[0068] One embodiment of this application provides an instruction processing method in which a compiler compiles multiple functional instructions. If, during the compilation process, a target functional instruction with a data hazard is identified among the multiple functional instructions, a check instruction is inserted before the target functional instruction to obtain an instruction sequence. The check instruction indicates that the target functional instruction will only be executed if the amount of valid data in the first storage area corresponding to the target functional instruction reaches the amount of valid data required for the execution of the target functional instruction, and / or if the free space in the second storage area corresponding to the target functional instruction is sufficient to accommodate the data output by the target functional instruction. The instruction sequence is then stored so that the processor can read the instruction sequence and execute the target functional instruction according to the instructions of the check instruction. This method detects and resolves data dependencies between instructions through a software-defined approach combined with hardware execution, thereby improving processing efficiency while simplifying hardware design.

[0069] Please see Figure 3 , Figure 3 A flowchart illustrating an embodiment of the instruction processing method provided in this application is shown. The following will focus on... Figure 3 The process shown will be described in detail. In this embodiment, the instruction processing method applied to the compiler may specifically include the following steps:

[0070] Step S210: Compile multiple function instructions.

[0071] For a detailed description of step S210, please refer to step S110, which will not be repeated here.

[0072] Step S220: If, during the compilation process, it is determined that a target function instruction among the plurality of function instructions contains a data hazard, then the check instruction is inserted before the target function instruction, and a data reservation instruction is inserted between the check instruction and the target function instruction to obtain the instruction sequence. The check instruction indicates that the target function instruction will only be executed if the amount of valid data in the first storage area corresponding to the target function instruction reaches the amount of valid data required for the execution of the target function instruction, and / or if the free space in the second storage area corresponding to the target function instruction is sufficient to accommodate the data output by the target function instruction. The data reservation instruction indicates the amount of valid data that needs to be reserved in the first storage area, and / or the amount of free space that needs to be reserved in the second storage area.

[0073] To achieve higher pipeline utilization efficiency, the AI ​​processor may allow another function instruction to be issued before the previous one has been completed, thus enabling out-of-order execution of instructions. In this embodiment, to ensure that corresponding resources (valid data or spare space) are not repeatedly allocated to multiple function instructions, in addition to checking whether the resource quantity reaches a preset threshold, a mechanism for reserving and recording resources can be implemented to ensure that the same data or space is not allocated to multiple function instructions (this error is referred to as data or space over-allocation).

[0074] In some implementations, the reservation mechanism can be implemented using separate data reservation instructions, such as the corresponding preserve command (PSV instruction) to indicate the amount of data or space that the hardware needs to reserve. In this embodiment, given a target function instruction, the compiler can generate check instructions and data reservation instructions based on the target function instruction. Given the target function instruction, check instructions, and data reservation instructions, a check instruction can be inserted before the target function instruction, and a data reservation instruction can be inserted between the check instruction and the target function instruction to obtain the instruction sequence.

[0075] Understandably, since the data reservation instruction is inserted between the check instruction and the target function instruction, the hardware can execute the data reservation instruction after the check instruction is completed and before the target function instruction is issued, thereby reserving the corresponding resources.

[0076] When generating data reservation instructions, the compiler can define these instructions to indicate the amount of valid data that needs to be reserved in the first storage area, and / or the amount of free space that needs to be reserved in the second storage area.

[0077] The first storage area needs to retain a certain amount of valid data, which is used to represent the data that will be used as input data for subsequent target function instructions. This data cannot be used as input data by other function instructions at the same time. Of course, if there are multiple first storage areas, the amount of valid data to be retained is defined for each of the multiple first storage areas.

[0078] The second storage area needs to reserve some free space to represent the space needed to store output data after the subsequent target function instructions are allowed to be executed but before they are completed. Of course, if there are multiple second storage areas, the free space to be reserved is defined for each of the multiple second storage areas.

[0079] Optionally, when determining the target function instruction, the compiler can determine whether the target function instruction corresponds to input data and whether it corresponds to output data. Specifically, if it is determined that the target function instruction only corresponds to input data and not output data, a data reservation instruction can be defined to indicate the amount of valid data that needs to be reserved in the first storage area. If it is determined that the target function instruction only corresponds to output data and not input data, a data reservation instruction can be defined to indicate the amount of free space that needs to be reserved in the second storage area. If it is determined that the target function instruction corresponds to both input data and output data, a data reservation instruction can be defined to indicate the amount of valid data that needs to be reserved in the first storage area and the amount of free space that needs to be reserved in the second storage area.

[0080] In some implementations, if it is determined that the target function instruction corresponds to input data, the compiler may define the data reservation instruction to include an input buffer ID for determining the first storage area and the effective amount of data required for the execution of the target function instruction when generating the data reservation instruction.

[0081] In some implementations, if it is determined that the target function instruction corresponds to output data, the compiler can define the data reservation instruction to include the free space required to determine the output buffer ID of the second storage area and the data output by the target function instruction when generating the data reservation instruction.

[0082] Step S230: Store the instruction sequence so that the processor can read the instruction sequence and execute the target function instruction according to the instructions of the check instruction.

[0083] For a detailed description of step S230, please refer to step S130, which will not be repeated here.

[0084] An embodiment of this application provides an instruction processing method that, compared to... Figure 2The instruction processing method shown in this embodiment further inserts a data reservation instruction between the inspection instruction and the target function. The data reservation instruction is used to indicate the amount of valid data that needs to be reserved in the first storage area and / or the amount of free space that needs to be reserved in the second storage area. This can avoid the risk of valid data being illegally overwritten or insufficient free space due to over-issuance of resources.

[0085] Please see Figure 4 , Figure 4 A flowchart illustrating an embodiment of the instruction processing method provided in this application is shown. The following will focus on... Figure 4 The process shown will be described in detail. In this embodiment, the instruction processing method is applied to a compiler, and the instruction processing method may specifically include the following steps:

[0086] Step S310: Compile multiple function instructions.

[0087] For a detailed description of step S310, please refer to step S110, which will not be repeated here.

[0088] Step S320: If, during the compilation process, it is determined that a target function instruction among the plurality of function instructions contains a data hazard, then the check instruction is inserted before the target function instruction, and an update instruction is inserted after the target function instruction to obtain the instruction sequence. The check instruction instructs that the target function instruction be executed only if the amount of valid data in the first storage area corresponding to the target function instruction reaches the amount of valid data required for the execution of the target function instruction, and / or if the free space in the second storage area corresponding to the target function instruction is sufficient to accommodate the data output by the target function instruction. The update instruction instructs that, upon completion of the execution of the target function instruction, the data space in the first storage area corresponding to the target function instruction be released, and / or the free space in the second storage area be updated.

[0089] In some implementations, given a target function instruction, the compiler can generate a corresponding update command, or UPD instruction, based on that instruction. Furthermore, the compiler can define the update command; specifically, it can be defined as an instruction to release the data space corresponding to the target function instruction in the first storage area and / or update the free space in the second storage area after the target function instruction has been executed. In this embodiment, given a check instruction, a target function instruction, and an update command, a check instruction can be inserted before the target function instruction, and an update command can be inserted after the target function instruction to obtain an instruction sequence.

[0090] It is understandable that, since the update instruction is inserted after the target function instruction, the hardware can execute the update instruction after the target function instruction has been executed, that is, release the data space in the first storage area corresponding to the target function instruction, and / or update the free space in the second storage area.

[0091] Specifically, releasing the data space corresponding to the target function instruction in the first storage area is used to represent the input data in the first storage area for the target function instruction. The corresponding data space can be released and marked as free space. Of course, if there are multiple first storage areas, the data space corresponding to the target function instruction in each of the multiple first storage areas needs to be released separately.

[0092] Specifically, updating the free space in the second storage area indicates that the free space in the second storage area used to store the output data of the target function instructions needs to be updated. Of course, if there are multiple second storage areas, the free space in each of the multiple second storage areas needs to be updated separately.

[0093] Optionally, when determining the target function instruction, the compiler can determine whether the target function instruction corresponds to input data and whether it corresponds to output data. Specifically, if it is determined that the target function instruction only corresponds to input data and not output data, an update instruction can be defined to instruct the release of the data space corresponding to the target function instruction in the first storage area. If it is determined that the target function instruction only corresponds to output data and not input data, an update instruction can be defined to instruct the updating of the free space in the second storage area. If it is determined that the target function instruction corresponds to both input data and output data, an update instruction can be defined to instruct the release of the data space corresponding to the target function instruction in the first storage area and the updating of the free space in the second storage area.

[0094] In some implementations, if it is determined that the target function instruction corresponds to input data, the compiler may define the update instruction to include an input buffer ID for determining the first storage area and the input data for the target function instruction when generating the update instruction.

[0095] In some implementations, if it is determined that the target function instruction corresponds to output data, the compiler may define the update instruction to include an output buffer ID for determining the output buffer ID of the second storage area and the amount of data output by the target function instruction when generating the update instruction.

[0096] Step S330: Store the instruction sequence so that the processor can read the instruction sequence and execute the target function instruction according to the instructions of the check instruction.

[0097] For a detailed description of step S330, please refer to step S130, which will not be repeated here.

[0098] An embodiment of this application provides an instruction processing method that, compared to... Figure 2 In the instruction processing method shown in this embodiment, an update instruction is inserted after the target function instruction. The update instruction is used to indicate that when the target function instruction is completed, the data space corresponding to the target function instruction in the first storage area is released, and / or the free space in the second storage area is updated, so as to ensure the normal use of the data space and free space by subsequent instructions, so as to ensure the normal and smooth execution of the instructions.

[0099] Please see Figure 5 , Figure 5 This paper presents a hardware design scheme for implementing instruction synchronization and scheduling using check instructions, data reservation instructions, and update instructions. Figure 5 The processor shown can be a Neural Processing Unit (NPU), a Digital Signal Processor (DSP), a Central Processing Unit (CPU), etc., and is not limited thereto. This processor may include hardware units such as an instruction dispatcher, a scheduler, and a sub-engine. The scheduler may include a callback module, which will be discussed in subsequent embodiments. Figure 5 The above-mentioned hardware units provide a detailed explanation of the instruction processing methods.

[0100] In this embodiment, the processor may include one or more processing units or sub-computation engines, denoted as sub-engine1, sub-engine2, etc. A sub-engine is defined as a processing unit capable of architecture-level parallelism. For example, while sub-engine1 is processing a block of data, sub-engine2 can synchronously prefetch the next block of data. In AI processors, sub-engines often correspond to parallelizable sub-computation engines, such as DMA sub-computation engines, Vector sub-computation engines, Matrix sub-computation engines, etc., and are not limited here.

[0101] It is understandable that the smallest computational node in each sub-computation engine is an atomic computational node. Each atomic computational node corresponds to its own dedicated input and output data cache space. A single atomic computational node may contain one or more instructions, but the data space involved in these instructions is confined to the data cache space of this atomic computational node. In AI computing, an atomic computational node is often defined as an operator. Due to the limitations of on-chip memory, in AI processors, a set of atomic nodes is often defined as a subgraph. Data processing of a subgraph can often be completed in on-chip memory.

[0102] in addition, Figure 5 A scoreboard is used to record and update data dependencies. The scoreboard includes information about the corresponding data's consumer, producer, total data space, and remaining free space. It's understood that the scoreboard is a representation of information stored in the storage space. The instruction synchronization and scheduling scheme proposed in this embodiment is not limited to using a scoreboard for maintaining data dependencies; other related technologies such as map tables can also be adapted to this scheme.

[0103] Please see Figure 6 , Figure 6 A flowchart illustrating an instruction processing method provided in an embodiment of this application is shown. This method involves a compiler defining a check instruction that is inserted before a function instruction containing a data hazard. The processor then executes the function instruction according to the check instruction's directive. This method, through a combination of software definition and hardware execution, detects and resolves data dependencies between instructions, improving processing efficiency while simplifying hardware design. In this embodiment, the processor includes an instruction dispatch unit, a scheduler, and a sub-computing engine. The following will focus on... Figure 6 The process shown will be described in detail. The instruction processing method may specifically include the following steps:

[0104] Step S410: The instruction dispatch unit reads the instruction sequence, wherein the instruction sequence is obtained by the compiler inserting a check instruction before the target function instruction when it determines that there is a data hazard among the multiple function instructions during the compilation process of multiple function instructions. The check instruction is used to instruct that the target function instruction is executed only if the parameter information corresponding to the target function instruction meets the specified parameter information. The specified parameter information includes that the amount of effective data in the first storage area corresponding to the target function instruction reaches the amount of effective data required for the execution of the target function instruction, and / or that the free space in the second storage area corresponding to the target function instruction is sufficient to accommodate the data output by the target function instruction.

[0105] The instruction sequence can be generated through steps S110-S130 above, and will not be described in detail here.

[0106] In this embodiment, the instruction distribution unit can read the instruction sequence. For example, if the instruction sequence is stored in the target address space, the instruction distribution unit can read the instruction sequence from the target address space.

[0107] Step S420: The scheduler executes the inspection instruction, and if it determines that the parameter information corresponding to the target function instruction meets the specified parameter information, it releases the target function instruction.

[0108] Optionally, the scheduler can be responsible for executing check instructions, data reservation instructions, and update instructions. Simultaneously, the scheduler can update and maintain relevant data dependency graphs based on these instructions. A data dependency graph is a graphical representation used to show the dependencies between data. Such graphs are very useful in database design, software engineering, and data analysis, helping people better understand the relationships and constraints between data.

[0109] In this embodiment, the scheduler can be responsible for executing the check instructions and determining whether to allow the target function instruction based on the execution status of the check instructions. That is, the scheduler executes the check instructions and allows the target function instruction if it determines that the amount of valid data in the first storage area corresponding to the target function instruction reaches the amount of valid data required for the execution of the target function instruction, and / or that the free space in the second storage area corresponding to the target function instruction is sufficient to accommodate the data output by the target function instruction.

[0110] In some implementations, when the target function instruction corresponds to input data, the check instruction includes an input cache identifier and the amount of valid data required to execute the target function instruction. Based on this, when executing the check instruction, the scheduler queries the data dependency graph to determine the amount of valid data in the first storage area corresponding to the input cache identifier. If the amount of valid data in the first storage area reaches the amount of valid data required to execute the target function instruction, the scheduler allows the target function instruction to proceed. Alternatively, when executing the check instruction, the scheduler first queries the data dependency graph based on the input cache identifier in the check instruction, and then confirms whether the amount of valid data in the first storage area reaches the amount of valid data required to execute the target function instruction. If it does, the scheduler can allow the target function instruction to proceed.

[0111] In some implementations, when the target function instruction corresponds to output data, the check instruction includes an output cache identifier and the available space required for the data output by the target function instruction. Based on this, when executing the check instruction, the scheduler queries the data dependency graph to determine the available space in the second storage area corresponding to the output cache identifier. If the available space in the second storage area is sufficient to accommodate the data output by the target function instruction, the scheduler allows the target function instruction to proceed. Alternatively, when executing the check instruction, the scheduler first queries the data dependency graph based on the output cache identifier in the check instruction, and then confirms whether the available space in the second storage area is sufficient to accommodate the data output by the target function instruction. If sufficient, the scheduler can allow the target function instruction to proceed.

[0112] In some implementations, when the target function instruction corresponds to input data and output data, the check instruction includes an input cache identifier and the amount of valid data required to execute the target function instruction, as well as the free space required to include the output cache identifier and the data output by the target function instruction. Based on this, when executing the check instruction, the scheduler queries the data dependency graph and then determines whether the amount of valid data in the first storage area corresponding to the input cache identifier reaches the amount of valid data required to execute the target function instruction, and whether the free space in the second storage area corresponding to the output cache identifier is sufficient to accommodate the data output by the target function instruction. If the amount of valid data in the first storage area reaches the amount of valid data required to execute the target function instruction, and the free space in the second storage area is sufficient to accommodate the data output by the target function instruction, then the scheduler allows the target function instruction to proceed.

[0113] In some implementations, the inspection instruction may include a bitmask, wherein, in this embodiment, each bit of the bitmask corresponds to a first storage region or a second storage region. The scheduler executes the inspection instruction and, based on the value of each bit in the bitmask, determines whether to inspect the valid data volume corresponding to the first storage region and whether to inspect the free space corresponding to the second storage region.

[0114] Please see Figure 7 , Figure 7 A flowchart illustrating the execution of inspection instructions provided in an embodiment of this application is shown. Figure 7As shown, a bitmask can be used to determine whether to check the output space (i.e., the free space in the second storage area). If so, the data dependency graph can be consulted to confirm whether the free output space meets the threshold (i.e., whether the free space in the second storage area is sufficient to accommodate the data output by the target function instruction). A bitmask can also be used to determine whether to check the valid data for input 0 (i.e., the amount of valid data in the first storage area when the bit is 0). If so, the data dependency graph can be consulted to confirm whether the valid data for Input Buffer 0 meets the threshold (i.e., whether the amount of valid data in the first storage area when the bit is 0 reaches the amount of valid data required for the execution of the target function instruction). Similarly, a bitmask can be used to determine whether to check the valid data for input 1 (i.e., the amount of valid data in the first storage area when the bit is 1). If so, the data dependency graph can be consulted to confirm whether the valid data for Input Buffer 1 meets the threshold (i.e., whether the amount of valid data in the first storage area when the bit is 1 reaches the amount of valid data required for the execution of the target function instruction).

[0115] Optionally, if it is determined that the target function instruction does not correspond to input data, a bitmask can be used to indicate whether to check the valid data volume in the corresponding first storage area. For example, by setting the corresponding bit to 0, the scheduler can choose not to check the valid data volume in the corresponding first storage area when it determines that the bit in the bitmask is 0. Similarly, if it is determined that the target function instruction does not correspond to output data, a bitmask can be used to indicate whether to check the free space in the corresponding second storage area. For example, by setting the corresponding bit to 0, the scheduler can choose not to check the free space in the corresponding second storage area when it determines that the bit in the bitmask is 0.

[0116] Step S430: The sub-computing engine executes the target function instruction.

[0117] In this embodiment, if the scheduler allows the target function instruction, the sub-computing engine can execute the target function instruction.

[0118] When distributing function instructions, the instruction distribution unit can distribute the corresponding function instructions to the re-order buffer based on the sub-engine ID carried in the function instructions. Subsequently, the sub-computing engine corresponding to the engine ID can execute the function instructions.

[0119] In some implementations, the number of sub-computing engines can be one or more. When there are multiple sub-computing engines, each sub-computing engine can correspond to a single instruction cache region, or each sub-computing engine can correspond to its own dedicated instruction cache region. Optionally, when there are multiple sub-computing engines, this embodiment sets each sub-computing engine to correspond to its own dedicated instruction cache region to avoid backpressure from a single sub-computing engine causing the entire processor to become blocked at the instruction dispatch unit, thereby leading to performance degradation or even deadlock.

[0120] In some implementations, when there are multiple sub-computing engines and each sub-computing engine has its own instruction cache area, the instruction distribution unit can determine the engine identifier carried by the target function instruction for the target function unit, determine the corresponding target sub-computing engine from the multiple sub-computing engines based on the engine identifier, distribute the target function instruction to the instruction cache area corresponding to the target sub-computing engine, and then the target sub-computing engine can read the target function instruction from the corresponding instruction cache area for execution.

[0121] Since different instructions are distributed to different sub-computing engines for execution, and the scheduler can see all the instructions, the current mechanism can resolve the data dependency between different instructions within the same sub-computing engine, as well as the dependency between two instructions distributed to different sub-computing engines (indirectly achieving the resolution of data dependency between engines).

[0122] It is understandable that in this embodiment, all instruction data dependency checks and updates, instruction scheduling and distribution, and instruction blocking and recovery are handled by the scheduler. Each sub-computing engine only needs to execute the instruction sequence issued by the scheduler sequentially, without needing to perform additional checks or synchronization.

[0123] An embodiment of this application provides an instruction processing method in which an instruction dispatch unit reads an instruction sequence. This instruction sequence is obtained by the compiler during the compilation of multiple functional instructions. When the compiler determines that a target functional instruction contains a data hazard, it inserts a check instruction before the target functional instruction. The check instruction indicates that the target functional instruction will only be executed if the amount of valid data in the first storage area corresponding to the target functional instruction reaches the amount of valid data required for the execution of the target functional instruction, and / or if the free space in the second storage area corresponding to the target functional instruction is sufficient to accommodate the data output by the target functional instruction. The scheduler executes the check instruction and, if it determines that the amount of valid data in the first storage area reaches the amount of valid data required for the execution of the target functional instruction, and / or if the free space in the second storage area is sufficient to accommodate the data output by the target functional instruction, it allows the target functional instruction to proceed. The sub-computing engine then executes the target functional instruction. This method, through a combination of software definition and hardware execution, detects and resolves data dependencies between instructions, thereby improving processing efficiency while simplifying hardware design.

[0124] Please see Figure 8 , Figure 8 A schematic flowchart of an instruction processing method according to an embodiment of this application is shown. In this embodiment, the processor includes an instruction dispatch unit, a scheduler, and a sub-computing engine. The following will focus on... Figure 8 The process shown will be described in detail. The instruction processing method may specifically include the following steps:

[0125] Step S510: The instruction dispatch unit reads the instruction sequence, wherein the instruction sequence is obtained by the compiler inserting a check instruction before the target function instruction when it determines that there is a data hazard among the multiple function instructions during the compilation process of multiple function instructions. The check instruction is used to instruct that the target function instruction is executed only if the parameter information corresponding to the target function instruction meets the specified parameter information. The specified parameter information includes that the effective data amount in the first storage area corresponding to the target function instruction reaches the effective data amount required for the execution of the target function instruction, and / or that the free space in the second storage area corresponding to the target function instruction is sufficient to accommodate the data output by the target function instruction. The check instruction includes data reservation information.

[0126] Step S520: The scheduler executes the inspection instruction, and if it determines that the parameter information corresponding to the target function instruction meets the specified parameter information, it releases the target function instruction.

[0127] For a detailed description of steps S510-S520, please refer to steps S110-S120, which will not be repeated here.

[0128] Step S530: If the inspection instruction is completed, the scheduler updates the data dependency graph according to the data reservation information to obtain the updated first data dependency graph, wherein the first storage area retains the amount of valid data, and / or the second storage area reserves the free space.

[0129] Optionally, when generating the check instructions, the compiler may define the check instructions to include data reservation information, wherein the data reservation information is used to indicate the amount of valid data that needs to be reserved in the first storage area, and / or the amount of free space that needs to be reserved in the second storage area.

[0130] In this embodiment, the scheduler executes a check instruction, and upon completion of the check instruction (referred to as "Retire"), the scheduler needs to update the data dependency graph to reserve relevant resources in the first and / or second storage areas for subsequent execution of the target function instruction. This is to prevent the risk of valid data being illegally overwritten or insufficient remaining free space due to over-issuance of resources. Therefore, if it is determined that the check instruction has been completed, the scheduler can update the data dependency graph based on the data reservation information to obtain the updated first data dependency graph. It can be understood that in the first data dependency graph, the first storage area retains the amount of valid data required by the target function instruction, and / or, the second storage area reserves sufficient free space to accommodate the data output by the target function instruction.

[0131] In some implementations, if it is determined that the target function instruction corresponds only to input data and not output data, the data reservation information can be used only to indicate the amount of valid data that needs to be reserved in the first storage area. Accordingly, in the first data dependency graph, only the first storage area retains the amount of valid data required by the target function instruction. If it is determined that the target function instruction corresponds only to output data and not input data, the data reservation information can be used only to indicate the amount of free space that needs to be reserved in the second storage area. Accordingly, in the first data dependency graph, only the second storage area reserves enough free space to accommodate the data output by the target function instruction. If it is determined that the target function instruction corresponds to both input data and output data, the data reservation information can be used to indicate the amount of valid data that needs to be reserved in the first storage area and the amount of free space that needs to be reserved in the second storage area. Accordingly, in the first data dependency graph, the first storage area retains the amount of valid data required by the target function instruction, and the second storage area reserves enough free space to accommodate the data output by the target function instruction.

[0132] Step S540: The sub-computing engine executes the target function instruction.

[0133] An embodiment of this application provides an instruction processing method that, compared to... Figure 6 The instruction processing method shown in the figure, when checking that the instruction has been executed, the scheduler updates the data dependency graph according to the data reservation information in the checked instruction to obtain the updated first data dependency graph. In the first data dependency graph, the first storage area reserves the amount of valid data required by the target function instruction, and / or the second storage area reserves the free space required for the output data of the target function instruction. This can avoid the risk of over-allocation of resources leading to the illegal overwriting of valid data or insufficient free space.

[0134] Please see Figure 9 , Figure 9 A schematic flowchart of an instruction processing method according to an embodiment of this application is shown. In this embodiment, the processor includes an instruction dispatch unit, a scheduler, and a sub-computing engine. The following will focus on... Figure 9 The process shown will be described in detail. The instruction processing method may specifically include the following steps:

[0135] Step S610: The instruction dispatch unit reads the instruction sequence, wherein the instruction sequence is obtained by the compiler inserting a check instruction before the target function instruction when it determines that there is a data hazard among the multiple function instructions during the compilation process of multiple function instructions. The check instruction is used to indicate that the target function instruction is executed only if the parameter information corresponding to the target function instruction meets the specified parameter information. The specified parameter information includes that the effective data amount in the first storage area corresponding to the target function instruction reaches the effective data amount required for the execution of the target function instruction, and / or that the free space in the second storage area corresponding to the target function instruction is sufficient to accommodate the data output by the target function instruction.

[0136] Step S620: The scheduler executes the inspection instruction, and if it determines that the parameter information corresponding to the target function instruction meets the specified parameter information, it releases the target function instruction.

[0137] For a detailed description of steps S610-S620, please refer to steps S110-S120, which will not be repeated here.

[0138] Step S630: If the check instruction is completed, the scheduler updates the data dependency graph according to the data reservation instruction to obtain the updated second data dependency graph, wherein, in the second data dependency graph, the first storage area retains the amount of valid data, and / or, the second storage area reserves the free space.

[0139] Optionally, when the target function instruction is determined, the compiler can generate a check instruction and a data reservation instruction based on the target function instruction. When the target function instruction, check instruction, and data reservation instruction are determined, a check instruction can be inserted before the target function instruction, and a data reservation instruction can be inserted between the check instruction and the target function instruction. The data reservation instruction is used to indicate the amount of valid data that needs to be reserved in the first storage area, and / or the amount of free space that needs to be reserved in the second storage area.

[0140] In this embodiment, the scheduler executes a check instruction, and upon completion of the check instruction (referred to as "Retire"), the scheduler needs to update the data dependency graph to reserve relevant resources in the first and / or second storage areas for subsequent execution of the target function instruction. This is to prevent the risk of valid data being illegally overwritten or insufficient remaining free space due to over-issuance of resources. Therefore, if it is determined that the check instruction has been completed, before the subsequent target function instruction is issued, the scheduler can execute a data reservation instruction to update the data dependency graph, obtaining an updated second data dependency graph. It is understood that in the second data dependency graph, the first storage area retains the amount of valid data required by the target function instruction, and / or, the second storage area reserves sufficient free space to accommodate the data output by the target function instruction.

[0141] In some implementations, if it is determined that the target function instruction corresponds only to input data and not output data, the data reservation instruction can be used only to indicate the amount of valid data that needs to be reserved in the first storage area. Accordingly, in the second data dependency graph, only the first storage area retains the amount of valid data required by the target function instruction. If it is determined that the target function instruction corresponds only to output data and not input data, the data reservation instruction can be used only to indicate the amount of free space that needs to be reserved in the second storage area. Accordingly, in the second data dependency graph, only the second storage area reserves enough free space to accommodate the data output by the target function instruction. If it is determined that the target function instruction corresponds to both input data and output data, the data reservation instruction can be used to indicate the amount of valid data that needs to be reserved in the first storage area and the amount of free space that needs to be reserved in the second storage area. Accordingly, in the second data dependency graph, the first storage area retains the amount of valid data required by the target function instruction, and the second storage area reserves enough free space to accommodate the data output by the target function instruction.

[0142] Step S640: The sub-computing engine executes the target function instruction.

[0143] An embodiment of this application provides an instruction processing method that, compared to... Figure 6The instruction processing method shown in this embodiment further inserts a data reservation instruction between the check instruction and the target function instruction. When the check instruction is completed, the scheduler updates the data dependency graph according to the data reservation instruction to obtain the updated second data dependency graph. In the second data dependency graph, the first storage area stores the amount of valid data required by the target function instruction, and / or the second storage area reserves the free space required for the output data of the target function instruction. This can avoid the risk of over-allocation of resources leading to illegal overwriting of valid data or insufficient free space.

[0144] Please see Figure 10 , Figure 10 A flowchart illustrating an embodiment of the instruction processing method provided in this application is shown. In this embodiment, the processor includes an instruction dispatch unit, a scheduler, and a sub-computing engine. The scheduler includes a callback module, which will be discussed below. Figure 10 The process shown will be described in detail. The instruction processing method may specifically include the following steps:

[0145] Step S710: The instruction dispatch unit reads the instruction sequence, wherein the instruction sequence is obtained by the compiler inserting a check instruction before the target function instruction when it determines that there is a data hazard among the multiple function instructions during the compilation process of multiple function instructions. The check instruction is used to instruct that the target function instruction is executed only if the parameter information corresponding to the target function instruction meets the specified parameter information. The specified parameter information includes that the amount of effective data in the first storage area corresponding to the target function instruction reaches the amount of effective data required for the execution of the target function instruction, and / or that the free space in the second storage area corresponding to the target function instruction is sufficient to accommodate the data output by the target function instruction.

[0146] Step S720: The scheduler executes the inspection instruction, and if it determines that the parameter information corresponding to the target function instruction meets the specified parameter information, it releases the target function instruction.

[0147] Step S730: The sub-computing engine executes the target function instruction.

[0148] For a detailed description of steps S710-S730, please refer to steps S410-S430, which will not be repeated here.

[0149] Step S740: The callback module records the number of instructions contained in the target function instruction and receives the completion signal returned by the sub-computing engine, wherein the sub-computing engine uploads a completion signal once when it completes executing an instruction.

[0150] In this embodiment, the compiler can generate corresponding update instructions based on the target function instructions, insert check instructions before the target function instructions, and insert update instructions after the target function instructions to obtain an instruction sequence.

[0151] The processor's callback module is used to execute relevant update instructions. The callback module can cache update instructions and record the number of instructions preceding the update instruction and following the previous check instruction. After the relevant function instructions are issued to the corresponding sub-computing engine, the sub-computing engine will send a corresponding completion signal (FIN signal) back to the callback module upon completion of the function instruction. When the number of FIN signals collected by the callback module equals the number of issued instructions, the callback module will execute the update instructions and update the data dependency graph based on the relevant information in the update instructions.

[0152] Understandably, the purpose of the callback mechanism is to enable the issuance of the next instruction before the previous instruction is completed. That is, after the current instruction is issued, if there is no preceding check instruction, or if the subsequent instruction meets the indication of the check instruction, it can be issued continuously. Its core purpose remains to further improve the hardware's instruction processing efficiency and support out-of-order execution of instructions. For some systems or specific sub-engines that do not prioritize performance, this function may not be necessary. It is permissible to require that the issuance of subsequent instructions only begin after the FIN signals of all preceding instructions have been received.

[0153] Therefore, in this embodiment, the callback module can record the number of instructions contained in the target function instruction, as well as the completion signals returned by the sub-computing engine. Furthermore, it determines whether the number of completion signals returned by the sub-computing engine is equal to the number of instructions to obtain a judgment result.

[0154] Step S750: When the number of received completion signals equals the number of instructions, the callback module executes the update instruction and updates the data dependency graph according to the update instruction to obtain the updated third data dependency graph. In the third data dependency graph, the data space in the first storage area corresponding to the target function instruction is released, and / or the free space in the second storage area is updated.

[0155] In this embodiment, if the number of completion signals returned by the sub-computing engine is equal to the number of instructions based on the above judgment result, the callback module can execute the update instruction and update the data dependency graph according to the relevant information in the update instruction to obtain the updated third data dependency graph. It can be understood that in the third data dependency graph, the data space corresponding to the target function instruction in the first storage area is released, and / or the free space in the second storage area is updated.

[0156] In some implementations, if it is determined that the target function instruction corresponds only to input data and not to output data, the update instruction can be used only to instruct the release of the data space corresponding to the target function instruction in the first storage area. Accordingly, in the third data dependency graph, only the data space corresponding to the target function instruction in the first storage area is released. If it is determined that the target function instruction corresponds only to output data and not to input data, the update instruction can be used only to instruct the update of the free space in the second storage area. Accordingly, in the third data dependency graph, only the free space in the second storage area is updated. If it is determined that the target function instruction corresponds to both input data and output data, the update instruction is used to instruct the release of the data space corresponding to the target function instruction in the first storage area and the update of the free space in the second storage area. Accordingly, in the third data dependency graph, the data space corresponding to the target function instruction in the first storage area is released, and the free space in the second storage area is updated.

[0157] An embodiment of this application provides an instruction processing method that, compared to... Figure 6 In the instruction processing method shown in this embodiment, an update instruction is inserted after the target function instruction. The processor's sub-computing engine executes the target function instruction, and the processor's callback module records the number of instructions contained in the target function instruction and receives the completion signal returned by the sub-computing engine. The sub-computing engine uploads a completion signal when it completes one instruction. When the number of received completion signals equals the number of instructions, the scheduler executes the update instruction and updates the data dependency graph according to the update instruction to obtain the updated third data dependency graph. In the third data dependency graph, the data space corresponding to the target function instruction in the first storage area is released, and / or the free space in the second storage area is updated, thereby ensuring the normal use of data space and free space by subsequent instructions under high processing efficiency, so as to ensure the normal and smooth execution of instructions.

[0158] In some embodiments, one example of this application provides an instruction processing apparatus applied to a compiler. The instruction processing apparatus includes: a compilation module, an instruction insertion checking module, and an instruction sequence storage module, wherein:

[0159] The compiler module is used to compile multiple function instructions.

[0160] The check instruction insertion module is used to insert a check instruction before the target function instruction to obtain an instruction sequence if a data hazard is found in the target function instruction among the plurality of function instructions during the compilation process. The check instruction is used to instruct that the target function instruction be executed only if the amount of valid data in the first storage area corresponding to the target function instruction reaches the amount of valid data required for the execution of the target function instruction, and / or if the free space in the second storage area corresponding to the target function instruction is sufficient to accommodate the data output by the target function instruction.

[0161] Furthermore, the inspection instruction insertion module includes: a data reservation instruction insertion submodule, wherein:

[0162] A data reservation instruction insertion submodule is used to insert the check instruction before the target function instruction and insert a data reservation instruction between the check instruction and the target function instruction to obtain the instruction sequence, wherein the data reservation instruction is used to indicate the amount of valid data that needs to be reserved in the first storage area and / or the amount of free space that needs to be reserved in the second storage area.

[0163] Furthermore, the inspection instruction insertion module includes: an update instruction insertion submodule, wherein:

[0164] An update instruction insertion submodule is used to insert the check instruction before the target function instruction and insert an update instruction after the target function instruction to obtain the instruction sequence. The update instruction is used to instruct that, when the target function instruction is executed, the data space corresponding to the target function instruction in the first storage area is released, and / or the free space in the second storage area is updated.

[0165] An instruction sequence storage module is used to store the instruction sequence so that the processor can read the instruction sequence and execute the target function instruction according to the instructions of the check instruction.

[0166] In some implementations, one embodiment of this application provides a processor, which includes an instruction dispatch unit, a scheduler, and a sub-computing engine, wherein:

[0167] The instruction dispatch unit is used to read an instruction sequence, wherein the instruction sequence is obtained by the compiler inserting a check instruction before the target function instruction when it determines that there is a data hazard among the multiple function instructions during the compilation process of multiple function instructions. The check instruction is used to instruct that the target function instruction is executed only if the parameter information corresponding to the target function instruction meets the specified parameter information. The specified parameter information includes that the amount of valid data in the first storage area corresponding to the target function instruction reaches the amount of valid data required for the execution of the target function instruction, and / or that the free space in the second storage area corresponding to the target function instruction is sufficient to accommodate the data output by the target function instruction.

[0168] The scheduler is used to execute the inspection instruction and, if it is determined that the parameter information corresponding to the target function instruction meets the specified parameter information, release the target function instruction.

[0169] The sub-computing engine is used to execute the target function instructions.

[0170] In some implementations, one embodiment of this application provides a chip that may include the processor described above.

[0171] In some implementations, one embodiment of this application provides an electronic device that may include the processor described above.

[0172] Optionally, the aforementioned electronic device may also include a memory, a sensor, a display, etc., without limitation.

[0173] In summary, the instruction processing method, processor, chip, and electronic device provided in this application, during the compilation of multiple functional instructions by the compiler (a software component), insert a check instruction before the target functional instruction containing data hazards. The check instruction specifies that the target functional instruction is executed only if the amount of valid data in the first storage area corresponding to the target functional instruction reaches the amount of valid data required for its execution, and / or if the free space in the second storage area corresponding to the target functional instruction is sufficient to accommodate the data output by the target functional instruction. Subsequently, the instruction dispatch unit (a hardware component) reads the instruction, and the scheduler (a hardware component) determines whether to allow the target functional instruction based on the check instruction. If permission is granted, the sub-computing engine (a hardware component) executes the target functional instruction. This achieves the detection and resolution of data dependencies between instructions through a combination of software definition and hardware execution, improving processing efficiency while simplifying hardware design.

[0174] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. An instruction processing method, characterized in that, Applied to a compiler, the method includes: Compile multiple function instructions; If, during the compilation process, it is determined that there is a target function instruction with a data hazard among the plurality of function instructions, a check instruction is inserted before the target function instruction to obtain an instruction sequence. The check instruction is used to indicate that the target function instruction is executed only if the amount of valid data in the first storage area corresponding to the target function instruction reaches the amount of valid data required for the execution of the target function instruction, and / or if the free space in the second storage area corresponding to the target function instruction is sufficient to accommodate the data output by the target function instruction. The instruction sequence is stored so that the processor can read the instruction sequence and execute the target function instruction according to the instructions of the check instruction.

2. The method according to claim 1, characterized in that, When the target function instruction corresponds to input data, the check instruction includes a method for determining the input cache identifier of the first storage area and the amount of valid data required to execute the target function instruction.

3. The method according to claim 1, characterized in that, When the target function instruction corresponds to output data, the check instruction includes a function to determine the output cache identifier of the second storage area and the free space required for the data output by the target function instruction.

4. The method according to claim 1, characterized in that, The inspection instruction includes a bitmask, wherein each bit in the bitmask corresponds to the first storage area or the second storage area. The bitmask is used to indicate whether to check the valid data volume of the corresponding first storage area and whether to check the free space of the corresponding second storage area based on the value of each bit.

5. The method according to any one of claims 1-4, characterized in that, The inspection instruction includes data reservation information, which indicates the amount of valid data that needs to be reserved in the first storage area and / or the amount of free space that needs to be reserved in the second storage area.

6. The method according to any one of claims 1-4, characterized in that, The step of inserting a check instruction before the target function instruction to obtain the instruction sequence includes: The check instruction is inserted before the target function instruction, and a data reservation instruction is inserted between the check instruction and the target function instruction to obtain the instruction sequence, wherein the data reservation instruction is used to indicate the amount of valid data that needs to be reserved in the first storage area, and / or the amount of free space that needs to be reserved in the second storage area.

7. The method according to any one of claims 1-4, characterized in that, The step of inserting a check instruction before the target function instruction to obtain the instruction sequence includes: The check instruction is inserted before the target function instruction, and the update instruction is inserted after the target function instruction to obtain the instruction sequence, wherein the update instruction is used to instruct that, when the target function instruction is executed, the data space corresponding to the target function instruction in the first storage area is released, and / or the free space in the second storage area is updated.

8. An instruction processing method, characterized in that, Applied to a processor, the processor including an instruction dispatch unit, a scheduler, and a sub-computing engine, the method includes: The instruction dispatch unit reads an instruction sequence, wherein the instruction sequence is obtained by the compiler inserting a check instruction before the target function instruction when it determines that there is a data hazard among the multiple function instructions during the compilation of multiple function instructions. The check instruction is used to indicate that the target function instruction is executed only if the parameter information corresponding to the target function instruction meets the specified parameter information. The specified parameter information includes that the effective data amount in the first storage area corresponding to the target function instruction reaches the effective data amount required for the execution of the target function instruction, and / or that the free space in the second storage area corresponding to the target function instruction is sufficient to accommodate the data output by the target function instruction. The scheduler executes the inspection instruction, and if it determines that the parameter information corresponding to the target function instruction meets the specified parameter information, it releases the target function instruction. The sub-computing engine executes the target function instructions.

9. The method according to claim 8, characterized in that, When the target function instruction corresponds to input data, the check instruction includes an input buffer identifier and the amount of valid data required to execute the target function instruction; the scheduler executes the check instruction, and if it determines that the parameter information corresponding to the target function instruction meets the specified parameter information, it releases the target function instruction, including: The scheduler queries the data dependency graph to determine the effective amount of data in the first storage area corresponding to the input cache identifier; If the effective data volume in the first storage area reaches the effective data volume required for the execution of the target function instruction, then the scheduler allows the target function instruction to proceed.

10. The method according to claim 8, characterized in that, When the target function instruction corresponds to output data, the check instruction includes an output buffer identifier and the free space required for the data output by the target function instruction; The scheduler executes the inspection instruction, and if it determines that the parameter information corresponding to the target function instruction meets the specified parameter information, it releases the target function instruction, including: The scheduler queries the data dependency graph to determine the available space in the second storage area corresponding to the output cache identifier; If the free space in the second storage area is sufficient to accommodate the data output by the target function instruction, then the scheduler allows the target function instruction to proceed.

11. The method according to claim 8, characterized in that, The inspection instruction includes a bitmask, wherein each bit in the bitmask corresponds to either the first storage region or the second storage region; the method further includes: The scheduler determines whether to check the amount of valid data corresponding to the first storage area and whether to check the free space corresponding to the second storage area based on the value of each bit in the bitmask.

12. The method according to claim 8, characterized in that, The inspection instruction includes data reservation information; After the scheduler executes the check instruction, the following is also included: If the inspection instruction is completed, the scheduler updates the data dependency graph according to the data reservation information to obtain the updated first data dependency graph, wherein the first storage area retains the amount of valid data, and / or the second storage area reserves the free space.

13. The method according to claim 8, characterized in that, The compiler inserts a data reservation instruction between the check instruction and the target function instruction; After the scheduler executes the check instruction, the following is also included: If the check instruction is completed, the scheduler updates the data dependency graph according to the data reservation instruction to obtain the updated second data dependency graph, wherein the first storage area retains the amount of valid data, and / or the second storage area reserves the free space.

14. The method according to claim 8, characterized in that, The number of sub-computing engines is multiple, and each sub-computing engine has its own instruction cache area; After the instruction distribution unit reads the instruction sequence, the following is also included: The instruction distribution unit determines the engine identifier carried by the target function instruction; The instruction distribution unit determines the target sub-computing engine from the plurality of sub-computing engines based on the engine identifier, and distributes the target function instruction to the instruction cache area corresponding to the target sub-computing engine.

15. The method according to claim 8, characterized in that, The scheduler includes a callback module, and the compiler inserts update instructions after the target function instructions; after the sub-computing engine executes the target function instructions, the following is also included: The callback module records the number of instructions contained in the target function instruction and receives the completion signal returned by the sub-computing engine, wherein the sub-computing engine uploads a completion signal once when it completes executing an instruction. When the number of received completion signals equals the number of instructions, the callback module executes the update instruction and updates the data dependency graph according to the update instruction to obtain the updated third data dependency graph. In the third data dependency graph, the data space in the first storage area corresponding to the target function instruction is released, and / or the free space in the second storage area is updated.

16. A processor, characterized in that, It includes an instruction dispatch unit, a scheduler, and sub-computing engines, among which: The instruction dispatch unit is used to read the instruction sequence, wherein the instruction sequence is obtained by the compiler inserting a check instruction before the target function instruction when it determines that there is a data hazard among the multiple function instructions during the compilation of multiple function instructions. The check instruction is used to indicate that the target function instruction will be executed only if the parameter information corresponding to the target function instruction meets the specified parameter information. The specified parameter information includes that the effective data amount in the first storage area corresponding to the target function instruction reaches the effective data amount required for the execution of the target function instruction, and / or the free space in the second storage area corresponding to the target function instruction is sufficient to accommodate the data output by the target function instruction. The scheduler is used to execute the inspection instruction and, if it is determined that the parameter information corresponding to the target function instruction meets the specified parameter information, allow the target function instruction to proceed. The sub-computing engine is used to execute the target function instructions.

17. A chip or electronic device, characterized in that, Includes the processor as described in claim 16.

Images