A pending transaction bus bridge, control method and storage medium

Abstract

Embodiments of the present application provide a pending transaction bus bridge, a control method and a storage medium, wherein the pending transaction bus bridge can include a configuration register, a request queue and a pending transaction counter; wherein the configuration register at least includes a state bit segment and a maximum number of unfinished transaction bit segment, the state bit segment saves the configuration adjustment active state of the pending transaction bus bridge, and the maximum number of unfinished transaction bit segment saves the maximum number of unfinished transactions of the pending transaction bus bridge at the current time; the request queue saves transaction requests to be sent; and the pending transaction counter saves the number of transactions that have been sent to the downstream but have not received a response. Embodiments of the present application can save the maximum processing capacity and configuration adjustment state of the pending transaction through the configuration register, thereby realizing accurate scheduling of the pending transaction, dynamically adjusting the maximum number of unfinished transactions of the pending transaction according to the actual business demand, expanding the parallelism of the transaction, and improving the transaction data transmission efficiency.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a pending transaction bus bridge, control method, and storage medium. Background Technology

[0002] With the rapid development of integrated circuit technology, modern System-on-Chip (SoC) integrates dozens or even hundreds of complex intellectual property (IP) cores, such as Central Processing Units (CPUs), Graphics Processing Units (GPUs), Digital Signal Processors (DSPs), various controllers, and peripheral interfaces. The normal operation of each IP core depends on the correct configuration of its numerous internal function registers. These registers control the IP's operating mode, interrupt status, data flow, and performance parameters, forming the cornerstone of the entire SoC control system.

[0003] Configuring these widely distributed and numerous registers typically relies on the main CPU executing software instructions. The CPU initiates read / write transactions via the SoC's internal system bus, traversing multiple bus interconnects to ultimately reach the register interface of the target IP. To improve transmission efficiency, most current configuration bus designs set the outstanding transaction capacity to its maximum value and maintain the same outstanding transaction capacity setting during system startup and operation. This fixed outstanding transaction capacity design lacks flexibility and has the following two limitations: 1. For scenarios with relatively low system configuration throughput, the same complex logic must still be used, which is not power-efficient. 2. For scenarios with high single-access response latency requirements, the uncertainty caused by queuing and scheduling may lead to significant latency for that access. Therefore, there is an urgent need for a pending transaction processing device with flexible configuration capabilities. Summary of the Invention

[0004] This invention provides a pending transaction bus bridge, a control method, and a storage medium. The pending transaction bus bridge provided by this invention can store the maximum processing capacity of pending transactions and the configuration adjustment status through configuration registers, thereby realizing precise scheduling of pending transactions and dynamically adjusting the maximum number of unfinished pending transactions according to actual business needs. This expands the parallelism of transactions and improves the efficiency of transaction data transmission.

[0005] According to one aspect of the present invention, a pending transaction bus bridge is provided, wherein the pending transaction bus bridge includes a configuration register, a request queue, and a pending transaction counter;

[0006] The configuration register includes at least a status field and a maximum number of unfinished transactions field. The status field stores the configuration adjustment activation status of the pending transaction bus bridge, and the maximum number of unfinished transactions field stores the maximum number of unfinished transactions of the pending transaction bus bridge at the current time.

[0007] The request queue stores transaction requests to be sent;

[0008] The pending transaction counter stores the number of transactions that have been sent downstream but for which no response has been received.

[0009] According to another aspect of the present invention, a method for controlling a pending transaction bus bridge is provided, wherein the method includes:

[0010] If the configuration adjustment activation state of the pending transaction bus bridge is detected to be in the first state, adjust the maximum number of uncompleted transactions of the pending transaction bus bridge.

[0011] Transaction scheduling is performed based on the adjusted maximum number of incomplete transactions.

[0012] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the pending transaction bus bridge control method according to any embodiment of the present invention.

[0013] The technical solution of this invention stores the configuration adjustment activation state and the maximum number of pending transactions in a configuration register, stores pending transaction requests in a request queue, and stores the number of transactions sent downstream but for which no response has been received through a pending transaction counter. This invention allows the configuration adjustment activation state to be changed according to actual needs, thereby adjusting the maximum number of pending transactions. This makes the pending transaction bus bridge suitable for actual application scenarios, enhances the matching degree of pending transaction capabilities, expands the parallelism of transactions, and improves the efficiency of transaction data transmission.

[0014] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of a pending transaction bus bridge according to an embodiment of the present invention;

[0017] Figure 2 This is an example diagram of a pending transaction bus bridge provided according to an embodiment of the present invention;

[0018] Figure 3 This is a flowchart of a pending transaction bus bridge control method provided by an embodiment of the present invention;

[0019] Figure 4 This is a flowchart of another pending transaction bus bridge control method provided by an embodiment of the present invention;

[0020] Figure 5 This is a schematic diagram of another pending transaction bus bridge control device provided according to an embodiment of the present invention;

[0021] Figure 6 This is a schematic diagram of the structure of an electronic device that implements the pending transaction bus bridge control method of the present invention. Detailed Implementation

[0022] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0023] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0024] Figure 1 This is a schematic diagram of a pending transaction bus bridge according to an embodiment of the present invention. See also... Figure 1The pending transaction bus bridge provided in this embodiment of the invention includes: a configuration register 101, a request queue 102, and a pending transaction counter 103; wherein, the configuration register 101 includes at least a status bit field and a maximum number of uncompleted transactions bit field, the status bit field storing status information indicating the configuration adjustment activation state of the pending transaction bus bridge, and the maximum number of uncompleted transactions bit field storing the maximum number of uncompleted transactions of the pending transaction bus bridge at the current time; the request queue 102 stores transaction requests to be sent; and the pending transaction counter 103 stores the number of transactions that have been sent downstream but have not received a response.

[0025] The configuration register 101 can store configuration information related to pending transactions. The configuration register 101 can specifically include on-chip registers, off-chip registers, or memory-mapped registers. The configuration register 101 can include at least a status field and a maximum number of pending transactions field. The status field can indicate the configuration adjustment activation state of the pending transaction bus bridge. This configuration adjustment activation state indicates whether the maximum number of pending transactions stored in the configuration register 101 can be adjusted. For example, when the configuration adjustment activation state is in the first state, the maximum number of pending transactions stored in the configuration register 101 can be adjusted; when the configuration adjustment activation state is in the second state, the maximum number of pending transactions stored in the configuration register 101 cannot be adjusted.

[0026] In this embodiment of the invention, the request queue 102 can be a hardware device used by the pending transaction bus bridge to store transaction requests. Specifically, the request queue 102 can be implemented using a dual-port random access memory. The request queue 102 can follow a first-in-first-out (FIFO) rule and can have synchronous or asynchronous logic. The request queue 102 can store transaction requests sent by upstream devices.

[0027] Specifically, the pending transaction counter 103 is a core module used to track the number of transactions that have been sent downstream but have not yet received a response in real time. Its implementation must meet the requirements of accurate counting, time synchronization, and fault tolerance. The counting trigger condition for the pending transaction counter 103 is that the count is incremented by 1 when a transaction request is dequeued from the request queue 102 and successfully sent to the downstream bus, and decremented by 1 when the downstream returns the final response to the transaction.

[0028] This invention, in its embodiments, stores the configuration adjustment activation status and the maximum number of pending transactions in a configuration register, stores pending transaction requests in a request queue, and stores the number of transactions sent downstream but for which no response has been received through a pending transaction counter. This invention allows for changes to the configuration adjustment activation status according to actual needs, thereby adjusting the maximum number of pending transactions. This makes the pending transaction bus bridge suitable for real-world application scenarios, enhances the matching degree of pending transaction capabilities, expands transaction parallelism, and improves transaction data transmission efficiency.

[0029] Based on the above embodiments of the invention, the depth of the request queue 102 corresponds to the maximum number of uncompleted transactions stored in the maximum number of uncompleted transactions field in the current configuration register 101.

[0030] In this embodiment of the invention, the maximum number of unfinished transactions stored in the configuration register 101 of the pending transaction bus bridge in its current state can be dynamically configured. To ensure that the request queue 102 can meet the above-mentioned dynamically configured maximum number of unfinished transactions, the depth of the request queue 102 needs to be matched with the maximum number of unfinished transactions in the configuration register 101. This matching may include the depth of the request queue 102 being greater than or equal to the maximum value allowed to be configured in the maximum number of unfinished transactions.

[0031] In other embodiments of the invention, the status field is configured to a first state, and the number of transactions stored in the pending transaction counter is zero. The maximum number of pending transactions stored in the maximum number of pending transactions field is adjusted according to the configuration information.

[0032] The configuration information can be pre-configured indication information for indicating the maximum number of incomplete transactions. The configuration information can carry the maximum number of incomplete transactions or the index value of the maximum number of incomplete transactions.

[0033] Specifically, when the configuration register is configured to the first state and the number of transactions stored in the pending transaction counter is zero, a maximum number of uncompleted transactions can be determined according to the configuration information. The determined maximum number of uncompleted transactions can be stored in the status bit field of the configuration register, thereby updating the maximum number of uncompleted transactions of the pending transaction bus bridge.

[0034] Figure 2 This is an example diagram of a pending transaction bus bridge according to an embodiment of the present invention. This embodiment provides a flexibly configurable pending transaction bus bridge, offering dynamic adjustability for configuring network pending transactions, and overcoming the high power consumption and latency drawbacks of existing pending transaction capabilities. See also... Figure 2 The outstanding transaction bus bridge may include configuration registers, request queues, outstanding transaction (OT) counters, and control finite state machine (Control FSM).

[0035] 1. The configuration register can be a simple register with a maximum number of pending transactions field, such as OT_CFG_REG[3:0]. The value (0-15) that this field can store defines the maximum number of allowed pending transactions (OT). The configuration register also includes a status bit BUSY. When there are pending transactions in the pending transaction bus bridge, this bit is set to 1, indicating that the software should not modify the configuration at this time. When this bit is set to 0, it indicates that the software can modify the configuration at this time.

[0036] 2. The request queue can be a FIFO with a physical depth of N (e.g., 16) to store AXI write addresses and write data channel information sent from upstream. Its "full" signal is not determined by the physical depth, but by a configurable OT value. Through a comparator, when the number of transactions sent but not yet responded to in the queue equals the value of OT_CFG_REG, assert back-pressure is sent to the master device, preventing the master device from sending new requests.

[0037] 3. The OT counter is a counter that tracks the number of requests sent to downstream devices that have not yet received a response. The counting rules for this counter are as follows:

[0038] (1) The counter is incremented by 1 each time a request is retrieved from the queue and successfully sent to the downstream bus;

[0039] (2) The counter is decremented by 1 whenever a final response (BRESP or RRESP) is received from downstream.

[0040] In this embodiment of the invention, the value of the counter is compared with the value of OT_CFG_REG in the configuration register in real time to generate a flow control signal.

[0041] 4. The control state machine can manage the working state of the pending transaction bus bridge. For example, it can trigger the pending transaction bus bridge to switch between states such as "configuration change synchronization" and "error handling".

[0042] This invention provides a dynamically adjustable hardware feature for configuring network pending transaction capabilities, enabling system software to configure different pending transaction capabilities according to the needs of different scenarios. For scenarios with relatively low system throughput, power consumption can be reduced by configuring pending transaction capabilities to a smaller value or even disabling them. For scenarios with high single-access response latency requirements, pending transaction capabilities can be configured to a minimum value or even deactivated to avoid uncertainties caused by queuing and scheduling, thereby reducing access response latency.

[0043] Figure 3This is a flowchart of a pending transaction bus bridge control method according to an embodiment of the present invention. This embodiment is applicable to situations where the maximum number of pending transactions is dynamically adjusted by the pending transaction bus bridge. This method can be executed by the pending transaction bus bridge, which can be implemented in hardware and / or software. Figure 3 As shown, the method includes:

[0044] Step 110: The configuration adjustment activation state of the pending transaction bus bridge is detected to be in the first state. Adjust the maximum number of uncompleted transactions of the pending transaction bus bridge.

[0045] In this embodiment of the invention, the pending transaction bus bridge can detect the configuration adjustment activation state. When the configuration adjustment activation state is in the first state, it can indicate that the maximum number of outstanding transactions within the pending transaction bus bridge can be adjusted; that is, the maximum number of outstanding transactions that the pending transaction bus bridge can carry can be changed. The pending transaction bus bridge can dynamically adjust the maximum number of outstanding transactions when the configuration adjustment activation state is in the first state, thereby enabling the pending transaction bus bridge to be used in scenarios with different throughputs and reducing the system's power consumption.

[0046] Step 120: Schedule transactions based on the adjusted maximum number of incomplete transactions.

[0047] Specifically, after adjusting the maximum number of outstanding transactions on the pending transaction bus bridge, transactions can be scheduled according to the adjusted maximum number of outstanding transactions. For example, the pending transaction bus bridge can schedule transactions based on the maximum number of outstanding transactions it carries, and can save transactions that have been initiated but not yet completed and have not received a final response.

[0048] In this embodiment of the invention, the maximum number of pending transactions is flexibly adjusted by adjusting the activation state of the pending transaction bus bridge according to the saved configuration, and transactions are scheduled according to the adjusted maximum number of pending transactions. This embodiment of the invention allows the configuration adjustment activation state to be changed according to actual needs, thereby adjusting the maximum number of pending transactions. This makes the pending transaction bus bridge suitable for actual application scenarios, enhances the matching degree of pending transaction capabilities, expands the parallelism of transactions, and improves the efficiency of transaction data transmission.

[0049] Figure 4 This is a flowchart of another pending transaction bus bridge control method provided by an embodiment of the present invention. This embodiment illustrates the process of adjusting the maximum number of pending transactions. See [link to flowchart]. Figure 4 The method provided in this embodiment of the invention specifically includes the following steps:

[0050] Step 210: Detect that the configuration adjustment activation state of the pending transaction bus bridge is in the first state, write the maximum number of unfinished transactions into the configuration register of the pending transaction bus bridge according to the preset configuration information, and adjust the configuration adjustment activation state to the second state.

[0051] In this embodiment of the invention, when the configuration adjustment activation state of the pending transaction bus bridge is set to the first state, preset configuration information can be obtained. This preset configuration information can be obtained in real time or pre-configured. The maximum number of pending transactions that need to be used can be determined according to the obtained preset configuration information. The maximum number of pending transactions can be set to the configuration register of the pending transaction bus bridge, and the configuration adjustment activation state can be set to the second state. For example, the second state or the indication information of the second state can be written into the status bit field of the configuration register of the pending transaction bus bridge, thereby realizing the update of the configuration adjustment activation state.

[0052] Step 220: Schedule transactions based on the adjusted maximum number of incomplete transactions.

[0053] Step 230: If the pending transaction bus bridge meets the preset conditions, the configuration adjustment activation state is adjusted to the first state.

[0054] The preset conditions can be conditions under which the pending transaction bus bridge can adjust the maximum number of pending transactions. The preset conditions may include the configuration activation status of the pending transaction bus bridge, the working status of the pending transaction counter, and / or the working status of the request queue of the pending transaction bus bridge.

[0055] Specifically, the pending transaction bus bridge can periodically or irregularly check its own working status to determine whether its working status meets preset conditions. If it does, it can switch the configuration adjustment activation state of the pending transaction bus bridge from the second state back to the first state, thereby adjusting the maximum number of uncompleted transactions again. If it does not meet the conditions, it will not switch the configuration adjustment activation state of the pending transaction bus bridge and will continue to wait for the next self-check of its working status.

[0056] Based on the above embodiments of the invention, the preset conditions include at least one of the following: determining that the number of transactions in the pending transaction counter of the pending transaction bus bridge is zero; determining that the request queue of the pending transaction bus bridge is empty.

[0057] Specifically, when the number of transactions in the pending transaction counter of the pending transaction bus is zero, and / or the request queue of the pending transaction bus bridge is empty, the configuration adjustment activation state can be adjusted to the first state.

[0058] In this embodiment of the invention, by detecting that the configuration adjustment activation state of the pending transaction bus bridge is in a first state, the maximum number of outstanding transactions is written into the configuration register of the pending transaction bus bridge according to preset configuration information, and the configuration adjustment activation state is adjusted to a second state. Transaction scheduling is performed according to the adjusted maximum number of outstanding transactions. When it is determined that the pending transaction bus bridge meets preset conditions, the configuration adjustment activation state is switched back to the first state. This embodiment of the invention allows the configuration adjustment activation state to be changed according to actual needs, thereby adjusting the maximum number of outstanding transactions. This makes the pending transaction bus bridge suitable for actual application scenarios, enhances the matching degree of pending transaction capabilities, helps ensure transaction processing latency, and reduces system performance overhead.

[0059] Furthermore, based on the above embodiments of the invention, transaction scheduling is performed according to the adjusted maximum number of incomplete transactions, including:

[0060] Receive transaction requests transmitted from upstream devices of the pending transaction bus bridge and save the transaction requests to the request queue; obtain transaction requests popped from the request queue, send the transaction requests to downstream devices, and trigger the pending transaction counter of the pending transaction bus bridge to increment by 1; receive response information from downstream devices for transaction requests and control the pending transaction counter to decrement by 1.

[0061] In an AXI bus, the upstream device is the one that initiates the transaction request. This is typically the master device, responsible for actively initiating read / write operations and sending address, data, and other information to the bus. The downstream device, on the other hand, receives and responds to the transaction request. This is typically the slave device, responsible for completing the data read / write operation based on the upstream request and returning a response. A transaction request can be an operation instruction initiated by the upstream device. It can carry address, data, and control information to instruct the downstream device to perform the operation. Transaction requests can be categorized into write transaction requests, read transaction requests, etc., and different types of transaction requests can be transmitted through different transmission channels. For example, a write transaction request can be transmitted through both the address and data channels, while a read data channel can be transmitted through the address channel.

[0062] In this embodiment of the invention, when scheduling transactions according to the adjusted maximum number of outstanding transactions, a transaction request issued by an upstream device can be received and saved to the request queue of the pending transaction bus bridge. It is understood that the transaction request can be added to the tail of the request queue according to the receiving time, the transaction request at the head of the request queue can be popped, the transaction request can be sent to the downstream device, and the pending transaction counter of the pending transaction bus bridge can be incremented by 1. Furthermore, each time a response message for a transaction request is received from a downstream device, the pending transaction counter in the pending transaction bus bridge is decremented by 1.

[0063] In other embodiments of the invention, the method further includes: upon receiving transaction address information corresponding to a transaction request sent by an upstream device, determining whether the count value of the pending transaction counter is equal to the maximum number of uncompleted transactions on the pending transaction bus bridge; if so, receiving the transaction request; otherwise, preventing the upstream device from sending the transaction request.

[0064] Specifically, before processing a transaction request, the pending transaction bus bridge can determine whether the count value of the pending transaction counter is equal to the maximum number of uncompleted transactions of the pending transaction bus bridge when it receives the transaction address information corresponding to the transaction request sent by the upstream device. That is, it can determine whether the processing capacity of the pending transaction bus bridge has reached its limit. If so, the transaction request can be received; otherwise, the upstream device can issue an assert back-pressure to prevent it from sending a new request.

[0065] Figure 5 This is a schematic diagram of another pending transaction bus bridge control device provided according to an embodiment of the present invention, such as... Figure 5 As shown, the device includes:

[0066] The configuration adjustment module 310 is used to detect that the configuration adjustment activation state of the pending transaction bus bridge is in the first state, and adjust the maximum number of uncompleted transactions of the pending transaction bus bridge.

[0067] The transaction scheduling module 320 is used to schedule transactions based on the adjusted maximum number of incomplete transactions.

[0068] In this embodiment of the invention, the configuration adjustment module flexibly adjusts the maximum number of outstanding transactions according to the saved configuration adjustment activation state of the pending transaction bus bridge, and the transaction scheduling module schedules transactions according to the adjusted maximum number of outstanding transactions. This embodiment of the invention allows the configuration adjustment activation state to be changed according to actual needs, thereby adjusting the maximum number of outstanding transactions. This makes the pending transaction bus bridge suitable for actual application scenarios, enhances the matching degree of pending transaction capabilities, expands the parallelism of transactions, and improves the efficiency of transaction data transmission.

[0069] Based on the above embodiments of the invention, the configuration adjustment module 310 is specifically used to: write the maximum number of unfinished transactions into the configuration register of the pending transaction bus bridge according to the preset configuration information, and adjust the configuration adjustment activation state to the second state.

[0070] Based on the above embodiments of the invention, it further includes: an activation module, used to determine that the pending transaction bus bridge meets preset conditions, and then adjust the configuration adjustment activation state to the first state.

[0071] Based on the above embodiments of the invention, the preset conditions include at least one of the following:

[0072] The number of transactions in the pending transaction counter of the pending transaction bus bridge is determined to be zero;

[0073] The request queue of the pending transaction bus bridge is determined to be empty.

[0074] Based on the above embodiments of the invention, the transaction scheduling module 320 includes:

[0075] The request saving unit is used to receive transaction requests transmitted by the upstream device of the pending transaction bus bridge and save the transaction requests to the request queue.

[0076] The transaction sending unit is used to obtain the transaction request popped from the request queue, send the transaction request to the downstream device, and trigger the pending transaction counter of the pending transaction bus bridge to increment by 1.

[0077] The pending processing unit is used to receive the response information from the downstream device in response to the transaction request and control the pending transaction counter to decrement by 1.

[0078] Based on the above embodiments, the invention further includes: an information determination module, configured to, upon receiving the transaction address information corresponding to the transaction request sent by the upstream device, determine whether the count value of the pending transaction counter is equal to the maximum number of uncompleted transactions of the pending transaction bus bridge; if yes, then receive the transaction request; if no, then prevent the upstream device from sending the transaction request.

[0079] The pending transaction bus bridge control device provided in the embodiments of the present invention can execute the pending transaction bus bridge control method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0080] Figure 6 A schematic diagram of an electronic device 10, which can be used to implement embodiments of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0081] like Figure 6As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0082] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0083] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as the pending transaction bus bridge control method.

[0084] In some embodiments, the pending transaction bus bridge control method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the pending transaction bus bridge control method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the pending transaction bus bridge control method by any other suitable means (e.g., by means of firmware).

[0085] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0086] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0087] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0088] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0089] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0090] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0091] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0092] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A pending transaction bus bridge, characterized in that, The pending transaction bus bridge includes a configuration register, a request queue, a pending transaction counter, and a control state machine; The configuration register includes at least a status field and a maximum number of unfinished transactions field. The status field stores the configuration adjustment activation state of the pending transaction bus bridge, and the maximum number of unfinished transactions field stores the maximum number of unfinished transactions of the pending transaction bus bridge at the current time. When the configuration adjustment activation state is in the first state, the maximum number of unfinished transactions stored in the configuration register can be adjusted. When the configuration adjustment activation state is in the second state, the maximum number of unfinished transactions stored in the configuration register cannot be adjusted. The request queue stores transaction requests to be sent; The pending transaction counter stores the number of transactions that have been sent downstream but for which no response has been received; The control state machine manages the working state of the pending transaction bus bridge, wherein the working state includes at least a configuration change synchronization state and an error handling state.

2. The pending transaction bus bridge according to claim 1, characterized in that, The depth of the request queue corresponds to the maximum number of incomplete transactions stored in the maximum number of incomplete transactions bit field of the current configuration register.

3. The pending transaction bus bridge according to claim 1, characterized in that, The status field is configured to the first state, and the number of transactions stored in the pending transaction counter is zero. The maximum number of pending transactions stored in the maximum number of pending transactions field is adjusted according to the configuration information.

4. A method for controlling a pending transaction bus bridge, characterized in that, Applied to a pending transaction bus bridge, the method includes: If the configuration adjustment activation state of the pending transaction bus bridge is detected to be in the first state, adjust the maximum number of uncompleted transactions of the pending transaction bus bridge. Transaction scheduling is performed based on the adjusted maximum number of unfinished transactions, including: writing the maximum number of unfinished transactions into the configuration register of the pending transaction bus bridge according to preset configuration information, and adjusting the configuration adjustment activation state to the second state; Specifically, when the configuration adjustment activation state is in the first state, the maximum number of incomplete transactions stored in the configuration register can be adjusted; when the configuration adjustment activation state is in the second state, the maximum number of incomplete transactions stored in the configuration register cannot be adjusted.

5. The method according to claim 4, characterized in that, Also includes: If the pending transaction bus bridge is determined to meet the preset conditions, the configuration adjustment activation state is adjusted to the first state.

6. The method according to claim 5, characterized in that, The preset conditions include at least one of the following: The number of transactions in the pending transaction counter of the pending transaction bus bridge is determined to be zero; The request queue of the pending transaction bus bridge is determined to be empty.

7. The method according to claim 4, characterized in that, The transaction scheduling based on the adjusted maximum number of incomplete transactions includes: Receive transaction requests transmitted from the upstream device of the pending transaction bus bridge and save the transaction requests to the request queue; The transaction request popped from the request queue is obtained, the transaction request is sent to the downstream device, and the pending transaction counter of the pending transaction bus bridge is incremented by 1. Upon receiving the response information from the downstream device regarding the transaction request, the pending transaction counter is decremented by 1.

8. The method according to claim 7, characterized in that, Also includes: When the transaction address information corresponding to the transaction request sent by the upstream device is received, it is determined whether the count value of the pending transaction counter is equal to the maximum number of uncompleted transactions of the pending transaction bus bridge; If yes, then accept the transaction request; otherwise, prevent the upstream device from sending the transaction request.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that is executed by at least one processor to enable the at least one processor to perform the pending transaction bus bridge control method according to any one of claims 4-8.

Images