Low-power-consumption multi-core SOC

Abstract

The invention provides a low-power-consumption multi-core SOC, and relates to the technical field of chip design, the low-power-consumption multi-core SOC comprises a first CPU, a second CPU, a clock network, a peripheral unit attached to the first CPU and a peripheral unit attached to the second CPU, and the clock network is used for providing clock signals for the first CPU, the second CPU, the peripheral unit attached to the first CPU and the peripheral unit attached to the second CPU; the configuration register LPMCR is used for configuring the clock gating modes of the multi-core SOC, and the clock gating modes comprise three clock gating modes. The low-power-consumption multi-core SOC chip has multiple low-power-consumption modes, and has a configurable protection field mode for a power-down mode; wakeup supporting multiple modes comprises internal interrupt wakeup and external GPIO wakeup.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip design technical field, specifically, a kind of low-power multi-core SOC. BACKGROUND

[0002] Power consumption is divided into dynamic power consumption and static power consumption.When gate circuit flips, i.e. load capacitor charges and discharges, dynamic power consumption accounts for the majority. Static power consumption accounts for the majority when gate circuit does not flip but is still in power supply state. With the continuous update iteration of chip manufacturing process and the functional integration of chip design itself, power consumption becomes a key factor affecting its performance. Therefore, more and more designs reduce power consumption through power gating or clock gating technology.

[0003] Clock network affects power consumption of more than half of the total dynamic power consumption. In the clock network, energy is mainly consumed in the clock tree, which is the unit with the highest flip rate in the entire system, and in order to ensure to reduce the network delay of the clock, these clock buffers usually have high driving capability. The purpose of clock flip is to drive the update of register data, and when the register does not need to work, the clock connected to the register can be turned off, which is clock gating. Power gating technology is similar, when a module does not work, turn off its power supply so that static power consumption will not be generated, and when it needs to work, turn it on. Gated power counting is more complex than gated clock counting, including gated power controller, power switch network, controlled module, always-on module, isolator and other basic parts. In SOC, the controlled module is connected to the power supply output by the power switch network, and the power switch input is the always-on voltage and logic switch control.

[0004] Currently, clock gating is mainly used to achieve a low-power state, but different applications have different requirements for low power consumption. Especially in SOC products, some application environments require the CPU to be in low-power mode, and peripherals need to work. Some application environments require the CPU and peripherals controlled by the CPU clock to be in low-power mode. In some multi-chip joint scenarios, a SOC chip does not need to work for a long time. In this case, power gating technology is used to turn off the power supply of most circuits of the SOC, which requires multiple low-power modes to meet the power consumption needs of different scenarios.

[0005] For power gating technology, power failure itself can damage the internal logic state of the device. Some application scenarios need to save the data before power failure. The current method is to temporarily store some key content through external communication through external devices. This solution is very redundant.

[0006] After entering the low power mode, the non-power-off low power mode can only be implemented by the external port through a wake-up frame to wake up. The efficiency is low. SUMMARY

[0007] To solve the above technical problems in the related art, the application provides a low power multi-core SOC, which comprises a first CPU, a second CPU, a clock network, a peripheral unit for the first CPU, and a peripheral unit for the second CPU. The clock network is used to provide clock signals for the first CPU, the second CPU, the peripheral unit for the first CPU, and the peripheral unit for the second CPU respectively. A configuration register LPMCR is configured to configure a clock gating mode of the multi-core SOC. The clock gating mode comprises three clock gating modes. The first clock gating mode is to close the clock of the first CPU or the second CPU. The second clock gating mode is to close the clock of the first CPU or the second CPU, the clock of the peripheral unit for the first CPU, and the clock of the peripheral unit for the second CPU. The third clock gating mode is to close the clock of the first CPU, the second CPU, the peripheral unit for the first CPU, and the peripheral unit for the second CPU.

[0008] Specifically, the clock network comprises a first clock source INTOSC1, a second clock source INTOSC2, and a third clock source X1. A clock selection circuit CLKSRCCTL1 is used to select the corresponding clock source. A peripheral clock register CPUx.PCLKCRx is used to configure the clock of the corresponding peripheral.

[0009] Specifically, the clock selection circuit CLKSRCCTL1 is used to select the corresponding clock source. The 0th bit of CLKSRCCTL1 is used for clock source selection. The 1st bit of CLKSRCCTL1 is used for whether to use the frequency multiplication clock output by the PLL. The 2nd bit is used to check whether the clock of the watchdog is closed in the third clock gating mode.

[0010] Specifically, the low power multi-core SOC enters different clock gating modes by setting the LPMCR register and executing the IDLE instruction.

[0011] Specifically, the first clock gating mode is entered in the following way: the LPMCR register is written as 0, and then the ILDE instruction is executed.

[0012] Specifically, the second clock gating mode is entered in the following way: the LPMCR register is written as 1, the wake-up interrupt enable is turned on, the required GPIO is configured as a wake-up signal to trigger the low power module, the duration of the low level is set, and the IDLE instruction is executed to enter the second clock gating mode.

[0013] Specifically, the way to enter the third clock gating mode is: disabling all interrupts of the two CPUs except the wake-up interrupt; putting the second CPU into the first clock gating mode, configuring the LPMCR as 2, configuring the used GPIO as the wake-up signal, setting the watchdog clock valid as 0, turning off the clocks of the first clock source INTOSC1 and the second clock source INTOSC2, and executing the IDLE instruction on the first CPU.

[0014] Specifically, in the third clock gating mode, the first CPU saves the necessary application-specific context into the first CPU dedicated RAM block which does not power off in the third clock gating mode.

[0015] Specifically, the way to exit the second clock gating mode is: driving the selected GPIO to low level, and if the GPIO driving level becomes high during the low level, the counter will restart counting; at the end of the low level defined period, the PLL makes the clock source clock enter the CPU, and the wake-up interrupt is locked in the peripheral interrupt extension module.

[0016] Specifically, the way to exit the third clock gating mode is: maintaining the selected GPIO at least low level for 5us; pulling the GPIO high to start the initialization of the analog part and the PLL; waiting for 16us plus 1024 OSCLK periods to make the PLL stable, and the WAKEINT interrupts of the two CPUs are triggered.

[0017] The low-power multi-core SOC has multiple clock gating modes, which can further reduce the power consumption of the SOC, in addition, there are configurable protection field modes for the power-off mode; and supports multiple wake-up modes including internal interrupt wake-up and external GPIO wake-up. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0019] Figure 1 is a low-power multi-core SOC structure schematic diagram provided by the embodiment of the present application; Figure 2 is a clock network schematic diagram provided by the embodiment of the present application. DETAILED DESCRIPTION

[0020] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments of the present application, all the other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present application.

[0021] Reference Figure 1 , Figure 1 is a multi-core SOC structure schematic diagram of the embodiment, which includes a first CPU 1 and a second CPU 2. Each CPU subsystem has four dedicated RAM blocks: M0, M1, D0 and D1. M0 / M1 memories are small memory blocks that are tightly coupled with the CPU. Only the CPU can access these memories. Other hosts (including DMA) cannot access these memories. Each CPU also has a dedicated special hardware accelerator CLA, which has an independent instruction set and can execute control algorithms in parallel to provide the response speed of the system. Each CPU also has a dedicated memory corresponding to the CLA.

[0022] Among them, the dedicated RAM, DxRAM, x is 0, 1, is a functional RAM with security protection (CPU fetch / CPU write protection).

[0023] The system shared memory MSGRAM is used for sharing between the CPUs and the DMA of the two subsystems (GSx RAM), and for sending and receiving messages between the processors (MSGRAM).

[0024] The RAM block dedicated to each subsystem and only accessible by its CPU and CLA is called local shared RAM (LSxRAM).

[0025] The RAM block accessible from the CPU and its respective DMA is called global shared RAM (GSx RAM). Based on the configuration of their respective bits in the GSxMSEL register (one bit for each GSx memory), each shared RAM can be owned by any CPU subsystem.

[0026] All these RAMs are configurable to implement the control of write access and value access to different hosts.

[0027] The embodiment discloses a low-power multi-core SOC, which includes a first CPU, a second CPU, a clock network, a peripheral unit belonging to the first CPU, and a peripheral unit belonging to the second CPU. The clock network is used for providing clock signals for the first CPU, the second CPU, the peripheral unit belonging to the first CPU, and the peripheral unit belonging to the second CPU, respectively. A configuration register LPMCR is configured to configure a clock gating mode of the multi-core SOC, the clock gating mode including three clock gating modes, a first clock gating mode: turning off the clock of the first CPU or the second CPU; a second clock gating mode: turning off the clock of the first CPU or the second CPU, the clock of the first CPU-attached peripheral unit, and the clock of the second CPU-attached peripheral unit; and a third clock gating mode: turning off the clock of the first CPU, the second CPU, the first CPU-attached peripheral unit, and the second CPU-attached peripheral unit. Specifically, the first CPU and the second CPU of the embodiment provide corresponding clock signals CPUCLK through a clock network, and the corresponding peripherals are also provided with peripheral clock signals SYSCLK by the clock network.

[0028] Reference Figure 2 , Figure 2 The clock network of the embodiment includes a first clock source INTOSC1, a second clock source INTOSC2, and a third clock source X1. The first clock source and the second clock source are both on-chip crystal oscillators OSC, which can directly output a 10M clock signal; the second clock source INTOSC2 is a main internal clock source and is the default system clock at reset; the first clock source is a backup clock source and can automatically switch to the first clock source INOSC1 when the second clock source INTOSC2 has no clock output. The third clock source is a passive crystal oscillator, and the X1 needs to be externally connected to an oscillation circuit to output a clock signal.

[0029] The clock selection circuit CLKSRCCTL1 is used to select the corresponding clock source. The 0th bit of CLKSRCCTL1 is used for clock source selection, the 1st bit of CLKSRCCTL1 is used for whether to use the frequency multiplication clock output by the PLL, and the 2nd bit is whether the clock of the watchdog is turned off in the third clock gating mode.

[0030] The peripheral clock register CPUx.PCLKCRx corresponds to one peripheral for each bit. The peripheral clock configuration CPUSELx determines which CPU the peripheral clock belongs to.

[0031] The system frequency division register SYSCLKDIVSEL is used to divide the frequency by 1 to 126, and the default is 4 after power-on.

[0032] The peripherals include some communication peripherals such as SPI and SCI, and some analog peripherals such as ADC.

[0033] The system phase-locked loop System PLL can multiply the input clock source and output the multiplied clock. The multiplied clock can be divided to obtain the PLLSYSCLK.

[0034] PLLSYSCLK will control some global RAM. The clock of CPU will be controlled by gating and some logic control to get the clock belonging to CPUx, which can control some memory.

[0035] The clock is provided by the on-chip 10MHz oscillator INTOSC2 at power-up, which is used to run the boot ROM and can be used as the system clock source for the application. The external clock is X1, which has small frequency tolerance and can meet the clock quality requirements of peripherals such as CAN USB.

[0036] Specifically, the low-power multi-core SOC enters different clock gating modes by setting the LPMCR register and executing the IDLE instruction.

[0037] Specifically, the configuration of the LPMCR register is received, and the LPMCR register of the embodiment is addressable, and data can be written to the corresponding address through software layer operation.

[0038] The first clock gating mode is entered in the following way: write 0 to the LPMCR register, and then execute the ILDE instruction to enter the first gating mode. In the first clock gating mode (clock gating mode 1), any enabled interrupt will wake up the CPU from the clock gating mode 1 mode. The clock gating mode 1 of the embodiment only turns off the clock of CPUx. In the clock gating mode 1, the watchdog interrupt signal can generate an interrupt to the CPU to make the CPU exit the clock gating mode 1. Like other peripherals, in the clock gating mode 1, the watchdog interrupt will trigger the WAKEINT interrupt in the peripheral interrupt expansion module PIE.

[0039] Specifically, the first CPU and the second CPU of the embodiment each correspond to an LRMCR register, and the embodiment determines the specific CPU to enter the clock gating mode 1 by writing the value of the corresponding LRMCR register.

[0040] The second clock gating mode (clock gating mode 2) is entered in the following way: write 1 to the LPMCR register to open the wake-up interrupt enable, configure the required GPIO as a wake-up signal to trigger the low-power module; set the duration of the low level, and execute the IDLE instruction to enter the second clock gating mode.

[0041] Clock-gating mode 2 controls the clock of the CPU and the peripheral clock from the CPU SYSCLK to be gated. In clock-gating mode 2, the clock of all peripherals within the CPU subsystem is turned off. The only peripheral that remains functional is the watchdog, as the watchdog module relies on the oscillator clock (OSCCLK) to operate. The watchdog interrupt signal is fed to the low-power mode (LPM) block to wake up the CPU from the standby low-power mode.

[0042] If the watchdog interrupt is used to wake up from clock-gating mode 1 or clock-gating mode 2, the software must ensure that the watchdog interrupt signal goes back to high before attempting to re-enter clock-gating mode. When a watchdog interrupt is generated, the watchdog interrupt signal will remain low and maintain 512 OSCCLK cycles. The current state of the watchdog interrupt signal can be determined by reading the watchdog interrupt status bit (WDINTS) bit in the SCSR register.

[0043] Clock-gating mode 2 exit: The selected GPIO is driven low. If the GPIO drive level goes high during the low period, it will cause the counter to restart counting.

[0044] At the end of the low period, the PLL will cause the internal oscillator OSC clock in the clock source to enter the CPU, and the wake-up interrupt is latched in the peripheral interrupt extension module.

[0045] The system has exited clock-gating mode 2.

[0046] The program can execute normally, and the CPUx and the related peripherals of CPUx can be configured with clocks normally.

[0047] The way to enter the third clock-gating mode (clock-gating mode 3) is to disable all interrupts of the two CPUs except the wake-up interrupt; to put the second CPU into the first clock-gating mode, to configure the LPMCR to 2, to configure the GPIO used as the wake-up signal, to set the watchdog clock valid CLKSRCCTL1.WDHALTI to 0, to turn off the clocks of the first clock source INTOSC1 and the second clock source INTOSC2, and to execute the IDLE instruction on the first CPU.

[0048] Clock-gating mode 3 is a global low-power mode. Almost all system clocks can be gated, and the clocks of the oscillator and analog module can also be turned off. This mode affects both CPU subsystems.

[0049] In clock gating mode 3, if the user has set the watchdog clock active CLKSRCCTL1.WDHALTI = 1, the internal oscillator and CPU1 watchdog will remain active. The watchdog reset will wake the system from HALT mode, but not the watchdog interrupt. This embodiment assumes that the watchdog clock is being calibrated, the watchdog is functioning, and the watchdog needs to be fed at intervals to ensure that the program is executing normally, or a reset will occur if the watchdog is not fed.

[0050] Exit clock gating mode 3: Hold the selected GPIO low for at least 5us.

[0051] Pull the GPIO high to start the initialization of the analog section and PLL.

[0052] Wait for 16us plus 1024 OSCLK cycles for the PLL to stabilize and for the WAKEINT interrupts of both CPUs to be triggered.

[0053] The third clock gating mode (power down mode) gates most of the power supply voltages of the system. This mode affects both CPU subsystems. The power down mode is essentially a controlled power down mode with remote wake-up capability and can be used to save power when the system is inactive for long periods of time. Since gating the power supply voltages can corrupt the logic state, a reset is required to exit the power down mode. To prevent the external system from being affected by the reset, the power down mode provides for the saving of the state of the registers before the power down by the M0 and M1 memories and provides for the isolation of the I / O pins.

[0054] If desired by the user, the first CPU saves the necessary application specific context to the M0 / M1 memories. If I / O isolation is used, the GPIO state is included. The LPMCR register of the first CPU is configured for the power down mode.

[0055] Execute the IDLE instruction to place the device in the power down mode.

[0056] The device is now in the power down mode. If configured, the I / O isolation is enabled and the M0 and M1 memories are preserved. CPU1 and CPU2 are powered down. The digital peripherals are powered down. The oscillators, PLLs, analog peripherals, and flash are in software controlled clock gating mode. The Dx, LSx, and GSx memories are also powered down and their memory contents are lost.

[0057] A falling edge on the GPIOHIBWAKEn pin will wake the device clock sources INTOSC1, INTOSC2, and X1. The wake-up source must hold the GPIOHIBWAKEn pin low long enough to ensure that these clock sources are fully powered up.

[0058] After the clock source is powered on, GPIOHIBWAKEn must be driven high to trigger the wake-up sequence of the rest of the device.

[0059] Then, the BootROM will begin execution. The BootROM code will jump to the user-defined IoRestore function (if it is configured).

[0060] At this point, the device exits power-down mode, and the application can continue to run.

[0061] The IoRestore feature is a user-defined feature that allows applications to reconfigure GPIO states, disable I / O isolation, reconfigure PLLs, restore peripheral configurations, or jump to application code.

[0062] If the application does not jump to application code, BootROM will continue after IoRestore is complete. If no processing occurs within IoRestore, it will automatically disable I / O isolation. At this point, CPU2 will also exit the reset state.

[0063] The program jumps to the main function entry point.

[0064] The low-power multi-core SoC in this embodiment has the following power consumption modes: Clock-gated mode 1 disables the CPU clock (CPUx.CPUCLK) while keeping all peripheral clocks running. Clock-gated mode 1 can be used to reduce system power consumption when the CPU is waiting for peripheral events. When one CPU is idle, it has no effect on other CPU subsystems. Any enabled interrupt will wake the CPU from mode 1. To enter clock-gated mode 1, low-power related registers must be set and specific instructions executed.

[0065] Clock gating mode 2 consumes less power than mode 1. It gates the CPU clock and peripheral clocks from the CPU SYSCLK. However, the watchdog timer is active. Similar to clock gating mode 1, this mode only affects one CPU subsystem. Other CPU subsystems and all their peripherals are unaffected. Clock gating mode 2 is best suited for applications where the wake-up signal comes from an external system (or CPU subsystem) rather than a peripheral input. Any of GPIOs 0-63 can be configured to wake up the subsystem when active low.

[0066] Clock Gated Mode 3 is a global low-power mode that gates almost the entire system clock and allows the oscillator and analog modules to shut down. This mode affects two CPU subsystems.

[0067] The entering into different clock gating modes is user-defined, and different modes are entered by configuring different values of a register LPMCR according to actual application, and clock domains of the three different modes are different.

[0068] The advantage is simple configuration, the user can configure according to the clock domain used by himself, and each CPU and the CPU has corresponding RAM for data storage, and the data processing is more flexible, and the wake-up mode is also simple, and the external GPIO is pulled down for a period of time, and considering different packages, the GPIO can be configured as a wake-up.

[0069] The above merely describes the preferred embodiments of the present application, and is not used to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A low-power multi-core SOC, comprising a first CPU, a second CPU, a clock network, peripheral units associated with the first CPU, and peripheral units associated with the second CPU, wherein the clock network provides clock signals to the first CPU, the second CPU, the peripheral units associated with the first CPU, and the peripheral units associated with the second CPU, respectively; characterized in that: The configuration register LPMCR is used to configure the clock gating mode of the multi-core SoC. The clock gating mode includes three clock gating modes: the first clock gating mode: turning off the clock of the first CPU or the second CPU; the second clock gating mode: turning off the clock of the first CPU or the second CPU, the clock of the peripheral unit associated with the first CPU, and the clock of the peripheral unit associated with the second CPU; the third clock gating mode: turning off the clock of the first CPU, the second CPU, the peripheral unit associated with the first CPU, and the clock of the peripheral unit associated with the second CPU.

2. The low-power multi-core SOC according to claim 1, characterized in that: The clock network includes: a first clock source INTOSC1, a second clock source INTOSC2, a third clock source X1; a clock selection circuit CLKSRCCTL1, which is used to select the corresponding clock source; and a peripheral clock register CPUx.PCLKCRx, which is used to configure the clock of the corresponding peripheral.

3. The low-power multi-core SOC according to claim 2, characterized in that: The clock selection circuit CLKSRCCTL1 is used to select the corresponding clock source. The 0th bit of CLKSRCCTL1 is used for clock source selection, the 1st bit of CLKSRCCTL1 is used to determine whether to use the frequency multiplier clock output by the PLL, and the 2nd bit is used to determine whether the watchdog clock is turned off in the third clock gating mode.

4. The low-power multi-core SoC according to any one of claims 1-3, characterized in that: The low-power multi-core SoC enters different clock gating modes by setting the LPMCR register and executing the IDLE instruction.

5. The low-power multi-core SOC according to claim 4, characterized in that: To enter the first clock-gated mode, write 0 to the LPMCR register and then execute the ILDE instruction.

6. The low-power multi-core SOC according to claim 4, characterized in that: To enter the second clock-gated mode: write 1 to the LPMCR register, enable the wake-up interrupt, configure the required GPIO as a wake-up signal to trigger the low-power module; set the duration of the low level, and execute the IDLE instruction to enter the second clock-gated mode.

7. The low-power multi-core SOC according to claim 4, characterized in that: The third clock gating mode is entered by disabling all interrupts of the two CPUs except for the wake-up interrupt; setting the second CPU to the first clock gating mode, configuring LPMCR to 2, configuring the used GPIOs as wake-up signals, setting the watchdog clock to 0, disabling the clocks of the first clock source INTOSC1 and the second clock source INTOSC2, and executing the IDLE instruction on the first CPU.

8. The low-power multi-core SOC according to claim 7, characterized in that: In the third clock-gated mode, the first CPU saves the necessary application-specific context to the first CPU dedicated RAM block, which does not lose power in the third clock-gated mode.

9. The low-power multi-core SOC according to claim 6, characterized in that: To exit the second clock gating mode: drive the selected GPIO low. If the GPIO drive level goes high during the low-level period, the counter will restart counting. At the end of the low-level period, the PLL causes the clock source to enter the CPU, and the wake-up interrupt is latched in the peripheral interrupt extension module.

10. The low-power multi-core SOC according to claim 7, characterized in that: To exit the third clock gating mode: Keep the selected GPIO low for at least 5µs; pull the GPIO high to start the initialization of the analog section and PLL; wait 16µs plus 1024 OSCLK cycles to allow the PLL to stabilize and the WAKEINT interrupts of both CPUs to be triggered.

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