D flip-flop circuit with storing and loading functions

Abstract

The invention belongs to the technical field of analog integrated circuit design, circuit control and memories, and provides a D flip-flop circuit with saving and loading functions. The D flip-flop circuit is in the same physical space, switching of a storage state circuit and a loading state circuit is achieved through a CMOS switch, and in the storage state, voltage is applied to two RRAM devices through the CMOS switch and an MOS tube, so that the two RRAM devices are in a low-resistance state and a high-resistance state respectively; and in a loading state, the CMOS switch is used for controlling the on-off of the circuit, and the voltage at the two ends of the RRAM device is read. The D flip-flop circuit makes up the defects of functions of an existing nonvolatile D flip-flop, state storage and loading are achieved, meanwhile, through the independent state storage circuit, it is avoided that RRAM state switching affects the speed of the D flip-flop, data are not lost after power failure, and the working current of an RRAM is prevented from increasing the power consumption of the D flip-flop.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of analog integrated circuits, and relates to a D flip-flop circuit with saving and loading functions. BACKGROUND

[0002] Resistive Random Access Memory (RRAM) is an emerging memory technology in which information is saved in the resistance of a memory cell. These cells are usually composed of a very thin dielectric layer on the nanometer scale, which is usually an insulator. By forcing a current through the cell, a small conductive filament consisting of ion vacancies (and positive charges) can be formed in the dielectric material, causing a change in resistance. By applying a current in the opposite direction, the filament can break, causing an increase in resistance. The resistance difference between the formed and broken filaments can be interpreted as different cell states and used as memory, with the stored data being non-volatile and not lost after power failure. The D flip-flop is one of the most basic and important timing logic units in digital circuits. Its core function is to sample and store input data (D) at a specific edge (usually the rising or falling edge) of the clock signal and hold it as output (Q) until the next clock active edge.

[0003] The existing non-volatile D flip-flop usually connects RRAM directly into the D flip-flop circuit, which has the following defects: 1) RRAM state switching will damage the speed of the D flip-flop, limiting the high-frequency application of the D flip-flop; 2) The read and write of RRAM require mA-level current, which will increase the dynamic power consumption of the D flip-flop; 3) The stability of RRAM is insufficient, and the high resistance state will fluctuate with temperature.

[0004] The present application is dedicated to improving the speed of the D flip-flop and reducing the dynamic power consumption of the D flip-flop. SUMMARY

[0005] The purpose of the present application is to design a D flip-flop circuit with saving and loading functions to overcome the defects of the existing non-volatile D flip-flop, such as limited high-frequency application and high dynamic power consumption, which can save the state of the D flip-flop in RRAM and will not lose it after power failure, and can also read the saved state from RRAM.

[0006] To achieve the above purpose, the present application adopts the following technical solutions: As a first aspect of the present invention, a D flip-flop circuit with storage and loading functions is proposed, including a D flip-flop unit and a read / write control circuit, comprising: at least one D flip-flop unit and each D flip-flop unit including a D flip-flop and a state storage circuit; the state storage circuit including an RRAM for storing the state of the D flip-flop and a CMOS switch. The D flip-flops in each D flip-flop unit are connected to an external read / write control circuit through a state storage circuit. When the read / write control circuit inputs a write signal, the write signal controls the CMOS switch to control the state storage circuit to enter the write state and store the state of the D flip-flops in the RRAM. When the read / write control circuit inputs a read signal, the CMOS switch controls the state storage circuit to enter the read state and reads the stored state of the D flip-flops from both ends of the RRAM.

[0007] The RRAM for storing the state of the D flip-flop consists of two RRAMs, R1 and R2, which are used to store the 0 state and 1 state of the D flip-flop, respectively.

[0008] The CMOS switches include two sets; when the read / write control circuit inputs a write signal, the write signal controls the first set of CMOS switches to enter the write state.

[0009] When the read / write control circuit receives a read signal, it enters the read state through the second set of CMOS switch control state storage circuits.

[0010] The state preservation circuit is used to preserve the state of the D flip-flops in the D flip-flop unit.

[0011] The external read / write control circuit is connected to the state storage circuit within each D flip-flop unit.

[0012] The D flip-flop circuit described in this invention is configured with a state saving circuit for each D flip-flop, forming a D flip-flop unit that can save the state. With the help of an external read / write circuit, it is easy to realize the saving and loading of the state of N D flip-flop arrays and the overall array. Each state saving circuit in the D flip-flop circuit can independently save the state, and the state saving process will not affect the speed of the D flip-flop in its own D flip-flop unit or other D flip-flop units. The state preservation circuit of the D flip-flop circuit is disconnected from the D flip-flop when the D flip-flop is working normally, which reduces the power consumption of the D flip-flop. As a second aspect of the present invention, a method for saving and loading the state of a D flip-flop circuit is proposed, comprising two parts: state saving and state loading; the state saving includes the following steps: Step 1, the read-write control circuit gives a write signal regsave, and outputs a high and a low write control signal wen and wenn to the state saving circuit through two inverters; the D flip-flop outputs Q and Qn to the state saving circuit; Step 2, the state saving circuit receives a high and a low write control signal wen and wenn and accordingly closes the first group of CMOS switches and opens the second group of CMOS switches.

[0013] Under the state saving condition, when Q is 1 and Qn is 0, R1 of the RRAM is set to 1 and R2 is set to 0; Under the state saving condition, when Q is 0 and Qn is 1, R1 of the RRAM is set to 0 and R2 is set to 1.

[0014] The state loading, i.e. the state reading process, includes the following steps: S1, based on the read-write control circuit read signal regload, a high and a low read control signal ren and renn is output to the state saving circuit through two inverters; S2, the state saving circuit accepts signals ren and renn, controls the second group of CMOS switches to close, and reads the voltage on the two RRAM devices; at this time, R1 and R2 of the RRAM are loaded with the states of Q and Qn respectively.

[0015] The D flip-flop circuit capable of saving and loading states in real time includes a D flip-flop circuit, a state saving circuit and a read-write control circuit. The D flip-flop circuit obtains an input signal, generates states Q and Qn and keeps them until the next clock active edge.

[0016] The state saving circuit is used to save and load the required states, and convert the states (0 and 1) into high resistance and low resistance states of the RRAM.

[0017] The read-write control circuit is used to control the state saving circuit in all the savable state D flip-flop units, and control the saving or loading of states.

[0018] The connection relationship of the D flip-flop circuit capable of saving and loading states is as follows: In each savable state D flip-flop unit, the D flip-flop circuit is connected to the state saving circuit, n savable state D flip-flop units form an array, and the read-write control circuit outside the array is connected to the state saving circuit in all the savable state D flip-flop units.

[0019] Compared with the existing state saving method, the state saving and loading method of the D flip-flop circuit uses RRAM to save the states (0 and 1) as low resistance and high resistance states of the RRAM, so that the saved states will not be lost after power failure.

[0020] The D flip-flop circuit with the saving and loading functions has the following beneficial effects compared with the prior art D flip-flop circuit: 1. The circuit is provided with a state saving circuit for each D flip-flop, thereby forming a D flip-flop unit capable of saving states, and cooperating with an external read-write circuit to facilitate the saving and loading of N D flip-flop arrays and the overall state of the arrays. 2. Each state saving circuit in the D flip-flop circuit can independently save states, and the state saving process does not affect the speed of the D flip-flop in the D flip-flop unit and other D flip-flop units. 3. The state saving circuit of the D flip-flop circuit is disconnected from the D flip-flop when the D flip-flop is normally working, thereby reducing the power consumption of the D flip-flop. 4. Compared with the prior art state saving method, the D flip-flop circuit uses RRAM to save states (0 and 1) as low resistance states and high resistance states of RRAM, thereby ensuring that the saved states will not be lost after power failure. BRIEF DESCRIPTION OF DRAWINGS

[0021] The accompanying drawings, which are included to provide a further understanding of the application, form a part of the application and, along with the specification, serve to explain the application. The illustrative embodiments of the application and their description serve to explain the application and do not limit the application in any manner. In the drawings: Figure 1 a is a signal flow chart of the D flip-flop circuit with the saving and loading functions when writing states, Figure 1 b is a signal flow chart of the D flip-flop circuit with the saving and loading functions when reading states; Figure 2 is a circuit principle diagram of the state saving circuit in the D flip-flop circuit with the saving and loading functions; Figure 3 is a circuit principle diagram of the read-write control circuit in the D flip-flop circuit with the saving and loading functions; Figure 4 is a circuit block diagram of the state saving circuit in the D flip-flop circuit with the saving and loading functions; Figure 5 is a circuit block diagram of the state saving circuit in the D flip-flop circuit with the saving and loading functions; DETAILED DESCRIPTION

[0022] In order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, the terms of "first", "second", and the like are used to distinguish the same items or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and the order is not limited. Those skilled in the art can understand that the terms of "first", "second", and the like do not limit the quantity and the execution order, and the terms of "first", "second", and the like do not necessarily mean different.

[0023] It should be noted that in the present application, the words of "exemplary" or "for example" are used to represent an example, illustration, or description. Any embodiment or design scheme described as "exemplary" or "for example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. In fact, the words of "exemplary" or "for example" are intended to present the relevant concept in a specific way.

[0024] In the present application, "at least one" means one or more, and "multiple" means two or more. The association relationship of the associated objects is described, which means that there can be three kinds of relationships, for example, A and / or B, which can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. The following at least one (or similar expressions) means any combination of these items, including any combination of single item (or multiple items). For example, at least one of a, b, or c can represent: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b, and c, where a, b, and c can be single or multiple.

[0025] The D flip-flop circuit with the saving and loading functions proposed in the present application will be described in detail below in combination with the drawings and embodiments.

[0026] Embodiment 1 The present application proposes a D flip-flop circuit with saving and loading functions, which acquires an input signal, generates states Q and Qn, and keeps them to the next clock active edge. Figure 5 is the circuit schematic diagram of the existing D flip-flop that can save the state, and the differences between the present application and the existing D flip-flop are as follows: (1) the RRAM device is placed inside the D flip-flop circuit (2) there is no special read-write control circuit, and the state is automatically saved in the RRAM when the D flip-flop is normally running (3) the saved state is not the state Q and Qn output by the D flip-flop, but the voltage of a node in the D flip-flop circuit. The specific embodiments will be described in detail below.

[0027] The D flip-flop circuit includes D flip-flop units and read-write control circuit, and the D flip-flop units are not less than 1 and each D flip-flop unit includes a D flip-flop and a state saving circuit; the state saving circuit includes RRAM for saving the state of the D flip-flop and a CMOS switch; the D flip-flop circuit can save the loading state in real time; The state saving circuit is used for saving and loading the required state, and converting the state (0 and 1) into the high resistance state and the low resistance state of the RRAM; the read-write control circuit is used for controlling the state saving circuit in all the D flip-flop units which can save the state, and controlling the state saving circuit to save or load the state.

[0028] Figure 1 a is a signal flow chart of the circuit when the D flip-flop circuit writes the state, a write signal regsave is input into the read-write control circuit, a signal wen and wenn are output from the read-write control circuit to the state saving circuit to control the CMOS switch in the state saving circuit; a clock signal CLK and signals D0, D1, D2, D3 and D4 are input into the D flip-flop, and the D flip-flop in each D flip-flop unit outputs two states Q and Qn to the state saving circuit, and the state saving circuit saves the two states as the high resistance state and the low resistance state of the two RRAMs respectively.

[0029] Figure 1 b is a signal flow chart of the circuit when reading the state, a read signal regload is input into the read-write control circuit, a signal ren and renn are output from the read-write control circuit to the state saving circuit to control the CMOS switch in the state saving circuit; the voltage between the two ends of the RRAM is directly read out from the state saving circuit.

[0030] Figure 2 It is a circuit principle diagram of the state saving circuit, and includes NMOS1, NMOS2, NMOS3, NMOS4, NMOS5, NMOS6, NMOS7, NMOS8, PMOS1, PMOS2, PMOS3, PMOS4, PMOS5, PMOS6, PMOS7, PMOS8, R1 and R2. Figure 3 It is a circuit principle diagram of the read-write control circuit, and includes PMOS1, PMOS2, PMOS3, PMOS4, PMOS5, NMOS1, NMOS2, NMOS3 and NMOS4. Figure 4 It is a circuit block diagram of the state saving circuit, and the switch 1 includes NMOS2 and PMOS2; the switch 2 includes NMOS3 and PMOS4; the switch 3 includes NMOS5 and PMOS5; the switch 4 includes NMOS6 and PMOS6; and the switch 5 includes NMOS7 and PMOS7.

[0031] The connection relationships of the D flip-flop circuit that can save and load states are as follows: Within each storable state D flip-flop unit, the D flip-flop circuit is connected to the state storage circuit. n storable state D flip-flop units form an array, and the read / write control circuit outside the array is connected to the state storage circuit in all storable state D flip-flop units.

[0032] The D flip-flops in each D flip-flop unit are connected to an external read / write control circuit through a state storage circuit. When the read / write control circuit inputs a write signal, the write signal controls the CMOS switch to control the state storage circuit to enter the write state and store the state of the D flip-flops in the RRAM. When the read / write control circuit inputs a read signal, the CMOS switch controls the state storage circuit to enter the read state and reads the stored state of the D flip-flops from both ends of the RRAM.

[0033] The RRAM for storing the state of the D flip-flop consists of two RRAMs, R1 and R2, which are used to store the 0 state and 1 state of the D flip-flop, respectively.

[0034] The CMOS switches include two sets; when the read / write control circuit inputs a write signal, the write signal controls the first set of CMOS switches to enter the write state.

[0035] When the read / write control circuit receives a read signal, it enters the read state through the second set of CMOS switch control state storage circuits.

[0036] The state preservation circuit is used to preserve the state of the D flip-flops in the D flip-flop unit.

[0037] The external read / write control circuit is connected to the state storage circuit within each D flip-flop unit.

[0038] The D flip-flop circuit described in this invention is configured with a state saving circuit for each D flip-flop, forming a D flip-flop unit that can save the state. With the help of an external read / write circuit, it is easy to realize the saving and loading of the state of N D flip-flop arrays and the overall array. Each state saving circuit in the D flip-flop circuit can independently save the state, and the state saving process will not affect the speed of the D flip-flop in its own D flip-flop unit or other D flip-flop units. The state preservation circuit of the D flip-flop circuit is disconnected from the D flip-flop when the D flip-flop is working normally, which reduces the power consumption of the D flip-flop. Compared with existing state saving methods, the state saving and loading method of the D flip-flop circuit uses RRAM to save the state (0 and 1) as the low-resistance state and high-resistance state of RRAM, ensuring that the saved state will not be lost after power failure.

[0039] The first group of CMOS switches includes switch 1, switch 2 and switch 3; switch 1 includes NMOS 1 and PMOS 2, switch 2 includes NMOS 3 and PMOS 4, and switch 3 includes NMOS 5 and PMOS 5; The second group of CMOS switches includes switch 4 and switch 5; switch 4 includes NMOS 6 and PMOS 6, and switch 5 includes NMOS 7 and PMOS 7.

[0040] The state saving circuit includes eight NMOS tubes, eight PMOS tubes and two RRAMs; the eight NMOS tubes include NMOS 1, NMOS 2, NMOS 3, NMOS 4, NMOS 5, NMOS 6, NMOS 7 and NMOS 8; the eight PMOS tubes include PMOS 1, PMOS 2, PMOS 3, PMOS 4, PMOS 5, PMOS 6, PMOS 7 and PMOS 8; and the two RRAMs include R1 and R2; the drain of PMOS 1 is connected to the drain of PMOS 8, the gate of PMOS 1 is connected to the source of PMOS 8, the source of PMOS 1 is connected to the gate of PMOS 8 and the drain of NMOS 1, the source of NMOS 1 is connected to the source of NMOS 4 and the source of NMOS 8, the gate of NMOS 2 is connected to the gate of NMOS 3 and the gate of NMOS 5, the drain of NMOS 2 is connected to the source of PMOS 1, the source of PMOS 2, the drain of NMOS 3 and the source of PMOS 4, the source of NMOS 2 is connected to the drain of PMOS 2, the source of PMOS 3 and the first end of R2, the gate of PMOS 2 is connected to the gate of PMOS 4 and the gate of PMOS 5, the gate of PMOS 3 is connected to the gate of PMOS 6 and the gate of NMOS 7, the source of NMOS 3 is connected to the drain of NMOS 4, the source of PMOS 4 and the first end of R1, the gate of NMOS 4 is connected to the gate of NMOS 6 and the gate of PMOS 7, the second end of R1 is connected to the source of NMOS 5, the drain of PMOS 5, the drain of NMOS 6 and the second end of R2, the drain of NMOS 5 is connected to the source of PMOS 5, the source of PMOS 8 and the drain of NMOS 8, the source of NMOS 6 is connected to the drain of NMOS 7 and the source of PMOS 7, the source of NMOS 7 is connected to the drain of PMOS 7; the body of all NMOS tubes in the circuit is grounded, and the body of all PMOS tubes is connected to the write voltage vwr; the write voltage vwr is connected to the drain of PMOS 1, the write signal wenn and wen are respectively connected to the gate of PMOS 2 and the gate of NMOS 2, the read signal renn and ren are respectively connected to the gate of NMOS 4 and the gate of PMOS 3, the D flip-flop state signals Q and Qn are respectively connected to the gate of NMOS 1 and the gate of NMOS 8, the source of NMOS 1 is grounded, and the drain of PMOS 3 is connected to the voltage vcc.

[0041] The read-write control circuit comprises 5 PMOS tubes and 4 NMOS tubes; Wherein, the gate of PMOS 9 is connected with the gate of NMOS 9, the source of PMOS 9 is connected with the drain of NMOS 9, the gate of PMOS 10 and the gate of NMOS 10, the drain of PMOS 9 is connected with the drain of PMOS 10, the drain of PMOS 11, the drain of PMOS 12 and the drain of PMOS 13, the source of NMOS 9 is connected with the source of NMOS 10, the source of NMOS 11 and the source of NMOS 12, the source of PMOS 10 is connected with the drain of NMOS 10, the gate of PMOS 11 is connected with the gate of NMOS 11, the source of PMOS 11 is connected with the drain of NMOS 11, the gate of PMOS 12, the gate of NMOS 12 and the gate of PMOS 13, the source of PMOS 12 is connected with the drain of NMOS 12, the body of all PMOS tubes is connected with the power supply vrram, the body of all NMOS tubes is connected with the ground, the gate of PMOS 9 is connected with the loading state signal regload, the gate of PMOS 11 is connected with the saving state signal regsave, the source of NMOS 9 is connected with the ground, the drain of PMOS 9 is connected with vrram, the source of PMOS 13 outputs the writing voltage vwr, the source of PMOS 9 and the source of PMOS 10 respectively output the reading signals renn and ren, and the source of PMOS 11 and the source of PMOS 12 respectively output the writing signals wenn and wen.

[0042] The D flip-flop circuit state saving process comprises the following steps: Step 1, the read-write control circuit is given the writing signal regsave, and two inverters output two writing control signals wen and wenn to the state saving circuit.

[0043] Step 2, the state saving circuit accepts the signals wen and wenn, and the switches 1, 2 and 3 are closed. When Q is 1 (high potential) and Qn is 0 (low potential), R1 is in a low resistance state (set to 1) and R2 is in a high resistance state (set to 0); when Q is 0 (low potential) and Qn is 1 (high potential), R1 is in a high resistance state (set to 0) and R2 is in a low resistance state (set to 1).

[0044] The D flip-flop circuit state reading process comprises the following steps: Step 1, based on the reading signal regload of the read-write control circuit, two inverters output two reading control signals ren and renn to the state saving circuit.

[0045] Step 2, the state saving circuit accepts the signals ren and renn, and the switches 4 and 5 are opened to read the voltages on the two RRAM devices.

[0046] Although the present application has been described in connection with various embodiments thereof, it will be understood that other modifications and variations will be apparent to those skilled in the art in view of the foregoing disclosure, the drawings, and the appended claims. It is therefore contemplated to cover any and all such modifications and variations that fall within the scope of the present application. It should be understood that "comprising" or "comprise" or "including" or "include" or "consisting of" or "consist of" as used herein is intended to mean the inclusion of one or more recited elements or steps, but not the exclusion of other recited elements or steps. A single processor or other unit can implement several items recited in the specification. Some measures are described in mutually different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0047] Although the present application has been described in connection with specific features thereof, it will be evident to those skilled in the art that various modifications and changes can be made to the application without departing from the spirit and scope thereof. Accordingly, it is intended to include all modifications and alterations, and all equivalents thereof, insofar as they come within the scope of the present application. It is to be understood that the present application is not limited to particular examples described, as such may, of course, vary. The application can be practiced according to the claims and incorporating modifications obvious to those skilled in the art. The application is further limited by the scope of the following claims, and their equivalents.

Claims

1. A D flip-flop circuit with save and load functions, comprising a D flip-flop unit and a read / write control circuit, characterized in that, include: The D flip-flop unit is not less than one, and each D flip-flop unit includes a D flip-flop and a state storage circuit; the state storage circuit includes an RRAM for storing the state of the D flip-flop and a CMOS switch. The D flip-flops in each D flip-flop unit are connected to an external read / write control circuit through a state storage circuit. When the read / write control circuit inputs a write signal, the write signal controls the CMOS switch to control the state storage circuit to enter the write state and store the state of the D flip-flops in the RRAM. When the read / write control circuit inputs a read signal, the CMOS switch controls the state storage circuit to enter the read state and reads the stored state of the D flip-flops from both ends of the RRAM.

2. The D flip-flop circuit with save and load functions according to claim 1, characterized in that, The RRAM for storing the state of the D flip-flop consists of two RRAMs, R1 and R2, which are used to store the 0 state and 1 state of the D flip-flop, respectively.

3. A D flip-flop circuit with save and load functions according to claim 1, characterized in that, The CMOS switches include two sets; when the read / write control circuit inputs a write signal, the write signal controls the first set of CMOS switches to enter the write state.

4. A D flip-flop circuit with save and load functions according to claim 3, characterized in that, When the read / write control circuit receives a read signal, it enters the read state through the second set of CMOS switch control state storage circuit.

5. A D flip-flop circuit with save and load functions according to claim 1, characterized in that, The state preservation circuit is used to preserve the state of the D flip-flops in the D flip-flop unit.

6. A D flip-flop circuit with save and load functions according to claim 1, characterized in that, The external read / write control circuit is connected to the state storage circuit within each D flip-flop unit.

7. A method for saving and loading the state of a D flip-flop circuit, characterized in that, It includes two parts: state saving and state loading; the state saving includes the following steps: Step 1: The read / write control circuit is given a write signal regsave, which is then passed through two inverters to output two write control signals, wen and wenn, one high and one low, to the state preservation circuit; the D flip-flop outputs Q and Qn to the state preservation circuit. Step 2: The state preservation circuit receives a high and a low write control signal wen and wenn, and closes the first group of CMOS switches and opens the second group of CMOS switches accordingly.

8. The method for saving and loading the state of a D flip-flop circuit according to claim 7, characterized in that, Under the state saving condition, when Q is 1 and Qn is 0, R1 of RRAM is set to 1 and R2 is set to 0.

9. The method for saving and loading the state of a D flip-flop circuit according to claim 8, characterized in that, Under the state saving conditions, when Q is 0 and Qn is 1, R1 of RRAM is set to 0 and R2 is set to 1.

10. The method for saving and loading the state of a D flip-flop circuit according to claim 7, characterized in that, The state loading, or state reading process, includes the following steps: S1. Based on the read signal regload of the read-write control circuit, two inverters output two read control signals ren and renn, one high and one low, to the state preservation circuit. S2. The state preservation circuit receives signals ren and renn, controls the second set of CMOS switches to close, and reads the voltage on the two RRAM devices. At this time, R1 and R2 of the RRAM are loaded with the states of Q and Qn, respectively.

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