Antenna packaging structure and preparation method thereof

Abstract

The invention discloses an antenna packaging structure and a preparation method thereof, the antenna packaging structure comprises a substrate, a chip, a first conduction structure and an antenna module, the substrate comprises a first surface and a second surface which are opposite to each other along the thickness direction, and the first surface is provided with a first connection part; the chip is arranged on the first surface and electrically connected with the first connecting part, and a first through hole is formed in the chip; the first conduction structure is electrically connected with the chip and extends to one side, deviating from the substrate, of the chip through the first through hole; the antenna module is arranged on the side, away from the substrate, of the chip, and the antenna module is electrically connected with the first conduction structure. The use performance of the antenna packaging structure can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to an antenna packaging structure and a preparation method thereof. BACKGROUND

[0002] With the extreme pursuit of high frequency, high speed and miniaturization of communication terminals, the number of components in the antenna and the radio frequency front end will increase, and the available area of the radio frequency front end is increasingly limited. Especially in the millimeter wave frequency band, the performance of the transmission path has a greater impact on signal loss, and the traditional chip + substrate + antenna architecture mode also faces technical challenges.

[0003] Therefore, the packaging antenna technology emerges as the times require. The packaging antenna is based on packaging materials and processes to integrate the antenna and the chip in the same package, which improves the integration level and takes into account the antenna performance, cost and size. However, the use performance of the current antenna packaging structure needs to be improved. SUMMARY

[0004] Embodiments of the present application provide an antenna packaging structure and a preparation method thereof, aiming to improve the use performance of the antenna packaging structure.

[0005] The first aspect of the present application provides an antenna packaging structure, which comprises a substrate, a chip, a first conduction structure and an antenna module. The substrate comprises a first surface and a second surface opposite to each other in the thickness direction, and the first surface is provided with a first connecting part. The chip is arranged on the first surface and electrically connected to the first connecting part, and the chip is provided with a first through hole. The first conduction structure is electrically connected to the chip and extends to the side of the chip away from the substrate through the first through hole. The antenna module is arranged on the side of the chip away from the substrate, and the antenna module is electrically connected to the first conduction structure.

[0006] According to the embodiment of the first aspect of the present application, the active surface of the chip is arranged to face the substrate, and the back surface of the chip is arranged to face the antenna module.

[0007] According to any one of the preceding embodiments of the first aspect of the present application, the active surface of the chip is provided with a signal transmission layer, the signal transmission layer is electrically connected to the first connecting part, the first conduction structure is electrically connected to the signal transmission layer through the first through hole, and at least part of the first conduction structure is located on the back surface of the chip.

[0008] According to any one of the preceding embodiments of the first aspect of the present application, the first conduction structure comprises a first conduction part and a second conduction part, the first conduction part is located in the first through hole, the second conduction part is located on the back surface of the chip, and the first conduction part is electrically connected between the signal transmission layer and the second conduction part.

[0009] According to any of the foregoing embodiments of the first aspect of this application, a third connecting portion is further provided between the second conductive portion and the antenna module, the third connecting portion connecting the side of the second conductive portion away from the substrate and the side of the antenna module facing the substrate.

[0010] According to any of the foregoing embodiments of the first aspect of this application, the antenna packaging structure further includes a packaging layer that covers the chip and the antenna module, and the packaging layer covers a portion of the first surface.

[0011] According to any of the foregoing embodiments of the first aspect of this application, the material of the encapsulation layer includes a molding compound.

[0012] According to any of the foregoing embodiments of the first aspect of this application, the encapsulation layer includes a first encapsulation layer and a second encapsulation layer, wherein the second encapsulation layer is located on the side of the first encapsulation layer away from the substrate; wherein at least a portion of the first encapsulation layer is located on the side of the chip away from the substrate, and at least a portion of the second encapsulation layer is located on the side of the antenna module away from the substrate.

[0013] According to any of the foregoing embodiments of the first aspect of this application, the first encapsulation layer is further provided with a first opening to expose the side surface of the first conductive structure away from the substrate, and the antenna module is electrically connected to the first conductive structure through the first opening.

[0014] According to any of the foregoing embodiments of the first aspect of this application, a first gap is provided between the chip and the substrate, and a first filler adhesive is provided in the first gap; and / or, a second gap is provided between the antenna module and the chip, and a second filler adhesive is provided in the second gap.

[0015] According to any of the foregoing embodiments of the first aspect of this application, the substrate includes a carrier plate, a first wiring layer, a second wiring layer, and an interconnect structure. The first wiring layer and the second wiring layer are disposed opposite to each other on both sides of the carrier plate in the thickness direction. The interconnect structure passes through the carrier plate and connects the first wiring layer and the second wiring layer. The first connection portion is connected to the surface of the first wiring layer opposite to the second wiring layer.

[0016] According to any of the foregoing embodiments of the first aspect of this application, the second surface is provided with a second connecting portion, and the second connecting portion is electrically connected to the second wiring layer.

[0017] According to any of the foregoing embodiments of the first aspect of this application, the substrate further includes a first dielectric layer, with at least a portion of the first wiring layer located within the first dielectric layer; and / or, the substrate further includes a second dielectric layer, with at least a portion of the second wiring layer located within the second dielectric layer.

[0018] According to any of the foregoing embodiments of the first aspect of this application, the first wiring layer includes at least two sub-wiring layers.

[0019] A second aspect of this application provides a method for fabricating an antenna packaging structure, comprising: A substrate is prepared, the substrate including a first surface and a second surface that are opposite to each other along the thickness direction; A chip is disposed on a first surface, the chip is electrically connected to a substrate through a first connecting portion, and the chip has a first through hole; A first conductive structure is fabricated, which is electrically connected to the chip and extends through a first via to the side of the chip away from the substrate. An antenna module is disposed on the side of the chip away from the substrate, and the antenna module is electrically connected to the first conductive structure.

[0020] According to the second aspect of this application, after the step of preparing the first conductive structure, the preparation method further includes: preparing a first encapsulation layer to encapsulate the chip, wherein at least a portion of the first encapsulation layer is located on the side of the chip away from the substrate, and the first encapsulation layer has a first opening to expose the surface of the first conductive structure away from the substrate.

[0021] According to any of the foregoing embodiments of the second aspect of this application, after the step of fabricating the antenna module, the fabrication method further includes: A second filler adhesive is prepared to fill the second gap between the antenna module and the chip; A second encapsulation layer is prepared to encapsulate the antenna module. The second encapsulation layer covers the side surface of the antenna module and the side surface of the antenna module that is away from the substrate.

[0022] According to any of the foregoing embodiments of the second aspect of this application, after the step of setting the chip, the preparation method further includes: preparing a first filler adhesive to fill the first gap between the chip and the substrate.

[0023] According to any of the foregoing embodiments of the second aspect of this application, the steps for preparing the substrate include: Through-holes are fabricated on a carrier plate; Interconnect structures are fabricated within vias; Wiring layers and dielectric layers are fabricated on both sides of the carrier board, respectively.

[0024] According to any of the foregoing embodiments of the second aspect of this application, the step of preparing a through hole includes: preparing a through hole by laser-induced process or wet etching process.

[0025] A third aspect of this application provides an electronic device, which includes an antenna packaging structure provided in any of the embodiments of the first aspect above, or includes an antenna packaging structure formed in any of the embodiments of the second aspect above.

[0026] According to the antenna packaging structure of this application embodiment, the antenna packaging structure includes a substrate, a chip, a first conductive structure, and an antenna module. After the signal is generated or processed in the circuit inside the chip, it no longer needs to go through the traditional long path of "chip-substrate-transmission line-antenna". Instead, it directly transmits the signal to the other side through the first conductive structure from the thickness direction of the chip and interacts with the adjacent antenna module. The signal transmission path between the antenna module and the chip is greatly shortened and optimized, reducing the signal loss of the antenna and improving the performance of the antenna packaging structure. Attached Figure Description

[0027] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0028] Figure 1 This is a cross-sectional schematic diagram of an antenna packaging structure provided in an embodiment of this application; Figure 2 This is a cross-sectional view of another antenna packaging structure provided in this application embodiment; Figure 3 This is a schematic flowchart of a method for fabricating an antenna packaging structure according to an embodiment of this application; Figures 4 to 9 This is a schematic diagram of the structural changes corresponding to a method for fabricating an antenna packaging structure provided in this application embodiment.

[0029] Explanation of reference numerals in the attached figures: 1. Substrate; 11. First surface; 12. Second surface; 13. First connection portion; 14. Second connection portion; 15. Third connection portion; 101. Carrier plate; 102. First wiring layer; 103. Second wiring layer; 104. Interconnect structure; 105. First dielectric layer; 106. Second dielectric layer; 2. Chip; 20. First through-hole; 21. First conductive structure; 211. First conductive part; 212. Second conductive part; 22. Signal transmission layer; 3. Antenna module; 4. Encapsulation layer; 41. First encapsulation layer; 410. First opening; 42. Second encapsulation layer; 51. First gap; 52. Second gap; 53. First filler adhesive; 54. Second filler adhesive. Detailed Implementation

[0030] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0031] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0032] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0033] This application provides an antenna packaging structure and its fabrication method. The following description, in conjunction with the accompanying drawings, will illustrate various embodiments of the antenna packaging structure and its fabrication method.

[0034] Reference Figure 1 and Figure 2 The first aspect of this application provides an antenna packaging structure, including a substrate 1, a chip 2, a first conductive structure 21, and an antenna module 3. The substrate 1 includes a first surface 11 and a second surface 12 that are opposite to each other along the thickness direction. The first surface 11 is provided with a first connecting portion 13. The chip 2 is disposed on the first surface 11 and electrically connected to the first connecting portion 13. The chip 2 has a first through hole 20. The first conductive structure 21 is electrically connected to the chip 2 and extends through the first through hole 20 to the side of the chip 2 away from the substrate 1. The antenna module 3 is disposed on the side of the chip 2 away from the substrate 1, and the antenna module 3 is electrically connected to the first conductive structure 21.

[0035] The substrate 1 may include a carrier plate 101 and a wiring layer and an insulating layer disposed on the carrier plate 101. The insulating layer may have through holes to expose a portion of the wiring layer so that the chip 2 can be electrically connected to the wiring layer in the substrate 1 through the first connection portion 13. The first connection portion 13 may be a solder pad or a solder ball.

[0036] Chip 2 can refer to RF front-end chip 2, such as power amplifier, low-noise amplifier, switch, or even transceiver chip 2 in the millimeter-wave band. Chip 2 is directly mounted on the first surface 11 of substrate 1 and is electrically connected to the first connection part 13 by soldering or flip-chip bonding, thereby obtaining power, control, and low-frequency signals.

[0037] The first via 20 can be a TSV via etched inside the chip 2. A TSV is a tiny hole vertically drilled through the silicon chip 2 (or wafer) and filled with a conductive material (such as copper, polysilicon, etc.) to establish an electrical connection between the upper and lower surfaces of the chip 2. Part of the first conductive structure 21 is filled in the first via. The material of the first conductive structure 21 can be a conductive metal material, such as copper, to guide the circuit signals of the active surface of the chip 2 to the back surface of the chip 2.

[0038] The antenna module 3 is directly fabricated or mounted on the side of the chip 2 away from the substrate 1. It can be an antenna (such as a patch antenna) that is directly fabricated on the passivation layer of the chip 2 through semiconductor processes (such as deposition and photolithography), or it can be a separate antenna module 3 mounted on the side of the chip 2 away from the substrate 1.

[0039] In the embodiments of this application, the antenna packaging structure includes a substrate 1, a chip 2, a first conductive structure 21, and an antenna module 3. After the signal is generated or processed in the circuitry inside the chip 2, it no longer needs to travel through the traditional long path of "chip-substrate-transmission line-antenna." Instead, it is transmitted directly from the thickness direction of the chip 2 to the other side through the first conductive structure 21, interacting with the adjacent antenna module 3. The signal transmission path between the antenna module 3 and the chip 2 is greatly shortened and optimized, reducing antenna signal loss and improving the performance of the antenna packaging structure.

[0040] In the traditional architecture of related technologies, the antenna and chip 2 are located at different positions on the substrate 1, and the signal needs to travel through a long transmission line on the substrate 1, resulting in severe path loss. For example, millimeter-wave signals are prone to attenuation during transmission and are very sensitive to impedance discontinuities. Traditional long leads and substrate 1 traces introduce parasitic inductance and capacitance, leading to impedance mismatch and signal reflection.

[0041] In this embodiment, a shorter and more direct electrical connection is provided between chip 2 and the antenna. This is crucial for high-frequency signals (such as 5G and millimeter-wave antennas), effectively reducing signal loss and delay, improving antenna efficiency, reducing system power consumption, and increasing communication distance. Specifically, the antenna module 3 and chip 2 are vertically interconnected through the first through-hole 20 and the first conductive structure 21, making the structure of the antenna module 3 and chip 2 more compact, reducing parasitic effects, and making it easier to achieve good impedance matching, thereby ensuring the integrity of high-frequency signals and improving communication quality and speed.

[0042] In some alternative embodiments, the active surface of chip 2 is disposed facing the substrate 1, and the back surface of chip 2 is disposed facing the antenna module 3.

[0043] In these optional embodiments, chip 2 is mounted in a "flip-chip" configuration, meaning that its active side, which integrates transistors and other active circuitry, faces directly towards and connects to substrate 1 via a bump (first connection portion 13), while the unprocessed back side faces and supports antenna module 3. This achieves the ultimate optimization of the signal transmission path. Since the high-frequency millimeter-wave signal is generated or processed in the RF circuitry of the active side of chip 2, it is transmitted vertically upwards from its source to the antenna on the back side through the TSV aperture, virtually eliminating any lateral detour losses. The path is the shortest and cleanest, effectively reducing insertion loss and improving antenna radiation efficiency.

[0044] Meanwhile, the flip-chip design avoids traditional wire bonding, significantly reducing parasitic inductance and resistance, and further ensuring the integrity of high-frequency signals. Secondly, this embodiment also facilitates better packaging in three-dimensional integration. This layout allows chip 2 to simultaneously serve as the RF functional carrier and the antenna support platform, tightly stacking two key components within a very small vertical space. This greatly saves planar area, reduces package profile, and achieves device miniaturization and high integration, meeting the ultimate pursuit of high performance and small size in communication terminals.

[0045] In some optional embodiments, a signal transmission layer 22 is provided on the active surface of the chip 2. The signal transmission layer 22 is electrically connected to the first connection portion 13. The first conduction structure 21 is electrically connected to the signal transmission layer 22 via the first through hole 20, and at least a portion of the first conduction structure 21 is located on the back side of the chip 2.

[0046] In these embodiments, the signal transmission layer 22 on the active surface of chip 2 serves as a critical wiring layer. One end connects to the substrate 1 to obtain signals and power, while the other end penetrates vertically through chip 2 via the first conductive structure 21, constructing a straight upward path of "substrate-signal transmission layer-TSV-antenna," eliminating lateral signal routing within the substrate 1 and chip 2. This achieves ultra-short-distance, low-loss signal transmission from the source to the antenna, minimizing impedance mismatch and energy attenuation in the path. Simultaneously, the clear hierarchy and vertical interconnection greatly enhance wiring freedom and integration density, resulting in a more compact and reliable structure for the entire RF front-end while achieving excellent electrical performance.

[0047] It is understandable that the signal transmission layer 22 has multiple connection points, such as pads, and the connection point with the first connection part 13 is different from the connection point with the first conductive structure 21.

[0048] Optionally, the first conductive structure 21 includes a first conductive portion 211 and a second conductive portion 212. The first conductive portion 211 is located within the first via 20, and the second conductive portion 212 is located on the back side of the chip 2. The first conductive portion 211 is electrically connected between the signal transmission layer 22 and the second conductive portion 212. The first conductive structure 21 includes the first conductive portion 211 within the first via 20 and the second conductive portion 212 on the back side of the chip 2. The first conductive portion 211 ensures reliable contact with the signal transmission layer 22, while the second conductive portion 212 on the back side serves as a metal pad for interconnection with the antenna module 3. This improves process flexibility and electrical performance. The two parts can be processed using materials and processes best suited to their positions, which reduces the difficulty of TSV filling and forms a flat, low-loss interconnect interface on the back side of the chip 2, thereby optimizing impedance matching, reducing signal reflection and loss during vertical transmission to the antenna, and enhancing the overall reliability of the system.

[0049] Optionally, a third connecting part 15 is further provided between the second conductive part 212 and the antenna module 3. The third connecting part 15 connects the side of the second conductive part 212 away from the substrate 1 and the side of the antenna module 3 facing the substrate 1. The third connecting part 15 can be a solder ball.

[0050] In some optional embodiments, the antenna packaging structure further includes a packaging layer 4, which covers both the chip 2 and the antenna module 3, and also covers a portion of the first surface 11. The packaging layer 4 covers and encapsulates the chip 2 and the antenna module 3, forming a complete protective shell, which improves the mechanical strength, reliability, and environmental durability of the structure. The packaging layer 4 effectively prevents external factors such as physical damage, moisture, and dust from corroding the internal precision circuitry. Simultaneously, as a uniform dielectric environment, it helps stabilize the radiation performance of the antenna module 3, prevents parameter drift due to changes in air gaps, and provides a buffer against thermal and mechanical stress for the core components, thereby ensuring the long-term operational stability of the entire antenna packaging structure in complex application scenarios.

[0051] Optionally, the encapsulation layer 4 may be made of molding compound. The molding compound is poured into a mold and cured by heat, completely encapsulating irregularly shaped structures such as the chip 2 and antenna module 3 in one step, forming a dense insulating protective layer. This effectively prevents moisture, dust, and corrosion, and significantly improves mechanical strength to resist external stress. Simultaneously, its material properties are easily controlled, helping to maintain the stability of antenna radiation performance, thus contributing to high protection and excellent high-frequency electrical performance.

[0052] In some optional embodiments, the encapsulation layer 4 includes a first encapsulation layer 41 and a second encapsulation layer 42, with the second encapsulation layer 42 located on the side of the first encapsulation layer 41 facing away from the substrate 1; wherein at least a portion of the first encapsulation layer 41 is located on the side of the chip 2 facing away from the substrate 1, and at least a portion of the second encapsulation layer 42 is located on the side of the antenna module 3 facing away from the substrate 1. Optionally, the second encapsulation layer 42 covers the side surface of the antenna module 3 and the side surface of the antenna module 3 facing away from the substrate 1.

[0053] The first encapsulation layer 41 and the second encapsulation layer 42 can be fabricated in stages. First, the first encapsulation layer 41 is fabricated to encapsulate the chip 2. After the antenna module 3 is fabricated, the second encapsulation layer 42 is then fabricated. The first encapsulation layer 41 fills the space around and above the chip 2, forming a basic covering and stress buffer. The second encapsulation layer 42 completely covers the sidewalls and top of the antenna module 3 to provide protection. Both the first encapsulation layer 41 and the second encapsulation layer 42 can be made of encapsulating adhesive.

[0054] Optionally, the first encapsulation layer 41 also has a first opening 410 to expose the side surface of the first conductive structure 21 facing away from the substrate 1. The antenna module 3 is electrically connected to the first conductive structure 21 via the first opening 410. The first opening 410 on the first encapsulation layer 41, exposing the end contact surface of the first conductive structure 21, facilitates precise and reliable vertical interconnection between the antenna module 3 and the chip 2. The first opening 410 removes insulating materials such as encapsulation material at the interconnection interface, ensuring a low-resistance, highly consistent direct metal connection between the first conductive structure 21 and the antenna module 3, reducing signal transmission loss and interface reflection. Simultaneously, this opening provides clear alignment marks for the subsequent installation of the antenna module 3, improving the accuracy and yield of the encapsulation process, thereby ensuring the electrical integrity of the high-frequency signal path in the complex three-dimensional stacked structure.

[0055] In some optional embodiments, a first gap 51 is provided between the chip 2 and the substrate 1, and a first filler 53 is provided within the first gap 51; and / or, a second gap 52 is provided between the antenna module 3 and the chip 2, and a second filler 54 is provided within the second gap 52. The filler can effectively disperse and absorb the stress caused by the difference in the coefficients of thermal expansion of different materials, preventing the connection point from cracking or the chip 2 from being damaged due to stress concentration during temperature changes; at the same time, it can also remove air from the gap, enhance the stability of mechanical support, and prevent moisture or contaminants from accumulating in the gap, further improving the reliability of the package and enhancing the long-term operational reliability of the entire three-dimensional stacked structure in harsh environments.

[0056] Reference Figure 2 In some optional embodiments, the substrate 1 includes a carrier plate 101, a first wiring layer 102, a second wiring layer 103, and an interconnect structure 104. The first wiring layer 102 and the second wiring layer 103 are disposed opposite to each other on both sides of the carrier plate 101 in the thickness direction. The interconnect structure 104 passes through the carrier plate 101 and connects the first wiring layer 102 and the second wiring layer 103. The first connecting portion 13 is connected to the surface of the first wiring layer 102 opposite to the second wiring layer 103.

[0057] Optionally, the carrier plate 101 is a glass carrier plate 101. The interconnect structure 104 may include a seed layer and an interconnect layer, with the seed layer disposed between the interconnect layer and the carrier plate 101. Before fabricating the interconnect layer, a seed layer is deposited on the carrier plate 101 to provide conductivity, thereby improving the adhesion of the interconnect layer. Exemplarily, the seed layer may be prepared by sputtering, vapor deposition, or electroless plating, and the interconnect layer may be prepared by physical deposition (PVD) or electroplating.

[0058] The first wiring layer 102, the second wiring layer 103, and the interconnect structure 104 together form the redistribution layer (RDL). The redistribution layer is a core technology in wafer-level packaging, playing the role of XY plane electrical extension and interconnection. The RDL rearranges the original chip 2 line contact positions (I / O pads) through wafer-level metal wiring process and bump process, placing them in new, more spacious areas and forming a planar array arrangement.

[0059] In these embodiments, high-density system-level integration and efficient signal transmission are achieved by constructing a composite substrate 1 structure including a carrier board 101, double-sided wiring layers, and vertical interconnects. The first / second wiring layers 103 form a fine circuit network on the upper and lower surfaces of the substrate 1, respectively connecting the chip 2 and the external system; the interconnect structure 104 penetrating the carrier board 101 establishes a vertical path between the two. This provides a stable power supply and low-frequency signal channel for the chip 2, and by optimizing wiring resources, the RF signal path is made independent and shortened to its shortest length, effectively reducing transmission loss and crosstalk. Simultaneously, it gives the overall structure stronger circuit scalability and layout flexibility, supporting the high-performance, miniaturized integration requirements of complex RF front-ends.

[0060] Optionally, the second surface 12 is provided with a second connection portion 14, which is electrically connected to the second wiring layer 103. The second connection portion 14 serves as an external interface, enabling efficient input / output of RF signals, control signals, and power from the bottom of the package. This fully utilizes the vertical wiring resources of the substrate 1 to improve integration density, while simultaneously achieving path separation between high-frequency antenna signals and low-frequency system signals, effectively reducing crosstalk between signals. The second connection portion 14 can be a solder ball.

[0061] In some alternative embodiments, the substrate 1 further includes a first dielectric layer 105, with at least a portion of the first wiring layer 102 located within the first dielectric layer 105; and / or, the substrate 1 further includes a second dielectric layer 106, with at least a portion of the second wiring layer 103 located within the second dielectric layer 106.

[0062] The dielectric layer is an insulating material used to separate different conductive lines. It also serves as a support and protection layer. The dielectric layer provides solid mechanical support and reliable electrical insulation for delicate metal wiring, effectively preventing short circuits. While achieving high-density interconnection, it ensures the integrity and stability of signal transmission and improves the overall system performance.

[0063] Optionally, the first wiring layer 102 includes at least two sub-wiring layers. It is understood that the first wiring layer 102 and the second wiring layer 103 are not limited to a single-layer metal trace structure, but can also be a structure formed by combining multiple layers of metal traces. Specifically, when forming the first wiring layer 102 or the second wiring layer 103, after removing unnecessary portions of the first dielectric layer 105, a conductive layer is formed by methods such as copper plating. Unnecessary portions of the conductive layer are selectively removed, and then an insulating material is placed on the conductive layer again. Unnecessary portions are removed again, and then the next conductive layer is formed by methods such as plating. Simultaneously, when preparing different conductive layers, different conductive layers that need to be electrically connected can be electrically connected through vias. By repeating the above process, the desired first wiring layer 102 or second wiring layer 103 can be formed.

[0064] Reference Figure 3 and in conjunction with reference Figures 4 to 9 The second aspect of this application provides a method for fabricating an antenna packaging structure, comprising: S10, fabricate substrate 1, substrate 1 includes a first surface 11 and a second surface 12 that are opposite to each other along the thickness direction. For example... Figure 4 and Figure 5 As shown.

[0065] S20, a chip 2 is disposed on the first surface 11. The chip 2 is electrically connected to the substrate 1 through the first connecting part 13. The chip 2 has a first through hole 20.

[0066] The first through hole 20 of the chip 2 can be set before it is mounted on the first surface 11, or it can be formed after the chip 2 is mounted on the first surface 11.

[0067] S30, a first conductive structure 21 is fabricated, making the first conductive structure 21 electrically connected to the chip 2 and extending through the first through-hole 20 to the side of the chip 2 opposite to the substrate 1. Figure 6 and Figure 7 As shown.

[0068] Optionally, the material of the first conductive structure 21 can be copper, silver, tin, etc. A first through hole 20 is opened on the chip 2 and filled with metal, thereby leading the signal of the chip 2 from the active side to the back side of the chip 2, and a metal pad is made on the back side of the chip 2 to form the first conductive structure 21.

[0069] S40, an antenna module 3 is disposed on the side of the chip 2 away from the substrate 1, and the antenna module 3 is electrically connected to the first conductive structure 21. For example... Figure 9 As shown.

[0070] The antenna package structure fabricated according to this method includes a substrate 1, a chip 2, a first conductive structure 21, and an antenna module 3. After the signal is generated or processed in the circuitry inside the chip 2, it no longer needs to travel through the traditional long path of "chip-substrate-transmission line-antenna." Instead, it can be directly transmitted from the thickness direction of the chip 2 to the other side through the first conductive structure 21, interacting with the adjacent antenna module 3. The signal transmission path between the antenna module 3 and the chip 2 is greatly shortened and optimized, reducing signal loss and improving the performance of the antenna package structure.

[0071] In some alternative embodiments, refer to Figure 8 After step S30 and before step S40, the preparation method further includes: preparing a first encapsulation layer 41 to encapsulate the chip 2, at least a portion of the first encapsulation layer 41 being located on the side of the chip 2 away from the substrate 1, and the first encapsulation layer 41 having a first opening 410 to expose the surface of the first conductive structure 21 away from the substrate 1.

[0072] The first encapsulation layer 41 and the second encapsulation layer 42 can be fabricated in stages. The first encapsulation layer 41 is fabricated first to encapsulate the chip 2. After the antenna module 3 is fabricated, the second encapsulation layer 42 is then fabricated. The first encapsulation layer 41 first fills the space around and above the chip 2, forming a basic covering and stress buffer. The first opening 410 removes insulating materials such as encapsulation material at the interconnect interface, ensuring a low-resistance, highly consistent direct metal connection between the first conductive structure 21 and the antenna module 3, reducing signal transmission loss and interface reflection. Simultaneously, this opening provides clear alignment marks for the subsequent installation of the antenna module 3, improving the accuracy and yield of the encapsulation process, thereby ensuring the electrical integrity of the high-frequency signal path in the complex three-dimensional stacked structure.

[0073] In some optional embodiments, after step S40, the preparation method further includes: A second filler adhesive 54 is prepared to fill the second gap 52 between the antenna module 3 and the chip 2.

[0074] A second encapsulation layer 42 is prepared to encapsulate the antenna module 3. The second encapsulation layer 42 covers the side surface of the antenna module 3 and the side surface of the antenna module 3 that is away from the substrate 1.

[0075] In these embodiments, a second filler 54 is first prepared, and then a second encapsulation layer 42 is prepared to encapsulate the antenna module 3. The second filler 54 fills the gap between the chip 2 and the antenna module 3, eliminates air in the gap, enhances the mechanical support stability, and thus improves the reliability of the second encapsulation layer 42.

[0076] Optionally, after step S20, the preparation method further includes: preparing a first filler 53 to fill the first gap 51 between the chip 2 and the substrate 1.

[0077] Similarly, a gap may also be formed between the chip 2 and the substrate 1. By preparing the first filler adhesive 53 to fill the gap between the chip 2 and the substrate 1, the air in the gap is eliminated, the mechanical support stability is enhanced, and thus the reliability of the first encapsulation layer 41 can be improved.

[0078] Reference Figure 4 and Figure 5 In some optional embodiments, the step of preparing substrate 1 in S10 includes: Through holes are prepared on the carrier plate 101.

[0079] Interconnect structure 104 is fabricated within the via.

[0080] Wiring layers and dielectric layers are fabricated on both sides of the carrier board 101, respectively.

[0081] In these embodiments, the vias are filled with metal to form a vertical interconnect structure 104. The metal can be copper (Cu), or silver, tin, or a combination thereof. Various feasible fabrication processes can be used to form the metal interconnect structure 104 within the vias, including but not limited to: The first option is to use physical vapor deposition (PVD) to form a seed layer on the inner wall of the through-hole and the glass surface, followed by electroplating to fill the layer, and finally removing excess metal from the surface by grinding.

[0082] The second option is to first fill the holes with metal using PVD and electroplating processes, then use resin to plug the holes, and finally grind the surface to achieve planarization.

[0083] The third option involves plugging the holes with a metal slurry, then heating and curing the slurry to form a solid shape, and finally grinding it for surface treatment.

[0084] Optionally, after completing the metallization of the glass vias, dielectric layers and metal wiring are fabricated on the front and back sides of the glass substrate 101, respectively. Finally, solder balls are fabricated on the back side of the glass substrate 1 to provide an external electrical connection interface.

[0085] By first machining through-holes and forming vertical interconnects on the carrier board 101, and then simultaneously constructing wiring layers and dielectric layers on both sides, a highly efficient and precise three-dimensional interconnect structure 104 was manufactured. This process sequence ensures the alignment accuracy and electrical connection reliability of the vertical interconnects and the wiring layers on both sides, forming a stable signal and power transmission path. At the same time, the layered wiring layers, supported by the dielectric layer, achieve high-density wiring, effectively shortening the signal transmission distance, reducing high-frequency signal loss and crosstalk, and providing a high-performance, high-reliability interconnect platform for the integrated chip 2 and antenna module 3.

[0086] Optionally, the steps for fabricating vias include: fabricating vias using laser-induced processes or wet etching processes. Laser-induced processes utilize a high-energy laser beam for selective ablation, enabling high-precision and high-efficiency drilling, particularly suitable for hard and brittle glass materials, with precise control over via location and morphology. Wet etching processes, on the other hand, use chemical solutions for isotropic or anisotropic etching, suitable for batch parallel processing, and at a lower cost. Both processes provide flexible and reliable technical pathways for fabricating glass vias, capable of forming vias with good wall quality and suitable aspect ratios. This lays a crucial structural foundation for subsequent high-quality metal filling and stable vertical electrical interconnects, thereby ensuring the high performance and high reliability of the overall packaging structure.

[0087] A third aspect of this application provides an electronic device that includes an antenna packaging structure provided in any of the embodiments of the first aspect, or an antenna packaging structure formed in any of the embodiments of the second aspect. This electronic device may be a mobile phone, tablet computer, laptop computer, drone, augmented reality / virtual reality device, millimeter-wave radar module, satellite communication terminal, or Internet of Things module, etc.

[0088] Since the electronic device provided in the third aspect of this application includes the antenna packaging structure provided in any of the first aspects above, or is prepared by the preparation method of the antenna packaging structure in any of the second aspects above, the electronic device provided in the third aspect of this application has the beneficial effects of the antenna packaging structure in any of the first aspects above or the preparation method of the antenna packaging structure in any of the second aspects above, which will not be repeated here.

[0089] The embodiments described above are not exhaustive, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. An antenna packaging structure, characterized in that, include: The substrate includes a first surface and a second surface that are opposite to each other along the thickness direction, and the first surface is provided with a first connecting portion; A chip is disposed on the first surface and electrically connected to the first connection portion, and the chip has a first through hole; A first conductive structure is electrically connected to the chip and extends through the first through-hole to the side of the chip opposite to the substrate; An antenna module is disposed on the side of the chip away from the substrate, and the antenna module is electrically connected to the first conductive structure.

2. The antenna packaging structure according to claim 1, characterized in that, The active surface of the chip faces the substrate, and the back surface of the chip faces the antenna module. Preferably, the active surface of the chip has a signal transmission layer, the signal transmission layer is electrically connected to the first connection portion, the first conductive structure is electrically connected to the signal transmission layer via the first via, and at least a portion of the first conductive structure is located on the back side of the chip. Preferably, the first conductive structure includes a first conductive portion and a second conductive portion, the first conductive portion being located inside the first through hole, the second conductive portion being located on the back side of the chip, and the first conductive portion being electrically connected between the signal transmission layer and the second conductive portion; Preferably, a third connecting part is further provided between the second conductive part and the antenna module, the third connecting part connecting the side of the second conductive part away from the substrate and the side of the antenna module facing the substrate.

3. The antenna packaging structure according to claim 1, characterized in that, The antenna packaging structure further includes a packaging layer that covers the chip and the antenna module, and the packaging layer covers a portion of the first surface; Preferably, the material of the encapsulation layer includes a molding compound.

4. The antenna packaging structure according to claim 3, characterized in that, The encapsulation layer includes a first encapsulation layer and a second encapsulation layer, wherein the second encapsulation layer is located on the side of the first encapsulation layer that is away from the substrate; Wherein, at least a portion of the first encapsulation layer is located on the side of the chip away from the substrate, and at least a portion of the second encapsulation layer is located on the side of the antenna module away from the substrate; Preferably, the first encapsulation layer further has a first opening to expose the side surface of the first conductive structure facing away from the substrate, and the antenna module is electrically connected to the first conductive structure via the first opening.

5. The antenna packaging structure according to claim 1, characterized in that, The chip and the substrate have a first gap, and a first filler adhesive is provided in the first gap; and / or, the antenna module and the chip have a second gap, and a second filler adhesive is provided in the second gap.

6. The antenna packaging structure according to claim 1, characterized in that, The substrate includes a carrier plate, a first wiring layer, a second wiring layer, and an interconnect structure. The first wiring layer and the second wiring layer are disposed opposite to each other on both sides of the carrier plate in the thickness direction. The interconnect structure passes through the carrier plate and connects the first wiring layer and the second wiring layer. The first connection portion is connected to the surface of the first wiring layer opposite to the second wiring layer. Preferably, the second surface is provided with a second connecting portion, and the second connecting portion is electrically connected to the second wiring layer; Preferably, the substrate further includes a first dielectric layer, with at least a portion of the first wiring layer located within the first dielectric layer; and / or, the substrate further includes a second dielectric layer, with at least a portion of the second wiring layer located within the second dielectric layer; Preferably, the first wiring layer includes at least two sub-wiring layers.

7. A method for fabricating an antenna packaging structure, characterized in that, include: A substrate is prepared, the substrate comprising a first surface and a second surface that are opposite to each other along the thickness direction; A chip is disposed on the first surface, the chip is electrically connected to the substrate through a first connecting portion, and the chip has a first through hole; A first conductive structure is fabricated, which is electrically connected to the chip and extends through the first via to the side of the chip opposite to the substrate. An antenna module is disposed on the side of the chip away from the substrate, and the antenna module is electrically connected to the first conductive structure.

8. The method for fabricating the antenna packaging structure according to claim 7, characterized in that, After the step of preparing the first conductive structure, the preparation method further includes: A first encapsulation layer is prepared to encapsulate the chip, at least a portion of the first encapsulation layer is located on the side of the chip away from the substrate, and the first encapsulation layer has a first opening to expose the surface of the first conductive structure away from the substrate. Preferably, after the step of fabricating the antenna module, the fabrication method further includes: A second filler adhesive is prepared to fill the second gap between the antenna module and the chip; A second encapsulation layer is prepared to encapsulate the antenna module, the second encapsulation layer covering the side surface of the antenna module and the side surface of the antenna module facing away from the substrate; Preferably, after the step of setting the chip, the fabrication method further includes: A first filler adhesive is prepared to fill the first gap between the chip and the substrate.

9. The method for fabricating the antenna packaging structure according to claim 7, characterized in that, The steps for preparing the substrate include: Through-holes are fabricated on a carrier plate; An interconnect structure is fabricated within the through-hole; Wiring layers and dielectric layers are respectively fabricated on both sides of the carrier plate; Preferably, the step of preparing the through hole includes: Through-holes are fabricated using laser-induced processes or wet etching processes.

10. An electronic device, characterized in that, The antenna packaging structure includes any one of claims 1 to 6, or includes an antenna packaging structure prepared according to any one of claims 7 to 9.

Images