Sampling and holding circuit with low droop rate for battery power supply system

Abstract

The invention relates to a sample and hold circuit with low droop rate for a battery power supply system. The sample and hold circuit may include an operational amplifier including a first operational amplifier input, a second operational amplifier input, and an operational amplifier output. The sample and hold circuit may also include a first switch connected between the first operational amplifier input and a power supply node, a second switch connected between the second operational amplifier input and the power supply node, a first capacitor connected between the first operational amplifier input and a ground node, and a second capacitor connected between the second operational amplifier input and the ground node. A second capacitor connected to the second operational amplifier input, a third switch connected between the second capacitor and the sample input, and a fourth switch connected between the second capacitor and the operational amplifier output.

Description

Technical Field

[0001] This disclosure relates to sample-and-hold circuitry in a battery operating system, where minimizing power consumption is desired. Background Technology

[0002] Minimizing power consumption in efficient or battery-operated systems, such as vehicle systems when the vehicle is off, is desirable. In such systems, there are several circuit elements or modules, such as a reference voltage generator, which may remain active and consume significant power to produce a constant or stable voltage, for example, even when the system is off. Summary of the Invention

[0003] This disclosure describes several examples of sample-and-hold circuits. The described sample-and-hold circuits can be used in battery operating systems, such as vehicle systems. In such systems, it may be desirable to maintain a constant or stable voltage, for example, even when the system is off.

[0004] In some examples, this disclosure describes a circuit including: an operational amplifier including a first operational amplifier input, a second operational amplifier input, and an operational amplifier output; a first switch connected between the first operational amplifier input and a power supply node; a second switch connected between the second operational amplifier input and the power supply node; a first capacitor connected between the first operational amplifier input and a ground node; a second capacitor connected to the second operational amplifier input; a third switch connected between the second capacitor and a sample input; and a fourth switch connected between the second capacitor and the operational amplifier output. This circuit can be configured to perform a sample and hold operation on the sample input.

[0005] In some examples, this disclosure describes a method for operating circuitry to perform a sample and hold operation on a sample input, wherein the circuitry includes: an operational amplifier including a first operational amplifier input, a second operational amplifier input, and an operational amplifier output; a first switch connected to the first operational amplifier input and a power supply node; a second switch connected to the second operational amplifier input and a power supply node; a first capacitor connected between the first operational amplifier input and a ground node; a second capacitor connected to the second operational amplifier input; a third switch connected between the second capacitor and the sample input; and a fourth switch connected between the second capacitor and the operational amplifier output. The method may include: performing a sampling phase; and performing a hold phase. In some examples, the sampling phase includes: controlling the first switch to close, controlling the second switch to close, controlling the third switch to close, and controlling the fourth switch to open; and in some examples, the hold phase includes: controlling the first switch to open, controlling the second switch to open, controlling the third switch to open, and controlling the fourth switch to close.

[0006] Details of one or more examples of this disclosure are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of this disclosure will become apparent from the description, the drawings, and the claims. Attached Figure Description

[0007] Figure 1 This is an example circuit diagram of a sample and hold circuit according to this disclosure.

[0008] Figure 2 The illustration shows a clock signal that can define the sampling phase and the holding phase according to this disclosure.

[0009] Figure 3 This is another example circuit diagram of a sample and hold circuit according to this disclosure.

[0010] Figure 4 It is a block diagram based on an example of this disclosure.

[0011] Figure 5 This is another block diagram based on an example of this disclosure.

[0012] Figure 6 A more detailed block diagram based on the examples in this disclosure.

[0013] Figure 7 This is a circuit diagram showing a multiplier circuit that can be combined with a sample-and-hold circuit.

[0014] Figure 8 It shows that it can be used with Figure 7 The circuit diagram shown is a portion of the sample-and-hold circuit of the multiplier circuit combination shown.

[0015] Figure 9 This is a circuit diagram showing a combined multiplier circuit with a sample-and-hold circuit, both using the same operational amplifier at different stages.

[0016] Figure 10 - Figure 12 It is based on the example flowchart of this disclosure. Detailed Implementation

[0017] This disclosure describes examples of sampling and holding circuits that can help reduce power consumption in battery operating systems. Power consumption is a desired parameter for improvements in efficient or battery operating systems, such as vehicle systems (e.g., vehicle shutdown). In these cases, there are several modules, such as a reference voltage generator, that may remain active and consume significant power to generate a DC voltage. The amount of power used by the voltage generator to sustain it can be substantial, and in some cases, the circuit may be designed under other constraints, such as small area or other factors that can reduce the power efficiency of the circuit. Solutions to reduce this power consumption are desired, such as voltage generators or other circuits used in vehicle systems.

[0018] One solution for reducing the power consumption of a voltage reference generator is to sample the reference voltage and hold it using a long sample-and-hold circuit, for example, controlled by a very long clock signal, and then turn off the reference voltage generator. Figure 1 This is an example of a circuit 100 configured to perform sample-and-hold operations according to the present disclosure. Circuit 100 includes an operational amplifier 102, which includes a first operational amplifier input (e.g., + input), a second operational amplifier input (e.g., - input), and an operational amplifier output (e.g., corresponding to Vout). A first switch (S1) 112 is connected between the first operational amplifier input and a power supply node, and a second switch (S2) 114 is connected between the second operational amplifier input and a power supply node. A first capacitor (C1) 122 is connected between the first operational amplifier input and a ground node, and a second capacitor (C2) 124 is connected to the second operational amplifier input. A third switch (S3) 116 is connected between the second capacitor 124 and a sample input (e.g., corresponding to Vin), and a fourth switch (S4) 118 is connected between the second capacitor 124 and the operational amplifier output (e.g., corresponding to Vout).

[0019] According to some examples of this disclosure, circuit 100 can be configured to perform a sample-and-hold operation on a sample input, and for example, the sample-and-hold operation can hold the sample input voltage on the operational amplifier output for more than 100 milliseconds. The sample-and-hold operation includes a sampling phase and a holding phase, wherein in some examples, the length of the holding phase is greater than 500 times the length of the sampling phase. Figure 1 Consistently, in some examples, during the sampling phase, the first switch 112 is closed, the second switch 114 is closed, the third switch 116 is closed, and the fourth switch 118 is open. Then, during the holding phase, the first switch 112 is open, the second switch 114 is open, the third switch 116 is open, and the fourth switch 118 is closed.

[0020] In some examples, the sampling and holding phases are defined by a clock signal, and the first switch 112, the second switch 114, the third switch 116, and the fourth switch 118 are configured to receive a gate control signal defined by the clock signal. Figure 2 An example of clock signal 205 is shown. S It can refer to the sampling phase, and T H This can refer to the hold phase, and the edge of the CkS signal can be used to define the timing of the gate control signals used to control switches 112, 114, 116, and 118 as described above. In some examples, T H It can be greater than 100 milliseconds. In some examples, T H The length can be greater than T S It is 500 times longer than that.

[0021] Clock signal 205 can be generated in any of a variety of ways, such as by using a digital divider (e.g., a cascaded D flip-flop). In some cases, instead of relying solely on a digital divider (e.g., a cascaded D flip-flop), the technique used to generate clock signal 205 may use an analog divider, or possibly a combination of analog and digital dividers. In any case, clock signal 205 with a short sampling period and a long hold period can be effectively used to define the timing for the gates of control switches 112, 114, 116, and 118.

[0022] With the voltage reference generator always on (ON) (and without sample-and-hold operation), the average power consumption is P. VRG In the sampling and holding scheme and Figure 2 Under the condition of consistent timing, and with the sample-and-hold circuit always on while the reference generator is only on during the sampling phase, the average power consumption will be:

[0023] P S&H =((P) VRG +P S&H )·T S +P S&H ·T H ) / (T S +T H )

[0024] This allows for significant power savings, especially if the duty cycle (i.e., the ratio between the time the voltage reference generator is on and the entire cycle including on and off times, DC = T) is applied. S / (T S +T H The power consumption is relatively low. This is because the power consumption of the sample-and-hold circuit is expected to be lower than that of the reference voltage generator.

[0025] As an example, suppose P VRG =1uW,P S&H =200nW, T S =5usec,T H =100msec, the average power without sampling and holding will be

[0026] P noS&H =P VRG =1uW

[0027] The solution with sampling and holding will consume the average power given below:

[0028] P S&H =((P) VRG +P S&H )·T S +P S&H ·T H ) / (T S +T H ) = 200nW

[0029] Therefore, using this example, the sample-and-hold circuit can produce an 80% power saving, which can be achieved by utilizing a sample-and-hold circuit that consumes significantly less power than a voltage generator, while also guaranteeing a long hold time (T). H (low sag rate)

[0030] One desirable aspect of the circuit described herein is the ability to achieve a low droop rate and a long hold time. Conventional circuits for sampling and holding voltages may have the problem of leakage current causing voltage droop across the output capacitor. In some examples, the circuits and techniques of this disclosure can have reduced droop compared to conventional sample-and-hold circuits and can have very small (or acceptable) droop in the amount of time associated with the hold phase.

[0031] Figure 3This is another example of a circuit (i.e., circuit 300) that can be configured to perform sample-and-hold operations consistent with this disclosure. Circuit 300 includes an operational amplifier 302, which includes a first operational amplifier input (e.g., + input), a second operational amplifier input (e.g., - input), and an operational amplifier output (e.g., corresponding to Vout). A first switch (S1) 312 is connected between the first operational amplifier input and a power supply node, and a second switch (S2) 314 is connected between the second operational amplifier input and a power supply node. A first capacitor (C1) 322 is connected between the first operational amplifier input and a ground node, and a second capacitor (C2) 324 is connected to the second operational amplifier input. A third switch (S3) 316 is connected between the second capacitor 324 and a sample input (e.g., corresponding to Vin), and a fourth switch (S4) 118 is connected between the second capacitor 324 and the operational amplifier output (e.g., corresponding to Vout). The first capacitor 322 and the second capacitor 324 may be matched with approximately the same capacitance. In some examples, the capacitance ratings and structures of the first capacitor 322 and the second capacitor 324 may be similar or identical.

[0032] According to some examples of this disclosure, circuit 300 can be configured to perform a sample-and-hold operation on a sample input, and for example, the sample-and-hold operation can hold the sample input voltage on the operational amplifier output for more than 100 milliseconds. In some examples, the sample-and-hold operation includes a sampling phase and a holding phase, wherein the length of the holding phase is greater than 500 times the length of the sampling phase. Figure 3 Consistently, in some examples, during the sampling phase, the first switch 312 is closed, the second switch 314 is closed, the third switch 316 is closed, and the fourth switch 318 is open. Then, during the holding phase, the first switch 312 is open, the second switch 314 is open, the third switch 316 is open, and the fourth switch 318 is closed.

[0033] In some examples, the sampling phase and the holding phase are composed of similar... Figure 2 The clock signal defined by signal 205, and the first switch 312, the second switch 314, the third switch 316 and the fourth switch 318 can be configured to receive a gate control signal defined by the clock signal.

[0034] exist Figure 3 In the example shown, both the first switch 312 and the second switch 314 are PMOS transistors. Each PMOS transistor includes a source connection to a power node and a body connection to a power node (as shown in the circuit structure, where the body is connected to the power supply V). DD(at the source). This is desirable for limiting leakage current and avoiding drooping during the hold phase. Capacitor 324 is charged to V during the sampling phase. DD Subsequently, if the body of the second switch 314 is connected to the V DD (i.e., the power supply), then during the holding phase, little or no leakage current flows; for example, it flows through the body diode of the second power switch 314 because the power supply V connected to the body of the second switch 314... DD Similar to the charge placed on the second capacitor 324 during the sampling phase.

[0035] In some examples, Figure 3 The circuit 300 shown can be operated as follows:

[0036] During the sampling phase (e.g.) Figure 2 During the phase CkS shown, the input signal is at the reference V DD The sample is taken from C2, while C1 is precharged to V. DD .

[0037] During the maintenance phase (e.g.) Figure 2 During the phase CkH shown, sampling capacitor C2 is connected in the feedback, while capacitor C1 is connected to the positive input node of the operational amplifier, forcing that node to be at V. DD .

[0038] There is no leakage current because the positive node of the operational amplifier input is at V. DD When capacitor C2 is connected in the feedback, it forces

[0039] V out =V in

[0040] In the presence of leakage current, at least two characteristics or design factors can help avoid drooping in the sampling and holding circuits. When the operational amplifier input node is biased at V... DD At that time, the n-doped host was also attached to V. DD Therefore, this results in VBS = 0, and thus no mains leakage current flows. Regarding the channel current, since the MOS switch can be connected at the operational amplifier input node (at V... DD ) and V DD Between, therefore V exists DS =0, and then no channel current will flow. However, if the operational amplifier input node is moved (e.g., due to offset, finite gain, or other reasons), then this will cause V to... DS ≠0, and then the channel current will flow in both S1 and S2. In this case, I S1This can be collected in capacitor C1, and this can force the positive input node of the operational amplifier to shift as follows:

[0041] V P =V Po +t*I S1 / C1

[0042] Where V Po =V DD Note I S1 Depends on V DS1 .

[0043] In a similar manner, any leakage current from switch S2 can be collected on the armature of C2, thereby generating a voltage change on C2 as follows:

[0044] V C2 =V C2o +t*I S2 / C2

[0045] If S1 = S2 and the operational amplifier input node V p =V m (even if they are with V) DD If the leakage current I is different, then we can assume that the leakage current is different. S1 and I S2 With V DS1 =V DS2 Same (or very similar). Furthermore, if C2 is designed to be equal to C1, then V p The movement (due to I) S1 Load C1) is V m The movement on (due to I) S2 Load C2) compensation, therefore V out No change (but V) p and V m move).

[0046] Figure 4This is a basic block diagram according to an example of the present disclosure. As shown, circuit 400 may include voltage generator circuit 402 and sample-and-hold circuit 404. Voltage generator circuit 402 can be disabled after generating a voltage, and sample-and-hold circuit 404 can sample the voltage and hold it stable when voltage generator circuit 402 is disabled, which can save power in vehicle systems or other battery operating systems. In some cases, voltage generator circuit 402 is configured to generate a voltage during a sampling phase and is disabled during a holding phase. Sample-and-hold circuit 404 samples the voltage from voltage generator circuit 402 during the sampling phase and holds the voltage during the holding phase. In some examples, voltage generator circuit 402 is configured to generate a temperature-dependent voltage reference, which may be necessary in vehicle systems or other systems where the temperature associated with circuit operation can change.

[0047] Figure 5 This is another block diagram according to an example of the present disclosure. AC circuit 500 may include bandgap generator circuit 502, which is essentially two different voltage generator circuits configured to generate a first voltage and a second voltage. Therefore, circuit 500 includes two different sample-and-hold circuits 504, 506. Bandgap generator circuit 502 can be disabled after generating the bandgap voltage, and sample-and-hold circuits 504, 506 can sample the voltage and hold it stable while bandgap generator circuit 502 is disabled, which can save power in vehicle systems or other battery operating systems. In some cases, bandgap generator circuit 502 is configured to generate the bandgap voltage during the sampling phase, and bandgap generator circuit 502 is disabled during the hold phase. Sample-and-hold circuits 504, 506 can be configured to sample the corresponding bandgap voltage from bandgap generator 502 during the sampling phase, and sample-and-hold circuits 504, 506 can be configured to hold the bandgap voltage during the hold phase. In some examples, the bandgap generator circuit 502 is configured to generate a temperature-dependent bandgap voltage reference, which may be necessary in vehicle systems or other systems where the temperature associated with circuit operation can vary. Figure 5 Consistently, in some examples, circuit 500 may include a first sample and hold circuit 504 for a first reference voltage of the bandgap, and circuit 500 may include a sample and hold circuit 506 for a second reference voltage of the bandgap, wherein the second sample and hold circuit 506 is the same as or similar to the first sample and hold circuit 504, and in some cases, the second sample and hold circuit 506 is the same as the first sample and hold circuit 504.

[0048] Figure 6This is a more detailed block diagram based on an example of the present disclosure. Circuit 600 may include a low-power current generator 602 and a finite-current oscillator 604 that provides a clock signal (Clk). A switched-capacitor CTAT reference generator circuit 606 is configured to generate a CTAT current (i.e., a current "complementary to absolute temperature"). Furthermore, a PTAT reference generator circuit 608 is configured to generate a PTAT current (i.e., a current "proportional to absolute temperature"). CTAT reference generator circuit 606 and PTAT reference generator circuit 608 can be considered as an example of a bandgap generator circuit 502.

[0049] The current-to-analog converter (IDAC) 610 can be configured to output a current based on the summation 616 of the PTAT and CTAT currents. Furthermore, the CTAT and PTAT currents can be combined using a summation 612 and a voltage drop resistor 614. This definition can be used by multiplier circuits 622, 624 and is sampled and held by sample-and-hold circuitry. In the illustrated example, the input to multiplier circuits 622, 624 can be approximately 0.125 volts, and after multiplication, the output of amplifier circuit 622 can be 0.5 volts, and the output of amplifier circuit 624 can be 1.0 volt. Any other voltage or scaling can be used to define other voltage levels consistent with this disclosure, and the example values ​​of 0.125 volts and 0.5 volts are merely examples.

[0050] The sample and hold circuits 626 and 628 can each correspond to Figure 1 Circuit 100 or Figure 3 Circuit 300. During the sampling operation, Figure 6 All the cells shown can be active. During hold-up operation, cells 614, 608, 606, 622, and 624 can all be disabled to save power. Figure 1 Circuit 100 or Figure 3 The sampling and holding circuits 626, 628 of the circuit design of circuit 300 can ensure a stable voltage (without drooping) over a relatively long period of time, allowing power savings in the disable units 614, 608, 606, 622 and 624 during hold operation.

[0051] In other examples, the operational amplifier circuitry can overlap and reuse in circuit 630, for example, by using the same operational amplifier (or part of the same circuitry) by multiplier units 622, 624 and by sample and hold circuits 626, 628, because these elements can operate in a complementary manner.

[0052] Figure 7This is an example circuit that can generally correspond to a multiplier circuit. Operational amplifier 702 has a first operational amplifier input (corresponding to the + input), a second operational amplifier input (corresponding to the - input), and an operational amplifier output (corresponding to Vo). A first capacitor (CF) 701 is arranged between the second operational amplifier input and the operational amplifier output. A first switch 726 is connected to the second operational amplifier input in parallel with the first capacitor 704. A second capacitor 706 is arranged in series with the first switch 726 and is connected to floating ground. A second switch 722 is also arranged in series with the first switch 726 and is connected to a reference voltage (VREF). A third capacitor 708 is arranged in series with the first switch 726. The second capacitor 706, the second switch 722, and the third capacitor 708 are all arranged in parallel with each other. The third capacitor 708 is connected in series with a third switch 724, which is connected to the reference voltage (VREF). The third capacitor 708 is also connected in series with a fourth switch 728, which is connected to the operational amplifier output (Vo). The third switch 724 and the fourth switch 728 are connected in parallel.

[0053] In the first cycle (cycle 1), switches 722 and 724 are closed, while switches 726 and 728 are open. In the second cycle (cycle 2), switches 726 and 728 are closed, while switches 722 and 724 are open. Operational amplifier 702 can be active in cycle 1, and can be active in... Figure 7 The circuit shown is used by the sample and hold circuit during cycle 2.

[0054] Figure 8 This is another example of a sample-and-hold circuit 800. In this case, circuit 800 includes an operational amplifier 802, which includes a first operational amplifier input (corresponding to the + input), a second operational amplifier input (corresponding to the - input), and an operational amplifier output (corresponding to Vo). Circuit 800 includes a first switch 822 (corresponding to V in this case) connected between the first operational amplifier input and a power supply node. REF V REF In some examples, this may correspond to an N-doped substrate. Circuit 800 also includes a connection between the input of the second operational amplifier and V. REF The second switch between nodes is connected to the input of the first operational amplifier and V. REF A first capacitor 804 is connected between nodes, and a second capacitor is connected to the input of the second operational amplifier. A third switch 826 and a fourth switch 883 are connected in series with the second capacitor 806, and a fourth switch 832 is arranged in parallel with the operational amplifier 802, such that capacitor 806 is also arranged in parallel with the second capacitor 806. A fifth switch 826 is connected to capacitor 806 in parallel with the fourth switch 832.

[0055] By combination Figure 7 and Figure 8 The circuit can achieve something similar to Figure 1 and Figure 3 The sample and hold circuit also achieves efficiency by reusing a portion of the same circuit during complementary cycles of the multiplier circuit and the sample and hold circuit.

[0056] Figure 9 It shows that it can be Figure 7 and Figure 8 An example circuit combining circuits, whose implementation is similar to... Figure 1 and Figure 3 The sample and hold circuit is similar to the sample and hold circuit, while also achieving efficiency by reusing a portion of the same circuit during the complementary cycles of the multiplier circuit and the sample and hold circuit.

[0057] exist Figure 9 In the circuit, capacitor 912 can correspond to Figure 8 Capacitor 804, and capacitor 914 can correspond to capacitor 806. Figure 9 The operational amplifier 902 can correspond to Figure 8 The operational amplifier 802, and Figure 9 Switches 932, 934, and 942 correspond to respectively Figure 8 Switches 822, 824 and 826.

[0058] exist Figure 9 In a circuit, the multiplier functions similarly to Figure 9 The circuit 900 implements the functionality of the sample-and-hold operation. 7 can be implemented during complementary cycles with sample-and-hold operations, allowing the operational amplifier (e.g., operational amplifier 906) to be used for both multiplication and sample-and-hold operations. Circuit 900 also includes switches 936, 944, 946, and 938, which can be similar to... Figure 7 The switching operation in the circuit. Furthermore, circuit 900 includes capacitors 916 and 918, which can be similar to... Figure 7 Capacitors 708 and 706.

[0059] For Figure 9 The control scheme of the switches shown can operate in two cycles, whereby in cycle 1, switches 932, 934, 936, and 938 are closed, and switches 942, 944, and 946 are open. Then in cycle 2, switches 942, 944, and 946 are closed, and switches 932, 934, 936, and 938 are open.

[0060] According to this disclosure, switches 942 and 938 operate in a complementary manner, such that operational amplifiers 902 and 904 are active in a complementary cycle. Operational amplifier 906 (i.e., the second stage or output stage of the operational amplifier) ​​can be shared by operational amplifiers 902 and 904.

[0061] Therefore, operational amplifier 906 can be connected to a first circuit configured to perform a sample-and-hold operation, and then the same operational amplifier 906 can also be connected to another circuit (e.g., a multiplier circuit). The circuit can be configured to use operational amplifier 906 during the sampling phase of the sample-and-hold operation, and the other circuit (e.g., a multiplier circuit) can be configured to use operational amplifier 906 during the hold phase of the sample-and-hold operation.

[0062] use Figure 9 The circuit shown can achieve something similar to Figure 1 and Figure 3 The sampling and holding circuit, and includes similar to Figure 7 Another circuit of the multiplier circuit shown can operate in a complementary clock phase relative to the sample and hold circuit.

[0063] In some examples, the operational amplifier includes a two-stage operational amplifier (i.e., a combination of operational amplifier 902 and operational amplifier 906, or alternatively, a combination of operational amplifier 904 and operational amplifier 906). The sample-and-hold circuitry and the multiplier circuitry may each include a first stage of the two-stage operational amplifier (i.e., operational amplifier 902 for sample-and-hold and operational amplifier 904 for multiplier). However, in some examples, the sample-and-hold circuitry is configured to use a second stage of the two-stage operational amplifier (i.e., operational amplifier 906) during the sampling phase of the sample-and-hold operation, and the multiplier circuitry is configured to use the second stage of the operational amplifier (i.e., operational amplifier 906) during the hold phase of the sample-and-hold operation.

[0064] Figure 10 This is a flowchart illustrating the method of this disclosure. Figure 10 From Figure 1 or Figure 3 A perspective view of circuit 100 or 300 is provided. As shown, the method may include a sampling phase (1002) and a holding phase (1004). In the sampling phase, switches S1, S2, and S3 are ON, and switch S4 is OFF (1002). In the holding phase, switches S1, S2, and S3 are OFF, and switch S4 is ON. In these examples, the switch conducts when ON and does not conduct when OFF, i.e., it is not conducting. S1 corresponds to... Figure 1 Switch 112 or Figure 3 Switch 312, and S2 corresponds to Figure 1Switch 114 or Figure 3 Switch 314. S3 corresponds to Figure 1 Switch 116 or Figure 3 Switch 316, and S3 corresponds to Figure 1 Switch 118 or Figure 3 Switch 318.

[0065] Figure 11 This is a flowchart illustrating the method of this disclosure. Figure 11 From Figure 5 The circuit 500 is described in some aspects. In some examples, the bandgap generator circuit 502 may correspond to... Figure 6 The circuit elements 606 and 608, and the sample and hold circuits 504A and 504B can correspond to Figure 6 The circuit elements 626 and 628. The sample and hold circuits 504A and 504B can also each correspond to... Figure 1 Circuit 100 or Figure 3 Circuit 300.

[0066] like Figure 11 As shown, circuit 500 enables the bandgap generator (1102), that is, generates a reference voltage for the bandgap during sampling operations. Switches S1, S2, and S3 are controlled to be on, and switch S4 is controlled to be off (1104). Again, S1 corresponds to Figure 1 Switch 112 or Figure 3 Switch 312, and S2 corresponds to Figure 1 Switch 114 or Figure 3 Switch 314. S3 corresponds to Figure 1 Switch 116 or Figure 3 Switch 316, and S3 corresponds to Figure 1 Switch 118 or Figure 3 Switch 318.

[0067] Next, during the holding operation, circuit 500 disables the bandgap generator (1106), for example, to save power. During the holding operation, switches S1, S2, and S3 are controlled to be open, and switch S4 is controlled to be closed (1108).

[0068] Figure 12 This is a flowchart illustrating the method of this disclosure. Figure 12 From Figure 1 Circuit 100 or Figure 3 The circuit 300 is described in terms of aspects. As shown, the method may include a sampling phase and a holding phase. In the sampling phase, switches S1, S2, and S3 are turned on, and switch S4 is turned off (1202). Similarly, S1 corresponds to... Figure 1 Switch 112 or Figure 3Switch 312, and S2 corresponds to Figure 1 Switch 114 or Figure 3 Switch 314. S3 corresponds to Figure 1 Switch 116 or Figure 3 Switch 316, and S3 corresponds to Figure 1 Switch 118 or Figure 3 Switch 318. During the sampling phase, operational amplifiers 102 and 302 are used for the sampling operation (1204) of sample-and-hold circuits 100 and 300.

[0069] During the holding phase, switches S1, S2, and S3 are open, and switch S4 is closed (1206). Furthermore, according to... Figure 12 In this method, during the hold phase, operational amplifiers 102, 302 (or possibly a portion thereof, such as the output stage) are not used for the hold operation of the sample and hold circuits 100, 300. Therefore, the method may include: during the hold phase (1208), operational amplifiers 102, 302 (or possibly a portion thereof, such as the output stage) are used by different circuits (e.g., by multiplier circuitry).

[0070] The techniques and circuits disclosed herein can provide solutions for sampling and maintaining a very long duration with a low droop rate. In some examples, the technique can be based on two concepts: minimizing the voltage on the device controlling the two leakage currents, and utilizing a replica device without including any current mirrors. The described solution allows for robust performance. In a specific example, at 180°C, at C... s With a power density of 1pF, the DV after 80ms is approximately 0.5mV, enabling high-performance power reduction based on an active duty cycle scheme.

[0071] In various examples, the circuit described can be embedded in the full bandgap, thereby utilizing the concept of turning the bandgap voltage generator on and off and maintaining a reference voltage for a long time (i.e. saving power by turning off the bandgap voltage generator).

[0072] The techniques described in this disclosure can be implemented in circuit devices. In various examples, the techniques can be implemented at least in part as circuit devices, hardware, software, firmware, or any combination thereof. For example, various aspects of the techniques can be implemented within one or more logic elements, and switching control can be performed by a processor, which includes one or more microcontrollers, microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or any other equivalent integrated or discrete logic circuits, and any combination of such components. The terms "processor" or "processing circuit device" can generally refer to any of the aforementioned logic circuit devices, alone or in combination with other logic circuit devices, or any other equivalent circuit device. Control units, including hardware, can also perform one or more of the techniques of this disclosure.

[0073] Such circuit arrangements, hardware, software, and firmware may be implemented within the same device or integrated circuit or in separate devices to support the various operations and functions described in this disclosure. Furthermore, any of the described units, modules, or components may be implemented together or separately as discrete but interoperable logic devices. Describing different features as modules or units is intended to highlight different functional aspects and does not necessarily imply that such modules or units must be implemented by separate hardware or software components. Rather, the functions associated with one or more modules or units may be performed by separate hardware or software components, or integrated within common or separate hardware or possible software components.

[0074] The technology disclosed herein may also be described in the following terms.

[0075] Clause 1: A circuit comprising: an operational amplifier including a first operational amplifier input, a second operational amplifier input, and an operational amplifier output; a first switch connected between the first operational amplifier input and a power supply node; a second switch connected between the second operational amplifier input and the power supply node; a first capacitor connected between the first operational amplifier input and a ground node; a second capacitor connected to the second operational amplifier input; a third switch connected between the second capacitor and a sample input; and a fourth switch connected between the second capacitor and the operational amplifier output.

[0076] Clause 2: The circuit according to Clause 1, wherein the circuit is configured to perform a sampling and holding operation on the sample input.

[0077] Clause 3: The circuit according to Clause 2, wherein the sample and hold operation holds the sample input voltage on the operational amplifier output for more than 100 milliseconds.

[0078] Clause 4: The circuit of claim 2 or 3, wherein the sampling and holding operation includes a sampling phase and a holding phase, wherein the length of the holding phase is greater than 500 times the length of the sampling phase.

[0079] Clause 5: The circuit according to Clause 4, wherein during the sampling phase, the first switch is closed, the second switch is closed, the third switch is closed, and the fourth switch is open, and wherein during the holding phase, the first switch is open, the second switch is open, the third switch is open, and the fourth switch is closed.

[0080] Clause 6: The circuit according to Clause 4 or 5, wherein the sampling phase and the holding phase are defined by a clock signal, and the first switch, the second switch, the third switch and the fourth switch are configured to receive a gate control signal defined by the clock signal.

[0081] Clause 7: A circuit according to any one of Clauses 1-6, wherein both the first switch and the second switch are PMOS transistors, each of the PMOS transistors including a source connection to a power node and a body connection to a power node.

[0082] Clause 8: A circuit according to any one of Clauses 1-7, wherein the first capacitor and the second capacitor are matched with approximately the same capacitance.

[0083] Clause 9: A circuit according to any one of Clauses 1-8, wherein the circuit includes a first sampling and holding circuit for a first reference voltage of the bandgap, and the circuit further includes a second sampling and holding circuit for a second reference voltage of the bandgap, wherein the second sampling and holding circuit includes elements that are the same as or similar to the first sampling and holding circuit.

[0084] Clause 10: A circuit according to any one of Clauses 1-8, wherein the circuit is configured to perform a sample and hold operation, and wherein the operational amplifier is further connected to another circuit, wherein the circuit is configured to use the operational amplifier during the sampling phase of the sample and hold operation, and the other circuit is configured to use the operational amplifier during the hold phase of the sample and hold operation.

[0085] Clause 11: The circuit according to Clause 10, wherein the circuit includes a sample-and-hold circuit, and another circuit includes a multiplier circuit operating in a complementary clock phase relative to the sample-and-hold circuit.

[0086] Clause 12: The circuit according to Clause 11, wherein the operational amplifier includes two stages of operational amplifiers, wherein the sample and hold circuit and the multiplier circuit each include a first stage of the two stages of operational amplifiers, and wherein the sample and hold circuit is configured to use the second stage of the operational amplifiers during the sampling phase of the sample and hold operation, and the multiplier circuit is configured to use the second stage of the operational amplifiers during the hold phase of the sample and hold operation.

[0087] Clause 13: The circuit according to any one of Clauses 1-12 further includes a voltage generator circuit, wherein the voltage generator circuit is configured to generate a voltage during the sampling phase, and wherein the voltage generator circuit is disabled during the holding phase.

[0088] Clause 14: The circuit according to Clause 13, wherein the voltage generator circuit includes a bandgap generator that generates a first reference voltage and a second reference voltage, wherein the circuit includes a first sampling and holding circuit for the first reference voltage of the bandgap, and the circuit further includes a second sampling and holding circuit for the second reference voltage of the bandgap, wherein the second sampling and holding circuit includes the same or similar elements as the first sampling and holding circuit.

[0089] Clause 15: Circuits according to Clause 13 or 14, wherein the voltage generator circuit is configured to generate a temperature-dependent voltage reference.

[0090] Clause 16: A method of operating circuitry to perform a sample and hold operation on a sample input, wherein the circuitry includes: an operational amplifier including a first operational amplifier input, a second operational amplifier input, and an operational amplifier output; a first switch connected to the first operational amplifier input and a power supply node; a second switch connected to the second operational amplifier input and a power supply node; a first capacitor connected between the first operational amplifier input and a ground node; a second capacitor connected to the second operational amplifier input; a third switch connected between the second capacitor and a sample input; and a fourth switch connected between the second capacitor and the operational amplifier output, the method comprising: performing a sampling phase; and performing a hold phase.

[0091] Clause 17: The method according to Clause 16, wherein the sampling phase includes: controlling the first switch to close, controlling the second switch to close, controlling the third switch to close, and controlling the fourth switch to open, and wherein the holding phase includes: controlling the first switch to open, controlling the second switch to open, controlling the third switch to open, and controlling the fourth switch to close.

[0092] Clause 18: The method according to Clause 17, wherein the sampling phase and the holding phase are defined by a clock signal, wherein the holding phase holds the sampled input voltage on the operational amplifier output for more than 100 milliseconds, and wherein the length of the holding phase is greater than 500 times the length of the sampling phase.

[0093] Clause 19: The method according to any one of Clauses 16-18, wherein both the first switch and the second switch are PMOS transistors, each PMOS transistor including a source connection to a power node and a body connection to a power node, and wherein the first capacitor and the second capacitor are matched with substantially the same capacitance.

[0094] Clause 20: A method according to any one of Clauses 16-19, wherein the circuit includes a first sample and hold circuit for a first reference to the bandgap, the circuit further includes a second sample and hold circuit for a second reference to the bandgap, wherein the second sample and hold circuit includes the same or similar elements as the first sample and hold circuit, and the method further includes performing two different sample and hold operations on two different sample inputs to the bandgap.

[0095] Various examples of this disclosure have been described. These and other examples are within the scope of the following claims.

Claims

1. A circuit comprising: An operational amplifier, including a first operational amplifier input, a second operational amplifier input, and an operational amplifier output; The first switch is connected between the input of the first operational amplifier and the power supply node; A second switch is connected between the input of the second operational amplifier and the power supply node; The first capacitor is connected between the input of the first operational amplifier and the ground node; The second capacitor is connected to the input of the second operational amplifier; A third switch is connected between the second capacitor and the sample input; as well as A fourth switch is connected between the second capacitor and the output of the operational amplifier.

2. The circuit of claim 1, wherein the circuit is configured to perform a sampling and holding operation on the sample input.

3. The circuit of claim 2, wherein the sample and hold operation holds the sample input voltage on the operational amplifier output for more than 100 milliseconds.

4. The circuit of claim 2, wherein the sampling and holding operation includes a sampling phase and a holding phase, wherein the length of the holding phase is greater than 500 times the length of the sampling phase.

5. The circuit according to claim 4, During the sampling phase, the first switch is closed, the second switch is closed, the third switch is closed, and the fourth switch is open. During the holding phase, the first switch is open, the second switch is open, the third switch is open, and the fourth switch is closed.

6. The circuit of claim 5, wherein the sampling phase and the holding phase are defined by a clock signal, and the first switch, the second switch, the third switch, and the fourth switch are configured to receive a gate control signal defined by the clock signal.

7. The circuit of claim 5, wherein both the first switch and the second switch are PMOS transistors, each PMOS transistor including a source connection to the power node and a body connection to the power node.

8. The circuit of claim 1, wherein the first capacitor and the second capacitor are matched with approximately the same capacitance.

9. The circuit of claim 1, wherein the circuit includes a first sampling and holding circuit for a first reference voltage of the bandgap, and the circuit further includes: A second sampling and holding circuit for the second reference voltage of the bandgap, wherein the second sampling and holding circuit includes the same or similar elements as the first sampling and holding circuit.

10. The circuit of claim 1, wherein the circuit is configured to perform a sample and hold operation, and The operational amplifier is also connected to another circuit, which is configured to use the operational amplifier during the sampling phase of the sample-and-hold operation, and the other circuit is configured to use the operational amplifier during the hold phase of the sample-and-hold operation.

11. The circuit of claim 10, wherein the circuit includes a sample and hold circuit, and the other circuit includes a multiplier circuit operating in a complementary clock phase relative to the sample and hold circuit.

12. The circuit of claim 11, wherein the operational amplifier comprises a two-stage operational amplifier, wherein the sample-and-hold circuit and the multiplier circuit each comprise a first stage of the two-stage operational amplifier, and wherein the sample-and-hold circuit is configured to use the second stage of the operational amplifier during the sampling phase of the sample-and-hold operation, and the multiplier circuit is configured to use the second stage of the operational amplifier during the hold phase of the sample-and-hold operation.

13. The circuit of claim 1, further comprising a voltage generator circuit, wherein the voltage generator circuit is configured to generate a voltage during the sampling phase, and wherein the voltage generator circuit is disabled during the holding phase.

14. The circuit according to claim 13, The voltage generator circuit includes a bandgap generator that generates a first reference voltage and a second reference voltage. The circuit includes a first sampling and holding circuit for the first reference voltage of the bandgap, and the circuit further includes: A second sampling and holding circuit for the second reference voltage of the bandgap, wherein the second sampling and holding circuit includes the same or similar elements as the first sampling and holding circuit.

15. The circuit of claim 13, wherein the voltage generator circuit is configured to generate a temperature-dependent voltage reference.

16. A method of operating circuitry to perform sampling and holding operations on sample input, wherein the circuitry includes: An operational amplifier, including a first operational amplifier input, a second operational amplifier input, and an operational amplifier output; A first switch is connected to the input and power supply node of the first operational amplifier. A second switch is connected to the input of the second operational amplifier and the power supply node; The first capacitor is connected between the input of the first operational amplifier and the ground node; The second capacitor is connected to the input of the second operational amplifier; A third switch is connected between the second capacitor and the sample input; as well as A fourth switch is connected between the second capacitor and the operational amplifier output, the method comprising: Perform the sampling phase; as well as Execution maintenance phase.

17. The method according to claim 16, The sampling phase includes: Control the first switch to close, control the second switch to close, control the third switch to close, and control the fourth switch to open. The holding phase includes: controlling the first switch to open, controlling the second switch to open, controlling the third switch to open, and controlling the fourth switch to close.

18. The method of claim 17, wherein the sampling phase and the holding phase are defined by a clock signal, wherein the holding phase holds the sample input voltage on the operational amplifier output for more than 100 milliseconds, and wherein the length of the holding phase is greater than 500 times the length of the sampling phase.

19. The method according to claim 16, Both the first switch and the second switch are PMOS transistors, each including a source connection to the power node and a body connection to the power node. The first capacitor and the second capacitor are matched with approximately the same capacitance.

20. The method according to claim 16, The circuit includes a first sample-and-hold circuit for a first reference to the bandgap, and the circuit further includes: A second sampling and holding circuit for the second reference of the bandgap, wherein the second sampling and holding circuit includes the same or similar elements as the first sampling and holding circuit, the method further includes: Two different sampling and holding operations are performed on two different sample inputs to the bandgap.

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