Step-down circuit

Abstract

The invention discloses a step-down circuit. On-off states of a first switch unit and a second switch unit are controlled through a control stage. During dynamic response, the rising amplitude of the second voltage signal is relatively small, and the first voltage signal can be rapidly risen to be equal to the second voltage signal, so that the frequency of switching on the first switch unit by the driving circuit is improved. When the current at the output end changes suddenly, the faster the frequency change of the driving circuit for conducting the first switch unit is, the faster the current change of the charging and discharging unit is, and the output voltage of the step-down circuit can reach a stable state more quickly, so that the dynamic response time of the step-down circuit is shorter.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuits, and more specifically to a step-down circuit. Background Technology

[0002] A "COT Buck circuit" refers to a buck circuit that uses fixed on-time control. A buck circuit converts a higher input DC voltage into a lower, stable DC output voltage by switching a transistor on and off. COT control, or fixed on-time control, is a control method for switching power supplies. It fixes the on-time of the transistor while dynamically adjusting the off-time based on output voltage feedback. When the output voltage is lower than the reference voltage, the transistor is turned on for a fixed time and then turned off. During the off-time, the output voltage gradually decreases until it falls below the reference voltage again. This process of turning the transistor on and off is repeated to obtain a stable output voltage.

[0003] COT Buck circuits in the prior art, such as Figure 1 As shown, the switching transistors M1 and M2 and the inductor L1 constitute the basic circuit structure of the power stage of the COT Buck circuit. L1 V is the inductor current. OUT For the output voltage, I OUT The output current is EA. The error amplifier EA, compensation circuit, triangular wave generation circuit, comparator, and COT generation circuit constitute the basic circuit structure of the control stage of the COT Buck circuit.

[0004] The waveform diagram of the steady-state operation of the existing COT Buck circuit is as follows: Figure 2 As shown. When the COT Buck circuit is working normally, the output voltage V OUT With reference voltage V REF The input is fed into error amplifier EA for error amplification, and after passing through a compensation circuit, the error signal V is obtained. EA V SW The input is fed into the triangular wave generation circuit, which generates a triangular wave signal V. RAMP With V EA The comparison is performed, and the comparator's output voltage controls the switching transistor's activation. When V... RAMP Less than V EA When the time is up, an on_start pulse signal is generated, which turns M1 on and increases the inductor current; after a fixed period of time, the COT generating circuit outputs an on_end pulse signal, which turns M1 off and decreases the inductor current.

[0005] The dynamic response waveform of the existing COT Buck circuit during load adjustment is shown in the figure below. Figure 3 As shown. In this circuit, V RAMP By V SW Signal generation, VSW The signal is related to the inductor current, therefore V RAMP The signal waveform is similar to the change in inductor current; both increase and decrease simultaneously. When I... OUT When V increases suddenly OUT Decrease, V EA As the frequency of the on_start pulse signal increases, the cycle of repeated on- and off-phase switching of the switching transistor becomes shorter due to the fixed on-time of the switching transistor. This increases the duty cycle of the COT Buck circuit and the inductor current I. L1 Increase until I L1 The average value and load current I OUT Only when the voltages are equal can the system's output voltage stabilize. In summary, existing COT Buck circuits require a certain amount of time for their output voltage to stabilize during dynamic response. Summary of the Invention

[0006] The main technical problem solved by this invention is that the output voltage of a step-down circuit with fixed on-time control takes too long to stabilize during dynamic response.

[0007] According to a first aspect, one embodiment provides a step-down circuit, comprising:

[0008] A power stage includes a first control terminal, a second control terminal, a first node, an input terminal, an output terminal, a first switching unit, a second switching unit, and a charging / discharging unit. The first switching unit is used to turn on when the signal from the first control terminal is valid to connect the input terminal and the first node. The input terminal is used to receive an input voltage. The second switching unit is used to turn on when the signal from the second control terminal is valid to connect the first node to a ground terminal. The charging / discharging unit is used to charge or discharge the output terminal using the voltage of the first node to form an output voltage.

[0009] A control level for controlling the switching states of the first switching unit and the second switching unit, the control level comprising:

[0010] A first voltage signal generating circuit is used to compare the output voltage of the power stage with a first reference voltage and output a first voltage signal. The first voltage signal is used to reflect the degree to which the output voltage of the power stage deviates from the first reference voltage.

[0011] The second voltage signal generating circuit is used to output a second voltage signal; when the first switching unit is turned on, the second voltage signal rises at a first speed; when the first switching unit is turned off, the second voltage signal remains unchanged in a first time period, and the second voltage signal falls at a second speed in a second time period; the first speed is less than the second speed.

[0012] The driving circuit is used to control the switching state of the first switching unit and the second switching unit through the first control terminal and the second control terminal. When the second voltage signal is less than the first voltage signal, the first switching unit is turned on.

[0013] In a further embodiment of the present invention, the second voltage signal generating circuit includes:

[0014] A segmented ramp wave generating circuit is used to output a second voltage signal. The segmented ramp wave generating circuit includes a first load resistor, a second load resistor, and a second capacitor.

[0015] When the first switching unit is turned on, the input of the segmented ramp generation circuit is a first level. The first load resistor and the second load resistor are connected in series. Current flows through the first load resistor and the second load resistor to charge the second capacitor. The voltage of the second capacitor rises at the first speed, and the voltage of the second capacitor is output as the second voltage signal.

[0016] When the first switching unit is turned off and is in the first time period, the second capacitor does not charge or discharge, the voltage of the second capacitor remains unchanged, and the voltage of the second capacitor is output as the second voltage signal.

[0017] When the first switching unit is turned off and is in the second time period, the input of the segmented ramp generation circuit is the second level, the first load resistor is short-circuited, the second capacitor discharges through the second load resistor, the voltage of the second capacitor decreases at the second speed, and the voltage of the second capacitor is output as the second voltage signal.

[0018] In a further embodiment of the present invention, the second voltage signal generating circuit includes:

[0019] A segmented timing circuit is used to time the step-down circuit and determine the time when the first time segment occurs.

[0020] When the first time period is in progress, the segmented timing circuit prevents the second capacitor from charging and discharging.

[0021] When not in the first time period, the segmented timing circuit allows the second capacitor to charge and discharge.

[0022] In a further embodiment of the present invention, the segmented timing circuit includes a third capacitor and a fourth capacitor, wherein the ratio of the third capacitor to the fourth capacitor is m;

[0023] When the first switching unit is turned on until the first switching unit is turned off, the third capacitor and the fourth capacitor discharge until the capacitor voltage is zero; the segmented timing circuit allows the second capacitor to be charged and discharged.

[0024] When the first switching unit is turned off until it is turned on, the third capacitor and the fourth capacitor are charged with the same current. The voltage of the fourth capacitor is compared with the maximum voltage of the third capacitor when the first switching unit was previously charged. If the voltage of the fourth capacitor is greater than the maximum voltage of the third capacitor when the first switching unit was previously charged, the segmented timing circuit prohibits the second capacitor from charging and discharging; otherwise, the segmented timing circuit allows the second capacitor to charge and discharge.

[0025] In a further embodiment of the present invention, the ratio of the sum of the durations of the first time period and the second time period to the duration of the first time period is m.

[0026] In a further embodiment of the present invention, the input of the segmented ramp generation circuit is the voltage of the first node; when the first switching unit is turned on, the input of the segmented ramp generation circuit is a first level; when the first switching unit is turned off, the input of the segmented ramp generation circuit is a second level.

[0027] In a further embodiment of the present invention, the driving circuit further includes:

[0028] A drive unit is used to control the switching states of the first switch unit and the second switch unit through the first control terminal and the second control terminal;

[0029] The delay circuit sends a shutdown signal to the driving unit after a fixed time when the second voltage signal is less than the first voltage signal, notifying the driving unit to shut down the first switching unit.

[0030] In a further embodiment of the present invention, the driving circuit further includes:

[0031] A comparator is used to compare the magnitudes of the first voltage signal and the second voltage signal;

[0032] When the second voltage signal is less than the first voltage signal, a conduction signal is sent to the driving unit and the delay circuit to notify the driving unit to conduct the first switching unit, and the delay circuit is notified to send a turn-off signal to the driving unit after a fixed time to notify the driving unit to turn off the first switching unit.

[0033] In a further embodiment of the present invention, the first voltage signal generating circuit includes an error amplifier, which takes the output voltage of the power stage and the first reference voltage as inputs and outputs an error signal, which is used to reflect the degree to which the output voltage of the power stage deviates from the first reference voltage.

[0034] In a further embodiment of the present invention, the first voltage signal generating circuit includes a compensation circuit, which takes the error signal as input, compensates for the oscillation of the error signal, and outputs the first voltage signal.

[0035] This application discloses a step-down circuit that controls the switching states of a first switching unit and a second switching unit through a control stage. Specifically, a first voltage signal generating circuit compares the output voltage of the power stage with a first reference voltage and outputs a first voltage signal; a second voltage signal generating circuit outputs a second voltage signal; and a driving circuit turns on the first switching unit when the second voltage signal is less than the first voltage signal.

[0036] In the buck circuit of this invention, when the first switching unit is turned on, the second voltage signal rises at a first speed; when the first switching unit is turned off, the second voltage signal remains unchanged in the first time period and decreases at a second speed in the second time period. During dynamic response, the rise amplitude of the second voltage signal is smaller, and the first voltage signal can rise to equal it more quickly, thereby increasing the frequency at which the drive circuit turns on the first switching unit. When the output current changes abruptly, since the on-time of the first switching unit of the buck circuit is fixed, the change in the current of the charging and discharging unit depends on the change in the frequency at which the drive circuit turns on the first switching unit. When the frequency at which the drive circuit turns on the first switching unit increases, the duty cycle of the buck circuit increases, and the current of the charging and discharging unit increases. The faster the frequency at which the drive circuit turns on the first switching unit changes, the faster the current of the charging and discharging unit changes, and the faster the output voltage of the buck circuit can reach a stable state, resulting in a shorter dynamic response time for the buck circuit. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the structure of a COT Buck circuit in the prior art;

[0038] Figure 2 This is a waveform diagram of a COT Buck circuit in steady-state operation in the prior art;

[0039] Figure 3 The waveform diagram shows the dynamic response of a COT Buck circuit in the prior art.

[0040] Figure 4 This is a schematic diagram of the step-down circuit in an embodiment of the present invention;

[0041] Figure 5This is a schematic diagram of the segmented ramp wave generating circuit according to an embodiment of the present invention;

[0042] Figure 6 This is a waveform diagram of the segmented ramp wave generator circuit according to an embodiment of the present invention;

[0043] Figure 7 A schematic diagram of the existing COT Buck circuit triangular wave generation circuit;

[0044] Figure 8 The waveform diagram of the existing COT Buck circuit triangular wave generation circuit is shown.

[0045] Figure 9 This is a schematic diagram of the segmented timing circuit according to an embodiment of the present invention;

[0046] Figure 10 This is a waveform diagram of the segmented timing circuit in an embodiment of the present invention;

[0047] Figure 11 This is a schematic diagram of the delay circuit according to an embodiment of the present invention;

[0048] Figure 12 This is a waveform diagram of the step-down circuit in steady-state operation according to an embodiment of the present invention;

[0049] Figure 13 This is a waveform diagram of the step-down circuit in an embodiment of the present invention during dynamic response;

[0050] Figure 14 The diagram shows the dynamic response characteristics of a COT Buck circuit in the prior art.

[0051] Figure 15 This is a diagram illustrating the dynamic response characteristics of the step-down circuit according to an embodiment of the present invention.

[0052] Figure 16 The following are waveform diagrams of the segmented timing circuit in other embodiments of the present invention;

[0053] Figure 17 The following is a waveform diagram of the segmented timing circuit in another embodiment of the present invention. Detailed Implementation

[0054] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0055] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0056] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0057] A COT (Constant On-Time) Buck circuit refers to a step-down circuit that uses fixed on-time control. A Buck circuit, or step-down circuit, converts a higher input DC voltage into a lower, stable DC output voltage by switching a transistor on and off. COT control, or fixed on-time control, is a control method for switching power supplies. It fixes the on-time of the transistor while dynamically adjusting the off-time based on feedback from the output voltage. When the output voltage is lower than the reference voltage, the transistor is turned on for a fixed time and then turned off. During the off-time, the output voltage gradually decreases until it falls below the reference voltage again. The process of turning the transistor on and off is repeated to obtain a stable output voltage.

[0058] In practical applications, it was found that during the dynamic response of the COT Buck circuit in load adjustment, when the output current suddenly increases, the output voltage drops, and the frequency of the first switching transistor being turned on by the drive circuit increases. Since the on-time of the switching transistor is fixed, the cycle of repeated on- and off-time of the switching transistor becomes shorter, the duty cycle of the COT Buck circuit increases, and the inductor current increases. The system output voltage can only stabilize when the average value of the inductor current is equal to the output current. This results in the technical problem that the output voltage of the COT Buck circuit takes too long to stabilize during dynamic response.

[0059] Based on this discovery, this application discloses a buck circuit that increases the frequency at which the first switching transistor of the driving circuit is turned on during dynamic response. When the output current changes abruptly, since the on-time of the first switching unit of the buck circuit is fixed, the change in current of the charging and discharging unit depends on the change in the frequency at which the first switching unit of the driving circuit is turned on. The faster the frequency at which the first switching unit of the driving circuit changes, the faster the current of the charging and discharging unit changes, and the faster the output voltage of the buck circuit can reach a stable state, resulting in a shorter dynamic response time for the buck circuit.

[0060] The concept of the present invention will be explained in detail below through specific embodiments.

[0061] In some embodiments, please refer to Figure 4 , Figure 4 This is the basic structure of the buck circuit in an embodiment of the present invention. The buck circuit includes a power stage 100, which includes a first control terminal 110, a second control terminal 120, a first node 130, an input terminal 140, an output terminal 150, a first switching unit 160, a second switching unit 170, and a charging and discharging unit 180.

[0062] In some embodiments, the first switching unit 160 and the second switching unit 170 can be PMOS transistors, whose core structure consists of two P-type doped regions formed on an N-type silicon substrate, serving as the source and drain, respectively. The conduction and cutoff of the channel are controlled by the gate voltage. This allows the first switching unit 160 to conduct when the signal at the first control terminal 110 is valid, thereby connecting the input terminal 140 and the first node 130; and the second switching unit 170 to conduct when the signal at the second control terminal 120 is valid, thereby connecting the first node 130 to the ground terminal.

[0063] In some embodiments, the charging and discharging unit 180 may be an inductor, and the charging and discharging unit 180 is used to charge or discharge the output terminal 150 through the voltage of the first node 130 to form an output voltage.

[0064] In some embodiments, the power stage 100 includes a first capacitor and a load resistor. When the first switching unit 160 is turned on, the input voltage stores energy in the charging / discharging unit 180 through the first switching unit 160, causing the inductor current to rise, and simultaneously supplying power to the first capacitor and the load resistor. When the second switching unit 170 is turned on, the first switching unit 160 is turned off, and the charging / discharging unit 180 freewheels through the second switching unit 170, causing the inductor current to decrease. The first capacitor maintains the output voltage, i.e., the voltage of the load resistor is stable.

[0065] In some embodiments, the buck circuit includes a control stage 200 for controlling the switching states of the first switching unit 160 and the second switching unit 170. The control stage 200 includes a first voltage signal generating circuit 210, a second voltage signal generating circuit 220, and a drive circuit 230.

[0066] In some embodiments, the first voltage signal generating circuit 210 includes an error amplifier 211, which takes the output voltage of the power stage 100 and a first reference voltage as inputs and outputs an error signal. The error signal reflects the degree to which the output voltage of the power stage 100 deviates from the first reference voltage. The first voltage signal generating circuit 210 also includes a compensation circuit 212, which takes the error signal as input, compensates for the oscillation of the error signal, and outputs a first voltage signal.

[0067] In some embodiments, the second voltage signal generating circuit 220 includes a segmented ramp generating circuit 221 and a segmented timing circuit 222. The segmented ramp generating circuit 221 is used to output a second voltage signal, and the segmented timing circuit 222 is used to control the occurrence time of the first time period of the segmented ramp generating circuit 221.

[0068] In some embodiments, please refer to Figure 5 as well as Figure 6 , Figure 5 This is the basic structure of the segmented ramp wave generating circuit 221 in this embodiment of the invention. Figure 6 This is a waveform diagram of the segmented ramp wave generating circuit 221 in an embodiment of the present invention. The segmented ramp wave generating circuit 221 includes a first load resistor 2211, a second load resistor 2212, and a second capacitor 2213.

[0069] In some embodiments, the input to the segmented ramp generation circuit 221 can be the voltage of the first node 130. Essentially, however, the voltage of the first node 130 represents the on / off state of the first switching unit 160 and the second switching unit 170. When the first switching unit 160 is on, the input to the segmented ramp generation circuit 221 is a first level, i.e., a high level; when the first switching unit 160 is off, the input to the segmented ramp generation circuit 221 is a second level, i.e., a low level.

[0070] In some embodiments, whether the first load resistor 2211 in the segmented ramp generation circuit 221 is short-circuited is controlled by the voltage of the first switching unit 160, i.e., controlled by the on or off state of the first switching unit 160. When the first switching unit 160 is on, the first load resistor 2211 is not short-circuited, and the first load resistor 2211 and the second load resistor 2212 are connected in series. When the first switching unit 160 is off, the first load resistor 2211 is short-circuited, and the load is provided only by the second load resistor 2212.

[0071] In some embodiments, whether the first load resistor 2211 and the second load resistor 2212 in the segmented ramp generation circuit 221 are connected to the second capacitor 2213 is controlled by the segmented timing circuit 222. When in the first time period, the segmented timing circuit 222 prohibits the second capacitor 2213 from charging and discharging; when not in the first time period, the segmented timing circuit 222 allows the second capacitor 2213 to charge and discharge.

[0072] When the first switching unit 160 is turned on, the input of the segmented ramp generation circuit 221 is at the first level. The first load resistor 2211 and the second load resistor 2212 are connected in series. Current flows through the first load resistor 2211 and the second load resistor 2212 to charge the second capacitor 2213. The voltage of the second capacitor 2213 rises at a first speed, and the voltage of the second capacitor 2213 is output as the second voltage signal. Because the first load resistor 2211 and the second load resistor 2212 are connected in series, the resistance is relatively large, which slows down the charging time of the second capacitor 2213 and the rise speed of the second voltage signal is smaller.

[0073] When the first switching unit 160 is turned off and is in the first time period, the second capacitor 2213 does not charge or discharge, the voltage of the second capacitor 2213 remains unchanged, and the voltage of the second capacitor 2213 is output as the second voltage signal. At this time, the magnitude of the second voltage signal remains unchanged.

[0074] When the first switching unit 160 is turned off and in the second time period, the input of the segmented ramp generation circuit 221 is at the second level, the first load resistor 2211 is short-circuited, the second capacitor 2213 discharges through the second load resistor 2212, the voltage of the second capacitor 2213 decreases at the second speed, and the voltage of the second capacitor 2213 is output as the second voltage signal. Because the first load resistor 2211 is short-circuited, the discharge time of the second capacitor 2213 is faster, and the rate of decrease of the second voltage signal, i.e., the second speed, is greater than the rate of increase of the second voltage signal, i.e., the first speed.

[0075] Compared with existing technologies, in existing COT Buck circuits, such as Figure 7 as well as Figure 8 As shown, Figure 7This is the basic structure of the existing COT Buck circuit triangular wave generation circuit. Figure 8 This is a waveform diagram of the existing COT Buck circuit generating a triangular wave. The existing COT Buck circuit is a simple RC circuit that converts the input square wave signal into a ramp signal that approximates a triangular wave.

[0076] Compared to existing technologies, for the same charging cycle duration, the segmented ramp wave generation circuit has a larger charging resistance during charging, resulting in a slower rise rate of the second voltage signal. During dynamic response, the smaller rise amplitude of the second voltage signal allows the first voltage signal to rise to equal it more quickly, thereby increasing the frequency at which the drive circuit 230 turns on the first switching unit 160. When the current at the output terminal 150 changes abruptly, since the on-time of the first switching unit 160 in the buck circuit is fixed, the change in current in the charging / discharging unit 180 depends on the frequency at which the drive circuit 230 turns on the first switching unit 160. As the frequency at which the drive circuit 230 turns on the first switching unit 160 increases, the duty cycle of the buck circuit increases, and the current in the charging / discharging unit 180 increases. The faster the frequency at which the drive circuit 230 turns on the first switching unit 160 changes, the faster the current in the charging / discharging unit 180 changes, and the faster the output voltage of the buck circuit can reach a stable state, resulting in a shorter dynamic response time for the buck circuit.

[0077] In some embodiments, please refer to Figure 9 as well as Figure 10 , Figure 9 This is the basic structure of the segmented timing circuit 222 in an embodiment of the present invention. Figure 10 This is a waveform diagram of the segmented timing circuit according to an embodiment of the present invention. The segmented timing circuit 222 includes a third capacitor 2221 and a fourth capacitor 2222, with a ratio of 2 between the third capacitor 2221 and the fourth capacitor 2222. The segmented timing circuit 222 is used to time the step-down circuit and determine the time of occurrence of the first time period. When the first time period is in progress, the segmented timing circuit 222 prohibits the second capacitor 2213 from charging and discharging; when the first time period is not in progress, the segmented timing circuit 222 allows the second capacitor 2213 to charge and discharge.

[0078] The segmented timing circuit 222 is mainly used to generate V. M2_HALF The signal controls the timing of the first segment of the segmented ramp generation circuit 221. The segmented timing circuit 222 consists of two capacitor charging branches, a voltage buffer, a comparator 231, and a NAND gate. The currents in the two capacitor charging branches are equal, both being I. p1 The capacitance of the third capacitor 2221 is twice that of the fourth capacitor 2222.

[0079]

[0080] Where I is the charging current of the third capacitor 2221 and the fourth capacitor 2222, t is the charging time of the third capacitor 2221 and the fourth capacitor 2222, C is the capacitance of the third capacitor 2221 and the fourth capacitor 2222, and V is the capacitor voltage of the third capacitor 2221 and the fourth capacitor 2222.

[0081] From the above formula, it can be seen that, within the same charging time, V CH2 Approximately V CH1 twice as much, V CH1 With V CH2 These are the voltages of the third capacitor 2221 and the fourth capacitor 2222 after they have been charged within the same time period, respectively. RST For V M2 That is, the reverse signal of the voltage of the second switching unit 170 serves as the reset signal for the fourth capacitor 2222 and the third capacitor 2221, while simultaneously controlling the discharge of the third capacitor 2221 and the fourth capacitor 2222. During discharge, V is set. CH1 and V CH2 =0; in V M2 When the signal is high, T RST When the signal is low, the voltages of the third capacitor 2221 and the fourth capacitor 2222 are cleared to zero, and charging begins. C HOLD To maintain capacitance, at T SMP When disconnected, maintain V SMP Voltage. During the clearing and charging of the third capacitor 2221, T SMP Disconnect, V SMP Maintain the charging voltage of the third capacitor 2221 from the previous cycle.

[0082] During the operation of the segmented timing circuit 222, from the time the first switching unit 160 is turned on until it is turned off, the third capacitor 2221 and the fourth capacitor 2222 discharge until their voltages are zero, and the segmented timing circuit 222 allows the second capacitor 2213 to charge and discharge. When the first switching unit 160 is turned off until it is turned on, the third capacitor 2221 and the fourth capacitor 2222 are charged with the same current. The voltage of the fourth capacitor 2222 is compared with the maximum voltage of the third capacitor 2221 during the previous charging by the first switching unit 160. If the voltage of the fourth capacitor 2222 is greater than the maximum voltage of the third capacitor 2221 during the previous charging by the first switching unit 160, the segmented timing circuit 222 prohibits the second capacitor 2213 from charging and discharging; otherwise, the segmented timing circuit 222 allows the second capacitor 2213 to charge and discharge.

[0083] Since the capacitance of the third capacitor 2221 is twice that of the fourth capacitor 2222, V will be at the end of charging. CH2 Approximately VCH1 Twice that. V SMP The voltage remains the same as the charging voltage of the third capacitor 2221 from the previous cycle. Therefore, when the first time period is half the sum of the first and second time periods, the output of comparator 231 flips.

[0084] In some embodiments, the driving circuit 230 is used to control the switching state of the first switching unit 160 and the second switching unit 170 through the first control terminal 110 and the second control terminal 120. When the second voltage signal is less than the first voltage signal, the first switching unit 160 is turned on.

[0085] In some embodiments, the driving circuit 230 includes a comparator 231, a driving unit 232, and a delay circuit 233. The comparator 231 compares the magnitudes of a first voltage signal and a second voltage signal. The driving unit 232 controls the switching states of the first switching unit 160 and the second switching unit 170 via a first control terminal 110 and a second control terminal 120. When the second voltage signal is less than the first voltage signal, a turn-on signal is sent to the driving unit 232 and the delay circuit 233 to notify the driving unit 232 to turn on the first switching unit 160, and to notify the delay circuit 233 to send a turn-off signal to the driving unit 232 after a fixed time, thereby notifying the driving unit 232 to turn off the first switching unit 160.

[0086] In some embodiments, please refer to Figure 11 , Figure 11 This is the basic structure of the delay circuit 233 in an embodiment of the present invention.

[0087] I1 and input voltage V in Related, A is the conductivity coefficient. I2 is the mirror proportional current of I1, used to charge the capacitor. When the second voltage signal is less than the first voltage signal, a conduction signal is sent to the drive unit 232 and the delay circuit 233, that is, an on_start signal is sent to control the capacitor discharge. The capacitor charging voltage V1 is compared with the output voltage V of the step-down circuit. out In comparison, a shutdown signal is sent to the drive unit 232, that is, an on_end signal is sent to control the conduction time of the first switching unit 160.

[0088] In practical applications, please refer to Figure 4 , Figure 12 as well as Figure 13 , Figure 12 This is a waveform diagram of the step-down circuit in steady-state operation according to an embodiment of the present invention. Figure 13This is a waveform diagram of the buck circuit in dynamic response according to an embodiment of the present invention. When the buck circuit is working normally, the output voltage and the first reference voltage are input to the error amplifier 211 for error amplification. After passing through the compensation circuit 212, a first voltage signal is obtained. The voltage at the first node 130 is input to the segmented ramp generation circuit 221, and the generated second voltage signal is compared with the first voltage signal. The output voltage of the comparator 231 controls the switching transistor to turn on. When the first voltage signal is less than the second voltage signal, a conduction signal is sent to the drive unit 232 and the delay circuit 233, notifying the drive unit 232 to turn on the first switching unit 160, and notifying the delay circuit 233 to send a turn-off signal to the drive unit 232 after a fixed time, thereby notifying the drive unit 232 to turn off the first switching unit 160.

[0089] For the same charging cycle duration, the second voltage signal rises at a slower rate due to the larger charging resistance of the segmented ramp wave generation circuit during charging. During dynamic response, the smaller rise amplitude of the second voltage signal allows the first voltage signal to rise to equal it more quickly, thus increasing the frequency at which the drive circuit 230 turns on the first switching unit 160. When the current at the output terminal 150 changes abruptly, since the on-time of the first switching unit 160 in the buck circuit is fixed, the change in current in the charging / discharging unit 180 depends on the frequency at which the drive circuit 230 turns on the first switching unit 160. As the frequency at which the drive circuit 230 turns on the first switching unit 160 increases, the duty cycle of the buck circuit increases, and the current in the charging / discharging unit 180 increases. The faster the frequency at which the drive circuit 230 turns on the first switching unit 160 changes, the faster the current in the charging / discharging unit 180 changes, and the faster the output voltage of the buck circuit can reach a stable state, resulting in a shorter dynamic response time for the buck circuit.

[0090] Compared with the buck circuit of the present invention, the existing COT Buck circuit is shown in the figure. Figure 14 as well as Figure 15 , Figure 14 The diagram shows the dynamic response characteristics of a COT Buck circuit in the prior art. Figure 15 This is a diagram showing the dynamic response characteristics of the step-down circuit in an embodiment of the present invention. Figure 14 In the diagram, the lower curve represents the load current, and the upper curve represents the output voltage. When the load current switches from 0.1A to 6A, the maximum range by which the output voltage falls below the final stable voltage value during the transient drop is 33mV. Figure 15 In the diagram, the lower curve represents the load current, and the upper curve represents the output voltage. When the load current switches from 0.1A to 6A, the maximum amplitude of the output voltage below the final stable voltage value during the transient drop is 18mV. It can be concluded that, compared with existing technologies, the output voltage of the buck circuit in this embodiment of the invention can reach a stable state more quickly, resulting in a shorter dynamic response time.

[0091] This application discloses a step-down circuit that controls the switching states of a first switching unit 160 and a second switching unit 170 via a control stage 200. A first voltage signal generation circuit 210 compares the output voltage of the power stage 100 with a first reference voltage and outputs a first voltage signal; a second voltage signal generation circuit 220 outputs a second voltage signal; and a drive circuit 230 turns on the first switching unit 160 when the second voltage signal is less than the first voltage signal. When the first switching unit 160 is on, the second voltage signal rises at a first speed; when the first switching unit 160 is off, the second voltage signal remains constant in a first time period and decreases at a second speed in a second time period. During dynamic response, the rise amplitude of the second voltage signal is smaller, allowing the first voltage signal to rise to equal it more quickly, thereby increasing the frequency at which the drive circuit 230 turns on the first switching unit 160. When the current at the output terminal 150 changes abruptly, since the on-time of the first switching unit 160 in the step-down circuit is fixed, the change in the current of the charging / discharging unit 180 depends on the frequency at which the drive circuit 230 turns on the first switching unit 160. As the frequency at which the drive circuit 230 turns on the first switching unit 160 increases, the duty cycle of the buck circuit increases, and the current of the charging and discharging unit 180 increases. The faster the frequency at which the drive circuit 230 turns on the first switching unit 160 changes, the faster the current of the charging and discharging unit 180 changes, and the faster the output voltage of the buck circuit can reach a stable state, resulting in a shorter dynamic response time for the buck circuit.

[0092] In some embodiments, please refer to Figure 9 as well as Figure 16 , Figure 16 This is a waveform diagram of the segmented timing circuit in an embodiment of the present invention. In this embodiment, the ratio of the third capacitor 2221 to the fourth capacitor 2222 is changed to 3 compared to the previous embodiment.

[0093] The segmented timing circuit 222 is used to time the step-down circuit and determine the time of the first time period. When the first time period is in progress, the segmented timing circuit 222 prevents the second capacitor 2213 from charging and discharging; when the first time period is not in progress, the segmented timing circuit 222 allows the second capacitor 2213 to charge and discharge.

[0094] The segmented timing circuit 222 is mainly used to generate V. M2_HALF The signal controls the timing of the first segment of the segmented ramp generation circuit 221. The segmented timing circuit 222 consists of two capacitor charging branches, a voltage buffer, a comparator 231, and a NAND gate. The currents in the two capacitor charging branches are equal, both being I. p1 The capacitance of the third capacitor 2221 is three times that of the fourth capacitor 2222.

[0095]

[0096] Where I is the charging current of the third capacitor 2221 and the fourth capacitor 2222, t is the charging time of the third capacitor 2221 and the fourth capacitor 2222, C is the capacitance of the third capacitor 2221 and the fourth capacitor 2222, and V is the capacitor voltage of the third capacitor 2221 and the fourth capacitor 2222.

[0097] From the above formula, it can be seen that, within the same charging time, V CH2 Approximately V CH1 Three times that of V CH1 With V CH2 These are the voltages of the third capacitor 2221 and the fourth capacitor 2222 after they have been charged within the same time period, respectively. RST For V M2 That is, the reverse signal of the voltage of the second switching unit 170 serves as the reset signal for the fourth capacitor 2222 and the third capacitor 2221, while simultaneously controlling the discharge of the third capacitor 2221 and the fourth capacitor 2222. During discharge, V is set. CH1 and V CH2 =0; in V M2 When the signal is high, T RST When the signal is low, the voltages of the third capacitor 2221 and the fourth capacitor 2222 are cleared to zero, and charging begins. C HOLD To maintain capacitance, at T SMP When disconnected, maintain V SMP Voltage. During the clearing and charging of the third capacitor 2221, T SMP Disconnect, V SMP Maintain the charging voltage of the third capacitor 2221 from the previous cycle.

[0098] During the operation of the segmented timing circuit 222, from the time the first switching unit 160 is turned on until it is turned off, the third capacitor 2221 and the fourth capacitor 2222 discharge until their voltages are zero, and the segmented timing circuit 222 allows the second capacitor 2213 to charge and discharge. When the first switching unit 160 is turned off until it is turned on, the third capacitor 2221 and the fourth capacitor 2222 are charged with the same current. The voltage of the fourth capacitor 2222 is compared with the maximum voltage of the third capacitor 2221 during the previous charging by the first switching unit 160. If the voltage of the fourth capacitor 2222 is greater than the maximum voltage of the third capacitor 2221 during the previous charging by the first switching unit 160, the segmented timing circuit 222 prohibits the second capacitor 2213 from charging and discharging; otherwise, the segmented timing circuit 222 allows the second capacitor 2213 to charge and discharge.

[0099] Since the capacitance of the third capacitor 2221 is three times that of the fourth capacitor 2222, V will be at the end of charging. CH2 Approximately V CH1 Three times that. V SMP The voltage remains the same as the charging voltage of the third capacitor 2221 from the previous cycle. Therefore, when the first time period is one-third of the sum of the first and second time periods, the output of comparator 231 flips.

[0100] This application discloses a step-down circuit that controls the switching states of a first switching unit 160 and a second switching unit 170 via a control stage 200. A first voltage signal generation circuit 210 compares the output voltage of the power stage 100 with a first reference voltage and outputs a first voltage signal; a second voltage signal generation circuit 220 outputs a second voltage signal; and a drive circuit 230 turns on the first switching unit 160 when the second voltage signal is less than the first voltage signal. When the first switching unit 160 is on, the second voltage signal rises at a first speed; when the first switching unit 160 is off, the second voltage signal remains constant in a first time period and decreases at a second speed in a second time period. During dynamic response, the rise amplitude of the second voltage signal is smaller, allowing the first voltage signal to rise to equal it more quickly, thereby increasing the frequency at which the drive circuit 230 turns on the first switching unit 160. When the current at the output terminal 150 changes abruptly, since the on-time of the first switching unit 160 in the step-down circuit is fixed, the change in the current of the charging / discharging unit 180 depends on the frequency at which the drive circuit 230 turns on the first switching unit 160. As the frequency at which the drive circuit 230 turns on the first switching unit 160 increases, the duty cycle of the buck circuit increases, and the current of the charging and discharging unit 180 increases. The faster the frequency at which the drive circuit 230 turns on the first switching unit 160 changes, the faster the current of the charging and discharging unit 180 changes, and the faster the output voltage of the buck circuit can reach a stable state, resulting in a shorter dynamic response time for the buck circuit.

[0101] In some embodiments, please refer to Figure 9 as well as Figure 17 , Figure 17 This is a waveform diagram of the segmented timing circuit 222 in an embodiment of the present invention. In this embodiment, the ratio of the third capacitor 2221 to the fourth capacitor 2222 is changed to 4 / 3, based on the previous embodiment.

[0102] The segmented timing circuit 222 is used to time the step-down circuit and determine the time of the first time period. When the first time period is in progress, the segmented timing circuit 222 prevents the second capacitor 2213 from charging and discharging; when the first time period is not in progress, the segmented timing circuit 222 allows the second capacitor 2213 to charge and discharge.

[0103] The segmented timing circuit 222 is mainly used to generate V.M2_HALF The signal controls the timing of the first segment of the segmented ramp generation circuit 221. The segmented timing circuit 222 consists of two capacitor charging branches, a voltage buffer, a comparator 231, and a NAND gate. The currents in the two capacitor charging branches are equal, both being I. p1 The capacitance of the third capacitor 2221 is 4 / 3 times the capacitance of the fourth capacitor 2222.

[0104]

[0105] Where I is the charging current of the third capacitor 2221 and the fourth capacitor 2222, t is the charging time of the third capacitor 2221 and the fourth capacitor 2222, C is the capacitance of the third capacitor 2221 and the fourth capacitor 2222, and V is the capacitor voltage of the third capacitor 2221 and the fourth capacitor 2222.

[0106] From the above formula, it can be seen that, within the same charging time, V CH2 Approximately V CH1 4 / 3 times, V CH1 With V CH2 These are the voltages of the third capacitor 2221 and the fourth capacitor 2222 after they have been charged within the same time period, respectively. RST For V M2 That is, the reverse signal of the voltage of the second switching unit 170 serves as the reset signal for the fourth capacitor 2222 and the third capacitor 2221, while simultaneously controlling the discharge of the third capacitor 2221 and the fourth capacitor 2222. During discharge, V is set. CH1 and V CH2 =0; in V M2 When the signal is high, T RST When the signal is low, the voltages of the third capacitor 2221 and the fourth capacitor 2222 are cleared to zero, and charging begins. C HOLD To maintain capacitance, at T SMP When disconnected, maintain V SMP Voltage. During the clearing and charging of the third capacitor 2221, T SMP Disconnect, V SMP Maintain the charging voltage of the third capacitor 2221 from the previous cycle.

[0107] During the operation of the segmented timing circuit 222, from the time the first switching unit 160 is turned on until it is turned off, the third capacitor 2221 and the fourth capacitor 2222 discharge until their voltages are zero, and the segmented timing circuit 222 allows the second capacitor 2213 to charge and discharge. When the first switching unit 160 is turned off until it is turned on, the third capacitor 2221 and the fourth capacitor 2222 are charged with the same current. The voltage of the fourth capacitor 2222 is compared with the maximum voltage of the third capacitor 2221 during the previous charging by the first switching unit 160. If the voltage of the fourth capacitor 2222 is greater than the maximum voltage of the third capacitor 2221 during the previous charging by the first switching unit 160, the segmented timing circuit 222 prohibits the second capacitor 2213 from charging and discharging; otherwise, the segmented timing circuit 222 allows the second capacitor 2213 to charge and discharge.

[0108] Since the capacitance of the third capacitor 2221 is 4 / 3 times that of the fourth capacitor 2222, V will be at the end of charging. CH2 Approximately V CH1 Three times that. V SMP The voltage remains the same as the charging voltage of the third capacitor 2221 from the previous cycle. Therefore, when the first time period is four-thirds of the sum of the first and second time periods, the output of comparator 231 flips.

[0109] This application discloses a step-down circuit that controls the switching states of a first switching unit 160 and a second switching unit 170 via a control stage 200. A first voltage signal generation circuit 210 compares the output voltage of the power stage 100 with a first reference voltage and outputs a first voltage signal; a second voltage signal generation circuit 220 outputs a second voltage signal; and a drive circuit 230 turns on the first switching unit 160 when the second voltage signal is less than the first voltage signal. When the first switching unit 160 is on, the second voltage signal rises at a first speed; when the first switching unit 160 is off, the second voltage signal remains constant in a first time period and decreases at a second speed in a second time period. During dynamic response, the rise amplitude of the second voltage signal is smaller, allowing the first voltage signal to rise to equal it more quickly, thereby increasing the frequency at which the drive circuit 230 turns on the first switching unit 160. When the current at the output terminal 150 changes abruptly, since the on-time of the first switching unit 160 in the step-down circuit is fixed, the change in the current of the charging / discharging unit 180 depends on the frequency at which the drive circuit 230 turns on the first switching unit 160. As the frequency at which the drive circuit 230 turns on the first switching unit 160 increases, the duty cycle of the buck circuit increases, and the current of the charging and discharging unit 180 increases. The faster the frequency at which the drive circuit 230 turns on the first switching unit 160 changes, the faster the current of the charging and discharging unit 180 changes, and the faster the output voltage of the buck circuit can reach a stable state, resulting in a shorter dynamic response time for the buck circuit.

[0110] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. A voltage reduction circuit, characterized by comprising: The application relates to a power supply circuit, comprising: a power stage, comprising a first control terminal, a second control terminal, a first node, an input terminal, an output terminal, a first switch unit, a second switch unit and a charge-discharge unit, the first switch unit is used for being turned on to turn on the input terminal and the first node when a signal of the first control terminal is effective, the input terminal is used for receiving an input voltage; the second switch unit is used for being turned on to turn on the first node and a ground terminal when a signal of the second control terminal is effective; and the charge-discharge unit is used for charging or discharging the output terminal through a voltage of the first node to form an output voltage; a control stage, used for controlling the switching state of the first switch unit and the second switch unit, and comprising: a first voltage signal generating circuit, used for comparing the output voltage of the power stage with a first reference voltage and outputting a first voltage signal, wherein the first voltage signal is used for reflecting the degree of deviation of the output voltage of the power stage from the first reference voltage; a second voltage signal generating circuit, used for outputting a second voltage signal; when the first switch unit is turned on, the second voltage signal rises at a first speed; when the first switch unit is turned off, the second voltage signal remains unchanged in a first time period and falls at a second speed in a second time period; and the first speed is smaller than the second speed; a driving circuit, used for controlling the switching state of the first switch unit and the second switch unit through the first control terminal and the second control terminal, and turning on the first switch unit when the second voltage signal is smaller than the first voltage signal.

2. The voltage reduction circuit of claim 1, wherein, The second voltage signal generating circuit comprises: a segmented ramp signal generating circuit, used for outputting a second voltage signal, and comprising a first load resistor, a second load resistor and a second capacitor; when the first switch unit is turned on, the input of the segmented ramp signal generating circuit is a first level, the first load resistor and the second load resistor are connected in series, current charges the second capacitor through the first load resistor and the second load resistor, the voltage of the second capacitor rises at the first speed, and the voltage of the second capacitor is outputted as the second voltage signal; when the first switch unit is turned off and in the first time period, the second capacitor does not charge and discharge, the voltage of the second capacitor remains unchanged, and the voltage of the second capacitor is outputted as the second voltage signal; when the first switch unit is turned off and in the second time period, the input of the segmented ramp signal generating circuit is a second level, the first load resistor is short-circuited, the second capacitor discharges through the second load resistor, the voltage of the second capacitor falls at the second speed, and the voltage of the second capacitor is outputted as the second voltage signal.

3. The voltage reduction circuit of claim 2, wherein, The second voltage signal generating circuit comprises: a segmented timing circuit, used for timing the voltage reduction circuit and determining the time when the first time period occurs; when in the first time period, the segmented timing circuit prohibits the second capacitor from charging and discharging; and when in the second time period, the segmented timing circuit allows the second capacitor to charge and discharge. When not in the first period, the segmented timing circuit allows the second capacitor to charge and discharge.

4. The voltage reduction circuit of claim 3, wherein, The segmented timing circuit includes a third capacitor and a fourth capacitor, and a ratio of the third capacitor to the fourth capacitor is m; When the first switch unit is on until the first switch unit is off, the third capacitor and the fourth capacitor discharge to a capacitor voltage of zero; the segmented timing circuit allows the second capacitor to charge and discharge; When the first switch unit is off until the first switch unit is on, the third capacitor and the fourth capacitor are charged with the same current; a voltage of the fourth capacitor is compared with a maximum voltage of the third capacitor at a previous time when the first switch unit is charged, if the voltage of the fourth capacitor is greater than the maximum voltage of the third capacitor at the previous time when the first switch unit is charged, the segmented timing circuit prohibits the second capacitor to charge and discharge; otherwise, the segmented timing circuit allows the second capacitor to charge and discharge.

5. The voltage reduction circuit of claim 4, wherein a ratio of a sum of the first period and the second period to the first period is m.

6. The voltage reduction circuit of claim 2, wherein an input of the segmented ramp generator circuit is a voltage of the first node; when the first switch unit is on, the input of the segmented ramp generator circuit is a first level; when the first switch unit is off, the input of the segmented ramp generator circuit is a second level. The driving circuit further comprises: a driving unit, configured to control switching states of the first switch unit and the second switch unit through the first control end and the second control end; 7. The voltage reduction circuit of claim 1, wherein, a delay circuit, configured to send an off signal to the driving unit after a fixed time when the second voltage signal is less than the first voltage signal, to inform the driving unit to turn off the first switch unit. The driving circuit further comprises: a comparator, configured to compare sizes of the first voltage signal and the second voltage signal; 8. The voltage reduction circuit of claim 7, wherein, when the second voltage signal is less than the first voltage signal, a turn-on signal is sent to the driving unit and the delay circuit, to inform the driving unit to turn on the first switch unit, and to inform the delay circuit to send an off signal to the driving unit after a fixed time, to inform the driving unit to turn off the first switch unit.

9. The voltage reduction circuit of claim 1, wherein the first voltage signal generation circuit comprises an error amplifier, configured to take the output voltage of the power stage and the first reference voltage as inputs, and output an error signal, the error signal being used to reflect a degree of deviation of the output voltage of the power stage from the first reference voltage.

10. The voltage reduction circuit of claim 9, wherein the first voltage signal generation circuit comprises a compensation circuit, configured to take the error signal as an input, to compensate for oscillation of the error signal, and to output the first voltage signal. ​ ​ ​ ​

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