A method for balancing capacitor voltage on dc side of inverter and computer program product

Abstract

This application discloses a method and computer program product for balancing the DC-side capacitor voltage of an inverter, belonging to the field of inverter technology. The method includes: establishing a spatial vector diagram in the αβ coordinate system based on the inverter topology; dividing the spatial vector diagram into six major sectors, each major sector into 12 minor sectors, or each major sector into 6 minor sectors, with each minor sector including a virtual vector; determining the target sector to which the reference vector to be synthesized belongs; initializing the clamping mode; verifying the initialized clamping mode according to the spatial vector modulation principle to determine the final clamping mode, thus obtaining the target switching sequence; establishing a set of action time equations; obtaining the action time of each vector based on the DC bus capacitor voltage balance constraint or natural balance; and generating a pulse width modulation signal to control the switches. This method can suppress DC-side capacitor voltage fluctuations and reduce inverter switching losses.

Description

Technical Field

[0001] This invention relates to the field of inverter technology, and in particular to a method for balancing the DC-side capacitor voltage of an inverter and a computer program product. Background Technology

[0002] To achieve higher capacity and reduce the size of copper busbars, the DC bus voltage of three-phase inverters in photovoltaic power generation and energy storage systems has gradually increased to 1500V or higher. Compared to three-level inverters, four-level tree-structure active neutral point clamped (TANPC) inverters exhibit lower voltage stress and lower current ripple without increasing the number of switching devices. Therefore, four-level TANPC inverters are more suitable for implementing 1500V inverters than three-level topologies. However, when the traditional Nearest Three Vectors (NTV) modulation scheme is applied to four-level inverters, it cannot achieve natural balance of the split capacitor voltage at high modulation index (MI). Unbalanced split capacitor voltages lead to AC output current distortion and increased voltage stress in the switching devices.

[0003] Existing technical literature 1, "K. Wang, Z. Zheng, and Y. Li, A Novel Carrier-Overlapped PWM Method for Four-Level Neutral-Point Clamped Converters, IEEE Trans. Power Electron., vol. 34, no. 1, pp. 7-12, Jan. 2019," proposes a carrier-overlapped pulse width modulation (COPWM) method, which overlaps carrier signals of different amplitudes to make the total current flowing through the intermediate capacitor zero during the switching cycle, and the voltage of the intermediate capacitor almost constant. However, the above method is a continuous pulse width modulation (CPWM) scheme, which leads to increased switching losses.

[0004] Existing technical document 2, "S. Busquets-Monge, J. Bordonau, and J. Rocabert, A Virtual-Vector Pulsewidth Modulation for the Four-Level Diode-Clamped DC–AC Converter, IEEE Trans. Power Electron., vol.23, no. 4, pp. 1964–1972, July 2008," proposes a Virtual Vector Pulse Width Modulation (VVPWM) method. By combining several basic vectors with a specific ratio, a virtual vector that has no effect on the capacitor current can be generated, which can reduce low-frequency split voltage fluctuations. However, this method introduces more switching cycles, significantly increasing switching losses.

[0005] Prior Art Document 3, "L. Zhang, Y. Zou, Y. Wu, X. Shen and Y. Xing, "Discontinuous Pulse-Width Modulation With Balanced DC-Link Capacitor Voltages for Three-Phase Four-Level Inverters," in IEEE Transactions on Power Electronics The paper, published in vol. 40, no. 10, pp. 15595-15606, Oct. 2025, proposes a four-level discontinuous pulse width modulation (4L-DPWM) method. By considering voltage balance constraints when calculating the vector action time, it achieves capacitor voltage balance and clamps the switching state of one phase arm within the switching cycle. However, this method cannot suppress voltage fluctuations between the upper and lower capacitors, and the number of switching cycles is significantly higher than that of three-level discontinuous modulation. Therefore, further optimization of this method is necessary and has room for improvement in both capacitor voltage fluctuation suppression and switching loss reduction.

[0006] Therefore, it is necessary to study a method for balancing the DC-side capacitor voltage of an inverter in order to further suppress DC-side capacitor voltage fluctuations or further reduce inverter switching losses. Summary of the Invention

[0007] The purpose of this application is to overcome the deficiencies of the prior art and provide a method for balancing the DC-side capacitor voltage of an inverter and a computer program product.

[0008] In a first aspect, this application provides a method for balancing the DC-side capacitor voltage of an inverter, comprising the following steps:

[0009] Based on the inverter topology, a spatial vector diagram is established in the αβ coordinate system. The spatial vector diagram is divided into six major sectors, each major sector is divided into 12 minor sectors, or each major sector is divided into 6 minor sectors. Each minor sector includes a virtual vector.

[0010] The target sector to which the reference vector to be synthesized belongs is determined, the clamping mode is initialized, and the initialized clamping mode is verified according to the principle of space vector modulation to determine the final clamping mode, thus obtaining the target switching sequence. The clamping modes include the first clamping mode, the second clamping mode, and the third clamping mode. When each large sector is divided into 12 small sectors, the first clamping mode or the second clamping mode is used. When each large sector is divided into 6 small sectors, each small sector includes a virtual vector, the third clamping mode is used.

[0011] Establish a set of action time equations, and solve the set of action time equations based on the DC bus capacitor voltage balance constraint or natural balance to obtain the action time of each vector in the target switching sequence.

[0012] Based on the target switching sequence and the duration of each vector, a pulse width modulation signal is generated to control the switching state.

[0013] Optionally, each large sector is divided into 6 smaller sectors. Each smaller sector includes a virtual vector, comprising:

[0014] The virtual vectors are 3V0, V30, 03V, 0V3, V03, and 30V, respectively.

[0015] Within the first large sector, the first small sector is the portion to the lower right of the line connecting 111 and 3V0 within the area enclosed by 332, 322, and 111. The second small sector is the portion to the upper left of the line connecting 111 and 3V0 within the area enclosed by 332, 322, and 111. The third small sector is the portion to the lower right of the line connecting 111 and 3V0 within the area enclosed by the lines connecting 332 and 322, 332 and 3V0, and 322 and 3V0. The fourth sub-sector is the area to the left of the line connecting 111 and 3V0 within the region enclosed by the lines connecting 332 and 322, 332 and 3V0, and 322 and 3V0. The fifth sub-sector is the region enclosed by the lines connecting 322 and 300, 322 and 3V0, and 300 and 3V0. The sixth sub-sector is the region enclosed by the lines connecting 332 and 330, 332 and 3V0, and 330 and 3V0.

[0016] In the second large sector, the first small sector is the portion to the left of the line connecting 111 and V30 within the area enclosed by 332, 232, and 111; the second small sector is the portion to the right of the line connecting 111 and V30 within the area enclosed by 332, 232, and 111; and the third small sector is the portion to the left of the line connecting 111 and V30 within the area enclosed by the lines connecting 332 and 232, 332 and V30, and 232 and V30. The fourth sub-sector is the area to the right of the line connecting 111 and V30 within the region enclosed by the lines connecting 332 and 232, 332 and V30, and 232 and V30. The fifth sub-sector is the region enclosed by the lines connecting 232 and 030, 232 and V30, and 030 and V30. The sixth sub-sector is the region enclosed by the lines connecting 332 and 330, 332 and V30, and 330 and V30.

[0017] In the third major sector, the first sub-sector is the portion to the upper right of the line connecting 111 and 03V within the area enclosed by 232, 233, and 111. The second sub-sector is the portion to the lower left of the line connecting 111 and 03V within the area enclosed by 232, 233, and 111. The third sub-sector is the portion to the right of the line connecting 111 and 03V within the area enclosed by the lines connecting 232 and 233, 232 and 03V, and 233 and 03V. The upper part, the fourth small sector is the area to the lower left of the line connecting 111 and 03V in the region surrounded by the lines connecting 232 and 233, 232 and 03V, and 233 and 03V; the fifth small sector is the area surrounded by the lines connecting 232 and 030, 232 and 03V, and 030 and 03V; the sixth small sector is the area surrounded by the lines connecting 233 and 033, 233 and 03V, and 033 and 03V.

[0018] In the fourth major sector, the first sub-sector is the portion to the lower right of the line connecting 111 and 0V3 within the area enclosed by 233, 223, and 111. The second sub-sector is the portion to the upper left of the line connecting 111 and 0V3 within the area enclosed by 233, 223, and 111. The third sub-sector is the portion to the right of the line connecting 111 and 0V3 within the area enclosed by the lines connecting 223 and 233, 223 and 0V3, and 233 and 0V3. The lower part, the fourth sub-sector is the area to the upper left of the line connecting 111 and 0V3 within the area enclosed by the lines connecting 223 and 233, 223 and 0V3, and 233 and 0V3; the fifth sub-sector is the area enclosed by the lines connecting 223 and 003, 223 and 0V3, and 003 and 0V3; the sixth sub-sector is the area enclosed by the lines connecting 233 and 033, 233 and 0V3, and 033 and 0V3.

[0019] In the fifth major sector, the first sub-sector is the portion of the area enclosed by 223, 323, and 111 that lies to the left of the line connecting 111 and V03. The second sub-sector is the portion of the area enclosed by 223, 323, and 111 that lies to the right of the line connecting 111 and V03. The third sub-sector is the portion of the area enclosed by the lines connecting 223 and 323, 223 and V03, and 323 and V03 that lies to the left of the line connecting 111 and V03. The fourth sub-sector is the area to the right of the line connecting 111 and V03 within the region enclosed by the lines connecting 223 and 323, 223 and V03, and 323 and V03. The fifth sub-sector is the region enclosed by the lines connecting 223 and 003, 223 and V03, and 003 and V03. The sixth sub-sector is the region enclosed by the lines connecting 323 and 303, 323 and V03, and 303 and V03.

[0020] In the sixth major sector, the first sub-sector is the portion to the upper right of the line connecting 111 and 30V within the area enclosed by 322, 323, and 111. The second sub-sector is the portion to the lower left of the line connecting 111 and 30V within the area enclosed by 322, 323, and 111. The third sub-sector is the portion to the right of the line connecting 111 and 30V within the area enclosed by the lines connecting 322 and 323, 322 and 30V, and 323 and 30V. The upper part, the fourth sub-sector is the area to the lower left of the line connecting 111 and 30V, which is surrounded by the lines connecting 322 and 323, 322 and 30V, and 323 and 30V. The fifth sub-sector is the area surrounded by the lines connecting 322 and 300, 322 and 30V, and 300 and 30V. The sixth sub-sector is the area surrounded by the lines connecting 323 and 303, 323 and 30V, and 303 and 30V.

[0021] Optionally, 3V0 is composed of 310 and 320, defined as ;

[0022] V30 consists of 130 and 230, and is defined as follows: ;

[0023] 03V is composed of 031 and 032, and is defined as follows: ;

[0024] 0V3 is composed of 013 and 023, and is defined as ;

[0025] V03 is composed of 103 and 203, and is defined as follows: ;

[0026] 30V is composed of 301 and 302, and is defined as follows: ;

[0027] in, and They represent the reference vectors to be synthesized. of α shaft and β Axial components.

[0028] Optionally, the target sector to which the reference vector to be synthesized belongs is determined, the clamping mode is initialized, and the initialized clamping mode is verified according to the principle of space vector modulation to determine the final clamping mode, thus obtaining the target switching sequence. The clamping modes include a first clamping mode, a second clamping mode, and a third clamping mode. When each large sector is divided into 12 small sectors, the first clamping mode or the second clamping mode is used. When each large sector is divided into 6 small sectors, and each small sector includes a virtual vector, the third clamping mode is used, including:

[0029] Determine the target sector to which the reference vector to be synthesized belongs;

[0030] When each large sector is divided into 12 small sectors, the clamping mode is initialized. The sign of the voltage difference between the upper and lower capacitors is determined. When the voltage difference between the upper and lower capacitors is greater than or equal to zero, the sign of the sum of the average values ​​of the two midpoint currents is determined. If the sum of the average values ​​of the two midpoint currents is less than or equal to zero, the first clamping mode is selected; otherwise, the second clamping mode is selected. When the voltage difference between the upper and lower capacitors is less than zero, the sign of the sum of the average values ​​of the two midpoint currents is determined. If the sum of the average values ​​of the two midpoint currents is greater than or equal to zero, the first clamping mode is selected; otherwise, the second clamping mode is selected. When each large sector is divided into 6 small sectors, and each small sector includes a virtual vector, the third clamping mode is used.

[0031] The target switch sequence is determined based on the selected clamping mode.

[0032] Optionally, when each large sector is divided into 12 smaller sectors, a set of action time equations is established. The action time equations are solved based on the DC bus capacitor voltage balance constraint to obtain the action time of each vector in the target switching sequence. The expression for the action time equations is:

[0033]

[0034] in, and They represent the basic vectors respectively. of α shaft and β Axial components, i =1, 2, 3, 4, 5; and These represent the coefficients corresponding to the DC bus capacitor voltage balance constraint; Represents the fundamental vector within the switching cycle. Duration of action; and They represent the reference vectors to be synthesized. of α shaft and β Axial components; The duration of one switching cycle.

[0035] Optionally, if each large sector is divided into 12 smaller sectors, and the reference vector to be synthesized... When located within the first sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is: ;

[0036] If the reference vector to be synthesized When located within the first sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is: ;

[0037] If the reference vector to be synthesized When located within the second sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is: ;

[0038] If the reference vector to be synthesized When located within the second sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is: ;

[0039] If the reference vector to be synthesized When located within the third sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is: ;

[0040] If the reference vector to be synthesized When located within the third sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is: ;

[0041] If the reference vector to be synthesized When located in the fourth sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is: ;

[0042] If the reference vector to be synthesized When located in the fourth sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is: ;

[0043] If the reference vector to be synthesized When located within the fifth sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is: ;

[0044] If the reference vector to be synthesized When located within the fifth sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is: ;

[0045] If the reference vector to be synthesized When located in the sixth sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is: ;

[0046] If the reference vector to be synthesized When located within the sixth sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is: ;

[0047] If the reference vector to be synthesized When located in the seventh sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is: ;

[0048] If the reference vector to be synthesized When located within the seventh sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is: ;

[0049] If the reference vector to be synthesized When located in the eighth sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is: ;

[0050] If the reference vector to be synthesized When located within the eighth sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is: ;

[0051] If the reference vector to be synthesized When located within the ninth sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is: ;

[0052] If the reference vector to be synthesized When located within the ninth sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is as follows: ;

[0053] If the reference vector to be synthesized When located within the tenth sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is: ;

[0054] If the reference vector to be synthesized When located within the tenth sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is: ;

[0055] If the reference vector to be synthesized When located within the eleventh sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is: ;

[0056] If the reference vector to be synthesized When located within the eleventh sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is: ;

[0057] If the reference vector to be synthesized When located within the twelfth sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is: ;

[0058] If the reference vector to be synthesized When located within the twelfth sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is: ;

[0059] in, Represents the fundamental vector within the switching cycle. Duration of action i =1, 2, 3, 4, 5.

[0060] Optionally, the system of equations governing the action time can be solved based on natural equilibrium, and the expression is:

[0061]

[0062] in, and Represent the basic vectors within the vector sequence. of α shaft and β Axial components, n =1, 2, 3; The duration of one switching cycle; Represents the fundamental vector within a switching cycle. Duration of action; and They represent the reference vectors to be synthesized. of α shaft and β Axial components.

[0063] Optionally, the target switching sequence consists of multiple voltage vectors arranged in a symmetrical or asymmetrical order, and the target switching sequence is configured such that at least one phase bridge arm is clamped in each switching cycle.

[0064] Secondly, this application also provides an inverter, including: an inverter module and a control module, wherein the inverter module is connected to the control module; the inverter module includes a DC bus capacitor unit, a switching unit, and a filtering unit, wherein the DC bus capacitor unit, the switching unit, and the filtering unit are sequentially connected and then connected between a DC power supply and an AC power supply;

[0065] The control module includes: one or more processors; a storage device for storing one or more programs; and when the one or more programs are executed by the one or more processors, the one or more processors implement the inverter DC-side capacitor voltage balancing method as described in any one aspect.

[0066] Thirdly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the inverter DC-side capacitor voltage balancing method as described in any one of the first aspects.

[0067] This application provides a method for balancing the DC-side capacitor voltage of an inverter and an inverter in general. It can suppress voltage fluctuations in the upper and lower capacitors while maintaining the balance of the intermediate capacitor voltage. Within a single switching cycle, the intermediate capacitor voltage is balanced by optimizing the on-state sequence and vector action time. A combination of clamping modes across multiple switching cycles effectively regulates the voltages of the upper and lower capacitors. It also allows for some fluctuations in the three DC-side capacitor voltages, achieving dynamic balance naturally within half a fundamental cycle and further reducing inverter switching losses. Utilizing the symmetry of the three-phase current and combining it with virtual space vectors, the DC-side split capacitor voltages of a three-phase four-level inverter achieve natural balance within half a fundamental cycle. Optimizing the vector sequence further reduces the number of switching operations. This method, by integrating two different space vector modulation architectures, achieves effective balancing and fluctuation suppression of the DC-side split capacitor voltages of the inverter and significantly reduces switching losses. Through mode coordination across multiple cycles, it significantly improves voltage balancing capability and system reliability.

[0068] To make the above-mentioned features and advantages of the invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0069] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0070] Figure 1 This is a topology diagram of a three-phase four-level tree-structured active neutral-point clamped inverter.

[0071] Figure 2 This is a flowchart of an inverter DC-side capacitor voltage balancing method provided in one embodiment of this application.

[0072] Figure 3 This is a spatial vector diagram of a three-phase four-level inverter and a schematic diagram showing the division of large and small sectors in a specific embodiment of this application.

[0073] Figure 4 This is a flowchart of step S2 in an inverter DC-side capacitor voltage balancing method provided in one embodiment of this application.

[0074] Figure 5 This is a steady-state operating waveform diagram of a specific embodiment of this application when the modulation ratio MI=0.67.

[0075] Figure 6 This is a steady-state operating waveform diagram of a specific embodiment of this application when the modulation ratio MI=0.34.

[0076] Figure 7 This is a spatial vector diagram of a three-phase four-level inverter and a schematic diagram showing the division of large and small sectors, as shown in another specific embodiment of this application.

[0077] Figure 8 This is a steady-state operating waveform diagram when the modulation ratio MI=0.67 in another specific embodiment of this application.

[0078] Figure 9 This is a steady-state operating waveform diagram when the modulation ratio MI=0.34 in another specific embodiment of this application. Detailed Implementation

[0079] To make the objectives and technical solutions of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the described embodiments of this application without creative effort are within the scope of protection of this application.

[0080] In one embodiment, this application provides an inverter, including an inverter module and a control module, wherein the inverter module is connected to the control module; the inverter module includes a DC bus capacitor unit, a switching unit, and a filtering unit, wherein the DC bus capacitor unit, the switching unit, and the filtering unit are sequentially connected to a DC power supply. U dc The control module includes: one or more processors; a storage device for storing one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors control the inverter module.

[0081] As an example, the inverter module may be a neutral-point clamped three-phase four-level inverter, including but not limited to diode-neutral-point clamped, neutral-point direct-connected, and active neutral-point clamped three-phase four-level inverters with a single DC bus.

[0082] The following section uses a three-phase four-level tree-structured active neutral point clamped inverter module as an example to introduce the technical solution of this application. Figure 1 This is a topology diagram of a three-phase four-level tree-structured active neutral-point clamped inverter, including a DC bus capacitor unit 101, a switching unit 102, and a filter unit 103. The DC bus capacitor unit 101, the switching unit 102, and the filter unit 103 are connected in sequence and then connected to a DC power supply. U dc Between it and the three-phase power grid 104.

[0083] As an example, a three-phase four-level tree-structured active neutral-point clamped inverter is connected to a three-phase power grid 104, which includes an A-phase AC power supply. u sA Phase B AC power supply u sB and C-phase AC power supply u sC .

[0084] For example, please refer to Figure 1 The DC bus capacitor unit 101 includes a first DC bus filter capacitor. C d1 Second DC bus filter capacitor C d2 Third DC bus filter capacitor C d3 DC power supply U dc The first terminal and the first DC bus filter capacitor C d1The first end is connected to the two ends of the three points on the DC side respectively; the first DC bus filter capacitor C d1 The second terminal and the second DC bus filter capacitor C d2 The first end is connected to the two ends of the DC side; the second DC bus filter capacitor C d2 The second terminal and the third DC bus filter capacitor C d3 The first terminal is connected to both ends of point 1 on the DC side; the third DC bus filter capacitor C d3 The second terminal is connected to the DC power supply. U dc The second end is connected to both ends of the DC side 0 point; O is the virtual midpoint of the DC side, and the voltage between O and the DC side 0 point is half of the DC power supply voltage.

[0085] Optionally, DC power supply U dc The first terminal is the positive terminal, DC power supply. U dc The second end is the negative electrode.

[0086] Optionally, the first DC bus filter capacitor C d1 Second DC bus filter capacitor C d2 Third DC bus filter capacitor C d3 The first terminal is the positive terminal, and the first DC bus filter capacitor is... C d1 Second DC bus filter capacitor C d2 Third DC bus filter capacitor C d3 The second end is the negative electrode.

[0087] As an example, N 1. N 2 is the midpoint. i N1 and i N2 The midpoint of the outflow are respectively N 1 and N The current of 2 can be determined based on the inductor current collected by the current sensor and the switch status.

[0088] As an example, please continue reading Figure 1 The switching unit 102 includes a first power switching transistor. S 1. Second power switching transistor S 2. Third power switching transistor S3. Fourth power switching transistor S 4. Fifth power switching transistor S 5. Sixth power switching transistor S 6. Seventh power switching transistor S 7. Eighth power switching transistor S 8. Ninth power switching transistor S 9. Tenth power switching transistor S 10 Eleventh power switching transistor S 11 12th power switching transistor S 12 Thirteenth power switching transistor S 13 Fourteenth power switching transistor S 14 The fifteenth power switching transistor S 15 Sixteenth power switching transistor S 16 Seventeenth power switching transistor S 17 and the eighteenth power switching transistor S 18 The first power switch S 1 to 6 power switching transistors S The 6 connections form phase A bridge arm; the seventh power switch transistor S 7 to 12 power switching transistors S 12 The connection forms phase B of the bridge arm; the thirteenth power switch transistor. S 13 Up to the eighteenth power switching transistor S 18 The connection forms the C-phase bridge arm.

[0089] It is important to note that Figure 1 The first power switch in S 1 to the eighteenth power switching transistor S 18 This invention is not limited to any other switching element with control circuit conduction function, including but not limited to MOSFETs, IGBTs, etc.

[0090] In this specific embodiment, the first power switch transistor S 1 to the eighteenth power switching transistor S 18 MOSFETs are used. In the A-phase bridge arm, the first power switch... S The first terminal of 1 is connected to a DC power supply. U dc The first terminal and the first DC bus filter capacitor Cd1 The first terminal, the first power switch transistor S The second terminal of 1 is connected to the second power switch. S 2's first terminal; second power switch transistor S The second terminal of 2 is connected to the first DC bus filter capacitor. C d1 The second terminal; the third power switch transistor S The first terminal of 3 is connected to the third DC bus filter capacitor. C d3 The first terminal, the third power switch S The second terminal of 3 is connected to the fourth power switch. S The first terminal of 4; the fourth power switch transistor S The second terminal of 4 is connected to a DC power supply. U dc The second terminal and the third DC bus filter capacitor C d3 The second terminal; the fifth power switch transistor S The first terminal of 5 is connected to the first power switch transistor. S Terminal 1, fifth power switch S The second terminal of 5 is connected to the sixth power switch. S Terminal 6, the sixth power switch S The second terminal of 6 is connected to the fourth power switch. S 4's first terminal; fifth power switch transistor S 5 and the sixth power switch S The connection point of 6 is the output point A of phase A bridge arm.

[0091] In the B-phase bridge arm, the seventh power switch transistor S The first terminal of 7 is connected to a DC power supply. U dc The first terminal and the first DC bus filter capacitor C d1 The first terminal, the seventh power switch S The second terminal of 7 is connected to the eighth power switch. S The first terminal of 8; the eighth power switch transistor S The second terminal of 8 is connected to the first DC bus filter capacitor. C d1 The second terminal; the ninth power switch transistor S The first terminal of 9 is connected to the third DC bus filter capacitor. C d3 The first terminal, the ninth power switch S The second terminal of 9 is connected to the tenth power switch. S 10 The first terminal; the tenth power switch transistor S10 The second end is connected to a DC power supply. U dc The second terminal and the third DC bus filter capacitor C d3 The second terminal; the eleventh power switch transistor S 11 The first terminal is connected to the seventh power switch. S Terminal 7, eleventh power switch S 11 The second terminal is connected to the twelfth power switch. S 12 The first terminal, the twelfth power switch S 12 The second terminal is connected to the tenth power switch. S 10 The first terminal; the eleventh power switch transistor S 11 With the twelfth power switch S 12 The connection point is the output point B of phase B bridge arm.

[0092] In the C-phase bridge arm, the thirteenth power switch transistor S 13 The first end is connected to a DC power supply. U dc The first terminal and the first DC bus filter capacitor C d1 The first terminal, the thirteenth power switch S 13 The second terminal is connected to the fourteenth power switch. S 14 The first terminal; the fourteenth power switch transistor S 14 The second end is connected to the first DC bus filter capacitor. C d1 The second terminal; the fifteenth power switch transistor S 15 The first end is connected to the third DC bus filter capacitor. C d3 The first terminal, the fifteenth power switch transistor S 15 The second terminal is connected to the sixteenth power switch. S 16 The first terminal; the sixteenth power switch transistor S 16 The second end is connected to a DC power supply. U dc The second terminal and the third DC bus filter capacitor C d3 The second terminal; the seventeenth power switch transistorS 17 The first terminal is connected to the thirteenth power switch. S 13 The second terminal, the seventeenth power switch transistor S 17 The second terminal is connected to the eighteenth power switch. S 18 The first terminal, the eighteenth power switch transistor S 18 The second terminal is connected to the sixteenth power switch. S 16 The first terminal; the seventeenth power switch transistor S 17 With the eighteenth power switch S 18 The connection point is the output point C of phase C bridge arm.

[0093] Optionally, the first power switch transistor S 1 to the eighteenth power switching transistor S 18 The first terminal is the drain, and the first power switch transistor S 1 to the eighteenth power switching transistor S 18 The second end is the source pole.

[0094] As an example, please continue reading Figure 1 The filter unit 103 includes an A-phase filter inductor. L fa B-phase filter inductor L fb C-phase filter inductor L fc Phase A filter capacitor C fa Phase B filter capacitor C fb and C-phase filter capacitor C fc The A-phase filter inductor L fa The first terminal is connected to the output point A of phase A bridge arm, and the phase A filter inductor... L fa The second terminal is connected to the A-phase filter capacitor. C fa The first terminal is connected to phase A AC power supply u sA The first end; the B-phase filter inductor L fb The first terminal is connected to the output point B of phase B bridge arm, and the phase B filter inductor... L fb The second terminal is connected to the B-phase filter capacitor.C fb The first terminal is connected to the B-phase AC power supply. u sB The first end; the C-phase filter inductor L fc The first terminal is connected to the output point C of the C-phase bridge arm, and the C-phase filter inductor... L fc The second terminal is connected to the C-phase filter capacitor. C fc The first terminal and the C-phase AC power supply u sC The first terminal; the A-phase filter capacitor C fa The second terminal, phase B filter capacitor C fb The second terminal and the C-phase filter capacitor C fc The second end is connected to form a star-connected three-phase filter capacitor; the A-phase AC power supply u sA The second terminal, phase B AC power supply u sB The second terminal, and the C-phase AC power supply u sC The second end is connected to form a star-connected three-phase power grid, with the connection point being n.

[0095] As an example, the current flows through the A-phase filter inductor L fa The current is i La The current flows through the B-phase filter inductor L fb The current is i Lb The current flows through the C-phase filter inductor L fc The current is i Lc . i La , i Lb , i Lc This represents the three-phase inductor current.

[0096] As an example, the output current of phase A is i a The output current of phase B is i b The output current of phase C is i c .

[0097] Please see Figure 2This application also provides a method for balancing the DC-side capacitor voltage of an inverter, applied to the control module in the inverter, for controlling the inverter module, including the following steps: steps S1 to S4.

[0098] Step S1: Based on the inverter topology, establish a spatial vector map in the αβ coordinate system, divide the spatial vector map into six major sectors, each major sector into 12 minor sectors, or each major sector into 6 minor sectors, each minor sector including a virtual vector.

[0099] Step S2: Determine the target sector to which the reference vector to be synthesized belongs, initialize the clamping mode, verify the initialized clamping mode according to the principle of space vector modulation, determine the final clamping mode, and obtain the target switch sequence; the clamping mode includes the first clamping mode, the second clamping mode, and the third clamping mode. When each large sector is divided into 12 small sectors, the first clamping mode or the second clamping mode is used. When each large sector is divided into 6 small sectors, each small sector includes a virtual vector, the third clamping mode is used.

[0100] Step S3: Establish a set of action time equations, and solve the set of action time equations according to the DC bus capacitor voltage balance constraint or natural balance to obtain the action time of each vector in the target switching sequence.

[0101] Step S4: Generate a pulse width modulation signal based on the target switch sequence and the duration of each vector to control the switch state.

[0102] In the inverter DC-side capacitor voltage balancing method of this application, the sector is divided into multiple layers by establishing a refined αβ coordinate system spatial vector diagram, and three selectable clamping modes are combined for adaptive selection, realizing flexible optimization and precise control of the modulation process. It can maintain the consistency and efficiency of the switching sequence under complex operating conditions. By establishing a set of action time equations and introducing DC bus capacitor voltage balance constraints for solution, the action time of each vector can be directly and actively adjusted during vector synthesis, realizing natural or forced balance of the two DC-side capacitor voltages. This effectively suppresses the voltage imbalance problem caused by capacitor parameter differences or load fluctuations, which not only enhances the reliability and stability of the system, but also reduces capacitor stress and common-mode interference.

[0103] As an example, X Phase bridge arm output point X With DC side virtual midpoint O There are four switching states: 3, 2, 1, and 0. X express A , B or C When the switch state is 3, the bridge arm output point XThe bridge arm output voltage is connected to three points on the DC side via a power switch. When the switch state is 2, the bridge arm output point X The bridge arm output voltage is connected to point 2 on the DC side via a power switch. When the switch state is 1, the bridge arm output point X The bridge arm output voltage is connected to point 1 on the DC side via a power switch. When the switch state is 0, the bridge arm output point X The bridge arm output voltage is connected to the DC side 0 point via a power switch. Therefore, a three-phase four-level vector space exists. The three-phase bridge arm voltage combinations constitute 64 basic vectors in the αβ coordinate system. The relationship between the bridge arm output voltage and the switching state is shown in the following equation:

[0104]

[0105] in, for X Phase bridge arm output voltage, It is a DC power supply.

[0106] As an example, the 64 basic vectors are 333, 222, 111, 000, 322, 211, 100, 311, 200, 300, 321, 210, 310, 320, 332, 221, 110, 331, 220, 330, 231, 120, 230, 130, 232, 121, 010, 131, 020, 030, 132, 021, 031, 032, 233, 122, 011. 133, 022, 033, 123, 012, 023, 013, 223, 112, 001, 113, 002, 003, 213, 102, 103, 203, 323, 212, 101, 313, 202, 303, 312, 201, 302, 301, where 3 indicates that the bridge arm is in the on / off state 3, 2 indicates that the bridge arm is in the on / off state 2, 1 indicates that the bridge arm is in the on / off state 1, and 0 indicates that the bridge arm is in the on / off state 0.

[0107] In one specific embodiment, step S1 involves establishing a spatial vector diagram in the αβ coordinate system based on the three-phase four-level inverter topology, dividing the spatial vector diagram into six major sectors, and each major sector into 12 minor sectors, such as... Figure 3As shown. The six major sectors include Major Sector I, Major Sector II, Major Sector III, Major Sector IV, Major Sector V, and Major Sector VI. Each major sector has 12 sub-sectors: Sub-sector 1, Sub-sector 2, Sub-sector 3, Sub-sector 4, Sub-sector 5, Sub-sector 6, Sub-sector 7, Sub-sector 8, Sub-sector 9, Sub-sector 10, Sub-sector 11, and Sub-sector 12. Among them, V ref The reference vector to be synthesized. θ for V ref The angle between the α axis and the α axis.

[0108] As an example, active current PI regulators and reactive current PI regulators are used to generate d-axis control components based on the input signal. u d and q-axis control components u q Then, the dq / αβ converter transforms it into control components in the αβ coordinate system. u α and u β , and then u α and u β The reference vector to be synthesized is obtained by performing synthesis. V ref The expression is: .

[0109] For example, please refer to Figure 3 The first major sector I is the area surrounded by 333, 300, and 330; the second major sector II is the area surrounded by 333, 330, and 030; the third major sector III is the area surrounded by 333, 030, and 033; the fourth major sector IV is the area surrounded by 333, 033, and 003; the fifth major sector V is the area surrounded by 333, 003, and 303; and the sixth major sector VI is the area surrounded by 333, 303, and 300.

[0110] As an example, in the first large sector I, the first small sector 1 is the portion of the area enclosed by the midpoints of the lines connecting 322 and 311, 110 and 220, and 000, located below the line connecting the midpoints of 000 and 300 and 330; the second small sector 2 is the portion of the area enclosed by the midpoints of the lines connecting 322 and 311, 110 and 220, and 000, located above the line connecting the midpoints of 000 and 300 and 330; the third small sector 3 is the portion of the area enclosed by the midpoints of the lines connecting 322 and 311, 110 and 220, and 300 and 330, located below the line connecting the midpoints of 000 and 300 and 330, and to the left of the line connecting 330 and 303; the fourth... Sector 4 is the area enclosed by the midpoints of the lines connecting 322 and 311, 110 and 220, and 300 and 330, located above the line connecting the midpoints of 000 and 300 and 330, and to the lower left of the line connecting 030 and 321; Sector 5 is the area enclosed by the midpoints of the lines connecting 322 and 311, 110 and 220, and 300 and 330, located below the line connecting the midpoints of 000 and 300 and 330, to the lower left of the line connecting 321 and 300, and to the right of the line connecting 330 and 303; Sector 6 is the area enclosed by the midpoints of the lines connecting 322 and 311, 110 and 220, and 300 and 330. The first sub-sector 7 is the portion of the region located above the line connecting the midpoints of lines 000, 300, and 330, and to the upper right of the line connecting 321 and 030, and to the left of the line connecting 330 and 303. The second sub-sector 7 is the portion of the region enclosed by the midpoints of the lines 322 and 311, 110 and 220, and 300 and 330, located below the line connecting the midpoints of the lines 000, 300, and 330, and to the upper right of the line connecting 321 and 300. The third sub-sector 8 is the portion of the region enclosed by the midpoints of the lines 322 and 311, 110 and 220, and 300 and 330, located above the line connecting the midpoints of the lines 000, 300, and 330, and to the right of the line connecting 321 and 330. The ninth sub-sector 9 is the lower left portion of the area enclosed by the midpoints of the lines connecting 322 and 311, and the midpoints of the lines connecting 300, 300, and 330, located to the left of the line connecting 321 and 330; the tenth sub-sector 10 is the portion of the area enclosed by the midpoints of the lines connecting 110 and 220, and the midpoints of the lines connecting 330, 300, and 330, located to the left of the line connecting 321 and 330; the eleventh sub-sector 11 is the portion of the area enclosed by the midpoints of the lines connecting 322 and 311, and the midpoints of the lines connecting 300, 300, and 330, located to the upper right of the line connecting 321 and 300; the twelfth sub-sector 12 is the portion of the area enclosed by the midpoints of the lines connecting 110 and 220, and the midpoints of the lines connecting 330, 300, and 330, located to the right of the line connecting 321 and 330.

[0111] As an example, in the second large sector II, the first small sector 1 is the portion of the area enclosed by the midpoints of the lines connecting 232 and 131, the midpoints of the lines connecting 221 and 220, and 000, located to the left of the line connecting the midpoints of 000 and 030 and 330; the second small sector 2 is the portion of the area enclosed by the midpoints of the lines connecting 232 and 131, the midpoints of the lines connecting 221 and 220, and 000, located to the right of the line connecting the midpoints of 000 and 030 and 330; the third small sector 3 is the portion of the area enclosed by the midpoints of the lines connecting 232 and 131, the midpoints of the lines connecting 221 and 220, and the midpoints of the lines connecting 030 and 330, located to the left of the line connecting the midpoints of 000 and 030 and 330, and located to the lower right of the line connecting 231 and 021; the fourth... Sector 4 is the portion of the area enclosed by the midpoints of the lines connecting 232 and 131, 221 and 220, and 030 and 330, located to the right of the line connecting the midpoints of 000 and 030 and 330, and to the lower left of the line connecting 231 and 210. Sector 5 is the portion of the area enclosed by the midpoints of the lines connecting 232 and 131, 221 and 220, and 030 and 330, located to the left of the line connecting the midpoints of 000 and 030 and 330, and to the lower left of the line connecting 231 and 030, and to the upper left of the line connecting 231 and 021. Sector 6 is the portion of the area enclosed by the midpoints of the lines connecting 232 and 131, 221 and 220, and 030 and 330. The first sub-sector is located to the right of the line connecting the midpoints of lines 000, 030, and 330, and to the lower right of the line connecting 231 and 330, and to the upper right of the line connecting 231 and 210. The second sub-sector is located to the left of the line connecting the midpoints of lines 000, 030, and 330, and to the upper right of the line connecting 231 and 030, within the region enclosed by the midpoints of the lines connecting 232 and 131, 221 and 220, and 030 and 330. The third sub-sector is located to the right of the line connecting the midpoints of the lines 000, 030, and 330, and to the upper left of the line connecting 231 and 330, within the region enclosed by the midpoints of the lines connecting 232 and 131, 221 and 220, and 030 and 330. The ninth sub-sector 9 is the lower left portion of the area enclosed by the midpoints of the lines connecting 232 and 131, and the midpoints of the lines connecting 030, 030, and 330; the tenth sub-sector 10 is the lower right portion of the area enclosed by the midpoints of the lines connecting 110 and 220, and the midpoints of the lines connecting 330, 030, and 330; the eleventh sub-sector 11 is the upper right portion of the area enclosed by the midpoints of the lines connecting 232 and 131, and the midpoints of the lines connecting 030, 030, and 330; the twelfth sub-sector 12 is the upper left portion of the area enclosed by the midpoints of the lines connecting 110 and 220, and the midpoints of the lines connecting 330, 030, and 330.

[0112] As an example, in the third major sector III, the first sub-sector 1 is the upper right portion of the line connecting the midpoints of the lines 232 and 131, 011 and 022, and 000 within the region enclosed by these points; the second sub-sector 2 is the lower left portion of the line connecting the midpoints of the lines 000 and 030 and 033 within the region enclosed by these points; the third sub-sector 3 is the upper right portion of the line connecting the midpoints of the lines 000 and 030 and 033 within the region enclosed by these points; The fourth sub-sector 4 is the portion of the area enclosed by the midpoints of the lines connecting 232 and 131, 011 and 022, and 030 and 033, located to the lower left of the line connecting the midpoints of 000 and 030 and 033, and to the right of the line connecting 132 and 123. The fifth sub-sector 5 is the portion of the area enclosed by the midpoints of the lines connecting 232 and 131, 011 and 022, and 030 and 033, located to the upper right of the line connecting the midpoints of 000 and 030 and 033, and to the right of the line connecting 132 and 030, and to the upper left of the line connecting 132 and 120. The sixth sub-sector 6 is the portion of the area enclosed by the midpoints of the lines connecting 232 and 131, 011 and 022, and 030 and 033. The first sub-sector is the portion of the area enclosed by the midpoints of the lines connecting 000, 030, and 033, located to the lower left of the line connecting 132 and 033, and to the left of the line connecting 132 and 123. The second sub-sector is the portion of the area enclosed by the midpoints of the lines connecting 232 and 131, 011 and 022, and 030 and 033, located to the upper right of the line connecting the midpoints of 000, 030, and 033, and to the left of the line connecting 132 and 030. The third sub-sector is the portion of the area enclosed by the midpoints of the lines connecting 232 and 131, 011 and 022, and 030 and 033, located to the lower left of the line connecting the midpoints of 000, 030, and 033, and to the left of the line connecting 132 and 033. The upper part; the ninth sub-sector 9 is the part to the right of the line connecting 132 and 030 within the area enclosed by the midpoints of the lines connecting 232 and 131, and the midpoints of the lines connecting 030, 030 and 033; the tenth sub-sector 10 is the part to the lower right of the line connecting 132 and 033 within the area enclosed by the midpoints of the lines connecting 011 and 022, and the midpoints of the lines connecting 033, 030 and 033; the eleventh sub-sector 11 is the part to the left of the line connecting 132 and 030 within the area enclosed by the midpoints of the lines connecting 232 and 131, and the midpoints of the lines connecting 030, 030 and 033; the twelfth sub-sector 12 is the part to the upper left of the line connecting 132 and 033 within the area enclosed by the midpoints of the lines connecting 011 and 022, and the midpoints of the lines connecting 033, 030 and 033.

[0113] As an example, in the fourth major sector IV, the first sub-sector 1 is the lower right portion of the line connecting the midpoints of the lines 223 and 113, 011 and 022, and 000 within the area enclosed by 000, located at the midpoint of the line connecting 000 and 003 and 033; the second sub-sector 2 is the upper left portion of the line connecting the midpoints of the lines 223 and 113, 011 and 022, and 000 within the area enclosed by 000, located at the midpoint of the line connecting 000 and 003 and 033; the third sub-sector 3 is the lower right portion of the line connecting the midpoints of the lines 223 and 113, 011 and 022, and 003 and 033 within the area enclosed by 223 and 113, 011 and 022, and 003 and 033, located at the lower right of the line connecting 000 and 003 and 033, and also located at the upper right of the line connecting 123 and 102 within the area enclosed by 123 and 102. The fourth sub-sector 4 is the portion of the area enclosed by the midpoints of the lines connecting 223 and 113, 011 and 022, and 003 and 033, located to the upper left of the line connecting the midpoints of 000 and 003 and 033, and to the right of the line connecting 123 and 132; the fifth sub-sector 5 is the portion of the area enclosed by the midpoints of the lines connecting 223 and 113, 011 and 022, and 003 and 033, located to the lower right of the line connecting the midpoints of 000 and 003 and 033, and to the right of the line connecting 123 and 003, and to the lower left of the line connecting 123 and 102; the sixth sub-sector 6 is the portion of the area enclosed by the midpoints of the lines connecting 223 and 113, 011 and 022, and 003 and 033. The first sub-sector is the portion of the area enclosed by the midpoints of the lines connecting 000, 003, and 033, located to the upper left of the line connecting 123 and 033, and to the left of the line connecting 123 and 132. The second sub-sector is the portion of the area enclosed by the midpoints of the lines connecting 223 and 113, 011 and 022, and 003 and 033, located to the lower right of the line connecting the midpoints of 000, 003, and 033, and to the left of the line connecting 123 and 003. The third sub-sector is the portion of the area enclosed by the midpoints of the lines connecting 223 and 113, 011 and 022, and 003 and 033, located to the lower right of the line connecting the midpoints of 000, 003, and 033, and to the left of the line connecting 123 and 033. The fourth sub-sector is the portion of the area enclosed by the midpoints of the lines connecting 223 and 113, 011 and 022, and 003 and 033, located to the upper left of the line connecting the midpoints of 000, 003, and 033, and to the left of the line connecting 123 and 033. The lower part; the ninth sub-sector 9 is the part to the right of the line connecting 123 and 003 within the area enclosed by the midpoints of the lines connecting 223 and 113, and the midpoints of the lines connecting 003, 003 and 033; the tenth sub-sector 10 is the part to the upper right of the line connecting 123 and 033 within the area enclosed by the midpoints of the lines connecting 011 and 022, and the midpoints of the lines connecting 033, 003 and 033; the eleventh sub-sector 11 is the part to the left of the line connecting 123 and 003 within the area enclosed by the midpoints of the lines connecting 223 and 113, and the midpoints of the lines connecting 003, 003 and 033; the twelfth sub-sector 12 is the part to the lower left of the line connecting 123 and 033 within the area enclosed by the midpoints of the lines connecting 011 and 022, and the midpoints of the lines connecting 033, 003 and 033.

[0114] As an example, in the fifth major sector V, the first sub-sector 1 is the portion of the area enclosed by the midpoints of the lines connecting 223 and 113, 101 and 202, and 000, located to the left of the line connecting the midpoints of 000, 003, and 303; the second sub-sector 2 is the portion of the area enclosed by the midpoints of the lines connecting 223 and 113, 101 and 202, and 000, located to the right of the line connecting the midpoints of 000, 003, and 303; the third sub-sector 3 is the portion of the area enclosed by the midpoints of the lines connecting 223 and 113, 101 and 202, and 003, located to the left of the line connecting the midpoints of 000, 003, and 303, and located to the upper right of the line connecting 213 and 012; the fourth... Sector 4 is the portion of the area enclosed by the midpoints of the lines connecting 223 and 113, 101 and 202, and 003 and 303, located to the right of the line connecting the midpoints of 000 and 003 and 303, and to the upper left of the line connecting 213 and 201. Sector 5 is the portion of the area enclosed by the midpoints of the lines connecting 223 and 113, 101 and 202, and 003 and 303, located to the left of the line connecting the midpoints of 000 and 003 and 303, and to the upper left of the line connecting 213 and 003, and to the lower left of the line connecting 213 and 012. Sector 6 is the portion of the area enclosed by the midpoints of the lines connecting 223 and 113, 101 and 202, and 003 and 303. The first sub-sector is located to the right of the line connecting the midpoints of lines 000, 003, and 303, and to the upper right of the line connecting 213 and 303, and to the lower right of the line connecting 213 and 201. The second sub-sector is located to the left of the line connecting the midpoints of lines 223 and 113, 101 and 202, and 003 and 303, and to the lower right of the line connecting 213 and 003. The third sub-sector is located to the right of the line connecting the midpoints of lines 000, 003, and 303, and to the lower right of the line connecting 213 and 003, within the region enclosed by the midpoints of the lines 223 and 113, 101 and 202, and 003 and 303. The fourth sub-sector is located to the lower left of the line connecting the midpoints of the lines 213 and 303, within the region enclosed by the midpoints of the lines 223 and 113, 101 and 202, and 003 and 303. The ninth sub-sector 9 is the portion located to the upper left of the line connecting 213 and 003 within the area enclosed by the midpoints of the lines connecting 223 and 113, and the midpoints of the lines connecting 003, 003, and 303; the tenth sub-sector 10 is the portion located to the upper right of the line connecting 213 and 303 within the area enclosed by the midpoints of the lines connecting 101 and 202, and the midpoints of the lines connecting 303, 003, and 303; the eleventh sub-sector 11 is the portion located to the lower right of the line connecting 213 and 003 within the area enclosed by the midpoints of the lines connecting 223 and 113, and the midpoints of the lines connecting 003, 003, and 303; the twelfth sub-sector 12 is the portion located to the lower left of the line connecting 213 and 303 within the area enclosed by the midpoints of the lines connecting 101 and 202, and the midpoints of the lines connecting 303, 003, and 303.

[0115] As an example, in the sixth major sector VI, the first sub-sector 1 is the portion of the area enclosed by the midpoints of the lines connecting 322 and 311, 101 and 202, and 000, located to the upper right of the line connecting the midpoints of 000 and 300 and 303; the second sub-sector 2 is the portion of the area enclosed by the midpoints of the lines connecting 322 and 311, 101 and 202, and 000, located to the lower left of the line connecting the midpoints of 000 and 300 and 303; the third sub-sector 3 is the portion of the area enclosed by the midpoints of the lines connecting 322 and 311, 101 and 202, and 300 and 303, located to the upper right of the line connecting the midpoints of 000 and 300 and 303, and to the left of the line connecting 312 and 321; the... The fourth sub-sector, 4, is the portion of the area enclosed by the midpoints of the lines connecting 322 and 311, 101 and 202, and 300 and 303, located to the lower left of the line connecting the midpoints of 000 and 300 and 303, and to the upper left of the line connecting 312 and 213. The fifth sub-sector, 5, is the portion of the area enclosed by the midpoints of the lines connecting 322 and 311, 101 and 202, and 300 and 303, located to the upper right of the line connecting the midpoints of 000 and 300 and 303, and to the upper left of the line connecting 312 and 300, and to the right of the line connecting 312 and 321. The sixth sub-sector, 6, is the portion of the area enclosed by the midpoints of the lines connecting 322 and 311, 101 and 202, and 300 and 303. The seventh sub-sector 7 is the portion of the area enclosed by the midpoints of the lines connecting 000, 300, and 303, located to the left of the line connecting 312 and 303, and to the lower right of the line connecting 312 and 213; the eighth sub-sector 8 is the portion of the area enclosed by the midpoints of the lines connecting 322 and 311, 101 and 202, and 300 and 303, located to the upper right of the line connecting the midpoints of the lines connecting 000, 300, and 303, and to the lower right of the line connecting 312 and 303; the ninth sub-sector 8 is the portion of the area enclosed by the midpoints of the lines connecting 322 and 311, 101 and 202, and 300 and 303, located to the lower left of the line connecting the midpoints of the lines connecting 000, 300, and 303, and to the lower right of the line connecting 312 and 303. The right part; the ninth sub-sector 9 is the part to the upper left of the line connecting 312 and 300 within the area enclosed by the midpoints of the lines connecting 322 and 311, and the midpoints of the lines connecting 300, 300 and 303; the tenth sub-sector 10 is the part to the left of the line connecting 312 and 303 within the area enclosed by the midpoints of the lines connecting 101 and 202, and the midpoints of the lines connecting 303, 300 and 303; the eleventh sub-sector 11 is the part to the lower right of the line connecting 312 and 300 within the area enclosed by the midpoints of the lines connecting 322 and 311, and the midpoints of the lines connecting 300, 300 and 303; the twelfth sub-sector 12 is the part to the right of the line connecting 312 and 303 within the area enclosed by the midpoints of the lines connecting 101 and 202, and the midpoints of the lines connecting 303, 300 and 303.

[0116] Further, in step S2, the target sector to which the reference vector to be synthesized belongs is determined, the clamping mode is initialized, and the initialized clamping mode is verified according to the principle of space vector modulation to determine the final clamping mode, thereby obtaining the target switch sequence; the clamping mode includes a first clamping mode, a second clamping mode, and a third clamping mode. When each large sector is divided into 12 small sectors, the first clamping mode or the second clamping mode is used. When each large sector is divided into 6 small sectors, and each small sector includes a virtual vector, the third clamping mode is used.

[0117] For example, please refer to Figure 4 Step S2 may include the following steps: Step S21 to Step S23.

[0118] Step S21: Determine the target sector to which the reference vector to be synthesized belongs.

[0119] Step S22: When each large sector is divided into 12 small sectors, initialize the clamping mode, determine the sign of the voltage difference between the upper and lower capacitors. When the voltage difference between the upper and lower capacitors is greater than or equal to zero, determine the sign of the sum of the average values ​​of the two midpoint currents. If the sum of the average values ​​of the two midpoint currents is less than or equal to zero, select the first clamping mode; otherwise, select the second clamping mode. When the voltage difference between the upper and lower capacitors is less than zero, determine the sign of the sum of the average values ​​of the two midpoint currents. If the sum of the average values ​​of the two midpoint currents is greater than or equal to zero, select the first clamping mode; otherwise, select the second clamping mode. When each large sector is divided into 6 small sectors, and each small sector includes a virtual vector, the third clamping mode is used.

[0120] Step S23: Determine the target switch sequence based on the selected clamping mode.

[0121] The following is based on Figure 3 The following section details steps S21 to S23, using the sector division method shown as an example.

[0122] Specifically, in step S21, an active current PI regulator and a reactive current PI regulator can be used to generate a d-axis control component based on the input signal. u d and q-axis control components u q Then, the dq / αβ converter transforms it into control components in the αβ coordinate system. u α and u β , and then u α and u β The reference vector to be synthesized is obtained by performing synthesis. V ref .

[0123] Furthermore, the reference vector to be synthesized V ref The corresponding small sector is determined as the target sector, and the corresponding target switch sequence is obtained according to the different clamping modes.

[0124] As an example, the target switching sequence may consist of multiple voltage vectors arranged in a symmetrical or asymmetrical order. The target switching sequence is configured such that at least one phase bridge arm is clamped during each switching cycle to achieve discontinuous modulation.

[0125] For example, in this specific embodiment, multiple voltage vectors are arranged symmetrically to reduce harmonic content and reduce the number of switching operations.

[0126] As an example, the clamping modes may include a first clamping mode, a second clamping mode, and a third clamping mode. The first clamping mode is a high-level clamping, the second clamping mode is a low-level clamping, and the third clamping mode is a dynamic clamping. The first clamping mode and the second clamping mode are redundant clamping modes.

[0127] Table 1 shows the switching sequence for each sub-sector in the first major sector I. V s1 , V s2 , V s3 , V s4 , V s5 This represents five basic vectors, namely the current switching state combinations of the three-phase bridge arms A, B, and C, with the switching sequence relating to... V s5 Symmetry helps reduce harmonics; by selecting a combination of vectors capable of synthesizing the reference vector in the space vector plane according to the principle of space vector modulation, the average value of the current flowing through the upper and lower capacitors is zero or adjustable within the period. For example, when the reference vector to be synthesized... V ref When located in the first major sector I and the first minor sector 1, if the first clamping mode is used, the A-phase bridge arm is clamped to switch state 3, and the switching sequence is 311-321-322-332-333-332-322-321-311; if the second clamping mode is used, the C-phase bridge arm is clamped to switch state 0, and the switching sequence is 220-210-200-100-000-100-200-210-220. When the reference vector to be synthesized... V ref When the switch sequence is located in other smaller sectors of the first large sector, the method for determining the switch sequence and the reference vector to be synthesized are as follows: V refThe same applies when it is located in the first sub-sector of the first major sector; please refer to Table 1 for details, which will not be repeated here.

[0128] Table 1. Switching sequence of each sub-sector in the first major sector I.

[0129]

[0130] Table 2 shows the switching sequences for each sub-sector within the second major sector II. When the reference vector to be synthesized... V ref When located in the first sub-sector 1 of the second large sector II, if the first clamping mode is used, the B-phase bridge arm is clamped to switch state 3, and the switching sequence is 131-231-232-332-333-332-232-231-131; if the second clamping mode is used, the C-phase bridge arm is clamped to switch state 0, and the switching sequence is 220-120-020-010-000-010-020-120-220. When the reference vector to be synthesized... V ref When the switch sequence is located in other smaller sectors of the second largest sector, the method for determining the switch sequence and the reference vector to be synthesized are as follows: V ref The same applies when it is located in the first sub-sector of the second largest sector; please refer to Table 2 for details, which will not be repeated here.

[0131] Table 2. Switching sequence of each sub-sector in the second major sector II.

[0132]

[0133] Table 3 shows the switching sequences for each sub-sector within the third major sector (III). When the reference vector to be synthesized... V ref When located in the first sub-sector 1 of the third major sector III, if the first clamping mode is adopted, the B-phase bridge arm is clamped to switch state 3, and the switching sequence is 131-132-232-233-333-233-232-132-131; if the second clamping mode is adopted, the A-phase bridge arm is clamped to switch state 0, and the switching sequence is 022-021-020-010-000-010-020-021-022. When the reference vector to be synthesized... V ref When the switch sequence is located in other smaller sectors of the third largest sector, the method for determining the switch sequence and the reference vector to be synthesized are as follows: V ref The same applies when it is located in the first sub-sector of the third largest sector; please refer to Table 3 for details, which will not be repeated here.

[0134] Table 3 Switching sequences for each sub-sector in the third major sector III

[0135]

[0136] Table 4 shows the switching sequences for each sub-sector within the fourth major sector (Ⅳ). When the reference vector to be synthesized... V ref When located in the first sub-sector 1 of the fourth major sector IV, if the first clamping mode is adopted, the C-phase bridge arm is clamped to switch state 3, and the switching sequence is 113-123-223-233-333-233-223-123-113; if the second clamping mode is adopted, the A-phase bridge arm is clamped to switch state 0, and the switching sequence is 022-012-002-001-000-001-002-012-022. When the reference vector to be synthesized... V ref When the switch sequence is located in other smaller sectors of the fourth major sector, the method for determining the switch sequence and the reference vector to be synthesized are as follows: V ref The same applies when it is located in the first sub-sector of the fourth major sector; please refer to Table 4 for details, which will not be repeated here.

[0137] Table 4 Switching sequence of each sub-sector in the fourth major sector IV

[0138]

[0139] Table 5 shows the switching sequences for each sub-sector within the fifth major sector V. When the reference vector to be synthesized... V ref When located in the fifth major sector V, first minor sector 1, if the first clamping mode is used, the C-phase bridge arm is clamped to switch state 3, and the switching sequence is 113-213-223-323-333-323-223-213-113; if the second clamping mode is used, the B-phase bridge arm is clamped to switch state 0, and the switching sequence is 202-102-002-001-000-001-002-102-202. When the reference vector to be synthesized... V ref When the switch sequence is located in other smaller sectors of the fifth major sector, the method for determining the switch sequence and the reference vector to be synthesized are as follows: V ref The same applies when it is located in the first sub-sector of the fifth major sector; please refer to Table 5 for details, which will not be repeated here.

[0140] Table 5. Switching sequence of each sub-sector in the fifth major sector V

[0141]

[0142] Table 6 shows the switching sequences for each sub-sector within the sixth major sector VI. When the reference vector to be synthesized... V refWhen located in the first sub-sector 1 of the sixth major sector VI, if the first clamping mode is used, the A-phase bridge arm is clamped to switch state 3, and the switching sequence is 311-312-322-323-333-323-322-312-311; if the second clamping mode is used, the B-phase bridge arm is clamped to switch state 0, and the switching sequence is 202-201-200-100-000-100-200-201-202. When the reference vector to be synthesized... V ref When the switch sequence is located in other smaller sectors of the sixth major sector, the method for determining the switch sequence and the reference vector to be synthesized are as follows: V ref The same applies when it is located in the first sub-sector of the sixth major sector; please refer to Table 6 for details, which will not be repeated here.

[0143] Table 6. Switching sequence of each sub-sector in the sixth major sector VI

[0144]

[0145] Furthermore, in step S22, this specific embodiment divides each large sector into 12 small sectors and calculates the voltage difference between the upper and lower capacitors. The expression is ,in, For the third DC bus filter capacitor C d3 Voltage at both ends, The first DC bus filter capacitor C d1 Voltage at both ends.

[0146] Furthermore, the clamping mode is initialized to the first clamping mode, and the sum of the average currents flowing out of the two midpoints during the switching cycle in the first clamping mode is calculated. The expression is ,in, Midpoint of outflow N The current of 1, Midpoint of outflow N The current is 2. This is due to the sum of the average currents flowing from the two midpoints under the first and second clamping modes. The signs are opposite, and can be represented by the sum of the average values ​​of the currents flowing out of the two midpoints. The sign of the clamp determines the final clamping pattern.

[0147] Specifically, when the reference vector to be synthesized V ref When located in the first major sector I and the first minor sector I, the sum of the average currents at the two midpoints. If the voltage difference between the upper and lower capacitors Determine the sum of the average values ​​of the currents flowing out from the two midpoints. The sign of the current is determined by the sum of the average values ​​of the currents at the two midpoints. If the voltage difference between the upper and lower capacitors is within a certain range, the first clamping mode is selected; otherwise, the second clamping mode is selected. At that time, determine the sum of the average values ​​of the currents flowing out from the two midpoints. The sign of the current is determined by the sum of the average values ​​of the currents at the two midpoints. If the condition is met, the first clamping mode is used; otherwise, the second clamping mode is used.

[0148] When the reference vector to be synthesized V ref When the reference vector to be synthesized is located in other sectors, the method for determining the clamping mode is the same as when the reference vector to be synthesized is located in the first sub-sector of the first large sector. For details, please refer to the method when the reference vector to be synthesized is located in the first sub-sector of the first large sector. It will not be repeated here.

[0149] Furthermore, the switch sequence of the selected clamping mode is determined as the target switch sequence.

[0150] Furthermore, in step S3 of this specific embodiment, an action time equation set is established, and the action time equation set is solved according to the DC bus capacitor voltage balance constraint to obtain the action time of each vector in the target switching sequence.

[0151] Specifically, based on the principle of spatial vector synthesis, a system is established using five basic vectors from the target switch sequence. V s1 , V s2 , V s3 , V s4 , V s5 Duration of action The system of time equations for the unknown is expressed as follows:

[0152]

[0153] in, and They represent the basic vectors respectively. of α shaft and β Axial components, i =1, 2, 3, 4, 5; and These represent the coefficients corresponding to the DC bus capacitor voltage balance constraint, used to calculate the average impact of each basic vector on the voltage changes of the upper and lower split capacitors on the DC side during the action time. Represents the fundamental vector within the switching cycle. Duration of action; and They represent the reference vectors to be synthesized. of α shaft and β Axial components; The duration of one switching cycle.

[0154] Furthermore, based on the reference vector to be synthesized The location of the sector and the clamping mode determine the DC bus capacitor voltage balance constraint. When each large sector is divided into 12 smaller sectors, if the reference vector to be synthesized... When located within the first sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is:

[0155]

[0156] If the reference vector to be synthesized When located within the first sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is:

[0157]

[0158] If the reference vector to be synthesized When located within the second sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is:

[0159]

[0160] If the reference vector to be synthesized When located within the second sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is:

[0161]

[0162] If the reference vector to be synthesized When located within the third sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is:

[0163]

[0164] If the reference vector to be synthesized When located within the third sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is:

[0165]

[0166] If the reference vector to be synthesized When located in the fourth sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is:

[0167]

[0168] If the reference vector to be synthesized When located in the fourth sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is:

[0169]

[0170] If the reference vector to be synthesized When located within the fifth sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is:

[0171]

[0172] If the reference vector to be synthesized When located within the fifth sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is:

[0173]

[0174] If the reference vector to be synthesized When located in the sixth sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is:

[0175]

[0176] If the reference vector to be synthesized When located within the sixth sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is:

[0177]

[0178] If the reference vector to be synthesized When located in the seventh sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is:

[0179]

[0180] If the reference vector to be synthesized When located within the seventh sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is:

[0181]

[0182] If the reference vector to be synthesized When located in the eighth sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is:

[0183]

[0184] If the reference vector to be synthesized When located within the eighth sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is:

[0185]

[0186] If the reference vector to be synthesized When located within the ninth sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is:

[0187]

[0188] If the reference vector to be synthesized When located within the ninth sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is as follows:

[0189]

[0190] If the reference vector to be synthesized When located within the tenth sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is:

[0191]

[0192] If the reference vector to be synthesized When located within the tenth sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is:

[0193]

[0194] If the reference vector to be synthesized When located within the eleventh sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is:

[0195]

[0196] If the reference vector to be synthesized When located within the eleventh sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is:

[0197]

[0198] If the reference vector to be synthesized When located within the twelfth sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is:

[0199]

[0200] If the reference vector to be synthesized When located within the twelfth sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is:

[0201]

[0202] Furthermore, by substituting the DC bus capacitor voltage balance constraint into the set of action time equations, the action time of each vector in the target switching sequence can be obtained.

[0203] In step S4, please refer to Figure 2 In step S4, a pulse width modulation signal is generated based on the target switch sequence and the duration of each vector to control the switch state.

[0204] Specifically, based on the action order and action time of each vector in the target switching sequence determined in step S2, it is directly mapped to the on / off logic of the corresponding power switch in each phase arm of the three-phase four-level inverter. Through the PWM generator, based on the on / off logic and the target switching sequence, a discontinuous pulse width modulation drive signal containing the necessary dead time is generated, which ultimately controls the on / off of each switch in the three-phase four-level inverter. Thus, while outputting a multi-level voltage waveform, the periodic clamping of a specific phase arm is achieved, thereby reducing switching losses.

[0205] For example, to verify the effectiveness of the inverter DC-side capacitor voltage balancing method in this specific embodiment, the AC voltage standard of the three-phase four-level inverter can be set to 220V / 50Hz, the DC-side input voltage to 800V, the power to 6kVA, and the switching frequency to 60kHz. Figure 5 This is a waveform diagram of the steady-state operation experiment of this specific embodiment at a modulation ratio MI=0.67. Figure 6 This is a waveform diagram of the steady-state operation experiment of this specific embodiment at a modulation ratio MI=0.34, where, u dc2 This is the voltage of the second DC bus filter capacitor. u dc1 and u dc3 These are the voltages of the first DC bus filter capacitor and the third DC bus filter capacitor, respectively. u AO , uBO , u CO These are the voltages of the bridge arms in phases A, B, and C, respectively. i A The waveform below shows the output current of phase A, and the waveform below is the amplified voltage waveform of the bridge arm. It can be seen that... Figure 5 , Figure 6 Under the two different modulation ratios shown, the voltages of the three capacitors on the DC side remain balanced, and voltage fluctuations are significantly suppressed. Furthermore, as can be seen from the amplified waveform of the bridge arm voltage, in this specific embodiment, one phase bridge arm is clamped in each switching cycle, thus reducing switching losses, suppressing DC side capacitor voltage fluctuations, and achieving precise balance of the full capacitor voltage.

[0206] In another specific embodiment, step S1 involves establishing a spatial vector diagram in the αβ coordinate system based on the three-phase four-level inverter topology, dividing the spatial vector diagram into six major sectors, each major sector into six minor sectors, and each minor sector including a virtual vector, such as... Figure 7 As shown. The six major sectors include sector I, sector II, sector III, sector IV, sector V, and sector VI. Each major sector has six sub-sectors: sub-sector 1, sub-sector 2, sub-sector 3, sub-sector 4, sub-sector 5, and sub-sector 6. V ref The reference vector to be synthesized. θ for V ref The angle between the α axis and the α axis.

[0207] As an example, active current PI regulators and reactive current PI regulators are used to generate d-axis control components based on the input signal. u d and q-axis control components u q Then, the dq / αβ converter transforms it into control components in the αβ coordinate system. u α and u β , and then u α and u β The reference vector to be synthesized is obtained by performing synthesis. V ref The expression is: .

[0208] As an example, this embodiment uses only 32 basic vectors in the spatial vectors, and each sector includes a virtual vector, namely 3V0, V30, 03V, 0V3, V03 and 30V.

[0209] As an example, 3V0 is composed of 310 and 320, and is defined as follows:

[0210]

[0211] V30 consists of 130 and 230, and is defined as follows:

[0212]

[0213] 03V is composed of 031 and 032, and is defined as follows:

[0214]

[0215] 0V3 is composed of 013 and 023, and is defined as follows:

[0216]

[0217] V03 is composed of 103 and 203, and is defined as follows:

[0218]

[0219] 30V is composed of 301 and 302, and is defined as follows:

[0220]

[0221] in, and They represent the reference vectors to be synthesized. of α shaft and β Axial components.

[0222] For example, please refer to Figure 7 The first major sector I is the area surrounded by 111, 300, and 330; the second major sector II is the area surrounded by 111, 330, and 030; the third major sector III is the area surrounded by 111, 030, and 033; the fourth major sector IV is the area surrounded by 111, 033, and 003; the fifth major sector V is the area surrounded by 111, 003, and 303; and the sixth major sector VI is the area surrounded by 111, 303, and 300.

[0223] As an example, in the first large sector I, the first small sector 1 is the portion to the lower right of the line connecting 111 and 3V0 within the area enclosed by 332, 322, and 111; the second small sector 2 is the portion to the upper left of the line connecting 111 and 3V0 within the area enclosed by 332, 322, and 111; the third small sector 3 is the portion to the upper left of the line connecting 111 and 3V0 within the area enclosed by the lines connecting 332 and 322, 332 and 3V0, and 322 and 3V0. The lower right part; the fourth sub-sector 4 is the part located to the left of the line connecting 111 and 3V0 within the area enclosed by the lines connecting 332 and 322, 332 and 3V0, and 322 and 3V0; the fifth sub-sector 5 is the area enclosed by the lines connecting 322 and 300, 322 and 3V0, and 300 and 3V0; the sixth sub-sector 6 is the area enclosed by the lines connecting 332 and 330, 332 and 3V0, and 330 and 3V0.

[0224] As an example, in the second large sector II, the first small sector 1 is the portion of the area enclosed by 332, 232, and 111 located to the left of the line connecting 111 and V30; the second small sector 2 is the portion of the area enclosed by 332, 232, and 111 located to the right of the line connecting 111 and V30; the third small sector 3 is the portion of the area enclosed by the lines connecting 332 and 232, 332 and V30, and 232 and V30 located between the lines connecting 111 and V30. The part to the left; the fourth sub-sector 4 is the part to the right of the line connecting 111 and V30 within the area enclosed by the lines connecting 332 and 232, 332 and V30, and 232 and V30; the fifth sub-sector 5 is the area enclosed by the lines connecting 232 and 030, 232 and V30, and 030 and V30; the sixth sub-sector 6 is the area enclosed by the lines connecting 332 and 330, 332 and V30, and 330 and V30.

[0225] As an example, in the third major sector III, the first sub-sector 1 is the portion to the upper right of the line connecting 111 and 03V within the area enclosed by 232, 233, and 111; the second sub-sector 2 is the portion to the lower left of the line connecting 111 and 03V within the area enclosed by 232, 233, and 111; the third sub-sector 3 is the portion to the lower left of the line connecting 111 and 03V within the area enclosed by the lines connecting 232 and 233, 232 and 03V, and 233 and 03V. The upper right part of the line; the fourth sub-sector 4 is the part located to the lower left of the line connecting 111 and 03V within the area enclosed by the lines connecting 232 and 233, 232 and 03V, and 233 and 03V; the fifth sub-sector 5 is the area enclosed by the lines connecting 232 and 030, 232 and 03V, and 030 and 03V; the sixth sub-sector 6 is the area enclosed by the lines connecting 233 and 033, 233 and 03V, and 033 and 03V.

[0226] As an example, in the fourth major sector IV, the first sub-sector 1 is the portion to the lower right of the line connecting 111 and 0V3 within the area enclosed by 233, 223, and 111; the second sub-sector 2 is the portion to the upper left of the line connecting 111 and 0V3 within the area enclosed by 233, 223, and 111; the third sub-sector 3 is the portion to the upper left of the line connecting 111 and 0V3 within the area enclosed by the lines connecting 223 and 233, 223 and 0V3, and 233 and 0V3. The lower right part of the line; the fourth sub-sector 4 is the part located to the upper left of the line connecting 111 and 0V3 within the area enclosed by the lines connecting 223 and 233, 223 and 0V3, and 233 and 0V3; the fifth sub-sector 5 is the area enclosed by the lines connecting 223 and 003, 223 and 0V3, and 003 and 0V3; the sixth sub-sector 6 is the area enclosed by the lines connecting 233 and 033, 233 and 0V3, and 033 and 0V3.

[0227] As an example, in the fifth major sector V, the first sub-sector 1 is the portion of the area enclosed by 223, 323, and 111 located to the left of the line connecting 111 and V03; the second sub-sector 2 is the portion of the area enclosed by 223, 323, and 111 located to the right of the line connecting 111 and V03; the third sub-sector 3 is the portion of the area enclosed by the lines connecting 223 and 323, 223 and V03, and 323 and V03 located to the right of the line connecting 111 and V03. The portion to the left of the line; the fourth sub-sector 4 is the portion to the right of the line connecting 111 and V03 within the area enclosed by the lines connecting 223 and 323, 223 and V03, and 323 and V03; the fifth sub-sector 5 is the area enclosed by the lines connecting 223 and 003, 223 and V03, and 003 and V03; the sixth sub-sector 6 is the area enclosed by the lines connecting 323 and 303, 323 and V03, and 303 and V03.

[0228] As an example, in the sixth major sector VI, the first sub-sector 1 is the portion to the upper right of the line connecting 111 and 30V within the area enclosed by 322, 323, and 111; the second sub-sector 2 is the portion to the lower left of the line connecting 111 and 30V within the area enclosed by 322, 323, and 111; the third sub-sector 3 is the portion to the lower left of the line connecting 111 and 30V within the area enclosed by the lines connecting 322 and 323, 322 and 30V, and 323 and 30V. The upper right part of the line; the fourth sub-sector 4 is the area surrounded by the lines 322 and 323, 322 and 30V, and 323 and 30V, located to the lower left of the line 111 and 30V; the fifth sub-sector 5 is the area surrounded by the lines 322 and 300, 322 and 30V, and 300 and 30V; the sixth sub-sector 6 is the area surrounded by the lines 323 and 303, 323 and 30V, and 303 and 30V.

[0229] The following is based on Figure 7The following section uses the sector division method shown as an example to explain step S2 in detail.

[0230] Specifically, the reference vector to be synthesized V ref The small sector to which it belongs is determined as the target sector. Since each large sector is divided into 6 small sectors in this embodiment, and each small sector includes a virtual vector, the third clamping mode, i.e., dynamic clamping, is adopted. The target switch sequence is further determined according to the selected third clamping mode.

[0231] As an example, the target switching sequence may consist of multiple voltage vectors arranged in a symmetrical or asymmetrical order. The target switching sequence is configured such that at least one phase bridge arm is clamped during each switching cycle to achieve discontinuous modulation.

[0232] For example, in this specific embodiment, multiple voltage vectors are arranged symmetrically to reduce harmonic content and reduce the number of switching operations.

[0233] Table 7 shows the switch sequences for each small sector, where... V s1 , V s2 , V s3 This represents three fundamental vectors, namely the current combination of switching states of the three phase arms A, B, and C of the bridge, with the switching sequence relating to... V s3 Symmetry helps reduce harmonics; by selecting a combination of vectors capable of synthesizing the reference vector to be synthesized within the space vector plane according to the principle of space vector modulation, the average value of the current flowing through the upper and lower capacitors within the period is made zero or adjustable. Specifically, when the reference vector to be synthesized... V ref When located in the first major sector I and the first minor sector 1, the switching sequence is 211-221-222-221-211; when the reference vector to be synthesized... V ref When located in the first large sector I and the second small sector 2, the switching sequence is 111-211-221-211-111; when the reference vector to be synthesized... V ref When located in the first large sector I and the third small sector 3, the switching sequence is 3V0-211-221-211-3V0; when the reference vector to be synthesized... V ref When located in the first major sector I and the fourth minor sector 4, the switching sequence is 3V0-221-211-221-3V0; when the reference vector to be synthesized... V ref When located in the fifth sub-sector of the first major sector I, the switching sequence is 300-3V0-211-3V0-300; when the reference vector to be synthesized... Vref When located in the first major sector I and the sixth minor sector 6, the switching sequence is 330-3V0-221-3V0-330; when the reference vector to be synthesized... V ref When located in the first sub-sector 1 of the second largest sector II, the switch sequence is 010-110-111-110-010; when the reference vector to be synthesized... V ref When located in the second largest sector II and the second smallest sector 2, the switching sequence is 222-232-332-232-222; when the reference vector to be synthesized... V ref When located in the second largest sector II and the third smallest sector 3, the switching sequence is V30-232-332-232-V30; when the reference vector to be synthesized... V ref When located in the second largest sector II, fourth sub-sector 4, the switching sequence is V30-110-010-110-V30; when the reference vector to be synthesized... V ref When located in the fifth sub-sector of the second largest sector II, the switch sequence is 030-V30-232-V30-030; when the reference vector to be synthesized... V ref When located in the second largest sector II, sixth sub-sector 6, the switching sequence is 330-V30-110-V30-330; when the reference vector to be synthesized... V ref When located in the first sub-sector 1 of the third major sector III, the switch sequence is 010-011-111-011-010; when the reference vector to be synthesized... V ref When located in the second minor sector 2 of the third major sector III, the switching sequence is 222-232-233-232-222; when the reference vector to be synthesized... V ref When located in the third major sector III and the third minor sector 3, the switching sequence is 03V-232-233-232-03V; when the reference vector to be synthesized... V ref When located in the third major sector III and the fourth minor sector 4, the switching sequence is 03V-011-010-011-03V; when the reference vector to be synthesized... V ref When located in the third major sector III, fifth minor sector 5, the switching sequence is 030-03V-232-03V-030; when the reference vector to be synthesized... V ref When located in the third major sector III, sixth minor sector 6, the switching sequence is 033-03V-011-03V-033; when the reference vector to be synthesized... Vref When located in the first sub-sector 1 of the fourth major sector IV, the switching sequence is 112-122-222-122-112; when the reference vector to be synthesized... V ref When located in the fourth major sector IV, second minor sector 2, the switching sequence is 111-112-122-112-111; when the reference vector to be synthesized... V ref When located in the fourth major sector IV, third minor sector 3, the switching sequence is 0V3-112-122-112-0V3; when the reference vector to be synthesized... V ref When located in the fourth major sector IV and the fourth minor sector 4, the switching sequence is 0V3-122-112-122-0V3; when the reference vector to be synthesized... V ref When located in the fourth major sector IV and the fifth minor sector 5, the switching sequence is 003-0V3-112-0V3-003; when the reference vector to be synthesized... V ref When located in the fourth major sector IV and the sixth minor sector 6, the switching sequence is 033-0V3-122-0V3-033; when the reference vector to be synthesized... V ref When located in the fifth major sector V, first minor sector 1, the switch sequence is 001-101-111-101-001; when the reference vector to be synthesized... V ref When located in the fifth major sector V, the second minor sector 2, the switching sequence is 222-223-323-223-222; when the reference vector to be synthesized... V ref When located in the fifth major sector V and the third minor sector 3, the switching sequence is V03-223-323-223-V03; when the reference vector to be synthesized... V ref When located in the fifth major sector V and the fourth minor sector 4, the switching sequence is V03-101-001-101-V03; when the reference vector to be synthesized... V ref When located in the fifth major sector V and the fifth minor sector 5, the switch sequence is 003-V03-223-V03-003; when the reference vector to be synthesized... V ref When located in the fifth major sector V and the sixth minor sector 6, the switching sequence is 303-V03-101-V03-303; when the reference vector to be synthesized... V ref When located in the first sub-sector 1 of the sixth major sector VI, the switching sequence is 100-101-111-101-100; when the reference vector to be synthesized... V refWhen located in the second sub-sector 2 of the sixth major sector VI, the switching sequence is 222-322-323-322-222; when the reference vector to be synthesized... V ref When located in the third sub-sector 3 of the sixth major sector VI, the switching sequence is 30V-322-323-322-30V; when the reference vector to be synthesized... V ref When located in the sixth major sector VI, fourth minor sector 4, the switching sequence is 30V-101-100-101-30V; when the reference vector to be synthesized... V ref When located in the fifth sub-sector of the sixth major sector VI, the switching sequence is 300-30V-322-30V-300; when the reference vector to be synthesized... V ref When located in the sixth major sector VI and the sixth minor sector 6, the switching sequence is 303-30V-101-30V-303.

[0234] Table 7 Switching sequence for each sector

[0235]

[0236] As an example, as can be seen from Table 7, the number of switching cycles in the switching sequence of this specific embodiment is less than or equal to that of the four-level modulation strategy in the existing literature within each small sector. Therefore, the method of this specific embodiment can further reduce the switching losses of the three-phase four-level inverter and improve efficiency.

[0237] Furthermore, in step S3 of this specific embodiment, an action time equation set is established, and through virtual vectors, symmetry design, and switch sequence optimization, the natural dynamic balance of the capacitor voltage within half a fundamental cycle is achieved, thereby obtaining the action time of each vector in the target switch sequence.

[0238] Specifically, based on the principle of spatial vector synthesis, a system is established using three basic vectors from the target switch sequence. V s1 , V s2 , V s3 Duration of action The system of time equations for the unknown is expressed as follows:

[0239]

[0240] in, and Represent the basic vectors within the vector sequence. of α shaft and β Axial components, n =1, 2, 3; The duration of one switching cycle; Represents the fundamental vector within a switching cycle. Duration of action; and They represent the reference vectors to be synthesized. of α shaft and β Axial components.

[0241] Furthermore, in step S4, based on the action order and action time of each vector in the target switching sequence determined in step S2, it is directly mapped to the on / off logic of the corresponding power switch in each phase bridge arm of the three-phase four-level inverter. Through the PWM generator, based on the on / off logic and the target switching sequence, a discontinuous pulse width modulation drive signal containing the necessary dead time is generated, which ultimately controls the on / off of each switch in the three-phase four-level inverter. Thus, while outputting a multi-level voltage waveform, the periodic clamping of a specific phase bridge arm is achieved, thereby reducing switching losses.

[0242] For example, to verify the effectiveness of the inverter DC-side capacitor voltage balancing method in this specific embodiment, the AC voltage standard of the three-phase four-level inverter can be set to 220V / 50Hz, the DC-side input voltage to 800V, the power to 6kVA, and the switching frequency to 60kHz. Figure 8 This is a waveform diagram of the steady-state operation experiment of this specific embodiment at a modulation ratio MI=0.67. Figure 9 This is a waveform diagram of the steady-state operation experiment of this specific embodiment at a modulation ratio MI=0.34, where, u dc2 This is the voltage of the second DC bus filter capacitor. u dc1 and u dc3 These are the voltages of the first DC bus filter capacitor and the third DC bus filter capacitor, respectively. u AO This is the voltage of phase A bridge arm. i A This is the output current of phase A. It can be seen that... Figure 8 , Figure 9 Under the two different modulation ratios shown, the three capacitor voltages on the DC side can maintain dynamic balance naturally within half a fundamental frequency cycle. Furthermore, as can be seen from the bridge arm voltage waveform, the bridge arm voltage is clamped in a specific region under the modulation method of this specific embodiment, thus reducing switching losses. Moreover, at low modulation ratios, the bridge arm voltage can be clamped to levels 1 and 2, filling the gap in existing technologies for this clamping mode under capacitor voltage balance conditions.

[0243] It is understood that the modulation methods corresponding to the two sector division methods in this application can suppress the voltage fluctuations of the upper and lower capacitors on the DC side while maintaining the voltage balance of the intermediate capacitor, and can also naturally achieve dynamic balance within half a fundamental cycle, and further reduce the inverter switching losses. The method can be adaptively selected according to actual needs.

[0244] The inverter DC-side capacitor voltage balancing method of this application integrates two different space vector modulation architectures and adopts a unified modulation framework compatible with both balancing strategies. This achieves effective balancing and fluctuation suppression of the split capacitor voltage on the DC side of the inverter, and significantly reduces switching losses. It can automatically match the first, second, or third clamping modes according to different sector division strategies to generate corresponding target switching sequences, thereby maintaining the consistency and efficiency of the switching sequence under complex operating conditions and enhancing the flexibility and applicability of control. A redundant clamping mode dynamic selection mechanism is adopted, adaptively selecting the first clamping mode in each switching cycle based on the voltage difference between the upper and lower capacitors and the direction of the midpoint current. The first clamping mode or the second clamping mode can suppress voltage fluctuations of the upper and lower capacitors while maintaining the voltage balance of the intermediate capacitor. Within a single switching cycle, the intermediate capacitor voltage is balanced by optimizing the on-state sequence and vector action time. A combination of redundant clamping modes across multiple switching cycles effectively regulates the voltages of the upper and lower capacitors. The third clamping mode allows for some fluctuations in the three DC-side capacitor voltages, naturally achieving dynamic balance within half a fundamental cycle and further reducing inverter switching losses. By introducing a virtual space vector and utilizing the symmetry of the three-phase current, the DC-side capacitor voltage of the inverter achieves natural balance within half a fundamental cycle, further reducing the number of switching operations. This application further reduces the number of switching operations compared to existing four-level discontinuous modulation strategies. At low modulation ratios, it can be extended to a low-level clamping mode, thus suppressing capacitor voltage fluctuations and reducing switching losses while maintaining natural voltage balance. This significantly improves voltage balancing capability and system reliability, making it suitable for applications sensitive to switching losses and tolerating small periodic voltage fluctuations.

[0245] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the accompanying drawings may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps. In another embodiment, this application also provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, it implements the various steps of the inverter DC-side capacitor voltage balancing method provided in the above embodiments.

[0246] Computer programs used to implement the methods of this application may be written in any combination of one or more programming languages. These computer programs may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the functions / operations specified in the flowcharts and / or block diagrams are performed. The computer programs may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or electronic device.

[0247] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a cathode ray tube (CRT) or liquid crystal display (LCD) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices may also be used to provide interaction with the user; feedback provided to the user can be any form of sensory feedback (e.g., visual feedback or haptic feedback); and input from the user can be received in any form, including: sound input, voice input, or haptic input.

[0248] The systems and technologies described herein can be implemented in computing systems that include back-end components (e.g., as data electronic devices), or computing systems that include middleware components (e.g., application electronic devices), or computing systems that include front-end components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0249] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0250] Although this application has been disclosed above with reference to embodiments, it is not intended to limit this application. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of this application.

Claims

1. A method for balancing the DC-side capacitor voltage of an inverter, characterized in that, Includes the following steps: Based on the inverter topology, a spatial vector diagram is established in the αβ coordinate system. The spatial vector diagram is divided into six major sectors, each major sector is divided into six minor sectors, and each minor sector includes a virtual vector. Determine the target sector to which the reference vector to be synthesized belongs, and adopt the third clamping mode. Determine the target switching sequence based on the selected clamping mode. Establish a set of action time equations, and solve the set of action time equations according to natural equilibrium to obtain the action time of each vector in the target switch sequence; Based on the target switching sequence and the duration of each vector, a pulse width modulation signal is generated to control the switching state; The equations for the action time are solved based on natural equilibrium, and the expression is: in, and Represent the basic vectors within the vector sequence. of α shaft and β Axial components, n =1, 2, 3; The duration of one switching cycle; Represents the fundamental vector within a switching cycle. Duration of action; and They represent the reference vectors to be synthesized. of α shaft and β Axial components.

2. The inverter DC-side capacitor voltage balancing method according to claim 1, characterized in that, Each large sector is divided into 6 smaller sectors. Each smaller sector includes a virtual vector, which includes: The virtual vectors are 3V0, V30, 03V, 0V3, V03, and 30V, respectively. Within the first large sector, the first small sector is the portion to the lower right of the line connecting 111 and 3V0 within the area enclosed by 332, 322, and 111. The second small sector is the portion to the upper left of the line connecting 111 and 3V0 within the area enclosed by 332, 322, and 111. The third small sector is the portion to the lower right of the line connecting 111 and 3V0 within the area enclosed by the lines connecting 332 and 322, 332 and 3V0, and 322 and 3V0. The fourth sub-sector is the area to the left of the line connecting 111 and 3V0 within the region enclosed by the lines connecting 332 and 322, 332 and 3V0, and 322 and 3V0. The fifth sub-sector is the region enclosed by the lines connecting 322 and 300, 322 and 3V0, and 300 and 3V0. The sixth sub-sector is the region enclosed by the lines connecting 332 and 330, 332 and 3V0, and 330 and 3V0. In the second large sector, the first small sector is the portion to the left of the line connecting 111 and V30 within the area enclosed by 332, 232, and 111; the second small sector is the portion to the right of the line connecting 111 and V30 within the area enclosed by 332, 232, and 111; and the third small sector is the portion to the left of the line connecting 111 and V30 within the area enclosed by the lines connecting 332 and 232, 332 and V30, and 232 and V30. The fourth sub-sector is the area to the right of the line connecting 111 and V30 within the region enclosed by the lines connecting 332 and 232, 332 and V30, and 232 and V30. The fifth sub-sector is the region enclosed by the lines connecting 232 and 030, 232 and V30, and 030 and V30. The sixth sub-sector is the region enclosed by the lines connecting 332 and 330, 332 and V30, and 330 and V30. In the third major sector, the first sub-sector is the portion to the upper right of the line connecting 111 and 03V within the area enclosed by 232, 233, and 111. The second sub-sector is the portion to the lower left of the line connecting 111 and 03V within the area enclosed by 232, 233, and 111. The third sub-sector is the portion to the right of the line connecting 111 and 03V within the area enclosed by the lines connecting 232 and 233, 232 and 03V, and 233 and 03V. The upper part, the fourth small sector is the area to the lower left of the line connecting 111 and 03V in the region surrounded by the lines connecting 232 and 233, 232 and 03V, and 233 and 03V; the fifth small sector is the area surrounded by the lines connecting 232 and 030, 232 and 03V, and 030 and 03V; the sixth small sector is the area surrounded by the lines connecting 233 and 033, 233 and 03V, and 033 and 03V. In the fourth major sector, the first sub-sector is the portion to the lower right of the line connecting 111 and 0V3 within the area enclosed by 233, 223, and 111. The second sub-sector is the portion to the upper left of the line connecting 111 and 0V3 within the area enclosed by 233, 223, and 111. The third sub-sector is the portion to the right of the line connecting 111 and 0V3 within the area enclosed by the lines connecting 223 and 233, 223 and 0V3, and 233 and 0V3. The lower part, the fourth sub-sector is the area to the upper left of the line connecting 111 and 0V3 within the area enclosed by the lines connecting 223 and 233, 223 and 0V3, and 233 and 0V3; the fifth sub-sector is the area enclosed by the lines connecting 223 and 003, 223 and 0V3, and 003 and 0V3; the sixth sub-sector is the area enclosed by the lines connecting 233 and 033, 233 and 0V3, and 033 and 0V3. In the fifth major sector, the first sub-sector is the portion of the area enclosed by 223, 323, and 111 that lies to the left of the line connecting 111 and V03. The second sub-sector is the portion of the area enclosed by 223, 323, and 111 that lies to the right of the line connecting 111 and V03. The third sub-sector is the portion of the area enclosed by the lines connecting 223 and 323, 223 and V03, and 323 and V03 that lies to the left of the line connecting 111 and V03. The fourth sub-sector is the area to the right of the line connecting 111 and V03 within the region enclosed by the lines connecting 223 and 323, 223 and V03, and 323 and V03. The fifth sub-sector is the region enclosed by the lines connecting 223 and 003, 223 and V03, and 003 and V03. The sixth sub-sector is the region enclosed by the lines connecting 323 and 303, 323 and V03, and 303 and V03. In the sixth major sector, the first sub-sector is the portion to the upper right of the line connecting 111 and 30V within the area enclosed by 322, 323, and 111. The second sub-sector is the portion to the lower left of the line connecting 111 and 30V within the area enclosed by 322, 323, and 111. The third sub-sector is the portion to the right of the line connecting 111 and 30V within the area enclosed by the lines connecting 322 and 323, 322 and 30V, and 323 and 30V. The upper part, the fourth sub-sector is the area to the lower left of the line connecting 111 and 30V, which is surrounded by the lines connecting 322 and 323, 322 and 30V, and 323 and 30V. The fifth sub-sector is the area surrounded by the lines connecting 322 and 300, 322 and 30V, and 300 and 30V. The sixth sub-sector is the area surrounded by the lines connecting 323 and 303, 323 and 30V, and 303 and 30V.

3. The inverter DC-side capacitor voltage balancing method according to claim 2, characterized in that, 3V0 is composed of 310 and 320, and is defined as follows: ; V30 consists of 130 and 230, and is defined as follows: ; 03V is composed of 031 and 032, and is defined as follows: ; 0V3 is composed of 013 and 023, and is defined as ; V03 is composed of 103 and 203, and is defined as follows: ; 30V is composed of 301 and 302, and is defined as follows: ; in, and They represent the reference vectors to be synthesized. of α shaft and β Axial components.

4. A method for balancing the DC-side capacitor voltage of an inverter, characterized in that, Includes the following steps: Based on the inverter topology, a spatial vector diagram in the αβ coordinate system is established, and the spatial vector diagram is divided into six major sectors, each of which is further divided into 12 minor sectors. Determine the target sector to which the reference vector to be synthesized belongs, initialize the clamping mode, and determine the sign of the voltage difference between the upper and lower capacitors. When the voltage difference between the upper and lower capacitors is greater than or equal to zero, determine the sign of the sum of the average values ​​of the two midpoint currents flowing out. If the sum of the average values ​​of the two midpoint currents is less than or equal to zero, select the first clamping mode; otherwise, select the second clamping mode. When the voltage difference between the upper and lower capacitors is less than zero, determine the sign of the sum of the average values ​​of the two midpoint currents flowing out. If the sum of the average values ​​of the two midpoint currents is greater than or equal to zero, select the first clamping mode; otherwise, select the second clamping mode. Determine the target switching sequence based on the selected clamping mode. Establish a set of action time equations, and solve the set of action time equations based on the DC bus capacitor voltage balance constraint to obtain the action time of each vector in the target switching sequence; Based on the target switching sequence and the duration of each vector, a pulse width modulation signal is generated to control the switching state; When each large sector is divided into 12 smaller sectors, if the reference vector to be synthesized... When located within the first sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is: If the reference vector to be synthesized When located within the first sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is: If the reference vector to be synthesized When located within the second sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is: If the reference vector to be synthesized When located within the second sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is: If the reference vector to be synthesized When located within the third sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is: If the reference vector to be synthesized When located within the third sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is: If the reference vector to be synthesized When located in the fourth sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is: If the reference vector to be synthesized When located in the fourth sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is: If the reference vector to be synthesized When located within the fifth sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is: If the reference vector to be synthesized When located within the fifth sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is: If the reference vector to be synthesized When located in the sixth sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is: If the reference vector to be synthesized When located within the sixth sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is: If the reference vector to be synthesized When located in the seventh sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is: If the reference vector to be synthesized When located within the seventh sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is: If the reference vector to be synthesized When located in the eighth sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is: If the reference vector to be synthesized When located within the eighth sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is: If the reference vector to be synthesized When located within the ninth sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is: If the reference vector to be synthesized When located within the ninth sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is as follows: If the reference vector to be synthesized When located within the tenth sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is: If the reference vector to be synthesized When located within the tenth sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is: If the reference vector to be synthesized When located within the eleventh sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is: If the reference vector to be synthesized When located within the eleventh sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is: If the reference vector to be synthesized When located within the twelfth sub-sector of any large sector and using the first clamping mode, the DC bus capacitor voltage balance constraint is: If the reference vector to be synthesized When located within the twelfth sub-sector of any large sector and using the second clamping mode, the DC bus capacitor voltage balance constraint is: in, Represents the fundamental vector within the switching cycle. Duration of action i =1, 2, 3, 4, 5.

5. The inverter DC-side capacitor voltage balancing method according to claim 4, characterized in that, When each large sector is divided into 12 smaller sectors, a set of action time equations is established. These equations are then solved based on the DC bus capacitor voltage balance constraint to obtain the action time of each vector in the target switching sequence. The expression for the action time equations is as follows: in, and They represent the basic vectors respectively. of α shaft and β Axial components, i =1, 2, 3, 4, 5; and These represent the coefficients corresponding to the DC bus capacitor voltage balance constraint; Represents the fundamental vector within the switching cycle. Duration of action; and They represent the reference vectors to be synthesized. of α shaft and β Axial components; The duration of one switching cycle.

6. The inverter DC-side capacitor voltage balancing method according to claim 4, characterized in that, The target switching sequence consists of multiple voltage vectors arranged in a symmetrical or asymmetrical order, and the target switching sequence is configured such that at least one phase bridge arm is clamped in each switching cycle.

7. An inverter, characterized in that, include: An inverter module and a control module are provided, wherein the inverter module is connected to the control module; the inverter module includes a DC bus capacitor unit, a switching unit, and a filtering unit, wherein the DC bus capacitor unit, the switching unit, and the filtering unit are connected in sequence between the DC power supply and the three-phase power grid; The control module includes: one or more processors; a storage device for storing one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors implement the inverter DC-side capacitor voltage balancing method as described in any one of claims 1 to 6.

8. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the inverter DC-side capacitor voltage balancing method according to any one of claims 1 to 6.

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