Inverter phase synchronization method based on CAN bus and zero-crossing phase locking

Abstract

The invention discloses an inverter phase synchronization method based on a CAN bus and zero-crossing phase locking. According to the method, the existing CAN bus communication link of the parallel operation system is multiplexed, and the phase synchronization of the master and slave machines is realized by combining the zero-crossing phase locking technology. And the host triggers and sends a synchronization frame containing an equipment identifier, a zero-crossing time stamp and a power frequency period at the zero-crossing time of the inverter output voltage, the slave receives the synchronization frame, eliminates transmission deviation through hardware delay compensation, and dynamically adjusts the step length according to the phase error until the phase error in a plurality of continuous power frequency periods is at a preset threshold value, so that phase locking is completed and stability is maintained. And meanwhile, a dual-host redundancy design can be adopted, and synchronous interruption caused by a single-host fault is avoided through initial phase calibration, secondary calibration in operation and an automatic fault switching mechanism. An independent IO port does not need to be additionally configured, the synchronization precision is high, and operation is stable.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of inverter phase synchronization technology, and particularly relates to an inverter phase synchronization method based on CAN bus and zero-crossing phase-locked loop. BACKGROUND

[0002] In the fields of industrial power supply, micro-grid, backup power supply, etc., in order to meet the demand of load on power supply capacity and reliability, multiple inverters often adopt parallel operation mode. One of the core technical requirements of inverter parallel system is to realize the phase synchronization of output voltages of each inverter. If there is a phase deviation, it will cause circulating current in the parallel system, output voltage waveform distortion, and even damage the inverter power device, so the precision and stability of phase synchronization directly determine the operation quality of the parallel system. In the prior art, the technical solutions for realizing phase synchronization of wired inverter parallel system mainly include the following two types:

[0003] (1) Depend on separate IO port to send power frequency signal, and realize synchronization by combining zero-crossing phase-locked loop technology. The operation logic is as follows: a specified inverter is taken as a master, and a dedicated IO interface is used to continuously send a power frequency reference signal to other slave inverters. The slave inverter captures the zero-crossing moment of the power frequency signal through a zero-crossing detection circuit, and then adjusts its own output phase based on the zero-crossing phase-locked loop algorithm to match the master phase. However, this scheme has the following obvious defects: an independent IO port needs to be additionally configured for phase synchronization, which not only occupies redundant hardware resources, but also may need to redesign and modify the existing inverter hardware circuit. When the number of inverters in the parallel system needs to be expanded, the new slave inverter also needs to reserve the corresponding IO interface, which leads to poor system scalability and is not conducive to the later machine upgrade and maintenance.

[0004] (2) Realize synchronization by directly sending phase information through CAN bus. This scheme uses the existing CAN bus communication link in the parallel system, and the master inverter collects its own phase data in real time, and sends the complete phase information as a data frame to the CAN bus. The slave inverter directly adjusts its own phase according to the phase information received. Although this scheme does not require additional IO port resources, it has the following problems: the phase information transmitted by the CAN bus is easily affected by the electromagnetic interference in the industrial field, leading to data transmission errors, and further causing phase deviation of the slave inverter, which destroys the operation stability of the parallel system. At the same time, the master needs to continuously and frequently send phase data to ensure synchronization accuracy, and a large amount of phase information frames will significantly increase the communication load of the CAN bus, occupying the transmission bandwidth of other control instructions or state monitoring data, and reducing the overall communication efficiency of the bus.

[0005] In summary, existing technical solutions are either limited by hardware resource consumption and expansion difficulties, or face the risks of data interference and excessive bus load, making it difficult to meet the comprehensive requirements of current inverter parallel systems for low hardware cost, high synchronization accuracy, and high operational stability. Therefore, an optimized phase synchronization method is needed. Summary of the Invention

[0006] To address the issue that existing technologies cannot simultaneously balance hardware cost, synchronization stability, and bus communication efficiency, this invention proposes an inverter phase synchronization method based on CAN bus and zero-crossing phase-locked loop, comprising the following steps:

[0007] S1: System initialization configuration. The inverter completes CAN bus interface initialization, parameter preset and role definition, and determines one inverter as the master and the rest as slaves.

[0008] S2: Host zero-crossing detection and CAN synchronization information transmission. The host collects the zero-crossing moment of its own inverter output voltage in real time, encapsulates a CAN synchronization frame containing core synchronization information, and sends it immediately at the zero-crossing moment.

[0009] S3: Slave CAN information reception and delay compensation. The slave receives the synchronization frame through the CAN bus interrupt. After verification and parsing, it calculates and compensates for the phase offset corresponding to the transmission delay.

[0010] S4: Slave phase comparison and dynamic step size adjustment. The slave collects its own real-time phase and calculates the error with the zero-crossing phase of the master. The phase step size is dynamically adjusted according to the magnitude of the error to correct the phase deviation.

[0011] S5: Phase-locked loop success determination and stability maintenance. The slave device continuously monitors the phase error. After the phase-locked loop success condition is met, it switches to the phase fine-tuning mode to maintain long-term synchronization and stability.

[0012] Preferably, S1 includes:

[0013] S11: The interface initialization includes configuring the host and slave devices to a unified CAN bus baud rate and enabling the interrupt reception function;

[0014] S12: The preset parameters include preset power frequency standard phase period, initial value of phase step size, phase lock success error threshold and CAN transmission hardware delay reference value.

[0015] S13: The role definition includes specifying the master and slave through hardware DIP switches or software configuration, with the master undertaking the task of transmitting the phase reference and the slave performing the task of phase following adjustment.

[0016] Preferably, S2 includes:

[0017] S21: Voltage zero-crossing sampling, the host detects the zero-crossing moment of its own inverter output voltage through voltage comparator or ADC sampling algorithm;

[0018] S22: Synchronization information packaging, the host packages CAN synchronization frame, which includes host device identification, microsecond-level zero-crossing timestamp and power frequency standard period parameters, and controls synchronization frame length;

[0019] S23: Instantaneous sending of CAN frame, the host triggers CAN bus sending interrupt at the zero-crossing moment, so that the time difference between sending action and the zero-crossing moment is less than the time difference threshold.

[0020] Preferably, the S3 comprises:

[0021] S31: Interrupt receiving CAN frame, the slave monitors bus data through CAN bus interrupt, and suspends non-critical tasks when receiving the synchronization frame;

[0022] S32: Data verification and analysis, the slave verifies the CAN frame and verifies the host identification, and analyzes the zero-crossing timestamp and the power frequency standard period parameters after the verification is passed;

[0023] S33: Hardware delay compensation, the slave calls CAN sending hardware delay reference value, calculates the phase offset corresponding to the actual receiving delay, and the offset is delay time / power frequency period x 2π, and the offset is compensated and removed from the synchronization information.

[0024] Preferably, the S4 comprises:

[0025] S41: Self-phase sampling, after the delay compensation is completed, the slave determines its current real-time phase based on the corresponding relationship between the ADC sampling value and the power frequency period;

[0026] S42: Phase difference value judgment, the error value of the slave real-time phase and the host zero-crossing phase is calculated, and when the error value is 0 to π radian, it is determined that the slave phase is advanced, and when the error value is π to 2π radian, it is determined that the slave phase is lagged;

[0027] S43: Step adjustment execution, when advanced, the current phase step is reduced by 30% to 50%; when lagged, the current phase step is increased by 30% to 50%.

[0028] Preferably, the S5 comprises:

[0029] S51: Synchronization state detection, the slave re-collects the phase and calculates the error value after each step adjustment, and monitors the error change trend;

[0030] S52: Phase-locked success determination, when the phase error value is within the threshold range for a continuous preset number of power frequency periods, it is determined that the phase-locked is successful;

[0031] S53: stable maintenance mechanism, after phase-locked, slave switches to phase fine-tuning mode, adjusts phase step to 10% to 20% of initial value, receives main machine synchronization information once per preset interval.

[0032] The application further provides an inverter phase synchronization method based on dual-host redundancy, and the method comprises the following steps:

[0033] S201: dual-host redundancy initialization configuration, CAN bus initialization of two hosts and all slaves, redundancy parameter presetting and role redundancy relationship definition are completed;

[0034] S202: dual-host phase consistency calibration, after the two hosts are powered on, zero-crossing phase information is exchanged, and the phase is adjusted to be within a consistency error threshold range;

[0035] S203: dual-host synchronization and state monitoring in normal operation, the main host sends a synchronization frame and a heartbeat frame, the standby host listens and performs secondary phase calibration, and the slave receives the synchronization information of the main host;

[0036] S204: main host fault switching, after the standby host detects that the main host fails, the standby host switches to the main mode to send a synchronization frame, and the slave switches to receive the synchronization information of the standby host;

[0037] S205: fault host recovery and redundancy reset, after the fault host recovers, the fault host and the standby host re-calibrate the phase, the standby host returns the main host right, and the slave switches back to receive the synchronization information of the original main host.

[0038] Preferably, the S201 further comprises the following steps: two hosts are configured with independent and unique device identifiers, presetting host priority, main host heartbeat detection period, host fault determination threshold, dual-host phase consistency error threshold and fault switching response time, binding the two hosts as a redundancy pair and setting the main and standby roles, and the slave pre-stores the dual-host device identifiers and priority.

[0039] Preferably, the S202 further comprises the following steps: the main host sends a calibration frame containing a zero-crossing time stamp and a device identifier at the zero-crossing moment, the standby host receives the calibration frame, compensates for the delay and calculates the phase difference, the step is adjusted when the phase difference is out of limit, and the phase difference is within the threshold range in a continuous preset number of power frequency periods.

[0040] Preferably, the S204 further comprises the following steps: the standby host does not receive the main host heartbeat frame for a plurality of times, or detects that the phase mutation of the synchronization frame exceeds the threshold value, and determines that the main host fails, sends a fault warning frame, switches to the main mode, adds a takeover identifier bit to the synchronization frame and shortens the heartbeat frame period; after the slave receives the warning frame and the takeover synchronization frame, the phase fine-tuning is completed within two power frequency periods to recover the phase-locked, and the phase error is not more than the threshold value.

[0041] The present application has the following advantages:

[0042] (1) The multiplexing and parallel system of the present application has the existing CAN bus communication link, without additional configuration of independent IO port, greatly reducing the hardware deployment and transformation cost. When the system is expanded, the new slave machine only needs to complete the role definition through hardware dialing or software configuration, without reserving a dedicated synchronous interface, simplifying the expansion process and improving the convenience of system later upgrading and maintenance.

[0043] (2) The master machine triggers the CAN synchronization frame transmission at the zero-crossing moment, ensuring that the time difference between the transmission action and the zero-crossing moment is controlled in a very low range, and cooperating with the hardware delay compensation mechanism of the slave machine, the phase deviation caused by transmission delay can be accurately eliminated. Through the dynamic step adjustment strategy, the step size is flexibly adjusted according to the phase error size, avoiding the output voltage fluctuation caused by phase mutation.

[0044] (3) The synchronization data frame length packaged by the master machine is controlled within 8 bytes, only containing core synchronization information, and only triggering transmission at the zero-crossing moment, without the need for continuous high-frequency transmission of phase data, greatly reducing the communication load of CAN bus, avoiding the occupation of transmission bandwidth of other control instructions or state monitoring data, improving the overall communication efficiency of the bus, and ensuring the smoothness of system data transmission.

[0045] (4) Through the dual-host redundancy design and fault automatic switching mechanism, the synchronization interruption problem caused by single-host failure is effectively avoided. The initial phase consistency calibration of the dual-host and the secondary calibration in operation ensure that the phase reference of the standby host and the main host is consistent, significantly improving the running stability of the system in the industrial high-reliability scene, and widening the technical application range.

[0046] In summary, the present application has the characteristics of low hardware cost, high synchronization precision, high communication efficiency and high running reliability, and can meet the phase synchronization needs of inverter parallel system in different scenes such as industrial power supply, micro-grid, standby power supply, etc. BRIEF DESCRIPTION OF DRAWINGS

[0047] Figure 1 The present application is an embodiment method step diagram;

[0048] Figure 2 The present application is an embodiment method flowchart. DETAILED DESCRIPTION

[0049] With reference to the accompanying drawings, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of the present application.

[0050] Embodiment one

[0051] The flow of the phase synchronization of the inverter parallel operation of the embodiment of the present application based on the CAN bus and the zero-crossing phase-locked loop is suitable for a wired parallel operation system composed of one master inverter and at least one slave inverter. All inverters are connected through the CAN bus to establish communication. The phase synchronization of the master and slave inverters is realized through the zero-crossing trigger CAN communication and dynamic phase adjustment. As shown in FIGS. 1 and 2, the specific steps are as follows: Figure 1 、 Figure 2

[0052] S1: System initialization configuration.

[0053] S11. Hardware interface initialization: the master and all slave inverters complete the CAN bus interface initialization, configure a unified baud rate, recommend 250 Kbps or 500 Kbps, match the industrial parallel operation communication demand, enable the CAN bus interrupt receiving function, and ensure the stability of the communication link.

[0054] S12. Parameter presetting: all inverters preset core parameters, including the standard phase period of the power frequency, 20 ms for 50 Hz and 16.67 ms for 60 Hz; the initial value of the phase step, 0.01π-0.05π radian / adjustment period is recommended; the error threshold of the phase-locked success, set to ±0.005π radian, that is, ±0.9°, to meet the high-precision synchronization requirement; the CAN sending hardware delay reference value, usually 5-20 microseconds, is calibrated through pre-test and solidified to the system storage unit.

[0055] S13. Role definition: a single inverter is specified as the master through hardware code or software configuration, and the rest are slave inverters. The master undertakes the phase reference sending task, and the slave executes the phase following adjustment task.

[0056] S2: Master zero-crossing detection and CAN synchronization information sending.

[0057] S21. Voltage zero-crossing sampling: the master real-time collects the inverter output voltage signal, detects the voltage zero-crossing moment through the voltage comparator or ADC sampling algorithm, that is, the cross point of the voltage from positive to negative or negative to positive, and corresponds to the 0 radian position.

[0058] ​S22. Synchronization Information Encapsulation: After detecting the zero crossing moment, the host immediately encapsulates a frame of CAN synchronization data. The data frame includes the host device identifier, the zero crossing time stamp accurate to the microsecond level, and the power frequency standard cycle parameter, ensuring that the data frame length is controlled within 8 bytes to reduce communication latency.

[0059] S23. Instantaneous transmission of CAN frames: The host triggers a CAN bus transmission interrupt at the zero-crossing moment, and sends the encapsulated synchronization information frame to the CAN bus in real time, ensuring that the time difference between the transmission action and the zero-crossing moment does not exceed 3 microseconds.

[0060] S3: Slave CAN information reception and delay compensation.

[0061] S31. Interrupt CAN Frame Reception: The slave device monitors the bus data in real time through the CAN bus interrupt function. When it detects a synchronization information frame sent by the master, it immediately triggers a reception interrupt, suspends other non-critical tasks, and prioritizes the processing of synchronization data.

[0062] S32. Data Verification and Parsing: The slave device verifies the received CAN frames, including CRC verification and host identifier verification. After the verification is successful, the zero-crossing timestamp and power frequency standard cycle parameters are parsed out, and invalid frames that fail the verification are discarded.

[0063] S33. Hardware Delay Compensation: The slave device calls the pre-stored CAN transmission hardware delay reference value to calculate the actual reception delay, which is the time difference from the time the master sends the data to the time the slave device completes receiving it. The phase offset corresponding to this delay, i.e., delay time / power frequency period × 2π, is compensated and removed from the synchronization information to ensure that the true zero-crossing phase of the master device is obtained.

[0064] S4: Slave phase comparison and dynamic step size adjustment.

[0065] S41. Self-phase sampling: After completing the delay compensation, the slave device immediately samples the real-time phase of its current inverter output voltage and determines the current phase value based on the correspondence between the ADC sampling value and the power frequency period through the phase calculation algorithm.

[0066] S42. Phase Difference Judgment: Calculate the phase error value by comparing the slave's real-time phase with the host's zero-crossing phase. If the phase error value is greater than 0 and less than π radians, the slave's phase is determined to be ahead of the host, and phase deceleration adjustment is performed. If the phase error value is greater than π radians and less than 2π radians, the slave's phase is determined to be lagging behind the host, and phase acceleration adjustment is performed.

[0067] S43. Step length adjustment execution: dynamically adjust the phase step length according to the phase error size. Advance adjustment: reduce the current phase step length by 30%-50%, the minimum step length is not less than 0.005π radian, and the slave phase growth rate is reduced. Lags adjustment: increase the current phase step length by 30%-50%, the maximum step length is not more than 0.1π radian, and the slave phase growth rate is increased. Keep the step length change smooth during the adjustment process to avoid sudden changes that cause output voltage fluctuations.

[0068] S5: Phase-locked success determination and stable maintenance.

[0069] S51. Synchronization state detection: the slave re-acquires its own phase and calculates the error value with the master zero-crossing phase after each step length adjustment, and continuously monitors the error trend.

[0070] S52. Phase-locked success determination: when the phase error value is within the preset phase-locked success error threshold ±0.005π radian for 3 consecutive power frequency periods, it is determined that the phase-locked is successful, and the master-slave phase synchronization is achieved.

[0071] S53. Stable maintenance mechanism: after phase-locked success, the slave switches to phase fine-tuning mode, adjusts the phase step length to 10%-20% of the initial value, only compensates for small phase deviations, and receives synchronization information from the master every 5 power frequency periods to ensure synchronization stability in long-term operation.

[0072] The above steps can quickly and stably achieve the phase synchronization of the inverter parallel multi-machine.

[0073] Embodiment two

[0074] The embodiment of the application is based on the dual-host redundant inverter parallel multi-machine phase synchronization implementation process, and aims at the problem of synchronization interruption caused by host failure in single-host scenario. The design adopts two host backups and automatic fault switching, and is suitable for high-reliability industrial-grade inverter parallel systems, such as data center backup power supply and micro-grid parallel system. All inverters are interconnected through CAN bus. On the basis of embodiment one, the host redundancy mechanism is strengthened, and the specific steps are as follows:

[0075] S201: Dual-host redundancy initialization configuration.

[0076] 1. Hardware and communication initialization: two hosts are denoted as host A and host B, and all slaves complete CAN bus interface initialization. The baud rate is configured to be consistent with embodiment one, that is, 250Kbps or 500Kbps, and the CAN bus interrupt reception and fault detection functions are enabled. Host A and host B are configured with independent device identifiers, such as 0x01 and 0x02, and the slave device identifiers are numbered from 0x03, to ensure that the device identifiers on the CAN bus are unique.

[0077] 2. Redundancy parameter preset: On the basis of embodiment one, additional redundancy-related parameters are preset. These include host priority, with host A set as high priority and host B set as low priority; master host heartbeat detection period of 100 ms, i.e., 5 power frequency periods; host failure determination threshold, with 3 consecutive times of non-reception of heartbeat frames or synchronization frames determined as failure; dual-host phase consistency error threshold of ±0.003π radians, i.e., ±0.54°, to ensure consistency of the reference of the dual hosts; and failure switching response time ≤ 1 power frequency period, i.e., ≤ 20 ms.

[0078] 3. Role and redundancy relationship definition: Host A and host B are bound as a redundant pair through software configuration, with host A set as the default master host and host B as the standby host; all slaves pre-store the dual-host device identifiers and priorities, and by default receive the synchronization information of master host A while monitoring the state information of standby host B.

[0079] S202: Dual-host phase consistency calibration.

[0080] 1. Initial calibration trigger: After system power-up and completion of initialization, master host A and standby host B automatically trigger the phase consistency calibration process, establish a dedicated redundancy communication link through the CAN bus, and exchange zero-crossing phase information.

[0081] 2. Dual-host phase exchange: Host A sends a calibration frame at the zero-crossing moment of its own inverter voltage, including its own zero-crossing time stamp and device identifier, and host B receives the frame, compensates for the CAN transmission hardware delay, compares its own current zero-crossing phase with the zero-crossing phase of host A using the pre-stored reference value of embodiment one, and calculates the phase difference Δφ.

[0082] 3. Phase adjustment and consistency confirmation: If Δφ > 0.003π radians, host B lags behind, and host B increases the phase step, which can be increased by 36% - 60% of the step adjustment proportion of embodiment one, i.e., by 1.2 times. If Δφ < -0.003π radians, host B leads, and host B decreases the phase step, which can be decreased by 36% - 60% of the step adjustment proportion of embodiment one, i.e., by 1.2 times. This interactive adjustment process is repeated until Δφ is within the range of ±0.003π radians within 2 consecutive power frequency periods, and it is determined that the dual-host phase consistency calibration is complete, and host B enters the standby monitoring state.

[0083] S203: Dual-host synchronization and state monitoring in normal operation.

[0084] 1. Master host A sends synchronization information: Host A detects the zero-crossing time of its own inverter voltage in real time, encapsulates a synchronization frame containing device identification, zero-crossing time stamp, and power frequency cycle, triggers a CAN sending interrupt at the zero-crossing time, and sends the synchronization frame to the bus; at the same time, it sends a heartbeat frame every 100 ms, which contains its own running state and phase stability identification, for standby host and slave monitoring of its health status.

[0085] 2. Standby host B state monitoring and backup: Host B continuously monitors the synchronization frame and heartbeat frame of host A. Each time it receives a synchronization frame of host A, it records the zero-crossing phase of host A after compensating for the delay and performs secondary calibration with its current phase, with an adjustment step of 50% of that of embodiment one, to avoid frequent and large adjustments and ensure that its phase always remains consistent with that of host A. It also monitors the heartbeat frame of host A and starts a timeout timer if it does not receive it within 100 ms.

[0086] 3. Slave synchronization information reception and phase adjustment: All slaves receive the synchronization frame of host A by default and perform phase synchronization according to the delay compensation of S3, phase comparison and step adjustment of S4, and phase-locked determination of S5 in embodiment one, while monitoring the heartbeat frame of host A and recording the reception status.

[0087] S204: Master host fault switching process.

[0088] 1. Fault detection and confirmation: If host B does not receive the heartbeat frame of host A for 3 times continuously, i.e., within 300 ms, or receives the synchronization frame of host A for 2 times continuously with a phase mutation greater than 0.05π radians, it determines that host A has failed. At this time, host B immediately sends a host failure warning frame to the CAN bus to notify all slaves.

[0089] 2. Standby host takeover: After sending the warning frame, host B immediately switches to master host mode and sends synchronization frames according to the synchronization frame sending logic, starting at its own next zero-crossing time. The device identification in the synchronization frame is still 0x02, but an takeover identification bit is added, and the heartbeat frame sending period is shortened to 50 ms to speed up the state update frequency.

[0090] 3. Slave switching response: After receiving the host failure warning frame and the takeover synchronization frame of host B, the slave immediately stops monitoring the information of host A and switches to receiving the synchronization frame of host B. Based on the zero-crossing time stamp of the synchronization frame of host B, the slave re-executes the delay compensation using the original pre-stored CAN hardware delay reference value, compares its current phase with the zero-crossing phase of host B, and adjusts the phase through 1-2 power frequency cycles to quickly restore the phase-locked state, ensuring that the phase error during the switching process does not exceed 0.01π radians, i.e., ±1.8°.

[0091] S205: Fault host recovery and redundancy reset.

[0092] 1. Fault host recovery detection: after host A troubleshooting such as restart, fault repair, re-power initialization, a host recovery frame is sent through the CAN bus to inform host B and all slaves that it has recovered; after host B receives the host recovery frame, it suspends the sending of its own synchronization frame, starts secondary phase consistency calibration with host A, and the process is synchronized with step S202.

[0093] 2. Master right return: after the double host phase consistency again meets the requirement of ±0.003π radians, host B sends a master right return frame to inform all slaves to switch back to receiving the synchronization frame of host A; after receiving the master right return frame, host A resumes sending the synchronization frame and the standard 100ms periodic heartbeat frame, and host B switches back to the standby state and continues to monitor the status of host A, completing the redundancy reset.

[0094] 3. Slave reset synchronization: after the slave receives the master right return frame, it switches back to receiving the synchronization frame of host A, and through a phase fine-tuning of one power frequency cycle, it ensures synchronization with host A and maintains long-term stable operation of the system.

[0095] Through the above steps, the double host synchronization is completed, the system redundancy is increased, and the system reliability is improved.

[0096] The above only describes the preferred embodiments of the present application, and it should be noted that for ordinary skilled persons in the art, without departing from the technical principles of the present application, a number of improvements and refinements can be made, and these improvements and refinements should also be considered within the protection scope of the present application.

Claims

1. A phase synchronization method for an inverter based on CAN bus and zero-crossing phase-locked loop, characterized in that, Includes the following steps: S1: System initialization configuration. The inverter completes CAN bus interface initialization, parameter preset and role definition, and determines one inverter as the master and the rest as slaves. S2: Host zero-crossing detection and CAN synchronization information transmission. The host collects the zero-crossing moment of its own inverter output voltage in real time, encapsulates a CAN synchronization frame containing core synchronization information, and sends it immediately at the zero-crossing moment. S3: Slave CAN information reception and delay compensation. The slave receives the synchronization frame through the CAN bus interrupt. After verification and parsing, it calculates and compensates for the phase offset corresponding to the transmission delay. S4: Slave phase comparison and dynamic step size adjustment. The slave collects its own real-time phase and calculates the error with the zero-crossing phase of the master. The phase step size is dynamically adjusted according to the magnitude of the error to correct the phase deviation. S5: Phase-locked loop success determination and stability maintenance. The slave device continuously monitors the phase error. After the phase-locked loop success condition is met, it switches to the phase fine-tuning mode to maintain long-term synchronization and stability.

2. The inverter phase synchronization method based on CAN bus and zero-crossing phase-locked loop as described in claim 1, characterized in that, S1 includes: S11: The interface initialization includes configuring the host and slave devices to a unified CAN bus baud rate and enabling the interrupt reception function; S12: The preset parameters include preset power frequency standard phase period, initial value of phase step size, phase lock success error threshold and CAN transmission hardware delay reference value. S13: The role definition includes specifying the master and slave through hardware DIP switches or software configuration, with the master undertaking the task of transmitting the phase reference and the slave performing the task of phase following adjustment.

3. The inverter phase synchronization method based on CAN bus and zero-crossing phase-locked loop as described in claim 1, characterized in that, S2 includes: S21: Voltage zero-crossing sampling, the host detects the moment when its own inverter output voltage crosses zero through a voltage comparator or ADC sampling algorithm; S22: Synchronization information encapsulation, the host encapsulates a CAN synchronization frame, the synchronization frame includes the host device identifier, a microsecond-level zero-crossing time stamp and power frequency standard period parameters, and controls the length of the synchronization frame; S23: Immediately send CAN frames. The host triggers a CAN bus transmission interrupt at the zero-crossing moment to ensure that the time difference between the transmission action and the zero-crossing moment is less than the time difference threshold.

4. The inverter phase synchronization method based on CAN bus and zero-crossing phase-locked loop as described in claim 1, characterized in that, S3 includes: S31: Interrupt CAN frame reception. The slave device monitors bus data via CAN bus interrupt. Non-critical tasks are paused when receiving synchronization frames. S32: Data verification and parsing. The slave device verifies the CAN frame and verifies the host identifier. After the verification is successful, it parses the zero-crossing timestamp and the power frequency standard cycle parameters. S33: Hardware delay compensation. The slave device calls the CAN to send the hardware delay reference value and calculates the phase offset corresponding to the actual reception delay. The offset is the delay time / power frequency period × 2π, which is compensated and removed from the synchronization information.

5. The inverter phase synchronization method based on CAN bus and zero-crossing phase-locked loop as described in claim 1, characterized in that, S4 includes: S41: Self-phase sampling. After the slave device completes delay compensation, it determines its current real-time phase based on the correspondence between the ADC sampling value and the power frequency period. S42: Phase difference judgment. Calculate the error value between its own real-time phase and the zero-crossing phase of the host. When the error value is between 0 and π radians, the slave phase is determined to be ahead. When the error value is between π and 2π radians, the slave phase is determined to be lagging. S43: Step size adjustment is executed. If the current phase step size is ahead, it will be reduced by 30% to 50%; if the current phase step size is lagging, it will be increased by 30% to 50%.

6. The inverter phase synchronization method based on CAN bus and zero-crossing phase-locked loop as described in claim 1, characterized in that, S5 includes: S51: Synchronization status detection. After each step size adjustment, the slave device re-acquires the phase and calculates the error value to monitor the error change trend. S52: Phase-locked loop success determination: When the phase error value is within the threshold range for a consecutive preset number of power frequency cycles, the phase-locked loop is determined to be successful. S53: Stability maintenance mechanism. After successful phase locking, the slave device switches to phase fine-tuning mode, adjusting the phase step size to 10% to 20% of the initial value, and receiving master synchronization information once every preset interval.

7. A phase synchronization method for inverters based on dual-master redundancy, employing the method described in any one of claims 1 to 6, characterized in that, Includes the following steps: S201: Dual-master redundancy initialization configuration, completes the CAN bus initialization of two masters and all slaves, presets redundancy parameters and defines role redundancy relationships; S202: Dual-host phase consistency calibration. After the two hosts are powered on, they exchange zero-crossing phase information and adjust the phase to within the consistency error threshold range. S203: Dual-host synchronization and status monitoring during normal operation. The master host sends synchronization frames and heartbeat frames, the standby host listens and performs secondary phase calibration, and the slave receives synchronization information from the master host. S204: Master host failure switch. After the standby host detects the failure of the master host, it switches to master mode and sends a synchronization frame. The slave device switches to receive the synchronization information of the standby host. S205: Faulty host recovery and redundancy reset. After the faulty host is recovered, the phase is recalibrated with the standby host. The standby host returns the master right and the slave switches back to receiving the original master host synchronization information.

8. The inverter phase synchronization method based on dual-host redundancy according to claim 7, characterized in that, S201 further includes: configuring two hosts with independent and unique device identifiers, pre-setting host priority, primary host heartbeat detection cycle, host fault judgment threshold, dual host phase consistency error threshold and fault switching response time, binding the two hosts as a redundant pair and setting primary and backup roles, and pre-storing dual host device identifiers and priorities on the slave device.

9. The inverter phase synchronization method based on dual-master redundancy according to claim 7, characterized in that, S202 further includes: the primary host sends a calibration frame containing a zero-crossing timestamp and device identifier at the zero-crossing moment; the backup host receives the frame, compensates for the delay, and calculates the phase difference; when the phase difference exceeds the limit, the step size is adjusted until the phase difference is within the threshold range for a consecutive preset number of power frequency cycles.

10. The inverter phase synchronization method based on dual-host redundancy according to claim 7, characterized in that, S204 further includes: when the standby host fails to receive the heartbeat frame from the master host multiple times in a row, or detects a phase change in the synchronization frame exceeding the threshold, it determines that the master host is faulty, sends a fault warning frame, switches to master mode, adds a takeover flag bit to the synchronization frame, and shortens the heartbeat frame period; after the slave receives the warning frame and the takeover synchronization frame, it completes phase fine-tuning and phase-locked loop recovery within two power frequency cycles, and the phase error does not exceed the threshold.

Images