Multi-type hash scheme fusion system and method

Abstract

The invention provides a multi-type Hash scheme fusion system and a multi-type Hash scheme fusion method. The multi-type Hash scheme fusion system comprises: a control module configured to obtain a Hash scheme; decomposing a key generation process and a signature generation process of the Hash scheme into a plurality of Hash tasks; reading intermediate data for executing the Hash task in the storage module; the data preparation module is configured to determine a to-be-executed hash task; obtaining to-be-signed information of the to-be-executed hash task; generating address data of the to-be-executed hash task according to the control information; the Hash operation module is configured to confirm the Hash task type of the Hash task to be executed; determining an input path according to the Hash task type; sending the input data to a corresponding Hash calculation unit through an input path for calculation to obtain a Hash calculation result; and the result output module is configured to output a Hash calculation result so as to solve the problem that most of the existing Hash schemes only support a single Hash algorithm and cannot adapt to diversified scene requirements.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of hardware architecture, and in particular to a multi-type hash scheme fusion system and method. BACKGROUND

[0002] With the rapid development of quantum computing technology, the traditional public key cryptography system is facing a severe threat. In order to resist quantum computing attacks, the post-quantum cryptography (PQC) standardization project is launched. PQC algorithms are mainly divided into five categories: lattice-based, code-based, multivariate-based, isogeny-based and hash-based schemes. Among them, the hash-based signature (HBS) scheme is of great concern due to its security. HBS schemes can be divided into two categories: stateful and stateless. The stateful HBS scheme achieves shorter signature length and higher execution efficiency by maintaining private key state information, but requires strict state management mechanism to prevent key reuse. The stateless HBS scheme does not require state management and has stronger security robustness, but has larger signature length and verification overhead.

[0003] Considering the high similarity of HBS algorithms in structural design and the continuous growth of quantum security requirements, the current fusion of supporting multiple HBS algorithms through a unified hardware architecture can not only flexibly select the optimal algorithm in different application scenarios, but also significantly improve hardware resource utilization and system scalability. There are two related public works for supporting multiple HBS schemes: one is the fusion hardware implementation of LMS and XMSS. This scheme only supports the stateless HBS schemes LMS and XMSS, ignoring the more robust stateful hash schemes such as SPHINCS+, which has limited application scenarios and still has room for performance optimization. The second is the hardware and software co-implementation of the verification process of LMS, XMSS and SPHINCS+. This scheme only focuses on the verification process of HBS and does not involve more complex key and signature generation. Moreover, its software dependency limits its performance.

[0004] In summary, most existing schemes only support a single HBS algorithm implementation and cannot adapt to diverse scenario requirements. Considering the similarity of HBS schemes in structure, if multiple independent hardware modules are integrated to support multiple algorithms, it will cause huge resource waste, higher maintenance cost and lower design efficiency. In addition, for the few existing fusion implementation researches, there are still problems such as limited algorithm support range, incomplete functions, and limited face efficiency ratio. SUMMARY

[0005] The present application provides a multi-type hash scheme fusion system and method to solve the technical problem that most existing hash schemes only support a single hash algorithm implementation and cannot adapt to diverse scenario requirements.

[0006] The first aspect of the application provides a multi-type hash scheme fusion system, comprising: a control module, a storage module, a data preparation module, a hash operation module, and a result output module; The control module is configured to: obtain a hash scheme; the hash scheme comprises a stateful hash scheme and a stateless hash scheme; decompose a key generation process and a signature generation process of the hash scheme into a plurality of hash tasks; read intermediate data for executing the hash tasks in the storage module; send the intermediate data and control information to the data preparation module; the control information comprises a hash task type; The data preparation module is configured to: determine a hash task to be executed; obtain signature information to be executed for the hash task to be executed; generate address data of the hash task to be executed according to the control information, and pack the signature information to be executed, the address data, and the intermediate data into input data and send the input data to the hash operation module; The hash operation module is configured to: confirm a hash task type of the hash task to be executed; determine an input path according to the hash task type; send the input data to a corresponding hash calculation unit through the input path for calculation to obtain a hash calculation result and send the hash calculation result to the result output module; The result output module is configured to: determine whether the hash task to be executed is completed, and if so, output the hash calculation result.

[0007] In some embodiments, the control module comprises: a task scheduling unit, the task scheduling unit being configured to: determine a task algorithm according to the hash task; classify the hash tasks of the same task algorithm; the hash tasks of the same class have the same calculation process; a memory reading unit, the memory reading unit being configured to: read intermediate data for executing the hash tasks in the storage module according to the task algorithm.

[0008] In some embodiments, the data preparation module comprises: a message input unit, the message input unit being configured to: determine a hash task to be executed; obtain the to-be-signed information of the to-be-executed hash task; an address generation unit, configured to: generate address data of the to-be-executed hash task according to the control information, obtain intermediate data required by the to-be-executed hash task, and pack the to-be-signed information, the address data, and the intermediate data into input data and send the input data to the hash operation module.

[0009] In some embodiments, the hash operation module comprises: a hash input unit, configured to: receive the input data of the to-be-executed hash task; confirm the hash task type of the to-be-executed hash task; determine an input path according to the hash task type; send the input data through the input path to a corresponding hash calculation unit for calculation to obtain a hash calculation result and send the hash calculation result to the result output module.

[0010] In some embodiments, the hash input unit comprises: a 64-bit input register, a set-bit special register, and a padding shifter; the 64-bit input register is connected with a first input path, and the set-bit special register is connected with a second input path; the set-bit width of the set-bit special register is consistent with the input bit width of data required by a single calculation of a bottom hash function selected by the hash calculation unit; and the padding shifter is used for padding data.

[0011] In some embodiments, the hash input unit is further configured to: determine the first input path or the second input path according to the hash task type; if the input path is the first input path, slice the input data into a plurality of 64-bit wide slice data and send the slice data to the 64-bit input register, and then send the slice data from the 64-bit input register to the padding shifter, pad the slice data to a set-bit width, and then send the slice data to the hash calculation unit; if the input path is the second input path, pad the input data to a set-bit width to obtain padding data, and then send the padding data to the set-bit special register, and then send the padding data from the set-bit special register to the hash calculation unit.

[0012] In some embodiments, the hash calculation unit is configured to: obtain a calculation flow of the to-be-executed hash task of the type; determining, based on the computing procedure, a number of hash computations for the hash task to be executed; performing hash computation on the input data, and if the number of computations reaches the number of hash computations, obtaining a hash computation result and sending the hash computation result to the result output module.

[0013] In some embodiments, the result output module comprises: an identifier generation unit configured to: determine whether the number of computations of the hash computation result reaches the number of hash computations, and if so, generate a handshake signal; the handshake signal is used to control the data preparation module to determine a next round of hash task to be executed; a memory write unit configured to: send the hash computation result to the storage module.

[0014] In some embodiments, the storage module comprises: a register group, a signature memory, and an intermediate data memory; the register group, the signature memory, and the intermediate data memory are configured to: store the hash computation result; the register group is further configured to store input data; the signature memory is further configured to store a message to be signed; the intermediate data memory is further configured to store intermediate data required by a hash task.

[0015] The second aspect of the present application provides a multi-type hash scheme fusion method, applied to the multi-type hash scheme fusion system of any one of the first aspect, comprising: obtaining a hash scheme; the hash scheme comprises a stateful hash scheme and a stateless hash scheme; decomposing a key generation procedure and a signature generation procedure of the hash scheme into a plurality of hash tasks; reading intermediate data for executing the hash tasks in a storage module; determining a hash task to be executed; obtaining signature information to be signed of the hash task to be executed; generating address data of the hash task to be executed according to the control information, and packaging the signature information to be signed, the address data, and the intermediate data into input data; confirming a hash task type of the hash task to be executed; determining an input path according to the hash task type; send the input data to a corresponding hash calculation unit through the input channel for calculation to obtain a hash calculation result; determine whether the hash task to be executed is completed, and if so, output the hash calculation result.

[0016] The application provides a multi-type hash scheme fusion system and method. The system comprises a control module, a storage module, a data preparation module, a hash operation module and a result output module. The control module is configured to obtain a hash scheme, which comprises a stateful hash scheme and a stateless hash scheme. The key generation process and the signature generation process of the hash scheme are decomposed into a plurality of hash tasks. The intermediate data for executing the hash tasks in the storage module is read. The intermediate data and control information are sent to the data preparation module. The control information comprises a hash task type. The data preparation module is configured to determine a hash task to be executed, obtain signature information to be executed for the hash task to be executed, generate address data for the hash task to be executed according to the control information, and pack the signature information to be executed, the address data and the intermediate data into input data and send the input data to the hash operation module. The hash operation module is configured to determine a hash task type of the hash task to be executed, determine an input channel according to the hash task type, send the input data to a corresponding hash calculation unit through the input channel for calculation to obtain a hash calculation result, and send the hash calculation result to the result output module. The result output module is configured to determine whether the hash task to be executed is completed, and if so, output the hash calculation result. The application solves the problem that the current hash scheme mostly only supports a single hash algorithm implementation and cannot adapt to diversified scene requirements. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the application, the drawings needed in the embodiments will be briefly introduced. Obviously, for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0018] Figure 1 FIG. 1 is a structural schematic diagram of a multi-type hash scheme fusion system in the application; Figure 2 FIG. 2 is a structural schematic diagram of a hash input unit in the application; Figure 3 FIG. 3 is a structural schematic diagram of a hash input unit in an embodiment of the application.

[0019] Explanation of reference signs: 1 - control module; 11 - task scheduling unit; 12 - memory reading unit; 2 - storage module; 21 - register group; 22 - signature memory; 23 - intermediate data memory; 3 - data preparation module; 31 - message input unit; 32 - address generation unit; 4 - hash operation module; 41 - hash input unit; 411 - 64-bit input register; 412 - set bit dedicated register; 413 - padding shifter; 42 - hash calculation unit; 5 - result output module; 51 - identity generation unit; 52 - memory writing unit. DETAILED DESCRIPTION

[0020] In order for those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should fall within the scope of protection of the present application.

[0021] For example, with the rapid development of quantum computing technology, the traditional public key cryptography system is facing severe threats. In order to resist quantum computing attacks, the post-quantum cryptography (PQC) standardization project is launched. PQC algorithms are mainly divided into five categories: lattice-based, code-based, multivariate-based, isogeny-based and hash-based schemes. Among them, the hash-based signature (HBS) scheme is of great concern due to its security. HBS schemes can be divided into stateful and stateless: stateful HBS schemes achieve shorter signature length and higher execution efficiency by maintaining private key state information, but require strict state management mechanisms to prevent key reuse. Among them, LMS and XMSS have been adopted as standardized transitional schemes and standardized by IETF RFC 8554 and RFC 8391, respectively. Stateless HBS schemes do not require state management and have stronger security robustness, but have larger signature length and verification overhead. Among them, SPHINCS+ has become the third round of standardized algorithms and is the only non-lattice-based signature algorithm.

[0022] Considering the high similarity of mainstream HBS algorithms in structural design and the growing demand for quantum security, designing a fusion implementation scheme that can support multiple HBS algorithms on a unified hardware architecture can not only flexibly select the optimal algorithm in different application scenarios, but also significantly improve hardware resource utilization and system scalability. Such a fusion architecture has multiple advantages such as high computational efficiency, strong resource sharing, and superior flexibility. However, existing research mostly focuses on efficient hardware implementation of a single HBS algorithm, i.e., designing independent hardware accelerators for LMS, XMSS, SPHINCS+, etc. Currently, there is still limited public research on the fusion implementation of multiple HBS schemes. Moreover, in actual embedded systems, both stateful and stateless HBS schemes are often required to support high-performance tasks and critical security operations to adapt to diverse scenarios. For such application scenarios that require flexible switching between HBS schemes according to actual needs, existing single-algorithm hardware often has problems such as resource redundancy, complex control, and high design complexity.

[0023] In view of the technical problem that most hash schemes only support a single hash algorithm implementation and cannot adapt to diverse scenario requirements, the present application provides a multi-type hash scheme fusion system and method, which will be described below: As shown in Figure 1 , it is a structural schematic diagram of the multi-type hash scheme fusion system in the present application.

[0024] The first aspect of the present application provides a multi-type hash scheme fusion system, which comprises: a control module 1, a storage module 2, a data preparation module 3, a hash operation module 4, and a result output module 5.

[0025] The control module 1 is configured to: obtain a hash scheme; the hash scheme comprises a stateful hash scheme and a stateless hash scheme; and decompose the key generation process and the signature generation process of the hash scheme into a plurality of hash tasks.

[0026] read intermediate data for executing the hash tasks in the storage module 2; and send the intermediate data and control information to the data preparation module 3; the control information comprises a hash task type. In order to support multiple HBS algorithms in a unified hardware framework, the control module 1 adopts a parameterized reusable control method based on task decomposition, i.e., the key generation and signature generation processes of different HBS schemes are decomposed into multiple shareable hash tasks, which are then uniformly scheduled by the task scheduling unit 11 in the control module 1 according to the specific process of the corresponding algorithm.

[0027] Specifically, the control module 1 comprises: A task scheduling unit 11 configured to: According to the hash task, determine a task algorithm; classify the hash tasks of the same task algorithm; the calculation process of the hash tasks of the same class is the same. In order to realize efficient and flexible implementation of various HBS algorithms, the present application decomposes various stateless and stateful signature algorithms into different parameterized hash tasks, and most tasks can be shared by different HBS schemes. The task scheduling unit 11 in the control module 1 is responsible for uniformly scheduling the above-mentioned parameterized shared tasks to maximize the reuse of hardware resources.

[0028] A memory reading unit 12 configured to: According to the task algorithm, read the intermediate data of the hash task executed in the storage module 2. The memory reading unit 12 in the control module reads the intermediate data required by the currently executed task from the storage module 2. In addition, the control module 1 also needs to transmit the required intermediate data and specific task type control information to the data preparation module 3.

[0029] The storage module 2 includes a register group 21, a signature memory 22 and an intermediate data memory 23. The storage module 2 of the present system includes a register group 21, an intermediate data memory 23 and a signature memory 22, which are respectively used to store input data, intermediate data and final signature results in the algorithm execution process. The control module 1 and the result output module 5 can access the storage module 2, and are respectively responsible for reading the data required by the task and writing the hash output result.

[0030] The register group 21, the signature memory 22 and the intermediate data memory 23 are configured to: Store the hash calculation result.

[0031] The register group 21 is further configured to store input data.

[0032] The signature memory 22 is further configured to store a message to be signed.

[0033] The intermediate data memory 23 is further configured to store intermediate data required by the hash task.

[0034] The data preparation module 3 is configured to: determining a hash task to be executed; obtaining to-be-signed information of the hash task to be executed; generating address data of the hash task to be executed according to the control information, and packing the to-be-signed information, the address data, and intermediate data into input data and sending the input data to the hash operation module 4. The data preparation module 3 includes a message input unit 31 and an address generation unit 32, the former is responsible for receiving an input to-be-signed message, and the latter generates address data required for hash calculation according to control information. Thus, the data preparation module 3 can provide the hash operation module 4 with required input data including to-be-signed messages, intermediate data, and address data according to a specific task type.

[0035] The data preparation module 3 includes: The message input unit 31 is configured to: determining a hash task to be executed; obtaining to-be-signed information of the hash task to be executed.

[0036] The address generation unit 32 is configured to: generating address data of the hash task to be executed according to the control information, obtaining intermediate data required for the hash task to be executed, and packing the to-be-signed information, the address data, and the intermediate data into input data and sending the input data to the hash operation module 4.

[0037] The hash operation module 4 is configured to: confirming a hash task type of the hash task to be executed; determining an input channel according to the hash task type; sending the input data to a corresponding hash calculation unit 42 through the input channel for calculation to obtain a hash calculation result and send the hash calculation result to the result output module 5. After the hash input unit 41 of the hash operation module 4 receives the above data (input data), a corresponding input channel is selected according to a current task type, and corresponding hash input data is transmitted to the hash calculation unit 42. After the hash calculation unit 42 completes corresponding hash calculation, a hash result is output to the result output module 5.

[0038] Specifically, the hash operation module 4 is the operation core of the entire multi-hash fusion architecture, and integrates the hash input unit 41 and the hash calculation unit 42. Since different tasks of the same HBS scheme must be based on the same underlying hash function, and different HBS schemes can be based on the same underlying hash function, different HBS schemes supported by the proposed architecture can share the same hash calculation unit 42, thereby realizing hardware reuse, reducing resource overhead and design complexity. Moreover, the hash calculation unit 42 supports single-core or multi-core hash settings with arbitrary parallelism and arbitrary expansion order, as well as different underlying hash function selections such as SHA-2 and SHA-3, and is more flexible to adapt to different application scenarios.

[0039] As Figure 2 shown, it is a structure schematic diagram of the hash input unit in the present application.

[0040] The hash operation module 4 comprises: A hash input unit 41, configured to: receive the input data of the hash task to be executed; confirm the hash task type of the hash task to be executed; determine an input path according to the hash task type; send the input data to the corresponding hash calculation unit 42 through the input path for calculation, obtain a hash calculation result, and send the hash calculation result to the result output module 5.

[0041] The hash input unit 41 comprises: A 64-bit input register 411, a set bit special register 412, and a padding shifter 413; the 64-bit input register 411 is connected with a first input path, and the set bit special register 412 is connected with a second input path; the set bit width of the set bit special register 412 is consistent with the input bit width of the data required for single calculation of the underlying hash function selected by the hash calculation unit 42; and the padding shifter 413 is used for padding data. Considering that different tasks of the HBS scheme have great differences in the format requirements of input data, the present application provides an asymmetric double-path hash input unit 41. The design provides a special high-speed path (i.e. the path corresponding to the 64-bit input register 411) for the hash chain calculation task with the most frequent calculation and fixed data input format in the mainstream HBS scheme, and provides another path (i.e. the path corresponding to the set bit special register 412) for other tasks, which is more flexible and has higher area efficiency, so as to better balance the area and speed.

[0042] The hash input unit 41 is further configured to: determine the first input path or the second input path according to the hash task type. Through a double-path hash input unit 41, a special path and a flexible resource-optimized path are formed. For the hash chain calculation task, the high-speed special path provides a high-bit-width input register matched with the absorption rate of the underlying hash function, and single-cycle data loading can be realized. For other tasks with less execution times, a flexible special path based on the padding shifter 413 is adopted to avoid the resource and delay overhead caused by a wide multiplexer. Based on this, the hash input unit 41 reduces the area cost as much as possible on the basis of ensuring input flexibility, so that the overall architecture realizes a better area efficiency ratio.

[0043] If the input path is the first input path, the input data is sliced ​​into several 64-bit wide slices and sent to the 64-bit input register 411. The 64-bit input register 411 then sends the slice data to the fill shifter 413, which fills the slice data to a set bit width and then sends it to the hash calculation unit 42.

[0044] If the input path is the second input path, the input data is filled to a set bit width, the filled data is sent to the set bit dedicated register 412, and then the set bit dedicated register 412 sends the filled data to the hash calculation unit 42.

[0045] The hash calculation unit 42 is configured as follows: Obtain the calculation process of the hash task to be executed for this type; based on the calculation process, determine the number of hash calculations for the hash task to be executed; perform hash calculations on the input data, and if the number of calculations reaches the number of hash calculations, obtain the hash calculation result and send it to the result output module 5.

[0046] Specifically, for a dedicated high-speed path for hash chain computation, this application provides a high-width setting bit dedicated register 412. Its bit width matches the input bit width required for a single computation of the underlying hash function selected by the hash computation unit 42. This allows all the data required by the underlying hash function in each hash operation to be loaded into the setting bit dedicated register 412 in parallel at once, achieving fast hash input in a single cycle. Apart from hash chain computation tasks, other tasks have a very low execution frequency, and their input data length and format differ significantly. Therefore, for a general flexible path for other types of hash tasks, this application first divides the input data into 64-bit segments and stores them in a 64-bit input register 411, then outputs the 64-bit input data to a fill shifter 413, thereby dynamically receiving variable-length input data. Similar to the bit width setting of the dedicated bit register 412, the width of the fill shifter 413 also needs to be configured according to the underlying function used by the hash calculation unit 42, so that the total bit width of the fill shifter 413 is consistent with the input bit width of the hash calculation unit 42, ensuring that the input requirements of different hash tasks can be met. Although this dual-path hash input unit 41 introduces a few delay cycles into the hash input process, compared to designing a path for each input format, it avoids a huge multiplexer to maintain the simplicity of the design, thereby significantly saving hardware resources and optimizing layout, routing, and propagation delay.

[0047] The result output module 5 is configured as follows: Determine whether the hash task to be executed has been completed. If so, output the hash calculation result.

[0048] The result output module 5 comprises: An identity generation unit 51 configured to: determine whether the number of hash calculation results reaches the number of hash calculations, and if so, generate a handshake signal; the handshake signal is used to control the data preparation module 3 to determine the next round of hash tasks to be executed. The handshake signal indicates that the current round of hash tasks is completed, and controls the data preparation module 3 to determine the next round of hash tasks to be executed.

[0049] A memory write unit 52 configured to: send the hash calculation result to the storage module 2; and input the hash calculation result into the corresponding position of the storage module 2, including the register group 21, the signature storage 22, and the intermediate data storage 23.

[0050] The present application provides a multi-type hash scheme fusion system, which can uniformly support multiple hash signature schemes on a single hardware platform, and realize flexible switching between stateful and stateless hash signature schemes. The system effectively fills the research gap in this field, and achieves a good balance between security and performance, providing flexible and efficient solutions for various application scenarios with different security levels and performance requirements. The present application divides the processes of multiple HBS schemes into parameterized shareable tasks, and realizes the maximum reuse of hardware resources through unified task scheduling. In addition, the present application introduces an asymmetric double-path hash input logic, which provides a dedicated parallel input path for the hash chain calculation task that is frequently processed and has huge resource consumption in mainstream HBS schemes, and provides a serial input path implemented by a filler shifter for other tasks. Not only does it realize more flexible input control, but it also avoids the resource waste and propagation delay caused by a wide multiplexer.

[0051] As shown in Figure 3 , it is the structure schematic diagram of the hash input unit in an embodiment of the present application.

[0052] The present application provides a multi-type hash scheme fusion system, and the specific implementation is as follows: This example realizes stateless (LMS and XMSS) and stateful (SPHINCS+) HBS schemes through the fusion system provided by the present application. The hash calculation unit 42 in the example adopts a double-parallel two-expansion hash core, selects SHA-3 series SHAKE256 as the underlying hash function, and therefore the hash calculation unit adopts the keccak-p

[1600] permutation function, which requires 1088 bits of input data.

[0053] In this embodiment, the control module decomposes the key generation and signature generation processes of the three HBS schemes into 11 shared tasks (tasks 0-10), which are then uniformly scheduled by the task scheduling unit according to the specific algorithm. Among them, tasks 0, 1, 6, 7, 10 are shared by the three algorithms, corresponding to pseudo-random number generation, message digest calculation, WOTS private key generation, hash chain calculation and Merkle tree node calculation respectively; tasks 2, 4 and 5 are FORS (Forest of Random Subsets) private key / leaf node generation, FORS tree node calculation and FORS public key generation dedicated to SPHINCS+; task 3 is WOTS private key seed generation shared by LMS and XMSS; task 8 is WOTS (Winternitz One Time Signature) public key generation shared by LMS and SPHINCS+; and task 9 is Ltree calculation unique to XMSS. At the same time, the memory reading unit 12 in the control module 1 also reads the intermediate data required by the current task from the storage module 2 as the input data of this hash. The control module 1 transmits the specific task type control information and the read intermediate data to the data preparation module 3.

[0054] The message input unit 31 of the data preparation module 3 receives the externally input message to be signed when performing task 1, and the address generation unit 32 generates address data as the input data of the hash according to the control information. In addition, the intermediate data and part of the control information received by the data preparation module 3 will also be transmitted to the hash operation module 4 as input data according to the specific task requirements.

[0055] In this embodiment, the complete hash operation module 4 is as follows Figure 3The embodiment selects two parallel keccak hash cores with 2 expansion levels as the hash calculation units 42. In order to maximize the reuse of hardware resources, the dedicated high-speed channel of the hash input unit 41 is shared by the two hash cores, and only one 1088-bit dedicated register is needed. However, in order to avoid timing conflicts, the two hash calculation units 42 need to be strictly controlled to be started in sequence. Moreover, since the general flexible channel in this embodiment needs 17 clock cycles to complete the hash input, the present application must set up a separate general flexible channel for each hash core, which is composed of a 64-bit general register and a 1088-bit padding shifter (17x64 bits). When the hash task type is hash chain calculation, the input data is spliced and expanded to 1088 bits to fill the dedicated register, and then the 1088-bit data is input into the hash calculation unit 42 started at the current time to perform keccak calculation with 2 expansion levels, and finally the low 256 bits of the keccak output are taken as the hash output. When performing other types of hash tasks, the input data is divided into 64-bit wide data segments, and is input into the padding shifter 413 through the 64-bit wide general register in sequence until all the valid data is filled, and then the 1088-bit data of the padding shifter is input into the hash calculation unit started at the current time to perform keccak calculation with 2 expansion levels, and finally the low 256 bits of the keccak output are taken as the hash output. After each hash task is completed, the hash operation module 4 transmits the final hash calculation result output to the result output module 5.

[0056] The identification generation unit 51 in the result output module 5 judges whether the task is completed according to the handshake signal. The memory writing unit 52 in the module is responsible for inputting the hash calculation result into the corresponding position in the storage module 2, including the register group 21, the signature storage 22 and the intermediate data storage 23, according to the task completion condition.

[0057] The second aspect of the present application provides a multi-type hash scheme fusion method, which is applied to the multi-type hash scheme fusion system of any of the above embodiments, and includes the following steps: obtaining a hash scheme; the hash scheme includes a stateful hash scheme and a stateless hash scheme; decomposing the key generation process and the signature generation process of the hash scheme into a plurality of hash tasks; reading the intermediate data for executing the hash tasks in the storage module; determining a hash task to be executed; obtaining signature information to be signed of the hash task to be executed; generating address data of the hash task to be executed according to the control information, and packaging the signature information to be signed, the address data and the intermediate data into input data; confirming a hash task type of the hash task to be executed; determining an input path according to the hash task type; sending the input data through the input path to a corresponding hash calculation unit for calculation to obtain a hash calculation result; judging whether the hash task to be executed is completed, and if yes, outputting the hash calculation result.

[0058] It should be noted that the effects of the above method embodiments can be referred to the effects of the above system embodiments, which will not be repeated here.

[0059] The above detailed description of the specific embodiments of the present application has further explained the purposes, technical solutions and beneficial effects of the embodiments of the present application. It should be understood that the above is only a specific embodiment of the present application, and is not used to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made on the basis of the technical solutions of the embodiments of the present application shall be included in the protection scope of the embodiments of the present application.

Claims

1. A multi-type hash scheme fusion system, characterized in that, include: Control module (1), storage module (2), data preparation module (3), hash operation module (4), result output module (5); The control module (1) is configured as follows: Obtain a hash scheme; the hash scheme includes: a stateful hash scheme and a stateless hash scheme; The key generation process and signature generation process of the hash scheme are decomposed into several hash tasks; Read the intermediate data from the storage module (2) used to perform the hash task; The intermediate data and control information are sent to the data preparation module (3); the control information includes: hash task type; The data preparation module (3) is configured as follows: Identify the hash task to be executed; Obtain the signature information of the hash task to be executed; Based on the control information, the address data of the hash task to be executed is generated, and the information to be signed, the address data, and the intermediate data are packaged into input data and sent to the hash operation module (4). The hash operation module (4) is configured as follows: Confirm the hash task type of the hash task to be executed; Determine the input path based on the hash task type; The input data is sent to the corresponding hash calculation unit (42) through the input path for calculation, and the hash calculation result is obtained and sent to the result output module (5). The result output module (5) is configured as follows: Determine whether the hash task to be executed has been completed. If so, output the hash calculation result.

2. The multi-type hash scheme fusion system according to claim 1, characterized in that, The control module (1) includes: Task scheduling unit (11), the task scheduling unit (11) is configured as follows: Based on the hash task, determine the task algorithm; Hash tasks using the same algorithm are grouped together; hash tasks within the same category have the same computation process. Memory read unit (12), the memory read unit (12) being configured to: According to the task algorithm, read the intermediate data of the hash task executed in the storage module (2).

3. The multi-type hash scheme fusion system according to claim 1, characterized in that, The data preparation module (3) includes: Message input unit (31), the message input unit (31) is configured to: Identify the hash task to be executed; Obtain the signature information of the hash task to be executed; Address generation unit (32), the address generation unit (32) is configured to: Based on the control information, the address data for the hash task to be executed is generated. Obtain the intermediate data required for the hash task to be executed, and package the information to be signed, address data, and intermediate data into input data and send it to the hash operation module (4).

4. The multi-type hash scheme fusion system according to claim 1, characterized in that, The hash operation module (4) includes: Hash input unit (41), the hash input unit (41) being configured as follows: Receive the input data for the hash task to be executed; Confirm the hash task type of the hash task to be executed; Determine the input path based on the hash task type; The input data is sent to the corresponding hash calculation unit (42) through the input path for calculation, and the hash calculation result is obtained and sent to the result output module (5).

5. The multi-type hash scheme fusion system according to claim 4, characterized in that, The hash input unit (41) includes: The system includes a 64-bit input register (411), a setting bit dedicated register (412), and a fill shifter (413). The 64-bit input register (411) is connected to the first input path, and the setting bit dedicated register (412) is connected to the second input path. The setting bit width of the setting bit dedicated register (412) is consistent with the input bit width of the data required for a single calculation of the underlying hash function selected by the hash calculation unit (42). The fill shifter (413) is used to fill data.

6. The multi-type hash scheme fusion system according to claim 5, characterized in that, The hash input unit (41) is further configured as follows: Based on the hash task type, determine the first input path or the second input path; If the input path is the first input path, the input data is sliced ​​into several 64-bit wide slice data and sent to the 64-bit input register (411). The 64-bit input register (411) then sends the slice data to the fill shifter (413), fills the slice data to a set bit width, and then sends it to the hash calculation unit (42). If the input path is the second input path, the input data is filled to the set bit width, the filled data is sent to the set bit dedicated register (412), and then the set bit dedicated register (412) sends the filled data to the hash calculation unit (42).

7. The multi-type hash scheme fusion system according to claim 2, characterized in that, The hash calculation unit (42) is configured as follows: Obtain the computation process of the hash task to be executed for this type; Based on the aforementioned calculation process, the number of hash calculations for the hash task to be executed is determined. The input data is hashed. If the number of hash calculations reaches the hash calculation count, the hash calculation result is obtained and sent to the result output module (5).

8. The multi-type hash scheme fusion system according to claim 1, characterized in that, The result output module (5) includes: Identifier generation unit (51), wherein the identifier generation unit (51) is configured to: Determine whether the number of calculations of the hash calculation result has reached the number of hash calculations. If so, generate a handshake signal. The handshake signal is used to control the data preparation module (3) to determine the next round of hash tasks to be executed. Memory write unit (52), the memory write unit (52) is configured to: The hash calculation result is sent to the storage module (2).

9. A multi-type hash scheme fusion system according to claim 1, characterized in that, The storage module (2) includes: Register set (21), signature memory (22) and intermediate data memory (23); The register group (21), signature memory (22), and intermediate data memory (23) are configured as follows: Store the hash calculation result; The register group (21) is also configured to store input data; The signature storage (22) is also configured to store messages to be signed; The intermediate data storage (23) is also configured to store intermediate data required for the hash task.

10. A method for fusing multiple types of hash schemes, applied to a system for fusing multiple types of hash schemes as described in any one of claims 1 to 9, characterized in that, include: Obtain the hash scheme; The hash schemes include: stateful hash schemes and stateless hash schemes; The key generation process and signature generation process of the hash scheme are decomposed into several hash tasks; Read the intermediate data from the storage module used to perform the hash task; Identify the hash task to be executed; Obtain the signature information of the hash task to be executed; Based on the control information, the address data of the hash task to be executed is generated, and the information to be signed, the address data, and the intermediate data are packaged into input data. Confirm the hash task type of the hash task to be executed; Determine the input path based on the hash task type; The input data is sent to the corresponding hash calculation unit through the input path for calculation to obtain the hash calculation result; Determine whether the hash task to be executed has been completed. If so, output the hash calculation result.

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