FC-AE-1553 remote Flash upgrading method, device and equipment based on FPGA and storage medium

Abstract

The invention relates to the technical field of electronic communication, and provides an FC-AE-1553 remote Flash upgrading method, device and equipment based on an FPGA (Field Programmable Gate Array) and a storage medium. The method comprises the following steps: generating a differential upgrading data packet through a ground control end, and carrying out differential calculation on firmware to be upgraded and current firmware to obtain a compressed differential data block; packaging the compressed differential data block into a protocol frame, and sending the protocol frame to an airborne FPGA (Field Programmable Gate Array) through an optical fiber communication link so as to transmit upgrading data to the airborne FPGA and obtain receiving confirmation information; carrying out decryption and signature verification on the received protocol frame by the airborne FPGA, writing data into a backup storage area after verification is passed, and obtaining a writing completion state; and triggering a storage area switching operation according to the write-in completion state, updating a guide address pointer and resetting a system, and completing firmware upgrading. According to the invention, the reliability of the non-contact firmware updating of the sensor network is improved.

Description

Technical Field

[0001] This application relates to the field of electronic communication technology, specifically to a method, apparatus, device, and storage medium for remote Flash upgrade of FC-AE-1553 based on FPGA. Background Technology

[0002] With the rapid development of avionics systems, the need for firmware updates for airborne equipment is becoming increasingly frequent. Traditional avionics firmware upgrades mainly rely on physical contact methods, including offline flashing via JTAG debugging interface, UART serial port, or direct removal of memory chips.

[0003] The existing technology has the following shortcomings: First, the upgrade efficiency is low and heavily reliant on manual operation. Traditional physical contact upgrade methods require maintenance personnel to disassemble equipment one by one and connect programming tools. For large aircraft with dozens of avionics nodes, a complete firmware upgrade can result in downtime of several days, seriously affecting mission continuity and equipment utilization efficiency. Second, the communication reliability is insufficient to adapt to the harsh aviation environment. Existing wireless upgrade solutions mostly use civilian communication protocols, which are prone to data loss or transmission interruption in the aviation environment with strong electromagnetic interference, high vibration, and wide temperature range, failing to meet the high standards of communication reliability required by avionics systems. Third, poor protocol compatibility leads to complex system integration. The existing remote upgrade system does not directly support aviation-specific bus protocols such as FC-AE-1553, requiring the deployment of additional protocol conversion gateway devices, which not only increases hardware costs and system complexity but also introduces additional points of failure. Fourth, the upgrade security mechanism is inadequate. The existing solution is insufficient in terms of data encryption, signature verification, and anti-tampering security measures, making it difficult to resist malicious firmware injection attacks, and it also lacks an effective fault recovery mechanism. Fifth, the single-bank storage architecture cannot guarantee service continuity. Traditional firmware upgrades directly overwrite the running firmware area, requiring the device to stop working during the upgrade process. Furthermore, if the upgrade fails, the system will not be able to start, lacking redundancy protection and atomic switching capabilities. Summary of the Invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a method, apparatus, device and storage medium for FC-AE-1553 remote flash upgrade based on FPGA.

[0005] The first aspect of this invention provides a remote Flash upgrade method based on FPGA for FC-AE-1553, comprising: S1. Generate differential upgrade data packets through the ground control terminal, perform differential calculations between the firmware to be upgraded and the current firmware, and obtain compressed differential data blocks; S2. Encapsulate the compressed differential data block into a protocol frame, and send the protocol frame to the airborne FPGA through an optical fiber communication link to transmit upgrade data to the airborne FPGA and obtain reception confirmation information. S3. The onboard FPGA decrypts and verifies the signature of the received protocol frame. After successful verification, the data is written to the backup storage area to obtain the write completion status. S4. Trigger a storage area switching operation based on the write completion status, update the boot address pointer and reset the system to complete the firmware upgrade.

[0006] According to the FPGA-based FC-AE-1553 remote Flash upgrade method provided by the present invention, step S1 further includes: S11. Obtain the current firmware binary file and the new version firmware binary file, perform a byte-level comparison, and generate a difference location index table; S12. The difference position index table is differentially encoded using the BsDiff algorithm to generate the original difference data; S13. The original differential data is losslessly compressed using the LZ4 compression algorithm to obtain compressed differential data; S14. Divide the compressed differential data into segments according to a preset block size, and assign an incrementing sequence number to each segment to obtain multiple compressed differential data blocks.

[0007] According to the FPGA-based FC-AE-1553 remote Flash upgrade method provided by the present invention, in step S2, when the protocol frame is sent to the airborne FPGA via an optical fiber communication link, a redundant link switching mechanism is adopted, and the redundant link switching mechanism further includes: Configure both the primary fiber optic link and the backup fiber optic link to remain active simultaneously. If the primary link times out without receiving a response frame, record the sequence number of the currently transmitted data block, switch to the backup link, and re-initiate transmission from the recorded sequence number.

[0008] According to the FPGA-based FC-AE-1553 remote Flash upgrade method provided by the present invention, step S2 further includes: S21. Construct the protocol frame header information; S22. Fill the data payload area of ​​the protocol frame with a single compressed differential data block; S23. Perform integrity calculation on the protocol frame using the CRC32 check algorithm, and append the integrity calculation result to the end of the protocol frame to obtain a complete protocol frame. S24. The complete protocol frame is sent to the onboard FPGA via the FC-AE-1553 physical layer interface, and the acknowledgment flag in the returned response frame is monitored. When a denial response is detected, a retransmission mechanism is triggered to obtain the reception confirmation information.

[0009] According to the FPGA-based FC-AE-1553 remote Flash upgrade method provided by the present invention, the protocol frame header information in step S21 includes a synchronization field, a command field, and a data block sequence number, wherein the synchronization field is set as a fixed synchronization identifier.

[0010] According to the FPGA-based FC-AE-1553 remote Flash upgrade method provided by the present invention, step S3 further includes: S31. Extract the encrypted data payload from the received protocol frame; S32. Call the pre-stored round key sequence to perform CBC mode block decryption on the encrypted data payload to obtain plaintext data blocks; S33. Extract digital signature information, verify the signature of the plaintext data block using the ECDSA algorithm, compare the consistency between the hash value and the signature hash value, and obtain the consistency comparison result. S34. When the consistency comparison result is that the signature verification is successful, the target storage address is calculated according to the data block sequence number, and a page write operation is performed to the backup Bank area through the SPI interface to obtain the write completion status.

[0011] According to the FPGA-based FC-AE-1553 remote Flash upgrade method provided by the present invention, step S4 further includes: S41. Perform integrity verification on all data blocks in the backup storage area, calculate the CRC32 checksum for each block and compare it with the original checksum value; S42. After all data blocks pass verification, lock the interrupt response mechanism and suspend peripheral access; S43. Modify the contents of the boot address register, updating the boot pointer from the current firmware storage area address to the starting address of the backup storage area; S44. A hardware reset signal is sent to the FPGA configuration logic. After the system reloads the configuration bitstream, it starts from the new boot address and completes the memory area switch to complete the firmware upgrade.

[0012] A second aspect of the present invention provides an FPGA-based FC-AE-1553 remote Flash upgrade device, comprising: The ground control unit is used to generate differential upgrade data packets and send them via fiber optic link. An onboard FPGA chip, integrating programmable logic resources and a GTX high-speed transceiver, is used to carry upgrade control logic; Dual BankFlash memory, divided into current firmware storage area and backup firmware storage area, is connected to the onboard FPGA chip via SPI interface; The FC-AE-1553 communication module, deployed inside the airborne FPGA chip, includes a protocol parsing unit and a data encapsulation unit, and is used to process Fibre Channel protocol frames. The security verification module, deployed inside the airborne FPGA chip, includes an AES decryption engine and an ECDSA signature verification unit, and is used to perform security verification on the received data. The storage control module, deployed inside the onboard FPGA chip, includes an SPI timing controller and a boot address register, and is used to manage the read, write, and switching operations of the dual-BankFlash memory.

[0013] A third aspect of the present invention provides an FPGA-based FC-AE-1553 remote Flash upgrade device, comprising: A memory and at least one processor, wherein the memory stores instructions; At least one of the processors invokes the instructions in the memory to cause an FPGA-based FC-AE-1553 remote Flash upgrade device to perform an FPGA-based FC-AE-1553 remote Flash upgrade method as described in any of the preceding claims.

[0014] A fourth aspect of the present invention provides a computer-readable storage medium storing instructions that, when executed by a processor, implement a remote Flash upgrade method for FC-AE-1553 based on FPGA as described in any of the preceding claims.

[0015] The FPGA-based FC-AE-1553 remote Flash upgrade method provided by this invention organically combines multiple technical aspects such as differential upgrade data packet generation, fiber optic protocol transmission, airborne decryption and verification, and memory area switching, demonstrating significant comprehensive advantages in high-reliability applications such as aerospace. Secondly, by utilizing the BsDiff algorithm and LZ4 compression technology, this invention significantly reduces the amount of differential data to be transmitted, effectively saving valuable bandwidth resources and significantly shortening the time window required for firmware upgrades, providing strong support for rapid system response and continuous operation. In the data transmission stage, the redundant link switching mechanism combined with CRC32 verification adopted in this invention can monitor the main link status in real time and seamlessly switch to the backup link in case of anomalies. The link, through acknowledgment and automatic retransmission mechanisms, ensures that upgrade data can be delivered completely and reliably even in complex electromagnetic environments, greatly improving the robustness and success rate of the remote upgrade process. At the airborne FPGA end, this invention introduces CBC-based block decryption and ECDSA digital signature verification, providing end-to-end security protection for transmitted data, effectively resisting malicious tampering and illegal injection, and ensuring the integrity and trustworthiness of the airborne firmware. Finally, this invention decouples the upgrade process from system operation through writing to the backup storage area and precise switching of the boot address. In the event of an upgrade failure, it can quickly revert to the original version, minimizing the risk of system downtime due to upgrade errors, thereby comprehensively enhancing the flexibility, security, and availability of system maintenance. Attached Figure Description

[0016] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 A schematic diagram of a remote Flash upgrade method based on FPGA FC-AE-1553 provided for embodiments of this application; Figure 2 This is a schematic diagram of the structure of an FPGA-based FC-AE-1553 remote Flash upgrade system provided in an embodiment of this application. Detailed Implementation

[0017] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0018] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0019] As mentioned in the background section, this application proposes a method, apparatus, device, and storage medium for remote Flash upgrade of FC-AE-1553 based on FPGA.

[0020] like Figure 1 As shown, this invention provides a remote Flash upgrade method for FC-AE-1553 based on FPGA, including: S1. Generate differential upgrade data packets through the ground control terminal, perform differential calculations between the firmware to be upgraded and the current firmware, and obtain compressed differential data blocks.

[0021] Step S1 further includes: S11. Obtain the current firmware binary file and the new version firmware binary file, perform a byte-level comparison, and generate a difference location index table.

[0022] In step S1, the ground control terminal first acquires the current firmware binary file and the new version firmware binary file stored locally. Then, the present invention compares the values ​​of the two binary files byte-by-byte in sequence. When a difference is detected in the value of a certain byte position, the offset address of that byte position is recorded in the difference position index table. The difference position index table adopts a structured storage format, and each record contains three fields: offset address, old byte value, and new byte value. The offset address is represented by a 32-bit unsigned integer, and the byte value is represented by an 8-bit hexadecimal number.

[0023] S12. The difference position index table is differentially encoded using the BsDiff algorithm to generate the original difference data.

[0024] In step S12, the BsDiff algorithm receives a difference position index table as input. The BsDiff algorithm uses the current firmware file as the source data stream and the new firmware file as the target data stream, constructing a string matching index between the two files using a suffix array. Subsequently, the present invention uses the BsDiff algorithm to traverse each byte sequence in the target data stream, searching for the longest common substring in the source data stream, and recording the matching position and matching length. For byte segments that cannot be matched, the algorithm marks them as insertion operations; for redundant byte segments in the source file, it marks them as deletion operations; and for byte segments with offset positions, it marks them as copy operations. The BsDiff algorithm then generates three data blocks: a control block recording the operation type and length, a difference block recording the byte values ​​to be modified, and an extra block recording the new byte sequence to be inserted. These three data blocks are combined to form the original difference data.

[0025] S13. The original differential data is losslessly compressed using the LZ4 compression algorithm to obtain compressed differential data.

[0026] In step S13, the present invention reads the original differential data using the LZ4 compression algorithm and constructs a sliding window dictionary. The algorithm scans the input data stream, calculates the hash value of the current 4-byte sequence as the dictionary index, and queries the dictionary to see if there is a historical sequence with the same hash value. When a matching sequence is found, the algorithm records the offset of the matching position and the matching length, and outputs a reference marker to replace the original byte sequence. For bytes that cannot be matched, the algorithm directly outputs the original literal value. Specifically, a 64KB sliding window is maintained during the compression process, and historical data exceeding the window range is removed from the dictionary. Finally, the compressed differential data output by the algorithm consists of alternating marker bytes and data bytes. The high 4 bits of the marker byte represent the literal value length, and the low 4 bits represent the matching length. The data bytes contain the actual literal value or offset.

[0027] S14. Divide the compressed differential data into segments according to a preset block size, and assign an incrementing sequence number to each segment to obtain multiple compressed differential data blocks.

[0028] In step S14, the present invention reads the total number of bytes of compressed differential data, performs integer division based on a preset block size ranging from 256 bytes to 2048 bytes, and calculates the number of segments. Then, the compressed differential data is sequentially truncated, with each truncated segment equal to the preset block size, and the truncated byte sequence is encapsulated into a data block. Each data block is assigned a 32-bit sequence number starting from 0, and the sequence number is stored together with the data block content, forming multiple compressed differential data blocks. The length of the last data block may be less than the preset block size; therefore, the present invention pads the end of this data block with 0x00 bytes up to the preset block size and records a valid data length field at the beginning of the data block.

[0029] S2. Encapsulate the compressed differential data block into a protocol frame, and send the protocol frame to the airborne FPGA through an optical fiber communication link to transmit upgrade data to the airborne FPGA and obtain reception confirmation information.

[0030] In step S2, when the protocol frame is sent to the airborne FPGA via the optical fiber communication link, a redundant link switching mechanism is adopted. The redundant link switching mechanism further includes: configuring the main optical fiber link and the backup optical fiber link to remain active at the same time; when the main link times out continuously without receiving a response frame, recording the sequence number of the currently transmitted data block, switching to the backup link, and re-initiating transmission from the recorded sequence number.

[0031] Furthermore, in the redundant link switching mechanism, this invention simultaneously configures GTX transceiver channels for both the primary and backup fiber optic links. The primary link channel is bound to the GTX0 interface, and the backup link channel is bound to the GTX1 interface. The clock source, encoding parameters, and transmission rate configurations of the two channels are identical. When sending protocol frames, this invention prioritizes sending data through the primary link channel and simultaneously starts the primary link acknowledgment monitoring timer. If the timer times out three consecutive times without receiving an acknowledgment frame, this invention determines that the primary link is faulty, reads the sequence number field of the currently to-be-sent data block, and stores it in the link switching register. Subsequently, this invention disables the transmission enable signal of the primary link channel, enables the transmission enable signal of the backup link channel, reads the sequence number from the link switching register, locates the corresponding compressed differential data block, and re-executes the protocol frame encapsulation and transmission process from steps S21 to S24 to complete the link switching.

[0032] Step S2 further includes: S21. Construct protocol frame header information; the protocol frame header information includes a synchronization field, a command field, and a data block sequence number, wherein the synchronization field is set to a fixed synchronization identifier.

[0033] In step S21, the present invention allocates a 4-byte buffer to store the synchronization field and writes a fixed synchronization identifier 0xAA55AA55 into the buffer. Then, a 2-byte buffer is allocated to store the command field, and a command code is written according to the current operation type: 0x0001 for an upgrade operation and 0x0002 for a data transmission operation. Next, a 4-byte buffer is allocated to store the data block sequence number, and the 32-bit sequence number of the data block to be sent is written into the buffer in big-endian byte order. Finally, the contents of the synchronization field, command field, and data block sequence number buffers are concatenated sequentially to form a 10-byte protocol frame header.

[0034] S22. Fill a single compressed differential data block into the data payload area of ​​the protocol frame.

[0035] Furthermore, in step S22, the present invention reads the byte content of a single compressed differential data block and measures the actual byte length of the data block. Then, a data payload buffer ranging from 256 bytes to 2048 bytes is allocated, and the data block byte content is written sequentially starting from the beginning of the buffer. After the data writing is complete, the used length of the data payload buffer is calculated, and the protocol frame header information is concatenated with the data payload buffer to form a semi-finished protocol frame containing both a header and payload.

[0036] S23. Perform integrity calculation on the protocol frame using the CRC32 check algorithm, and append the integrity calculation result to the end of the protocol frame to obtain a complete protocol frame.

[0037] In step S23, the CRC32 check algorithm initializes the 32-bit check register to 0xFFFFFFFF. The algorithm reads each byte of the protocol frame semi-finished product, performs an XOR operation between the current byte value and the lower 8 bits of the check register, and uses the result as an index to look up the pre-calculated CRC32 lookup table to obtain the corresponding 32-bit polynomial value. Then, the check register is shifted right by 8 bits and XORed with the polynomial value obtained from the lookup table to update the check register content. After traversing all bytes of the protocol frame semi-finished product, the final value of the check register is bitwise inverted to obtain the CRC32 integrity calculation result. Finally, this invention allocates a 4-byte buffer to store the calculation result, writes the calculation result into the buffer in big-endian byte order, and appends the buffer to the end of the protocol frame semi-finished product to form a complete protocol frame.

[0038] S24. The complete protocol frame is sent to the onboard FPGA via the FC-AE-1553 physical layer interface, and the acknowledgment flag in the returned response frame is monitored. When a denial response is detected, a retransmission mechanism is triggered to obtain the reception confirmation information.

[0039] In step S24, the GTX transceiver of the FC-AE-1553 physical layer interface receives the byte stream of the complete protocol frame. The transceiver groups the byte stream into 8-bit groups, performs 8B / 10B encoding on each group of 8-bit data, inserts 2 redundant bits to generate a 10-bit codeword. The codeword is sequentially converted into a differential electrical signal, driving the optoelectronic conversion module to modulate the electrical signal into a 1.0625Gbps optical signal, which is then transmitted to the onboard FPGA via an optical fiber link. After transmission, this invention starts a timer to monitor the return of the acknowledgment frame. The timer timeout threshold is set to a configurable value within the range of 20 microseconds to 1 millisecond. When an acknowledgment frame is received from the onboard FPGA, this invention parses the status field of the acknowledgment frame and extracts the binary value of the acknowledgment flag. A flag of 0x01 indicates a positive acknowledgment (ACK), and a flag of 0x00 indicates a negative acknowledgment (NAK). When a negative response is detected, the present invention reloads the current complete protocol frame into the transmission buffer, increments the timer timeout value according to the exponential backoff mechanism, and re-executes the transmission operation. When a positive response is detected, the present invention records the response frame status as a received confirmation message, terminates the timer, and clears the transmission buffer.

[0040] S3. The onboard FPGA decrypts and verifies the signature of the received protocol frame. After successful verification, the data is written to the backup storage area, and the write completion status is obtained.

[0041] Step S3 further includes: S31. Extract the encrypted data payload from the received protocol frame.

[0042] In step S31, after the FC-AE-1553 protocol stack of the airborne FPGA receives the complete protocol frame, it first extracts the byte sequence from the 11th byte to the 5th byte from the end of the protocol frame. This sequence is the encrypted data payload. The present invention groups the encrypted data payload into 128-bit groups, and each group of 16 bytes is sequentially input to the data input port of the AES-256 decryption module.

[0043] S32. Call the pre-stored round key sequence to perform CBC mode block decryption on the encrypted data payload to obtain plaintext data blocks.

[0044] In step S32, the AES-256 decryption module reads 15 pre-expanded round keys from the key memory, each round key being 128 bits long. The first stage of the decryption pipeline receives the first 16-byte ciphertext block and the 14th round key, and performs inverse round key addition, XORing each byte of the ciphertext block with the corresponding round key byte. The second to thirteenth stages sequentially perform three transformations: inverse row shift, inverse byte substitution, and inverse column obfuscation, using a round key with a decreasing sequence number at each stage. The inverse row shift transforms each row of the 128-bit state matrix to the right in a circular fashion: the first row shifts by 0 bits, the second by 1 bit, the third by 2 bits, and the fourth by 3 bits. The inverse byte substitution transform queries the inverse S-box table, using each byte value as an index to replace the original byte value with the lookup result. The inverse column obfuscation transforms each column of the state matrix as a polynomial over the GF(2^8) field and performs a modular multiplication with a fixed polynomial. The fourteenth stage performs the final round of reverse shift and reverse byte substitution, and then performs an XOR operation with the round 0 key to output a 16-byte plaintext block. The pipeline processes all 128-bit blocks of the encrypted data payload in sequence, and concatenates the output plaintext blocks in the order of receipt to form a complete plaintext data block.

[0045] S33. Extract digital signature information, verify the signature of the plaintext data block using the ECDSA algorithm, compare the consistency between the hash value and the signature hash value, and obtain the consistency comparison result.

[0046] In step S33, the present invention extracts 64 bytes of digital signature information from the configuration field of the protocol frame. The digital signature contains two 32-byte integers r and s. The ECDSA signature verification module first performs a SHA-256 hash operation on the plaintext data block, dividing the data block into 512-bit groups. Each group undergoes 64 rounds of compression function iteration, outputting a 256-bit hash value as a message digest. Subsequently, the module reads the public key coordinates (Qx, Qy) from the key storage and calculates the elliptic curve dot product operation. The signature verification module calculates w = s^(-1) mod n, where n is the order of the elliptic curve. Then, it calculates u1 = message digest × w mod n, u2 = r × w mod n. The module performs the dot product operation (x1, y1) = u1 × G + u2 × Q, where G is the base point of the elliptic curve and Q is the public key point. Finally, it compares the equality of x1 mod n with the signature value r. If x1 mod n equals r, the signature verification passes; otherwise, the verification fails.

[0047] S34. When the consistency comparison result is that the signature verification is successful, the target storage address is calculated according to the data block sequence number, and a page write operation is performed to the backup Bank area through the SPI interface to obtain the write completion status.

[0048] Further, in step S34, after the signature verification is successful, the present invention reads the sequence number field associated with the plaintext data block, multiplies the sequence number by the preset block size, and calculates the relative offset. Then, it reads the starting physical address 0x01000000 of the backup Bank area, adds the starting address to the relative offset, and obtains the target storage address. Subsequently, the present invention queries the bad block mapping table, which is a 256-bit bitmap, with each bit corresponding to the status of a 4KB sector. The target storage address is shifted right by 12 bits to obtain the sector index, and the value of the corresponding index bit in the bitmap is read; a value of 1 indicates a damaged sector. When a damaged sector is detected, the present invention increments the sector index by 1, recalculates the storage address, and repeats the query until a normal sector is found. After determining the final storage address, the present invention sends a write enable command 0x06 to the Flash via the SPI interface, followed by a page programming command 0x02 and a 24-bit address field. The SPI controller transmits plaintext data blocks byte by byte. Every 256 bytes transmitted, it automatically inserts a write status poll, reads the busy flag in the Flash status register, and waits for the flag to clear before continuing transmission. After all bytes have been written, the SPI controller sends a write disable command 0x04, sets the write completion status flag to 1, and establishes the write completion status.

[0049] In addition, during the data writing process in step S3, the present invention also sets up watchdog timeout monitoring. Specifically, the hardware watchdog counter is initialized, and the timeout threshold is set to 1 second; after each data block is written, a feed signal is sent to reset the counter; when the counter overflows and triggers a timeout event, the progress information saved in the backup partition is read, and subsequent steps are continued from the sequence number of the last successfully written data block.

[0050] S4. Trigger a storage area switching operation based on the write completion status, update the boot address pointer and reset the system to complete the firmware upgrade.

[0051] Step S4 further includes: S41. Perform integrity verification on all data blocks in the backup storage area, calculate the CRC32 checksum for each block and compare it with the original checksum value.

[0052] In step S41, the present invention reads the total number of data blocks recorded from the configuration partition, initializes the checksum counter to 0, and then traverses the backup storage area, reading each data block in ascending sequence order, extracting the 4-byte CRC32 checksum field at the end of the data block. The present invention re-performs CRC32 calculation on the valid data portion of the data block, initializes the checksum register to 0xFFFFFFFF, processes the data block content byte by byte, XORs each byte with the lower 8 bits of the checksum register, and then updates the register by looking up a table. After traversal, the register is inverted to obtain the recalculated checksum. Subsequently, the recalculated checksum is compared with the extracted original checksum using a 32-bit comparison; if the values ​​are equal, the check passes, and the counter is incremented by 1. Finally, after traversing all data blocks, the checksum counter is compared with the total number of data blocks; if they are equal, the integrity check is deemed successful.

[0053] S42. After all data blocks pass verification, lock the interrupt response mechanism and suspend peripheral access.

[0054] Furthermore, in step S42, after the verification passes, the present invention writes a global interrupt mask register to the interrupt controller, setting the register value to 0xFFFFFFFF to disable the response to all peripheral interrupt requests. Subsequently, 0x00 is written to the peripheral access control register to disable the bus access permissions of the DMA controller, timer, and communication interface, ensuring that there is no external interference during subsequent operations.

[0055] S43. Modify the contents of the boot address register, updating the boot pointer from the current firmware storage area address to the starting address of the backup storage area.

[0056] In step S43, the present invention reads the starting address 0x01000000 of the backup storage area, and then writes the 32-bit address value into the data field of the boot address register BOOT_PTR. The register update operation triggers the hardware latching mechanism to latch the new address value into the non-volatile configuration unit. The address value remains unchanged after power failure.

[0057] S44. A hardware reset signal is sent to the FPGA configuration logic. After the system reloads the configuration bitstream, it starts from the new boot address and completes the memory area switch to complete the firmware upgrade.

[0058] In step S44, the present invention writes a reset request bit 0x01 to the system reset control register, triggering a global reset signal on the FPGA. The reset signal clears all register states and resets the configuration state machine to its initial state. Subsequently, the configuration state machine reads a bitstream file from external Flash memory. The read address is provided by the boot address register BOOT_PTR. The state machine accesses address 0x01000000 via the SPI interface, reads the bitstream data sequentially, and loads it into the FPGA's internal configuration RAM. After configuration, the FPGA executes instructions starting from the reset vector address of the new firmware code, completing the firmware boot from the backup storage area and realizing the storage area switch.

[0059] In addition, during the execution of steps S2 to S4, the present invention also simultaneously performs environmental monitoring. Specifically, the FPGA core voltage value and Flash power supply voltage value are collected through an on-chip voltage sensor; the chip junction temperature data is obtained through a temperature sensor; when the voltage deviation exceeds 5% of the rated value or the junction temperature exceeds 85 degrees Celsius, the current data transmission is paused and the sequence number index of the received data block is saved to the configuration partition.

[0060] like Figure 2 As shown, the present invention also provides an FPGA-based FC-AE-1553 remote Flash upgrade device, comprising: Ground control terminal 100 is used to generate differential upgrade data packets and send them via fiber optic link.

[0061] Furthermore, the ground control terminal includes: an upgrade management computer that runs differential algorithm software and generates an encrypted upgrade package; an FC-AE-1553 interface card equipped with a photoelectric conversion module that converts electrical signals into optical signals at a rate of 1.0625Gbps; an optical fiber connector that uses an LC-type multimode optical fiber interface and supports a transmission distance of over 500 meters; and a power management unit that provides stable power to the upgrade management computer and the interface card.

[0062] The onboard FPGA chip 200 integrates programmable logic resources and a GTX high-speed transceiver to carry the upgrade control logic.

[0063] Furthermore, the airborne FPGA chip adopts the Xilinx Kintex-7 series, with no less than 200,000 logic units, no less than 400 built-in Block RAM resources, and integrates at least 4 GTX transceiver channels, with an operating temperature range of -40 degrees Celsius to 125 degrees Celsius.

[0064] The FC-AE-1553 communication module 210, deployed inside the airborne FPGA chip 200, includes a protocol parsing unit and a data encapsulation unit, and is used to process Fibre Channel protocol frames. The security verification module 220, deployed inside the airborne FPGA chip 200, includes an AES decryption engine and an ECDSA signature verification unit, and is used to perform security verification on the received data. The storage control module 230, deployed inside the airborne FPGA chip 200, includes an SPI timing controller and a boot address register, and is used to manage the read, write and switching operations of the dual-BankFlash memory 300.

[0065] The dual-BankFlash memory 300 is divided into a current firmware storage area and a backup firmware storage area, and is connected to the onboard FPGA chip 200 via an SPI interface.

[0066] Furthermore, the dual-bank Flash memory uses NOR flash memory chips with a single chip capacity of no less than 512Mb, supports Quad SPI working mode, and has a write / erase cycle of no less than 100,000 times; the current firmware storage area and the backup firmware storage area each occupy 16MB of space, and an additional 1MB configuration partition is set up for storing key information and status data.

[0067] This invention also provides an FPGA-based FC-AE-1553 remote Flash upgrade device, comprising: A memory and at least one processor, wherein the memory stores instructions; At least one of the processors invokes the instructions in the memory to cause an FPGA-based FC-AE-1553 remote Flash upgrade device to perform an FPGA-based FC-AE-1553 remote Flash upgrade method as described in any of the preceding claims.

[0068] The present invention also provides a computer-readable storage medium storing instructions that, when executed by a processor, implement an FPGA-based FC-AE-1553 remote Flash upgrade method as described in any of the preceding claims.

[0069] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A remote Flash upgrade method based on FPGA for FC-AE-1553, characterized in that, include: S1. Generate differential upgrade data packets through the ground control terminal, perform differential calculations between the firmware to be upgraded and the current firmware, and obtain compressed differential data blocks; S2. Encapsulate the compressed differential data block into a protocol frame, and send the protocol frame to the airborne FPGA through an optical fiber communication link to transmit upgrade data to the airborne FPGA and obtain reception confirmation information. S3. The onboard FPGA decrypts and verifies the signature of the received protocol frame. After successful verification, the data is written to the backup storage area to obtain the write completion status. S4. Trigger a storage area switching operation based on the write completion status, update the boot address pointer and reset the system to complete the firmware upgrade.

2. The FPGA-based FC-AE-1553 remote Flash upgrade method according to claim 1, characterized in that, Step S1 further includes: S11. Obtain the current firmware binary file and the new version firmware binary file, perform a byte-level comparison, and generate a difference location index table; S12. The difference position index table is differentially encoded using the BsDiff algorithm to generate the original difference data; S13. The original differential data is losslessly compressed using the LZ4 compression algorithm to obtain compressed differential data; S14. Divide the compressed differential data into segments according to a preset block size, and assign an incrementing sequence number to each segment to obtain multiple compressed differential data blocks.

3. The FPGA-based FC-AE-1553 remote Flash upgrade method according to claim 1, characterized in that, In step S2, when the protocol frame is sent to the airborne FPGA via the optical fiber communication link, a redundant link switching mechanism is adopted, which further includes: Configure both the primary fiber optic link and the backup fiber optic link to remain active simultaneously. If the primary link times out without receiving a response frame, record the sequence number of the currently transmitted data block, switch to the backup link, and re-initiate transmission from the recorded sequence number.

4. The FPGA-based FC-AE-1553 remote Flash upgrade method according to claim 1, characterized in that, Step S2 further includes: S21. Construct the protocol frame header information; S22. Fill the data payload area of ​​the protocol frame with a single compressed differential data block; S23. Perform integrity calculation on the protocol frame using the CRC32 check algorithm, and append the integrity calculation result to the end of the protocol frame to obtain a complete protocol frame. S24. The complete protocol frame is sent to the onboard FPGA via the FC-AE-1553 physical layer interface, and the acknowledgment flag in the returned response frame is monitored. When a denial response is detected, a retransmission mechanism is triggered to obtain the reception confirmation information.

5. The FPGA-based FC-AE-1553 remote Flash upgrade method according to claim 4, characterized in that, The protocol frame header information in step S21 includes a synchronization field, a command field, and a data block sequence number, wherein the synchronization field is set to a fixed synchronization identifier.

6. The FPGA-based FC-AE-1553 remote Flash upgrade method according to claim 1, characterized in that, Step S3 further includes: S31. Extract the encrypted data payload from the received protocol frame; S32. Call the pre-stored round key sequence to perform CBC mode block decryption on the encrypted data payload to obtain plaintext data blocks; S33. Extract digital signature information, verify the signature of the plaintext data block using the ECDSA algorithm, compare the consistency between the hash value and the signature hash value, and obtain the consistency comparison result. S34. When the consistency comparison result is that the signature verification is successful, the target storage address is calculated according to the data block sequence number, and a page write operation is performed to the backup Bank area through the SPI interface to obtain the write completion status.

7. The FPGA-based FC-AE-1553 remote Flash upgrade method according to claim 1, characterized in that, Step S4 further includes: S41. Perform integrity verification on all data blocks in the backup storage area, calculate the CRC32 checksum for each block and compare it with the original checksum value; S42. After all data blocks pass verification, lock the interrupt response mechanism and suspend peripheral access; S43. Modify the contents of the boot address register, updating the boot pointer from the current firmware storage area address to the starting address of the backup storage area; S44. A hardware reset signal is sent to the FPGA configuration logic. After the system reloads the configuration bitstream, it starts from the new boot address and completes the memory area switch to complete the firmware upgrade.

8. An FPGA-based FC-AE-1553 remote Flash upgrade device, characterized in that, include: The ground control unit is used to generate differential upgrade data packets and send them via fiber optic link. An onboard FPGA chip, integrating programmable logic resources and a GTX high-speed transceiver, is used to carry upgrade control logic; Dual BankFlash memory, divided into current firmware storage area and backup firmware storage area, is connected to the onboard FPGA chip via SPI interface; The FC-AE-1553 communication module, deployed inside the airborne FPGA chip, includes a protocol parsing unit and a data encapsulation unit, and is used to process Fibre Channel protocol frames. The security verification module, deployed inside the airborne FPGA chip, includes an AES decryption engine and an ECDSA signature verification unit, and is used to perform security verification on the received data. The storage control module, deployed inside the onboard FPGA chip, includes an SPI timing controller and a boot address register, and is used to manage the read, write, and switching operations of the dual-BankFlash memory.

9. An FPGA-based FC-AE-1553 remote Flash upgrade device, characterized in that, include: A memory and at least one processor, wherein the memory stores instructions; At least one of the processors invokes the instructions in the memory to cause an FPGA-based FC-AE-1553 remote Flash upgrade device to perform an FPGA-based FC-AE-1553 remote Flash upgrade method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed by a processor, implement an FPGA-based FC-AE-1553 remote Flash upgrade method as described in any one of claims 1 to 7.

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