Self-adaption method and system for megabit optical and gigabit optical Ethernet interfaces, and medium

Abstract

The invention relates to a megabit optical and gigabit optical Ethernet interface self-adaption method and system and a medium, and the method comprises the step of carrying out the rate judgment according to the identification information of a home terminal optical module. Based on the result of the rate judgment, the sending port is initialized to be the gigabit rate, processing logic is started, and the processing logic comprises the 100M processing logic and the gigabit processing logic. The received data is detected through the 100M processing logic, the received data is detected through the gigabit processing logic, and the detection is used for identifying whether the opposite-end equipment supports the 100M rate or the gigabit rate. And based on the detection result, switching the rate of the sending port to match the opposite terminal device. The problem of how to improve self-adaptive compatibility of 100-megabit optical and gigabit optical Ethernet interfaces in the prior art is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of network communication, in particular to a method and system for adapting 100 Mbps and 1000 Mbps Ethernet optical interfaces, and a medium. BACKGROUND

[0002] In current communication network devices (such as OTN, SPN, PTN, IPRAN, etc.) and access terminals, 100 Mbps (FE) and 1000 Mbps (GE) Ethernet optical interfaces coexist widely. In order to improve the compatibility and deployment flexibility of device ports, it has become a key technical requirement to realize automatic identification and adaptation of optical interfaces between different rates. The adaptive Ethernet optical port technology aims to enable the same physical port to intelligently identify the rate of the opposite device and complete dynamic switching.

[0003] In the prior art, the mainstream adaptive schemes mainly include two kinds: one is based on optical module information identification, that is, the type identification of the optical module is read through the I2C bus to judge the supported rate, but this method can only identify the local module and cannot perceive the opposite device capability, the compatibility is low, and if the rates of the two ends do not match, the link cannot be established; the other is based on the IEEE standard auto-negotiation mechanism, which is mature in the application of electrical ports, but in the optical port scene, especially when using SFP optical modules, the negotiation function is often disabled due to non-support or negotiation failure, the compatibility is low, and the reliability is insufficient.

[0004] At present, for the adaptive method of 100 Mbps and 1000 Mbps Ethernet optical interfaces, how to improve the compatibility of the adaptive method of 100 Mbps and 1000 Mbps Ethernet optical interfaces has not yet been proposed an effective solution. SUMMARY

[0005] Embodiments of the present application provide a method and system for adapting 100 Mbps and 1000 Mbps Ethernet optical interfaces, and a medium, to at least solve the problem of how to improve the compatibility of the adaptive method of 100 Mbps and 1000 Mbps Ethernet optical interfaces in related technologies.

[0006] In a first aspect, embodiments of the present application provide a method for adapting 100 Mbps and 1000 Mbps Ethernet optical interfaces, the method comprising: judging the rate according to the identification information of the local optical module; based on the result of the rate judgment, initializing the sending port to a gigabit rate and enabling a processing logic, the processing logic including a 100 Mbps processing logic and a 1000 Mbps processing logic; detecting the received data through the 100 Mbps processing logic and detecting the received data through the 1000 Mbps processing logic, wherein the detection is used to identify whether the opposite device supports the 100 Mbps rate or the 1000 Mbps rate; based on the detection result, switching the rate of the sending port to match the opposite device.

[0007] In an embodiment, the rate judgment according to the identification information of the local optical module comprises: reading the rate identification information of the local optical module through the I2C bus; if the identification information indicates that the optical module supports the 100M rate, configuring the sending port to the 100M rate; if the identification information indicates that the optical module supports the 1000M rate, enabling the processing logic.

[0008] In an embodiment, the initialization of the sending port to the 1000M rate based on the result of the rate judgment comprises: when the judgment result is that the optical module supports the 1000M rate, configuring the sending rate of the SerDes transceiver to the 1000M rate.

[0009] In an embodiment, the detection of the received data through the 100M processing logic comprises: synchronizing the received data at the 1000M rate with the sync word, and performing 8B or 10B decoding, and when the synchronization state machine confirms the lock, obtaining a 1000M synchronization success signal.

[0010] In an embodiment, the detection of the received data through the 1000M processing logic comprises: using oversampling to process the received data at the 1000M rate to restore the data at the 100M rate; performing decoding and link state detection on the data at the 100M rate; when continuously detecting the idle code stream conforming to the standard, obtaining a 100M link success signal.

[0011] In an embodiment, the using of the oversampling to process the received data at the 1000M rate to restore the data at the 100M rate comprises: restoring 1 valid 100M bit data from the 10-bit parallel data output by the SerDes transceiver under the 125MHz clock through a digital logic algorithm.

[0012] In an embodiment, based on the detection result, switching the rate of the sending port to match the opposite end device comprises: continuously polling the states of the 100M link success signal and the 1000M synchronization success signal; if the 100M link success signal is detected to be in the valid state, determining that the opposite end is a 100M device, and switching the rate of the sending port to the 100M rate; if the 1000M synchronization success signal is detected to be in the valid state, determining that the opposite end is a 1000M device, and keeping the rate of the sending port to be the 1000M rate.

[0013] In an embodiment, after switching the rate of the sending port to match the peer device, the method further comprises: disabling the processing logic that does not match the rate of the peer device.

[0014] In a second aspect, the embodiments of the present application provide a 100M optical and 1000M optical Ethernet interface adaptive system, which comprises a rate judging module, an initialization module, a detection module and a switching module; wherein: The rate judging module is configured to judge the rate according to the identification information of the local optical module. The initialization module is configured to initialize the sending port to the 1000M rate and enable the processing logic based on the result of the rate judging, wherein the processing logic comprises 100M processing logic and 1000M processing logic. The detection module is configured to detect the received signal through the 100M processing logic and detect the received signal through the 1000M processing logic, wherein the detection is used to identify whether the peer device supports the 100M rate or the 1000M rate. The switching module is configured to switch the rate of the sending port to match the peer device based on the detection result.

[0015] In a third aspect, the embodiments of the present application provide a computer device, which comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the 100M optical and 1000M optical Ethernet interface adaptive method of the first aspect.

[0016] In a fourth aspect, the embodiments of the present application provide a computer readable storage medium, which stores a computer program executable by a processor to implement the 100M optical and 1000M optical Ethernet interface adaptive method of the first aspect.

[0017] The 100M optical and 1000M optical Ethernet interface adaptive method, system and medium provided by the embodiments of the present application at least have the following technical effects.

[0018] By judging the rate according to the identification information of the optical module at the local end, the accurate pre-configuration of the initial port is realized, and invalid rate attempts are avoided. Based on the result of rate judgment, the sending port is initialized to gigabit rate, and processing logic is enabled, including megabit processing logic and gigabit processing logic, which not only ensures compatibility with high-speed devices, but also creates conditions for detecting low-speed devices. The received data is detected through the megabit processing logic and the received data is detected through the gigabit processing logic. The detection is used to identify whether the opposite device supports megabit rate or gigabit rate, realizing the non-missing identification of megabit and gigabit devices, and significantly improving the detection success rate and response speed. Based on the detection result, the rate of the sending port is switched to match the opposite device, ensuring the rate matching with any opposite device and improving the compatibility of the Ethernet optical interface. The problem of how to improve the compatibility of the gigabit optical and gigabit Ethernet interface adaptation in the related art is solved. BRIEF DESCRIPTION OF DRAWINGS

[0019] The drawings described herein are intended to provide further understanding of the present application, and form a part of the present application. The illustrative embodiments of the present application and their description serve to explain the present application, and do not constitute an improper limitation on the present application. In the drawings: Figure 1 It is a flowchart of a gigabit optical and gigabit Ethernet interface adaptive method; Figure 2 It is a whole flowchart of a gigabit optical and gigabit Ethernet interface adaptive method according to an exemplary embodiment; Figure 3 It is a structural schematic diagram of a gigabit optical and gigabit Ethernet interface adaptive method according to an exemplary embodiment; Figure 4 It is a flowchart of gigabit processing logic in step S103 according to an exemplary embodiment; Figure 5 It is a flowchart of oversampling processing according to an exemplary embodiment; Figure 6 It is a system structure block diagram of a gigabit optical and gigabit Ethernet interface adaptive according to an exemplary embodiment; Figure 7 It is a structural block diagram of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0020] In order to make the purposes, technical solutions, and advantages of the present application clearer, the present application is described and explained below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application and not to limit the present application. Based on the embodiments provided by the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort fall within the scope of the present application.

[0021] It is obvious that the accompanying drawings in the following description are only some examples or embodiments of the present application, and for those of ordinary skill in the art, the present application can be applied to other similar scenarios without creative effort based on the accompanying drawings. In addition, it can be understood that although the efforts made in the development process can be complex and lengthy, for those of ordinary skill in the art related to the content disclosed in the present application, some design, manufacture or production changes based on the technical content disclosed in the present application are only routine technical means and should not be understood as insufficient disclosure of the content disclosed in the present application.

[0022] In the present application, the phrase "embodiments" means that the specific features, structures or properties described in conjunction with the embodiments can be included in at least one embodiment of the present application. The appearance of this phrase at various places in the specification does not necessarily mean the same embodiment, nor is it an independent or alternative embodiment to other embodiments. It is explicitly and implicitly understood by those of ordinary skill in the art that the embodiments described in the present application can be combined with other embodiments without conflict.

[0023] Unless otherwise defined, technical terms and scientific terms used in the present application shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terms "a", "an", "one", "this", and the like, as used in the present application, do not denote a limitation of quantity and can be used in the sense of "one or more". The terms "include", "comprise", "have", and any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or device that comprises a list of steps or modules (units) is not limited to the listed steps or units, but can also include additional steps or units not expressly listed, or can also include steps or units inherent to such process, method, product, or device. The terms "connect", "connected", "coupling", and the like, are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The term "multiple" refers to two or more. The term "and / or" describes an associated relationship between associated objects, indicating that there can be three relationships, for example, "A and / or B" can mean that A exists alone, A and B exist together, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects. The terms "first", "second", "third", and the like, are merely used to distinguish similar objects, and do not represent a specific order for the objects.

[0024] In this document, it should be understood that the terms involved can be technical means or other summary technical terms for implementing part of the present application, for example, the terms can include: Local optical module: refers to an optical module component inserted on the local device, responsible for completing the conversion between electrical signals and optical signals, and is the core device for realizing the physical connection of the Ethernet optical interface.

[0025] Megabit rate: refers to a data transmission rate of 100 Mbps, i.e. 100 million bits per second. In the Ethernet standard, it is referred to as FE (Fast Ethernet).

[0026] Megabit light (megabit optical interface): refers to a Fast Ethernet (FE) optical interface with a rate of 100 Mbps.

[0027] Gigabit rate: refers to a data transmission rate of 1000 Mbps, i.e. 1 billion bits per second. In the Ethernet standard, it is referred to as GE (Gigabit Ethernet).

[0028] Gigabit light (gigabit optical interface): refers to a Gigabit Ethernet (GE) optical interface with a rate of 1000 Mbps.

[0029] SerDes: Serializer / Deserializer, a kind of key integrated circuit, which converts parallel data into serial data stream at the sending end and restores the received serial data stream into parallel data at the receiving end.

[0030] Sync FSM: a kind of finite state machine for link synchronization state control. In the physical layer of Gigabit Ethernet, it monitors the input data stream to find and lock a specific synchronization pattern (such as / K28.5 / ) to confirm that the link has reached symbol synchronization, which is the core logic to determine whether the Gigabit link is successfully established.

[0031] Idle code stream: a specific control character sequence continuously sent by the physical chip when there is no valid data transmission on the link in the Ethernet physical layer. Continuous detection of the standard idle code stream is an important indicator to determine that the physical link has been successfully established and is in a stable idle state.

[0032] In a first aspect, the embodiments of the present application provide a method for adapting 100M optical and 1000M optical Ethernet interfaces, Figure 1 A flowchart of a method for adapting 100M optical and 1000M optical Ethernet interfaces is shown in FIG. 1, which includes the following steps: Figure 1 Step S101: judging the rate according to the identification information of the local optical module.

[0033] Step S102: initializing the sending port to 1000M rate based on the result of the rate judgment, and enabling the processing logic, which includes 100M processing logic and 1000M processing logic.

[0034] Step S103: detecting the received data through 100M processing logic and 1000M processing logic, wherein the detection is used to identify whether the opposite end device supports 100M rate or 1000M rate.

[0035] Step S104: switching the rate of the sending port to match the opposite end device based on the detection result.

[0036] In summary, the embodiments of the present application provide a method for adapting 100M optical and 1000M optical Ethernet interfaces, Figure 2 A flowchart of a method for adapting 100M optical and 1000M optical Ethernet interfaces is shown in FIG. 1, which includes the following steps: Figure 2 ​As shown, by judging the rate according to the identification information of the local optical module, the initial port is accurately pre-configured, and invalid rate attempts are avoided. Based on the result of the rate judgment, the sending port is initialized to gigabit rate, and the processing logic is enabled, including megabit processing logic and gigabit processing logic, which not only ensures compatibility with high-speed devices, but also creates conditions for detecting low-speed devices. The received data is detected through the megabit processing logic and the gigabit processing logic, wherein the detection is used to identify whether the opposite end device supports megabit rate or gigabit rate, realizing the non-missing identification of megabit and gigabit devices, and significantly improving the detection success rate and response speed. Based on the detection result, the rate of the sending port is switched to match the opposite end device, ensuring the rate matching with any opposite end device and improving the compatibility of the Ethernet optical interface. The related technical problem of how to improve the compatibility of the gigabit optical and megabit optical Ethernet interface adaptation is solved.

[0037] In an embodiment, step S101, judging the rate according to the identification information of the local optical module. Specifically, the following steps are included: Step one, read the rate identification information of the local optical module through the I2C bus.

[0038] Step two, if the identification information indicates that the optical module supports megabit rate, the sending port is configured to megabit rate.

[0039] Step three, if the identification information indicates that the optical module supports gigabit rate, the processing logic is enabled.

[0040] Optionally, after the system is powered on or the optical module is detected to be inserted, the identification of the optical module is initialized. The I2C identification module reads the identification information of the optical module through the I2C bus. Rate pre-judgment, if the optical module rate identification is 155Mbps or 125Mbps, it is determined as FE optical module, the system is directly configured to FE mode (sending rate 125Mbps) by the top-level control logic, and only gigabit processing logic can be used. If the optical module rate identification is 1250Mbps, it is determined as GE optical module, and enters the adaptive process (processing logic).

[0041] Step S101 makes initial rate judgment by reading the optical module identification information based on the I2C bus, realizes accurate identification of the local hardware capability in the device startup stage, and establishes an accurate basis for subsequent processing; when it is identified as a hundred megabit module, it is directly configured as a hundred megabit mode, avoiding unnecessary processing flow and improving the link establishment efficiency in such a scene; when it is identified as a gigabit module, the complete processing logic is enabled, and the preparation for the possible connection of hundred megabit or gigabit opposite end devices is made; this hardware identification-based shunt processing mechanism not only ensures the rapid establishment of hundred megabit connection, but also provides the necessary processing basis for adaptive interconnection under gigabit module, and optimizes the device compatibility and connection efficiency as a whole.

[0042] In an embodiment, step S102 initializes the sending port to gigabit rate based on the result of rate judgment, and enables the processing logic, which includes hundred megabit processing logic and gigabit processing logic. Specifically, it includes: When the judgment result is that the optical module supports gigabit rate, the sending rate of the SerDes transceiver is configured to gigabit rate.

[0043] Optionally, the sending rate is initialized. Figure 3 The structure diagram of the adaptive method of the hundred megabit optical and gigabit optical Ethernet interface is shown according to an exemplary embodiment, as shown in Figure 3 The top-level control logic controls the rate control module to initialize the sending rate of the SerDes transceiver to 1250 Mbps (gigabit rate), and simultaneously and in parallel processes the hundred megabit processing logic and the gigabit processing logic in the module.

[0044] Step S102 initializes the sending rate of the SerDes transceiver to gigabit rate when it is identified that the local end is a gigabit optical module, ensuring the best compatibility with high-speed opposite end devices and providing a basis for establishing a high-performance link; at the same time, the hundred megabit and gigabit processing logics are enabled in parallel, creatively realizing the synchronous detection capability of two different rate opposite end devices, avoiding the time delay and missed detection risk caused by traditional serial detection; this combination of high-speed initialization and parallel detection mechanism enables the system to maintain the optimal connection performance with gigabit devices while seamlessly compatible with hundred megabit devices, significantly improving the success rate and response speed of the adaptive process.

[0045] In an embodiment, step S103 detects the received data through the hundred megabit processing logic. Specifically, it includes: The data received at the gigabit rate is subjected to synchronization word alignment and 8B or 10B decoding, and when the synchronization state machine confirms the lock, a gigabit synchronization success signal is obtained.

[0046] Optionally, the data stream is processed by standard Gigabit Ethernet physical layer, including synchronization word alignment and 8B / 10B decoding. When the synchronization state machine (Sync State Machine) confirms the lock, the unit outputs a synchronization success signal sync_ok and places it in the state register module.

[0047] By performing synchronization word alignment and 8B / 10B decoding on the Gigabit rate data in the hundred megabit processing logic, the ability to directly identify the standard Gigabit Ethernet physical layer characteristics in the high-speed data stream is achieved; the synchronization state machine is used for lock confirmation and generates a synchronization success signal, providing a clear and reliable Gigabit link state judgment basis for the system; the accuracy and high reliability of identifying the Gigabit opposite end device are ensured, effectively avoiding misjudgment, and at the same time, the detection results are stored in the state register in real time, providing a stable state input for the rapid decision of the subsequent control logic.

[0048] Figure 4 is a flow chart of the Gigabit processing logic in step S103 according to an exemplary embodiment, as shown in Figure 4 The data received is detected by the Gigabit processing logic in step S103, as shown in the figure. Specifically, the following steps are included: Step S1031, the received data at the Gigabit rate is processed by oversampling to restore the data at the hundred megabit rate. Specifically, the 10-bit parallel data output by the SerDes transceiver under the 125MHz clock is recovered into 1 valid hundred megabit data by a digital logic algorithm.

[0049] Step S1032, the data at the hundred megabit rate is decoded and the link state is detected.

[0050] Step S1033, when the standard idle code stream is continuously detected, a hundred megabit link success signal is obtained.

[0051] Optionally, to solve the problem of mismatch between the sending rate (1250Mbps) and the FE effective rate (125Mbps), Figure 5 is a flow chart of the oversampling processing according to an exemplary embodiment, as shown in Figure 5 The logic oversampling technology is used. Specifically, the 10-bit parallel data output by the SerDes (under the 125MHz clock domain) is regarded as 10 times sampling of 1 FE bit, and 1 valid FE bit data is recovered from it by a digital logic algorithm (such as majority voting), and then 4B / 5B decoding and link state detection are performed. Once the valid IDLE code stream is continuously detected, it is determined that the FE link is successful, the unit outputs a link success signal link_ok and places it in the state register module.

[0052] By using oversampling technology, 10-bit parallel data output by SerDes at 125MHz clock is recovered to 1 valid 100Mbps data, successfully solving the physical layer mismatch between 1000Mbps sending rate and 100Mbps effective rate, realizing accurate extraction of low-speed signal in high-speed data stream; decoding and link state detection are performed on the recovered 100Mbps data, ensuring that data processing conforms to 100Mbps Ethernet protocol specification; by continuously detecting standard-compliant idle code stream to generate 100Mbps link success signal, reliable 100Mbps link establishment judgment basis is provided, ultimately enabling 1000Mbps optical module to accurately identify 100Mbps opposite end device, breaking through the technical obstacle of traditional optical module rate incompatibility.

[0053] In an embodiment, step S104, based on the detection result, switches the sending port rate to match the opposite end device. Specifically, the following steps are included: Step one, continuously polling the status of 100Mbps link success signal and 1000Mbps synchronization success signal; Step two, if the 100Mbps link success signal is detected as valid, it is determined that the opposite end is a 100Mbps device, and the sending port rate is switched to 100Mbps; Step three, if the 1000Mbps synchronization success signal is detected as valid, it is determined that the opposite end is a 1000Mbps device, and the sending port rate is kept at 1000Mbps.

[0054] Optionally, the top-level control logic (a polling state machine) continuously polls the status register module. If the link_ok signal is read as valid, it is determined that the opposite end is an FE interface. The top-level control logic then controls the rate control module to dynamically switch the sending rate of the SerDes transceiver to 125Mbps to match the opposite end. Subsequently, the 100Mbps processing logic unit is optionally disabled to save power consumption. If the sync_ok signal is read as valid, it is determined that the opposite end is a GE interface. The top-level control logic controls the system to keep the sending rate at 1250Mbps. Subsequently, according to the standard auto-negotiation protocol or forced setting, the final switching of the link state is completed, and the 1000Mbps processing logic unit is optionally disabled.

[0055] Step S104 realizes real-time monitoring of the link establishment process by continuously polling the 100M and 1000M link state signals, providing timely and accurate state basis for the rate switching decision; when detecting that the 100M link success signal is valid, the sending port rate is immediately switched to 100M, ensuring that the local device can actively adapt to the low-speed opposite end device, solving the problem that the 1000M module cannot connect to the 100M device in the traditional scheme; and when detecting that the 1000M synchronization signal is valid, the 1000M rate is maintained, ensuring the optimal performance when connecting to the high-speed device; this intelligent rate switching strategy based on real-time detection results not only realizes true physical layer adaptation, but also optimizes system power consumption by subsequently selectively disabling unnecessary processing logic, thereby balancing the best energy efficiency and performance while ensuring compatibility.

[0056] In an embodiment, after switching the rate of the sending port to match the opposite end device, the method further comprises: disabling processing logic that does not match the rate of the opposite end device.

[0057] Optionally, by disabling the processing logic that does not match the rate of the opposite end device after completing the rate matching, unnecessary circuit modules can be actively closed on the basis of ensuring stable link establishment; the dynamic power consumption of the system is effectively reduced, and unnecessary logic operation resource occupation is reduced, thereby significantly improving the energy efficiency ratio of the device in long-term operation.

[0058] In summary, the embodiment of the present application provides a 100M optical and 1000M optical Ethernet interface adaptation method, which realizes accurate pre-configuration of the initial port by judging the rate according to the identification information of the local optical module, avoiding invalid rate attempts. Based on the result of the rate judgment, the sending port is initialized to 1000M rate, and processing logic is enabled, which includes 100M processing logic and 1000M processing logic, ensuring compatibility with high-speed devices and creating conditions for detecting low-speed devices. The received data is detected by 100M processing logic and 1000M processing logic, wherein the detection is used to identify whether the opposite end device supports 100M rate or 1000M rate, realizing non-missing identification of 100M and 1000M devices, significantly improving the detection success rate and response speed. Based on the detection result, the rate of the sending port is switched to match the opposite end device, ensuring rate matching with any opposite end device and improving the compatibility of the Ethernet optical interface. The problem of how to improve the compatibility of the 100M optical and 1000M optical Ethernet interface adaptation in related technologies is solved.

[0059] In a second aspect, the embodiment of the present application provides a 100M optical and 1000M optical Ethernet interface adaptation system. Figure 6 is a system structure block diagram of 100M optical and 1000M optical Ethernet interface adaptation according to an exemplary embodiment. As shown in Figure 6 The system includes a rate judgment module, an initialization module, a detection module, and a switching module; wherein: a rate judgment module, configured to perform rate judgment according to the identification information of the local optical module; an initialization module, configured to initialize the sending port to a gigabit rate based on the result of the rate judgment, and enable processing logic, the processing logic including a megabit processing logic and a gigabit processing logic; a detection module, configured to detect the received signal through the megabit processing logic and the gigabit processing logic, wherein the detection is used to identify whether the opposite end device supports a megabit rate or a gigabit rate; a switching module, configured to switch the rate of the sending port to match the opposite end device based on the detection result.

[0060] To sum up, the application provides a megabit optical and gigabit optical Ethernet interface adaptive system, the rate judgment module, the initialization module, the detection module and the switching module solve how to improve the compatibility of the megabit optical and gigabit optical Ethernet interface adaptation in the related art. Specifically, the initial port is precisely pre-configured by performing rate judgment according to the identification information of the local optical module, and invalid rate attempts are avoided. Based on the result of the rate judgment, the sending port is initialized to a gigabit rate, and processing logic is enabled, the processing logic including a megabit processing logic and a gigabit processing logic, which not only guarantees the compatibility with high-speed devices, but also creates conditions for detecting low-speed devices. The received data is detected through the megabit processing logic and the gigabit processing logic, wherein the detection is used to identify whether the opposite end device supports a megabit rate or a gigabit rate, which realizes the identification of megabit and gigabit devices without omission, and significantly improves the detection success rate and response speed. Based on the detection result, the rate of the sending port is switched to match the opposite end device, which ensures the rate matching with any opposite end device and improves the compatibility of the Ethernet optical interface. The compatibility of the megabit optical and gigabit optical Ethernet interface adaptive is improved in the related art.

[0061] It should be noted that the application provides a megabit optical and gigabit optical Ethernet interface adaptive system for realizing the above-mentioned embodiments, which has been described and will not be repeated. As used above, the terms "module", "unit", "sub-unit" and the like can be a combination of software and / or hardware that realizes a predetermined function. Although the above embodiments describe the device preferably realized in software, the implementation of hardware or a combination of software and hardware is also possible and conceived.

[0062] In a third aspect, the application provides an electronic device, Figure 7 is a block diagram of an electronic device according to an exemplary embodiment. As Figure 7 shown, the electronic device can include a processor 81 and a memory 82 storing computer program instructions.

[0063] In particular, the processor 81 can include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to perform the functions of the embodiments of the present application.

[0064] The memory 82 can include a mass storage for data or instructions. By way of example, and without limitation, the memory 82 can include a hard disk drive (HDD), a floppy disk drive, a solid-state drive (SSD), a flash memory, a compact disk read only memory (CD-ROM), a digital versatile disk (DVD), a tape drive, a USB drive, or a combination of two or more of these. Where appropriate, the memory 82 can include removable or non-removable (or fixed) media. Where appropriate, the memory 82 can be internal or external to the data processing apparatus. In certain embodiments, the memory 82 is a nonvolatile memory. In certain embodiments, the memory 82 includes a read only memory (ROM). Where appropriate, this ROM can be mask programmed ROM, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), electrically alterable ROM (EAROM), or flash memory (FLASH) or a combination of two or more of these. Where appropriate, the ROM can include a combination of these without limitation. Where appropriate, the memory 82 includes a random access memory (RAM). Where appropriate, this RAM can be static random access memory (SRAM) or dynamic random access memory (DRAM), which can be Fast Page Mode Dynamic random access memory (FPMDRAM), Extended Data Output Dynamic random access memory (EDODRAM), synchronous dynamic random access memory (SDRAM), or the like.

[0065] The memory 82 can be used to store or buffer various data files needed for processing and / or communication, and possible computer program instructions executed by the processor 81.

[0066] The processor 81 reads and executes the computer program instructions stored in the memory 82 to implement any one of the above-mentioned Gigabit and 10-Gigabit Ethernet interface adaptive methods.

[0067] In an embodiment, a Gigabit and 10-Gigabit Ethernet interface adaptive device can further include a communication interface 83 and a bus 80. Wherein, as shown in the figure, the processor 81, the memory 82, the communication interface 83 are connected through the bus 80 and complete the communication among each other. Figure 7

[0068] The communication interface 83 is used to realize the communication among various modules, devices, units and / or equipment in the embodiments of the present application. The communication interface 83 can also realize the data communication between other components, such as: external devices, image / data acquisition devices, databases, external storage and image / data processing workstations, etc.

[0069] ​Bus 80 includes hardware, software, or both, to couple various components of a Gigabit and 10-Gigabit Ethernet interface adaptive device to each other. A bus 80 includes, but is not limited to, a data bus, an address bus, a control bus, an expansion bus, a local bus, etc. For example, and not by way of limitation, bus 80 can include an Accelerated Graphics Port (AGP) or other graphics bus, an Extended Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an InfiniBand (IB) interconnect, a Low Pin Count (LPC) bus, a memory bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or another suitable bus or a combination of two or more of these. Where suitable, bus 80 can include one or more buses. Although this application describes and illustrates a particular bus, this application contemplates any suitable bus or interconnect.

[0070] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, having stored thereon a program, wherein the program is executed by a processor to implement the method of the first aspect.

[0071] More specifically, the computer readable storage medium can include, but is not limited to, a portable disc, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0072] In possible implementation manners, the present application can also be implemented in the form of a program product, which comprises program codes for causing a terminal device to perform the steps of the method for realizing the 100M / 1000M optical Ethernet interface adaptation provided by the first aspect when the program product is run on the terminal device.

[0073] The program codes for executing the present application can be written in any combination of one or more programming languages, and can be executed completely on a user device, partially on a user device, as a stand-alone software package, partially on a user device and partially on a remote device, or completely on a remote device.

[0074] The technical features of the above-described embodiments can be combined in any manner. For the sake of brevity, not all possible combinations of the technical features in the above-described embodiments are described, but it should be understood that any combination of the technical features is within the scope of the present disclosure, as long as the combination does not result in contradictions.

[0075] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be noted that, for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present application, and these are within the scope of the present application. Therefore, the scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for adaptive use of 100 Mbps and 1 Gbps optical Ethernet interfaces, characterized in that, The method includes: Rate determination is performed based on the identification information of the local optical module; Based on the result of the rate determination, the sending port is initialized to gigabit speed and the processing logic is enabled, which includes 100 Mbps processing logic and gigabit processing logic. The received data is detected by the 100Mbps processing logic and the received data is detected by the gigabit processing logic, wherein the detection is used to identify whether the peer device supports 100Mbps or gigabit speed. Based on the detection results, the rate of the sending port is switched to match the peer device.

2. The adaptive method for 100Mbps and 1Gbps optical Ethernet interfaces according to claim 1, characterized in that, The process of detecting the received data through the gigabit processing logic includes: Oversampling is used to process data received at gigabit speeds to recover data at 100 Mbps speeds. Decode and detect the link status of the data at the 100 Mbps rate; A 100Mbps link success signal is obtained when a continuous stream of idle data that meets the standard is detected.

3. The adaptive method for 100Mbps and 1Gbps optical Ethernet interfaces according to claim 2, characterized in that, The process of oversampling data received at gigabit speeds to recover data at 100 Mbps includes: The 10-bit parallel data output by the SerDes transceiver at a clock speed of 125MHz is used to recover a valid 100-megabit data using a digital logic algorithm.

4. The adaptive method for 100Mbps and 1Gbps optical Ethernet interfaces according to claim 1, characterized in that, The process of detecting the received data through the 100Mbps processing logic includes: The received data at gigabit speeds is aligned with a synchronization word and decoded using 8B or 10B. When the synchronization state machine confirms the lock, a gigabit synchronization success signal is obtained.

5. The adaptive method for 100 Mbps and 1 Gbps optical Ethernet interfaces according to claim 2 or 4, characterized in that, Based on the detection results, the rate of the transmitting port is switched to match the peer device, including: Continuously poll the status of the 100 Mbps link success signal and the gigabit synchronization success signal; If the 100Mbps link success signal is detected as valid, the peer device is determined to be a 100Mbps device, and the transmission port speed is switched to 100Mbps. If a valid gigabit synchronization success signal is detected, the peer device is determined to be a gigabit device, and the transmission port rate is maintained at gigabit speed.

6. The adaptive method for 100Mbps and 1Gbps optical Ethernet interfaces according to claim 1, characterized in that, The rate determination based on the identification information of the local optical module includes: The rate identification information of the local optical module is read via the I2C bus; If the identification information indicates that the optical module supports a 100 Mbps speed, then the transmitting port will be configured to support a 100 Mbps speed. If the identification information indicates that the optical module supports gigabit speeds, then the processing logic is enabled.

7. The adaptive method for 100Mbps and 1Gbps optical Ethernet interfaces according to claim 1, characterized in that, The initialization of the transmitting port to gigabit speed based on the rate determination result includes: When the determination result indicates that the optical module supports gigabit speeds, the transmission rate of the SerDes transceiver is configured to 1250Mbps.

8. The adaptive method for 100 Mbps and 1 Gbps optical Ethernet interfaces according to claim 1, characterized in that, After switching the rate of the transmitting port to match the peer device, the method further includes: Disable processing logic that is incompatible with the peer device's speed.

9. A system for adaptive use of 100 Mbps and 1 Gbps optical Ethernet interfaces, characterized in that, The system is used to execute the method according to any one of claims 1 to 8, and the system includes a rate determination module, an initialization module, a detection module, and a switching module; wherein: The rate determination module is used to determine the rate based on the identification information of the local optical module. The initialization module is used to initialize the sending port to gigabit speed based on the result of the rate judgment, and enable the processing logic, which includes 100 Mbps processing logic and gigabit processing logic. The detection module is used to detect the received signal through the 100 Mbps processing logic and to detect the received signal through the gigabit processing logic, wherein the detection is used to identify whether the peer device supports the 100 Mbps rate or the gigabit rate. The switching module is used to switch the rate of the sending port to match the peer device based on the detection results.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements an adaptive method for 100 Mbps and 1 Gbps optical Ethernet interfaces as described in any one of claims 1 to 8.

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