Semiconductor device and preparation method thereof, and electronic equipment

Abstract

The invention discloses a semiconductor device, a preparation method thereof and electronic equipment. The preparation method of the semiconductor device comprises the following steps: depositing a first insulating layer on a substrate, and etching to form a plurality of partition walls; alternately growing a semiconductor layer and a sacrificial layer to form a stacked structure; and forming a storage unit based on the stacked structure. The invention relates to but not limited to the technical field of semiconductor devices, in particular to a semiconductor device, a preparation method thereof and electronic equipment, and can solve the problem that dislocation density generated by epitaxial growth of a stacked structure is not ideal.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of semiconductor device technology, and in particular to a semiconductor device and its fabrication method, and electronic equipment. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that small differences in the manufacturing process may affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many memory cells as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] This disclosure provides a semiconductor device and its fabrication method, as well as an electronic device, which can solve the problem of unsatisfactory dislocation density caused by epitaxial growth of stacked structures.

[0005] This exemplary embodiment provides a method for fabricating a semiconductor device, comprising:

[0006] A first insulating layer is deposited on a substrate, and a plurality of partition walls are etched to form the partition walls. The partition walls extend along a first direction and are spaced apart in a second direction. A trench is formed between adjacent partition walls. Both the first direction and the second direction are parallel to the substrate.

[0007] Semiconductor layers and sacrificial layers are grown alternately to form a stacked structure, the stacked structure being located within the trench and / or on the side of the partition wall away from the substrate;

[0008] Storage cells are formed based on the stacked structure.

[0009] In some exemplary embodiments, the alternating growth of semiconductor layers and sacrificial layers to form a stacked structure includes:

[0010] The semiconductor layer and the sacrificial layer are grown alternately and directly on the substrate, and the stacked structure is located within the trench.

[0011] In some exemplary embodiments, the alternating growth of semiconductor layers and sacrificial layers to form a stacked structure includes:

[0012] A buffer layer is deposited on the substrate, the buffer layer being located within the trench;

[0013] The semiconductor layer and the sacrificial layer are alternately grown in the trench, and the stacked structure is located in the trench and on the side of the buffer layer away from the substrate.

[0014] In some exemplary embodiments, the alternating growth of semiconductor layers and sacrificial layers to form a stacked structure includes:

[0015] A buffer layer is deposited on the substrate, wherein the buffer layer is located within the trench and one end away from the substrate is configured to protrude from the partition wall;

[0016] The side of the buffer layer away from the substrate is polished;

[0017] The semiconductor layer and the sacrificial layer are alternately grown on the side of the buffer layer away from the substrate to form the stacked structure.

[0018] In some exemplary embodiments, the distance between two adjacent partition walls is set to D1, the thickness of any semiconductor layer is set to D2, and the thickness of any sacrificial layer is set to D3, wherein the ratio of D2 to D1 is greater than 1, and the ratio of D3 to D1 is greater than 1.

[0019] In some exemplary embodiments, the deposition of the buffer layer on the substrate includes:

[0020] Multiple gradient layers are sequentially deposited on the substrate, wherein the germanium content in the multiple gradient layers is set to increase linearly in the direction away from the substrate;

[0021] A fixing layer is deposited on the side of the gradient layer away from the substrate. The thickness of the fixing layer is greater than the thickness of any of the gradient layers. The germanium content in the fixing layer is set to remain constant along the direction away from the substrate and is greater than the germanium content in any of the gradient layers.

[0022] In some exemplary embodiments, the germanium content in any of the gradient layers is set to be no more than 20%. 8. The method for fabricating a semiconductor device as claimed in claim 2 or 3, characterized in that the step of depositing a first insulating layer on a substrate and etching the first insulating layer to form a plurality of partition walls includes:

[0023] A first insulating layer is deposited on the substrate;

[0024] The first insulating layer is etched to form multiple partition walls and multiple spacer structures, and the multiple spacer structures are disposed in the trench and spaced apart in the first direction.

[0025] In some exemplary embodiments, forming a storage cell based on the stacked structure includes:

[0026] The sacrificial layer is etched away, and the remaining semiconductor layer forms a plurality of semiconductor strips. The plurality of semiconductor strips extend along the first direction and are arranged in an array in the second direction and a third direction, wherein the third direction is perpendicular to the substrate.

[0027] Two support structures are deposited at both ends of the semiconductor strip along a first direction, the support structures being configured to support the semiconductor strip, and a spacer structure being provided between the two support structures;

[0028] The partition wall is etched away, while the partition structure is preserved.

[0029] In some exemplary embodiments, forming a storage cell based on the stacked structure further includes:

[0030] A first element is formed on a semiconductor strip;

[0031] Etching removes the spacer structure, forming a first space within the trench, the first space being configured to divide the semiconductor strip into two semiconductor pillars spaced apart in the first direction;

[0032] A second conductive layer is deposited within the first space to form a bit line.

[0033] In some exemplary embodiments, forming a storage cell based on the stacked structure includes:

[0034] Support structures are deposited at both ends of the stacked structure to form support structures;

[0035] The stacked structure is etched to form multiple semiconductor strips, the extension direction of the semiconductor strips is set to be consistent with the first direction or the second direction, and the support structure is located at both ends of the extension direction of the semiconductor strips;

[0036] Etching removes the sacrificial layer;

[0037] A first element is formed on the semiconductor strip.

[0038] In some exemplary embodiments, each of the semiconductor strips includes two semiconductor pillars arranged sequentially in the extending direction of the semiconductor strip;

[0039] The method of forming a memory cell based on the stacked structure further includes: depositing a second conductive layer at the junction of two semiconductor pillars to form a bit line, wherein the bit line is configured to be shared by a plurality of semiconductor strips arranged sequentially in a third direction, the third direction being perpendicular to the substrate.

[0040] In some exemplary embodiments, forming the first element on the semiconductor strip includes:

[0041] A dielectric layer, a first conductive layer, and a second insulating layer are sequentially deposited on the outer periphery of the semiconductor pillars. The second insulating layer is configured to separate first elements adjacent to each other in the third direction. The first conductive layers on a plurality of semiconductor pillars arranged sequentially in a direction perpendicular to the extension direction are connected to form word lines that are perpendicular to the extension direction and parallel to the substrate.

[0042] This exemplary embodiment provides a semiconductor device, configured to be obtained according to the above-described semiconductor device fabrication method, the semiconductor device comprising:

[0043] Substrate;

[0044] Multiple rows of memory cells, each of the memory cell rows including multiple memory cells stacked upward along a third direction on the substrate, each memory cell including a first element, the first element including a semiconductor pillar and a gate, the semiconductor pillar extending along a first direction or a second direction;

[0045] Multiple bit lines, each extending along a third direction, are arrayed in the first and second directions. Multiple semiconductor pillars stacked at the same position along the third direction share the same bit line. The third direction is perpendicular to the substrate.

[0046] Multiple word lines are provided, the extension direction of which is perpendicular to the extension direction of the semiconductor pillar, and multiple memory cells are arranged at intervals along the extension direction of the word lines. Each word line is formed by connecting the gates of the first elements of multiple memory cells arranged along the extension direction of the word line.

[0047] In some exemplary embodiments, a buffer layer and a partition wall disposed on the substrate are further included. The partition wall is provided in a plurality of such partition walls, which extend along the first direction and are spaced apart in the second direction. The plurality of partition walls are located between the buffer layer and the substrate.

[0048] The plurality of the memory cell columns are located on the side of the buffer layer away from the substrate.

[0049] This exemplary embodiment provides a semiconductor device, including:

[0050] Substrate;

[0051] Multiple partition walls are disposed on the substrate, the multiple partition walls extend along a first direction and are spaced apart in a second direction, and a groove is formed between two adjacent partition walls, the first direction and the second direction are both parallel to the substrate;

[0052] A buffer layer is disposed in the trench, wherein one end of the buffer layer away from the substrate extends to the side of the partition wall away from the substrate, and the side of the buffer layer away from the substrate is parallel to the substrate;

[0053] Multiple rows of storage cells are disposed on the side of the buffer layer away from the substrate.

[0054] In some exemplary embodiments, the buffer layer includes a gradient layer and a fixing layer, wherein the gradient layer is located on the side of the fixing layer closer to the substrate;

[0055] Both the gradient layer and the fixed layer are made of silicon and germanium. The germanium content in the gradient layer is set to increase linearly in the direction away from the substrate, and the germanium content in the fixed layer is set to remain unchanged in the direction away from the substrate and be greater than the germanium content in the gradient layer.

[0056] This exemplary embodiment provides an electronic device, including a semiconductor device obtained by the above-described semiconductor device fabrication method, or including the above-described semiconductor device.

[0057] The semiconductor device fabrication method proposed in this application adds a barrier wall, which can hinder the further propagation of penetrating dislocations, thereby reducing the dislocation density of the sacrificial layer and subsequently reducing the dislocation density of the semiconductor layer. This effectively avoids the problem of increased mismatch dislocation density caused by heteroepitaxial multilayering. The semiconductor device fabrication method of this application, combined with the advantages of a virtual substrate, first epitaxially layers a buffer layer and then other structures, which can reduce stress accumulation. In the semiconductor device fabrication method of this application, the buffer layer has a gradient layer. Within the gradient layer, the lattice mismatch at the interface of different compositions is small, and the dislocation nucleation rate is low. By setting a buffer layer with a gradient composition, the mobility of dislocations is enhanced, thereby causing dislocation lines in different directions to annihilate each other and reducing the dislocation density of the entire epitaxial layer. In the semiconductor device fabrication method of this application, the buffer layer has a fixed layer. The setting of a fixed layer with a large thickness and a fixed germanium content not only ensures the relaxation of the uppermost layer of the buffer layer but also isolates mismatch dislocations from the surface.

[0058] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0059] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0060] Figure 1A schematic cross-sectional view of a semiconductor device according to an exemplary embodiment of this invention;

[0061] Figure 2 for Figure 1 A schematic diagram of the storage cell column;

[0062] Figure 3 for Figure 2 A partial schematic diagram of the first part of the storage cell column;

[0063] Figure 4 for Figure 2 A second partial schematic diagram of the storage cell column in the diagram;

[0064] Figure 5 A schematic diagram of another semiconductor device according to this exemplary embodiment;

[0065] Figure 6 This is a schematic diagram of a preparation method according to an exemplary embodiment of the present invention;

[0066] Figure 7 This is a first schematic diagram of a partition wall according to an exemplary embodiment of the present invention;

[0067] Figure 8 This is a second schematic diagram of a partition wall according to an exemplary embodiment of the present invention;

[0068] Figure 9 This is a first fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention;

[0069] Figure 10 This is a second fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention;

[0070] Figure 11 This is a third fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention;

[0071] Figure 12 This is a fourth fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention;

[0072] Figure 13 This is a fifth fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention;

[0073] Figure 14 A sixth fabrication schematic diagram of a semiconductor device according to this exemplary embodiment;

[0074] Figure 15 A seventh fabrication schematic diagram of a semiconductor device according to this exemplary embodiment;

[0075] Figure 16 This is a schematic diagram of another preparation method of this exemplary embodiment;

[0076] Figure 17 This is an eighth fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention;

[0077] Figure 18 A ninth fabrication schematic diagram of a semiconductor device according to this exemplary embodiment;

[0078] Figure 19 This is a tenth schematic diagram illustrating the fabrication of a semiconductor device according to an exemplary embodiment of the present invention.

[0079] Figure 20 This is an eleventh fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention;

[0080] Figure 21 A schematic diagram illustrating yet another preparation method of this exemplary embodiment;

[0081] Figure 22 This is a schematic diagram illustrating the twelfth fabrication step of a semiconductor device according to an exemplary embodiment of the present invention;

[0082] Figure 23 This is a thirteenth fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention;

[0083] Figure 24 This is a fourteenth fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention;

[0084] Figure 25 This is a fifteenth fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention;

[0085] Figure 26 This is a sixteenth fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention;

[0086] Figure 27 This is a seventeenth fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention;

[0087] Figure 28 This is an eighteenth fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention;

[0088] Figure 29 This is a nineteenth schematic diagram illustrating the fabrication of a semiconductor device according to an exemplary embodiment of the present invention;

[0089] Figure 30 This is a twentieth fabrication schematic diagram of a semiconductor device according to an exemplary embodiment of the present invention;

[0090] Figure 31 This is a schematic diagram of another method for fabricating a semiconductor device according to this exemplary embodiment.

[0091] Figure label:

[0092] 100-Substrate, 200-Memory cell column, 300-Bit line, 400-Word line, 500-Support structure, 600-Buffer layer, 700-Partition wall, 800-Trench, 201-Memory cell, 202-Transistor, 203-Capacitor, 204-Semiconductor pillar, 205-Gate, 206-Source region, 207-Channel region, 208-Drain region, 209-Dielectric layer, 210-Internal electrode plate, 211-... Three insulating layers, 212-external electrode plate, 213-second insulating layer, 214-fourth insulating layer, 603-fixing layer, 604-gradient layer, 605-first gradient layer, 606-second gradient layer, 701-spacer structure, 702-semiconductor layer, 703-sacrificial layer, 704-stacked structure, 705-first gap, 706-semiconductor strip, 707-first conductive layer, 708-first space, 801-first trench. Detailed Implementation

[0093] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0094] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0095] The ordinal numbers such as "first," "second," and "third" in this disclosure are used to avoid confusion among the constituent elements, not to limit the quantity. "Multiple" in this disclosure includes two or more quantities.

[0096] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as appropriate.

[0097] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0098] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0099] In this disclosure, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0100] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components having one or more functions.

[0101] In this disclosure, "parallel" refers to a state in which the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore can include a state in which the angle is greater than or equal to -5° and less than 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore can include a state in which the angle is greater than or equal to 85° and less than 95°.

[0102] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0103] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0104] Currently, in the fabrication of 3D DRAM, silicon (Si) layers and silicon germanium (SiGe) layers need to be grown alternately on the substrate to form a stacked structure. The stacked structure often has defects and dislocations. These dislocations often propagate at a 45° angle to the growth direction. Multilayer heteroepitaxial (SiGe / Si multilayer structure) leads to an excessively high density of mismatched dislocations.

[0105] Figure 1 This is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention. Figure 2 for Figure 1 A schematic diagram of the storage cell column in the image. Figure 3 for Figure 2 A partial schematic diagram of the first part of the storage cell column in the diagram. Figure 4 for Figure 2 A second partial schematic diagram of the memory cell column in the image shows a semiconductor device provided in this embodiment. Figures 1 to 4As shown, the semiconductor device may include a substrate 100, a plurality of memory cell columns 200, a plurality of bit lines 300, and a plurality of word lines 400. Each memory cell column 200 may include a plurality of memory cells 201 spaced apart on the substrate 100 along a third direction perpendicular to the substrate 100. Each memory cell 201 may include a first element 202 and a second element 203. Both the first element 202 and the third element 203 are electronic components. The first element 202 may be a transistor, and the second element 203 may be a transistor or a capacitor. The first element 202 may include a semiconductor pillar 204 and a gate 205. Semiconductor pillars 204 may extend along a first direction. Each semiconductor pillar 204 may include a first source / drain region 206, a channel region 207, and a second source / drain region 208 arranged sequentially along the first direction. A gate 205 may be disposed on the outer periphery of the channel region 207. A second element 203 is configured to surround the outer periphery of the second source / drain region 208 away from the end of the channel region 207. In this example, the second element 203 may be a capacitor, but is not limited thereto. For example, the second element 203 may be a transistor complementary to the first element 202. Multiple bit lines 300 extend along a third direction and are spaced apart in a second direction. Multiple memory cells 201 in two adjacent memory cell columns 200 in the first direction share a bit line 300. Multiple word lines 400 extend along a second direction. Multiple memory cell columns 200 are spaced apart in the second direction. Each word line 400 is formed by connecting the gates 205 of the first element 202 of the multiple memory cells 201 arranged along the second direction.

[0106] In some exemplary embodiments, such as Figures 1 to 4 As shown, substrate 100 can be constructed from semiconductor materials, insulating materials, conductive materials, or any combination thereof. Substrate 100 can be a single-layer structure or a multi-layer structure. For example, substrate 100 can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, for example, substrate 100 can be a layered substrate comprising materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. In this example, substrate 100 can be a silicon substrate.

[0107] In some exemplary embodiments, such as Figures 1 to 4As shown, multiple memory cells 201 in a memory cell column 200 extend along a first direction, and the multiple memory cells 201 in a memory cell column 200 are arranged at equal intervals along a third direction. The first element 202 includes a semiconductor pillar 204 and a gate 205, as well as a dielectric layer 209 located between the semiconductor pillar 204 and the gate 205. The semiconductor pillar 204 can extend along the first direction, and each semiconductor pillar 204 may include a first source / drain region 206, a channel region 207, and a second source / drain region 208 arranged sequentially. The material of the semiconductor pillar 204 may include semiconductor materials, such as silicon, amorphous silicon, polycrystalline silicon, silicon carbide, or monocrystalline silicon, or transition-metal dichalcogenide (TMD) such as molybdenum disulfide (MoS2) or tungsten disulfide (WS2). In this example, the semiconductor pillar 204 can be made of silicon and can be formed by a thin film deposition process, including but not limited to CVD, PVD, ALD, sputtering, evaporation, or combinations thereof. The gate 205 can be disposed on the outer periphery of the channel region 207 of the semiconductor pillar 204. The gate 205 can be made of a metal or metal alloy, such as tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), cobalt (Co), nickel (Ni), titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), AlTi, or any combination thereof, and can also be conductive polycrystalline silicon, polycrystalline germanium, polycrystalline germanium silicon, amorphous silicon, etc. A dielectric layer 209 is sandwiched between the channel region 207 and the gate 205. The dielectric layer 209 can be made of a high-dielectric-constant dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, and / or any combination thereof. The dielectric layer 209 can be formed by one or more suitable deposition processes, such as CVD, PVD, and / or ALD.

[0108] In some exemplary embodiments, such as Figures 1 to 4 As shown, the second element 203 is, for example, a capacitor. The second element 203 is configured to surround the outer periphery of the second source / drain region 208 away from the end of the channel region 207. The second element 203 may include an inner electrode plate 210, a third insulating layer 211, and an outer electrode plate 212 disposed on the outer side of the semiconductor pillar 204. The inner electrode plate 210 and the outer electrode plate 212 may be made of metal or conductive metal compound. In this example, the inner electrode plate 210 and the outer electrode plate 212 may be made of the same material and both may be titanium nitride (TiN). The third insulating layer 211 may be a high dielectric constant dielectric material.

[0109] In some exemplary embodiments, such as Figures 1 to 4As shown, in the multiple memory cells 201, the first element 202 is located on the same side of the corresponding second element 203, and the first elements 202 of the multiple memory cells 201 in a memory cell column 200 correspond one-to-one, and the second elements 203 also correspond one-to-one. In addition, a second insulating layer 213 and a fourth insulating layer 214 are provided between two adjacent memory cells 201 in a memory cell column 200, a second insulating layer 213 is provided between the gates 205 of two adjacent memory cells 201, and a fourth insulating layer 214 is provided between the second elements 203 of two adjacent memory cells 201, which serves as insulation.

[0110] In some exemplary embodiments, such as Figures 1 to 4 As shown, multiple bit lines 300 are provided, each extending in a third direction. The material of the bit lines 300 can be metal; in this example, the material of the bit lines 300 can be tungsten. Multiple memory cells 201 in a memory cell column 200 share a single bit line 300. The first element 202 of each memory cell 201 is located on the side of the second element 203 near the bit line 300. The first source / drain region 206 of the semiconductor pillar 204 is connected to the bit line 300. Two memory cell columns 200 arranged sequentially in the first direction can share a bit line 300. The first source / drain regions 206 of the semiconductor pillars 204 of multiple memory cells 201 in the two memory cell columns 200 are all connected to a bit line 300. However, this is not the only possibility. For example, the two memory cell columns 200 arranged sequentially in the first direction can each be connected to two bit lines 300. That is, multiple memory cells 201 in one memory cell column 200 are connected to one bit line 300, and multiple memory cells 201 in the other memory cell column 200 are connected to another bit line 300.

[0111] In some exemplary embodiments, such as Figures 1 to 4 As shown, the word line 400 can be formed by connecting the gates 205 of multiple first elements 202. Multiple word lines 400 are provided, all extending along the second direction. The material of the word line 400 can be metal. Multiple memory cell columns 200 are arranged at equal intervals along the second direction. Multiple memory cells 201 corresponding to each other in the multiple memory cell columns 200 can be arranged at intervals along the second direction. The gates 205 of the multiple memory cells 201 are connected to form the word line 400. Alternatively, the gates 205 of the multiple memory cells 201 can be understood as part of the word line 400.

[0112] In some exemplary embodiments, such as Figures 1 to 4 As shown, multiple rows of memory cells 200 can be fabricated on a substrate 100. For support during the fabrication process, a support structure 500 is provided on the substrate 100. The support structure 500 can be located at both ends of the multiple rows of memory cells 200 in a first direction. The support structure 500 can be made of an oxide, such as silicon oxide.

[0113] Figure 5 This is a schematic diagram of another semiconductor device according to this exemplary embodiment. In some exemplary embodiments, such as Figure 5 As shown, the semiconductor device also includes a buffer layer 600 and partition walls 700 disposed on a substrate 100. Multiple partition walls 700 are provided, each extending along a first direction and spaced apart in a second direction. The multiple partition walls 700 are located between the buffer layer 600 and the substrate 100. Multiple memory cell columns 200 are located on the side of the buffer layer 600 away from the substrate 100. The partition walls 700 may be made of silicon oxide. Each memory cell column 200 may include multiple memory cells 201 spaced apart along a third direction. Each memory cell 201 may include a first element 202 and a second element 203. The first element 202 may be a transistor and may include a semiconductor pillar 204 and a gate 205. The semiconductor pillar 204 may extend along the second direction. The second element 203 may be a capacitor, but is not limited thereto; for example, the second element 203 may be a transistor complementary to the first element 202. Bit lines 300 extend along a third direction. Multiple memory cells 201 in two adjacent memory cell columns 200 in the second direction share a single bit line 300. However, this is not a limitation; for example, two memory cell columns 200 arranged sequentially in the second direction can each be connected to two bit lines 300, meaning multiple memory cells 201 in one memory cell column 200 are connected to one bit line 300, and multiple memory cells 201 in another memory cell column 200 are connected to another bit line 300. Multiple word lines 400 extend along a first direction, and the multiple memory cell columns 200 are spaced apart in the first direction. Each word line 400 is formed by connecting the gates 205 of the first elements 202 of multiple memory cells 201 arranged along the first direction. Thus, the partition wall 700 and the word lines 400 extend in the same direction (both along the first direction) and are both perpendicular to the extension direction of the semiconductor pillar 204. However, this is not the only possibility. For example, the extending directions of the partition wall 700 and the word line 400 may not be the same (i.e., the extending direction of the partition wall 700 is the first direction, and the extending direction of the word line 400 is the second direction). The extending direction of the partition wall 700 is perpendicular to the extending direction of the semiconductor pillar 204, and the extending direction of the semiconductor pillar 204 is the second direction. In some exemplary embodiments, such as... Figure 5As shown, the buffer layer 600 includes a gradient layer 604 and a fixing layer 603, with the gradient layer 604 located on the side of the fixing layer 603 closest to the substrate 100. Both the gradient layer 604 and the fixing layer 603 are made of silicon-germanium. The germanium content in the gradient layer 604 is set to increase linearly away from the substrate 100. For example, the germanium content at the end of the gradient layer 604 closest to the substrate 100 can be 0, and as it extends away from the substrate 100, the germanium content gradually increases, reaching approximately 20% at the end of the gradient layer 604 furthest from the substrate 100. The gradient layer 604 can be a multilayer stacked structure, i.e., multiple gradient layers 604 are stacked, with a smaller germanium content at the edge of the gradient layer 604 closest to the substrate 100 and a larger germanium content at the edge of the gradient layer 604 furthest from the substrate 100. The germanium content in the fixed layer 603 is set to remain constant along the direction away from the substrate 100, and is a fixed value that is greater than or equal to the maximum value of the germanium content in the gradient layer 604. For example, the germanium content at the end of the gradient layer 604 away from the substrate 100 can be 20%, and the germanium content in the fixed layer 603 can also be 20%.

[0114] Figure 6 This is a schematic diagram of a preparation method of this exemplary embodiment, as shown below. Figure 6 As shown, a method for fabricating a semiconductor device can be applied to, for example... Figure 1 The fabrication method of the semiconductor device shown solves the problem of unsatisfactory dislocation density caused by epitaxial growth of stacked structures formed by alternating silicon and silicon-germanium layers. The fabrication method includes:

[0115] S1: Deposit a first insulating layer on the substrate and etch to form multiple partition walls.

[0116] In some exemplary embodiments, such as Figure 7 and Figure 8 As shown, a first insulating layer is deposited on a substrate, and multiple partition walls are formed by etching. This includes: firstly, depositing the first insulating layer on the substrate 100, and then etching the first insulating layer to form multiple partition walls 700 and multiple spacer structures 701 extending along a second direction. The multiple partition walls 700 all extend along the first direction and are spaced apart in the second direction. A trench 800 is formed between two adjacent partition walls 700. Both the first and second directions are parallel to the substrate 100. The multiple spacer structures 701 and the trenches 800 correspond one-to-one and are configured to divide the trenches 800 into multiple first trenches 801 spaced apart in the first direction. Figure 8 Taking two first grooves 801 as an example. The spacer structure 701 is centrally arranged in the first direction within the groove 800, forming two symmetrical first grooves 801.

[0117] S2: Semiconductor layers and sacrificial layers are alternately grown on the substrate.

[0118] In some exemplary embodiments, such as Figure 9As shown, semiconductor layers and sacrificial layers are alternately grown on a substrate, including: alternatingly growing semiconductor layer 702 and sacrificial layer 703 on substrate 100. Both semiconductor layer 702 and sacrificial layer 703 are grown within trench 800. For example, a sacrificial layer 703 is first grown on substrate 100, and then a semiconductor layer 702 is grown on the side of sacrificial layer 703 away from substrate 100, and so on, alternatingly growing other sacrificial layers 703 and semiconductor layers 702. Semiconductor layer 702 and sacrificial layer 703 are separated into multiple parts by partition walls 700 and spacer structures 701. The material of semiconductor layer 702 may include semiconductor materials, such as silicon, amorphous silicon, polycrystalline silicon, silicon carbide, or monocrystalline silicon, or transition-metal dichalcogenide (TMD) such as molybdenum disulfide (MoS2) or tungsten disulfide (WS2). In this example, the semiconductor layer 702 can be made of silicon (Si) or germanium (Ge). The semiconductor layer 702 can be formed using a thin-film deposition process, including but not limited to CVD, PVD, ALD, sputtering, evaporation, or combinations thereof. The sacrificial layer 703 can be made of silicon-germanium (SiGe), germanium (Ge), or germanium-tin (GeSn). Multiple semiconductor layers 702 and multiple sacrificial layers 703 are stacked to form a silicon (Si) and silicon-germanium (SiGe) stacked structure 704, but not limited to this. For example, a silicon (Si) and germanium (Ge) stacked structure 704 can be formed, or a germanium (Ge) and germanium-tin (GeSn) stacked structure 704 can be formed.

[0119] In some exemplary embodiments, such as Figure 9 As shown, dislocations are prone to occur during the growth of semiconductor layer 702 and sacrificial layer 703. Taking sacrificial layer 703 as an example, the growth direction of sacrificial layer 703 is consistent with the third direction, and the dislocations propagate at a 45° angle to the growth direction of sacrificial layer 703. Figure 9 As shown by the dashed arrow, the partition wall 700 can hinder the further propagation of penetrating dislocations, thereby reducing the dislocation density of the sacrificial layer 703, which in turn reduces the dislocation density of the semiconductor layer 702, thus effectively avoiding the problem of increased mismatch dislocation density caused by heteroepitaxial multilayering.

[0120] In some exemplary embodiments, such as Figure 9As shown, the distance between two adjacent partition walls 700 can be D1, the thickness of any semiconductor layer 702 can be set to D2, and the thickness of any sacrificial layer 703 can be set to D3, wherein the ratio of D2 to D1 is greater than 1, and the ratio of D3 to D1 is greater than 1. The thickness of the sacrificial layer 703 can be the dimension of the sacrificial layer 703 in the third direction, and the thickness of the semiconductor layer 702 can be the dimension of the semiconductor layer 702 in the third direction. For example, the distance between two adjacent partition walls 700 can be D1, such as D1 = 50nm, that is, the trench width of the trench 800 is 50nm. In this case, the thickness of the single semiconductor layer 702 and the single sacrificial layer 703 should be greater than 50nm.

[0121] S3: Etch to remove the sacrificial layer.

[0122] In some exemplary embodiments, such as Figure 9 and Figure 10 As shown, the etching process for removing the sacrificial layer includes: selectively removing all sacrificial layers 703 by etching, retaining the semiconductor layer 702, and forming a first gap 705 in the original space of the sacrificial layer 703.

[0123] In some exemplary embodiments, such as Figure 9 , Figure 10 and Figure 13 As shown, the remaining semiconductor layer 702 forms a plurality of semiconductor strips 706, all of which extend along a first direction. The semiconductor strips 706 are arranged in an array in a second direction and a third direction, the third direction being perpendicular to the substrate 100. Each semiconductor strip 706 includes two semiconductor pillars 204, both of which extend along the first direction and are separated by a spacer structure 701.

[0124] S4: Form a supporting structure.

[0125] In some exemplary embodiments, such as Figure 10 and Figure 11 As shown, forming a support structure includes: depositing support structures 500 at both ends of a semiconductor strip 706 in a first direction, wherein the support structures 500 are configured to support the semiconductor strip 706. The support structures 500 are deposited on a substrate 100, and the material of the support structures 500 may be silicon oxide or the like.

[0126] S5: Remove the partition wall.

[0127] In some exemplary embodiments, such as Figure 11 , Figure 12 and Figure 13As shown, removing the partition wall includes: removing the partition wall 700 by etching, retaining the spacer structure 701, so that the semiconductor strip 706 is exposed, and the support structure 500 and the spacer structure 701 provide support for the semiconductor strip 706 to prevent collapse during the device fabrication process.

[0128] S6: Prepare the first element, the second element, and the word line.

[0129] In some exemplary embodiments, such as Figure 14 As shown, the fabrication of a first element, a second element, and a word line includes: growing a dielectric layer 209 and a first conductive layer 707 on a semiconductor strip 706 to form a first element 202 (transistor) and a word line 400. Specifically, the dielectric layer 209, the first conductive layer 707, and the second insulating layer 213 are sequentially deposited on the outer periphery of the channel region 207 of the semiconductor strip 706. The first conductive layer 707 constitutes the gate 205 of the first element 202 (transistor). The material of the first conductive layer 707 can be a metal or a metal alloy, such as tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), cobalt (Co), nickel (Ni), titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), AlTi, or any combination thereof, and can also be conductive polycrystalline silicon, polycrystalline germanium, polycrystalline germanium silicon, amorphous silicon, etc. The dielectric layer 209 may be made of a high dielectric constant dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, and / or any combination thereof. The dielectric layer 209 may be deposited using one or more suitable deposition processes, such as CVD, PVD, and / or ALD. A second insulating layer 213 is disposed on the first elements 202 adjacent to each other in a third direction. The material of the second insulating layer 213 may include silicon oxide. First conductive layers 707 are connected on a plurality of semiconductor strips 706 arranged sequentially in a second direction to form word lines 400 extending along the second direction.

[0130] In some exemplary embodiments, such as Figure 14As shown, the fabrication of the first element, the second element, and the word line also includes setting the second element 203 (capacitor) on the semiconductor strip 706. An inner electrode plate 210, a third insulating layer 211, and an outer electrode plate 212 are sequentially grown on the outer periphery of the second source / drain region 208 away from the channel region 207, resulting in the second element 203 (capacitor) surrounding the second source / drain region 208 away from the channel region 207. The inner electrode plate 210 and the outer electrode plate 212 can be made of metal or a conductive metal compound. In this example, the inner electrode plate 210 and the outer electrode plate 212 can be made of the same material, both being titanium nitride (TiN). The third insulating layer 211 can be a high-dielectric-constant dielectric material. Subsequently, a fourth insulating layer 214 is deposited between two adjacent second elements 203 (capacitors). The material of the fourth insulating layer 214 may include silicon oxide, and the fourth insulating layer 214 can space the second elements 203 of two adjacent memory cells 201.

[0131] S7: Remove the spacer structure.

[0132] In some exemplary embodiments, such as Figure 14 and Figure 15 As shown, removing the spacer structure 701 includes: removing the spacer structure 701 on the substrate 100 by etching, forming a first space 708 in the original position of the spacer structure 701, and the first space 708 is spaced by two semiconductor pillars 204 arranged correspondingly in a first direction.

[0133] S8: Prepare bit lines.

[0134] In some exemplary embodiments, such as Figure 1 and Figure 15 As shown, the fabrication of the bit line includes: depositing a second conductive layer in the first space 708 to form the bit line 300. The material of the second conductive layer can be a metal, a metallide, or other conductive material. In this example, the material of the second conductive layer can be tungsten, or a composite layer structure formed by tungsten and titanium nitride (TiN) or other conductive materials. This completes the fabrication of the semiconductor device.

[0135] Figure 16 This is a schematic diagram of another preparation method of this exemplary embodiment, as shown below. Figure 16 As shown, a method for fabricating a semiconductor device can be applied to, for example... Figure 1 The fabrication method of the semiconductor device shown solves the problem of unsatisfactory dislocation density caused by epitaxial growth of stacked structures formed by alternating silicon and silicon-germanium layers. Furthermore, by leveraging the advantages of a virtual substrate, epitaxially growing a buffer layer 600 before other structures reduces stress accumulation. The fabrication method includes:

[0136] S1: Deposit a first insulating layer on the substrate and etch to form multiple partition walls.

[0137] In some exemplary embodiments, such as Figure 7 and Figure 8 As shown, a first insulating layer is deposited on a substrate, and a plurality of partition walls are formed by etching. This includes: firstly, depositing the first insulating layer on the substrate 100, and then etching the first insulating layer to form a plurality of partition walls 700 and a plurality of spacer structures 701 extending along a second direction. The plurality of partition walls 700 all extend along the first direction and are spaced apart in the second direction. A trench 800 is formed between two adjacent partition walls 700. Both the first and second directions are parallel to the substrate 100. The plurality of spacer structures 701 and trenches 800 correspond one-to-one and are configured to divide the trenches 800 into a plurality of first trenches 801 spaced apart in the first direction, such as... Figure 8 The diagram shows two first trenches 801. A spacer structure 701 is centrally located within the trench 800 in a first direction, forming two symmetrical first trenches 801.

[0138] S2: Deposit a buffer layer on the substrate.

[0139] In some exemplary embodiments, such as Figure 17 and Figure 18 As shown, depositing a buffer layer on a substrate includes depositing a buffer layer 600 on the substrate 100 and within a trench 800, wherein the material of the buffer layer 600 may include silicon germanium (SiGe).

[0140] In some exemplary embodiments, such as Figure 17 and Figure 18 As shown, the process of depositing the buffer layer 600 can be as follows: First, multiple gradient layers 604 are sequentially deposited on the substrate 100. The multiple gradient layers 604 are stacked in the third direction. The multiple gradient layers 604 are made of the same material, which can all be silicon-germanium. The germanium content in the multiple gradient layers 604 is different and is set to increase linearly along the direction of the substrate 100. For example, the layer of multiple gradient layers 604 closest to the substrate 100 is the first gradient layer 605, and the germanium content of the first gradient layer 605 can be close to 0. The layer of multiple gradient layers 604 furthest from the substrate 100 is the second gradient layer 606, and the germanium content of the second gradient layer 606 can be 20%. The germanium content of the other gradient layers 604 between the first gradient layer 605 and the second gradient layer 606 can increase linearly along the direction away from the substrate 100, with a maximum value close to 20%.

[0141] Subsequently, a fixing layer 603 is deposited on the side of the gradient layer 604 away from the substrate 100. The thickness of the fixing layer 603 is greater than the thickness of any of the gradient layers 604, and the germanium content in the fixing layer 603 is set to a fixed value along the direction away from the substrate 100 and is greater than the germanium content in any of the gradient layers 604. For example, in this example, the germanium content in the fixing layer 603 is 20%.

[0142] In some exemplary embodiments, such as Figure 17 and Figure 18 As shown, within the gradient layer 604, the lattice mismatch at the interfaces of different compositions is small, resulting in a low dislocation nucleation rate. By setting a buffer layer 600 with a compositional gradient, the mobility of dislocations is enhanced, thereby causing dislocation lines in different directions to annihilate each other and reducing the dislocation density of the entire epitaxial layer. The setting of a fixed layer 603 with a relatively large thickness and a fixed germanium content not only ensures relaxation of the uppermost layer of the buffer layer 600 but also isolates mismatched dislocations from the surface.

[0143] S3: Semiconductor layers and sacrificial layers are alternately grown on the buffer layer.

[0144] In some exemplary embodiments, such as Figure 19 As shown, semiconductor layers and sacrificial layers are alternately grown on the buffer layer, including: alternatingly growing semiconductor layer 702 and sacrificial layer 703 on the end face of the buffer layer 600 away from the substrate 100. Both semiconductor layer 702 and sacrificial layer 703 are grown within trench 800. For example, first, a sacrificial layer 703 is grown on the buffer layer 600, this sacrificial layer 703 contacts the buffer layer 600, then a semiconductor layer 702 is grown on the side of the sacrificial layer 703 away from the substrate 100, and so on, alternatingly growing other sacrificial layers 703 and semiconductor layers 702. The semiconductor layer 702 and sacrificial layer 703 are separated into multiple parts by partition walls 700. The semiconductor layer 702 may be made of semiconductor materials, such as silicon, amorphous silicon, polycrystalline silicon, silicon carbide, or monocrystalline silicon, or transition-metal dichalcogenides (TMDs) such as molybdenum disulfide (MoS2) or tungsten disulfide (WS2). In this example, the semiconductor layer 702 may be made of silicon and can be formed by a thin-film deposition process, including but not limited to CVD, PVD, ALD, sputtering, evaporation, or combinations thereof. The sacrificial layer 703 may be made of silicon-germanium (SiGe). Multiple semiconductor layers 702 and multiple sacrificial layers 703 are stacked to form a stacked structure 704.

[0145] In some exemplary embodiments, such as Figure 19 As shown, dislocations are prone to occur during the growth of semiconductor layer 702 and sacrificial layer 703. Taking sacrificial layer 703 as an example, the growth direction of sacrificial layer 703 is consistent with the third direction, and the dislocations propagate at a 45° angle to the growth direction of sacrificial layer 703, just as... Figure 19 As shown by the dashed arrow, the partition wall 700 can hinder the further propagation of penetrating dislocations, thereby reducing the dislocation density of the sacrificial layer 703, which in turn reduces the dislocation density of the semiconductor layer 702, thus effectively avoiding the problem of increased mismatch dislocation density caused by heteroepitaxial multilayering.

[0146] In some exemplary embodiments, such as Figure 19 As shown, the distance between two adjacent partition walls 700 can be D1, the thickness of any semiconductor layer 702 can be set to D2, and the thickness of any sacrificial layer 703 can be set to D3, wherein the ratio of D2 to D1 is greater than 1, and the ratio of D3 to D1 is greater than 1. The thickness of the sacrificial layer 703 can be the dimension of the sacrificial layer 703 in the third direction, and the thickness of the semiconductor layer 702 can be the dimension of the semiconductor layer 702 in the third direction. For example, the distance between two adjacent partition walls 700 can be D1, such as D1 = 50nm, that is, the trench width of the trench 800 is 50nm. In this case, the thickness of the single semiconductor layer 702 and the single sacrificial layer 703 should be greater than 50nm.

[0147] S4: Etch to remove the sacrificial layer and buffer layer.

[0148] In some exemplary embodiments, such as Figure 19 and Figure 20 As shown, etching removes the sacrificial layer and the buffer layer, including: selectively removing all sacrificial layers 703 by etching, then etching removes the buffer layer 600, leaving the semiconductor layer 702.

[0149] In some exemplary embodiments, such as Figure 19 , Figure 20 and Figure 13 As shown, the remaining semiconductor layer 702 forms a plurality of semiconductor strips 706, all of which extend along a first direction. The semiconductor strips 706 are arranged in an array in a second direction and a third direction, the third direction being perpendicular to the substrate 100. Each semiconductor strip 706 includes two semiconductor pillars 204, both of which extend along the first direction and are separated by a spacer structure 701.

[0150] S5: Form a supporting structure.

[0151] In some exemplary embodiments, such as Figure 10 and Figure 11 As shown, forming a support structure includes: depositing support structures 500 at both ends of a semiconductor strip 706 along a first direction, wherein the support structures 500 are configured to support the semiconductor strip 706. The support structures 500 are deposited on a substrate 100, and the material of the support structures 500 may be silicon nitride.

[0152] S6: Remove the partition wall.

[0153] In some exemplary embodiments, such as Figure 11 , Figure 12 and Figure 13As shown, removing the partition wall includes: removing the partition wall 700 on the substrate 100 by etching, retaining the spacer structure 701, so that the semiconductor strip 706 is exposed, and the support structure 500 and the spacer structure 701 provide support for the semiconductor strip 706 to prevent it from collapsing during the formation of the semiconductor device.

[0154] S7: Prepare the first element, the second element, and the word line.

[0155] In some exemplary embodiments, such as Figure 14 As shown, the fabrication of a first element, a second element, and a word line includes: growing a dielectric layer 209 and a first conductive layer on a semiconductor strip 706 to form a first element 202 (transistor) and a word line 400. Specifically, a dielectric layer 209, a first conductive layer 707, and a second insulating layer 213 are sequentially deposited on the outer periphery of the channel region 207 of the semiconductor strip 706. The first conductive layer 707 constitutes the gate 205 of the first element 202 (transistor). The material of the first conductive layer 707 can be a metal or a metal alloy, such as tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), cobalt (Co), nickel (Ni), titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), AlTi, or any combination thereof, and can also be conductive polycrystalline silicon, polycrystalline germanium, polycrystalline germanium silicon, amorphous silicon, etc. The dielectric layer 209 may be made of a high dielectric constant dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, and / or any combination thereof. The dielectric layer 209 may be deposited using one or more suitable deposition processes, such as CVD, PVD, and / or ALD. A second insulating layer 213 is disposed on the first elements 202 adjacent to each other in a third direction. The material of the second insulating layer 213 may include silicon oxide. First conductive layers 707 are connected on a plurality of semiconductor strips 706 arranged sequentially in a second direction to form word lines 400 extending along the second direction.

[0156] In some exemplary embodiments, such as Figure 14As shown, the fabrication of the first element, the second element, and the word line also includes setting the second element 203 (capacitor) on the semiconductor strip 706. An inner electrode plate 210, a third insulating layer 211, and an outer electrode plate 212 are sequentially grown on the outer periphery of the second source / drain region 208 away from the channel region 207, resulting in the second element 203 (capacitor) surrounding the second source / drain region 208 away from the channel region 207. The inner electrode plate 210 and the outer electrode plate 212 can be made of metal or a conductive metal compound. In this example, the inner electrode plate 210 and the outer electrode plate 212 can be made of the same material, both being titanium nitride (TiN). The third insulating layer 211 can be a high dielectric material. Subsequently, a fourth insulating layer 214 is deposited between two adjacent second elements 203 (capacitors). The material of the fourth insulating layer 214 may include silicon oxide, and the fourth insulating layer 214 can space the second elements 203 (capacitors) between two adjacent memory cells 201.

[0157] S8: Remove the spacer structure.

[0158] In some exemplary embodiments, such as Figure 14 and Figure 15 As shown, removing the spacer structure includes: removing the spacer structure 701 on the substrate 100 by etching, forming a first space 708 in the original position of the spacer structure 701, and the first space 708 is spaced by two semiconductor pillars 204 arranged correspondingly in a first direction.

[0159] S9: Prepare bit lines.

[0160] In some exemplary embodiments, such as Figure 1 and Figure 15 As shown, the fabrication of the bit line includes: depositing a second conductive layer in the first space 708 to form the bit line 300. The material of the second conductive layer can be a metal, a metallide, or other conductive material. In this example, the material of the second conductive layer can be tungsten, or a composite layer structure formed by tungsten and conductive materials such as titanium nitride (TiN). Thus, the bit line 300 is fabricated. Figure 1 The fabrication of the semiconductor device shown.

[0161] Figure 21 This is a schematic diagram of another preparation method of this exemplary embodiment, as shown below. Figure 21 As shown, a method for fabricating a semiconductor device can be applied to, for example... Figure 5 The fabrication method of the semiconductor device shown solves the problem of unsatisfactory dislocation density caused by epitaxial growth of stacked structures formed by alternating silicon and silicon-germanium layers. Furthermore, by leveraging the advantages of a virtual substrate, epitaxially growing a buffer layer 600 before other structures reduces stress accumulation. The fabrication method includes:

[0162] S1: Deposit a first insulating layer on the substrate and etch to form multiple partition walls.

[0163] In some exemplary embodiments, such as Figure 22 and Figure 23 As shown, a first insulating layer is deposited on a substrate, and multiple partition walls are etched to form the partitions. This includes: firstly, depositing the first insulating layer on the substrate 100, and then etching the first insulating layer to form multiple partition walls 700. The multiple partition walls 700 extend along a first direction and are spaced apart in a second direction. A trench 800 is formed between two adjacent partition walls 700. Both the first and second directions are parallel to the substrate 100, and the trench 800 penetrates the first insulating layer in the first direction. However, this is not limited to this method. For example, the etched multiple partition walls 700 may partially extend along the first direction and partially extend along the second direction, with the two parts intersecting. Alternatively, the etched multiple partition walls 700 may all extend along the second direction and be spaced apart in the first direction.

[0164] S2: Deposit a buffer layer on the substrate.

[0165] In some exemplary embodiments, such as Figure 24 and Figure 25 As shown, depositing a buffer layer on a substrate includes depositing a buffer layer 600 on the substrate 100 and within a trench 800, wherein the material of the buffer layer 600 may include silicon germanium (SiGe).

[0166] In some exemplary embodiments, such as Figure 24 and Figure 25 As shown, the process of depositing the buffer layer 600 can be as follows: First, multiple gradient layers 604 are sequentially deposited on the substrate 100. The multiple gradient layers 604 are stacked in the third direction. The multiple gradient layers 604 are made of the same material, which can all be silicon-germanium. The germanium content in the multiple gradient layers 604 is different and is set to increase linearly along the direction of the substrate 100. For example, the layer of multiple gradient layers 604 closest to the substrate 100 is the first gradient layer 605, and the germanium content of the first gradient layer 605 can be close to 0. The layer of multiple gradient layers 604 furthest from the substrate 100 is the second gradient layer 606, and the germanium content of the second gradient layer 606 can be 20%. The germanium content of the other gradient layers 604 between the first gradient layer 605 and the second gradient layer 606 can increase linearly along the direction away from the substrate 100, with a maximum value close to 20%. Multiple gradient layers 604 are located within the trench 800, and the end face of the second gradient layer 606 away from the substrate is flush with the end face of the partition wall 700 away from the substrate 100.

[0167] Subsequently, a fixing layer 603 is deposited on the side of the gradient layer 604 away from the substrate 100. The thickness of the fixing layer 603 is greater than the thickness of any of the gradient layers 604, and the germanium content in the fixing layer 603 is set to a fixed value along the direction away from the substrate 100 and is greater than the germanium content in any of the gradient layers 604. For example, in this example, the germanium content in the fixing layer 603 is 20%. The fixing layer 603 constitutes the fixing layer 603. The fixing layer 603 is located outside the trench 800 and is connected to the second gradient layer 606 located in each trench 800. In other embodiments, the fixing layer 603 may also be partially located inside the trench 800 and partially located outside the trench 800, with the portion located inside the trench 800 contacting the second gradient layer 606. Thus, the buffer layer 600 composed of the gradient layer 604 and the fixing layer 603 is configured with a protruding partition wall 700 at one end away from the substrate 100, and the partition wall 700 is located between the buffer layer 600 and the substrate 100.

[0168] Next, the side of the buffer layer 600 away from the substrate 100 is polished.

[0169] In some exemplary embodiments, such as Figure 24 and Figure 25 As shown, within the gradient layer 604, the lattice mismatch at the interfaces of different compositions is small, resulting in a low dislocation nucleation rate. By setting a buffer layer 600 with a compositional gradient, the mobility of dislocations is enhanced, thereby causing dislocation lines in different directions to annihilate each other and reducing the dislocation density of the entire epitaxial layer. The setting of a fixed layer 603 with a relatively large thickness and a fixed germanium content not only ensures relaxation of the uppermost layer of the buffer layer 600 but also isolates mismatched dislocations from the surface.

[0170] S3: Semiconductor layers and sacrificial layers are alternately grown on the buffer layer.

[0171] In some exemplary embodiments, such as Figure 26As shown, semiconductor layers and sacrificial layers are alternately grown on the buffer layer, including: alternatingly growing a semiconductor layer 702 and a sacrificial layer 703 on the end face of the buffer layer 600 away from the substrate 100. Both semiconductor layer 702 and sacrificial layer 703 are grown outside the trench 800. For example, first, a sacrificial layer 703 is grown on the buffer layer 600, and this sacrificial layer 703 contacts the buffer layer 600. Then, a semiconductor layer 702 is grown on the side of the sacrificial layer 703 away from the substrate 100, and so on, alternatingly growing other sacrificial layers 703 and semiconductor layers 702. The material of the semiconductor layer 702 may include semiconductor materials, such as silicon, amorphous silicon, polycrystalline silicon, silicon carbide, or monocrystalline silicon, etc., or, for example, molybdenum disulfide (MoS2), tungsten disulfide (WS2), etc., transition-metal dichalcogenides (TMDs). In this example, the semiconductor layer 702 may be made of silicon and can be formed by a thin film deposition process, including but not limited to CVD, PVD, ALD, sputtering, evaporation, or a combination thereof. The sacrificial layer 703 may be made of silicon germanium (SiGe). Multiple semiconductor layers 702 and multiple sacrificial layers 703 are stacked to form a stacked structure 704.

[0172] S4: Form a supporting structure.

[0173] In some exemplary embodiments, such as Figure 26 and Figure 27 As shown, forming a support structure includes depositing support structures 500 at both ends of a stacked structure 704. The support structures 500 are located at both ends of the stacked structure 704 in a second direction and are perpendicular to the second direction; that is, in this exemplary embodiment, the support structures 500 are parallel to the partition wall 700. The support structures 500 are deposited on a substrate 100, and the material of the support structures 500 may be silicon nitride. In other exemplary embodiments, the support structures 500 may also be formed at both ends of the stacked structure 704 along the second direction; that is, the support structures 500 may also be perpendicular to the partition wall 700.

[0174] S5: Etch to remove the sacrificial layer.

[0175] In some exemplary embodiments, such as Figure 27 and Figure 28 As shown, the etching process for removing the sacrificial layer includes: first etching the stacked structure 704 to form multiple grooves extending along the second direction; the remaining semiconductor layer 702 forms multiple semiconductor strips 706; and then selectively removing all sacrificial layers 703 by etching, while retaining the buffer layer 600.

[0176] In some exemplary embodiments, such as Figure 27 and Figure 28As shown, a plurality of semiconductor strips 706 extend along a second direction, and the plurality of semiconductor strips 706 are arranged in an array in a first direction and a third direction, the third direction being perpendicular to the substrate 100. Each semiconductor strip 706 includes two semiconductor pillars 204, both of which extend along the first direction and are connected to each other.

[0177] S6: Prepare the first element, the second element, and the word line.

[0178] In some exemplary embodiments, such as Figure 28 and Figure 29 As shown, the fabrication of a first element, a second element, and a word line includes: growing a dielectric layer 209 and a first conductive layer on a semiconductor strip 706 to form a first element 202 (transistor) and a word line 400. Specifically, a dielectric layer 209, a first conductive layer 707, and a second insulating layer 213 are sequentially deposited on the outer periphery of the channel region 207 of the semiconductor strip 706. The first conductive layer 707 constitutes the gate 205 of the first element 202 (transistor). The material of the first conductive layer 707 can be a metal or a metal alloy, such as tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), cobalt (Co), nickel (Ni), titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), AlTi, or any combination thereof, and can also be conductive polycrystalline silicon, polycrystalline germanium, polycrystalline germanium silicon, amorphous silicon, etc. The dielectric layer 209 may be made of a high dielectric constant dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, and / or any combination thereof. The dielectric layer 209 may be deposited using one or more suitable deposition processes, such as CVD, PVD, and / or ALD. A second insulating layer 213 is disposed on the first elements 202 (transistors) adjacent in a third direction. The material of the second insulating layer 213 may include silicon oxide. First conductive layers 707 are connected on a plurality of semiconductor strips 706 arranged sequentially in a first direction to form word lines 400 extending along the first direction.

[0179] In some exemplary embodiments, such as Figure 28 and Figure 29As shown, the fabrication of the first element, the second element, and the word line also includes setting the second element 203 (capacitor) on the semiconductor strip 706. An inner electrode plate 210, a third insulating layer 211, and an outer electrode plate 212 are sequentially grown on the outer periphery of the second source / drain region 208 away from the channel region 207, resulting in the second element 203 (capacitor) surrounding the second source / drain region 208 away from the channel region 207. The inner electrode plate 210 and the outer electrode plate 212 can be made of metal or a conductive metal compound. In this example, the inner electrode plate 210 and the outer electrode plate 212 can be made of the same material, both being titanium nitride (TiN). The third insulating layer 211 can be a high dielectric material. Subsequently, a fourth insulating layer 214 is deposited between two adjacent second elements 203 (capacitors). The material of the fourth insulating layer 214 may include silicon oxide, and the fourth insulating layer 214 can space the second elements 203 (capacitors) between two adjacent memory cells 201.

[0180] S7: Prepare bit lines.

[0181] In some exemplary embodiments, such as Figure 5 and Figure 29 As shown, the fabrication of the bit line includes: firstly, etching the semiconductor strip 706 to cut it, thereby separating the two semiconductor pillars 204 constituting the semiconductor strip 706, with the space between the two semiconductor pillars 204 being a first space 708. The position where the semiconductor strip 706 is cut is the location where the source regions of the two semiconductor pillars meet.

[0182] The fabrication of the bit line further includes: depositing a second conductive layer on the substrate 100, the second conductive layer corresponding to the first space 708 to form the bit line 300. The material of the second conductive layer can be metal; in this example, the material of the second conductive layer can be tungsten. The bit line is configured to be shared by a plurality of semiconductor strips 706 arranged sequentially in a third direction. Thus, the following is completed: Figure 5 The fabrication of the semiconductor device shown.

[0183] In some exemplary embodiments, such as Figure 31 As shown, a method for fabricating a semiconductor device includes:

[0184] A first insulating layer is deposited on a substrate 100 and a plurality of partition walls 700 are etched to form the partition walls 700. The partition walls 700 extend along a first direction and are spaced apart in a second direction. A trench 800 is formed between two adjacent partition walls 700. The first direction and the second direction are both parallel to the substrate 100.

[0185] Semiconductor layers 702 and sacrificial layers 703 are alternately grown to form a stacked structure 704, which is located within the trench 800 or on the side of the partition wall 700 away from the substrate 100.

[0186] Storage cells are formed based on the stacked structure 704.

[0187] In some exemplary embodiments, a semiconductor device includes:

[0188] Substrate;

[0189] Multiple partition walls 700 are disposed on the substrate. The multiple partition walls 700 extend along a first direction and are spaced apart in a second direction. A trench 800 is formed between two adjacent partition walls 700. The first direction and the second direction are both parallel to the substrate.

[0190] A buffer layer 600 is disposed on the substrate, one end of the buffer layer 600 away from the substrate 100 extends to the side of the partition wall 700 away from the substrate, and the side of the buffer layer 600 away from the substrate 100 is parallel to the substrate 100.

[0191] Multiple rows of storage cells are disposed on the side of the buffer layer 600 away from the substrate 100.

[0192] This disclosure also provides an electronic device, which includes the semiconductor device provided in any of the above embodiments. The electronic device can be any electronic product with storage function, such as a storage device, smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank.

[0193] While the embodiments disclosed in this invention have been described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. It should be noted that the above embodiments or implementation methods are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the content specifically shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A first insulating layer is deposited on a substrate, and a plurality of partition walls are etched to form the partition walls. The partition walls extend along a first direction and are spaced apart in a second direction. A trench is formed between adjacent partition walls. Both the first direction and the second direction are parallel to the substrate. Semiconductor layers and sacrificial layers are grown alternately to form a stacked structure, the stacked structure being located within the trench and / or on the side of the partition wall away from the substrate; Storage cells are formed based on the stacked structure.

2. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The alternating growth of semiconductor layers and sacrificial layers forms a stacked structure, including: The semiconductor layer and the sacrificial layer are grown alternately and directly on the substrate, and the stacked structure is located within the trench.

3. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The alternating growth of semiconductor layers and sacrificial layers forms a stacked structure, including: A buffer layer is deposited on the substrate, the buffer layer being located within the trench; The semiconductor layer and the sacrificial layer are alternately grown in the trench, and the stacked structure is located in the trench and on the side of the buffer layer away from the substrate.

4. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The alternating growth of semiconductor layers and sacrificial layers forms a stacked structure, including: A buffer layer is deposited on the substrate, wherein the buffer layer is located within the trench and one end away from the substrate is configured to protrude from the partition wall; The side of the buffer layer away from the substrate is polished; The semiconductor layer and the sacrificial layer are alternately grown on the side of the buffer layer away from the substrate to form the stacked structure.

5. The method for fabricating a semiconductor device as described in claim 2 or 3, characterized in that, The distance between two adjacent partition walls is set as D1, the thickness of any semiconductor layer is set as D2, and the thickness of any sacrificial layer is set as D3, wherein the ratio of D2 to D1 is greater than 1, and the ratio of D3 to D1 is greater than 1.

6. The method for fabricating a semiconductor device as described in claim 3 or 4, characterized in that, The deposition of the buffer layer on the substrate includes: Multiple gradient layers are sequentially deposited on the substrate, wherein the germanium content in the multiple gradient layers is set to increase linearly in the direction away from the substrate; A fixing layer is deposited on the side of the gradient layer away from the substrate. The thickness of the fixing layer is greater than the thickness of any of the gradient layers. The germanium content in the fixing layer is set to remain constant along the direction away from the substrate and is greater than the germanium content in any of the gradient layers.

7. The method for fabricating a semiconductor device as described in claim 6, characterized in that, The germanium content in any of the gradient layers is set to be no more than 20%.

8. The method for fabricating a semiconductor device as described in claim 2 or 3, characterized in that, The process of depositing a first insulating layer on a substrate and etching the first insulating layer to form multiple partition walls includes: A first insulating layer is deposited on the substrate; The first insulating layer is etched to form multiple partition walls and multiple spacer structures, and the multiple spacer structures are disposed in the trench and spaced apart in the first direction.

9. The method for fabricating a semiconductor device as described in claim 8, characterized in that, The formation of storage cells based on the stacked structure includes: The sacrificial layer is etched away, and the remaining semiconductor layer forms a plurality of semiconductor strips. The plurality of semiconductor strips extend along the first direction and are arranged in an array in the second direction and a third direction, wherein the third direction is perpendicular to the substrate. Two support structures are deposited at both ends of the semiconductor strip along a first direction, the support structures being configured to support the semiconductor strip, and a spacer structure being provided between the two support structures; The partition wall is etched away, while the partition structure is preserved.

10. The method for fabricating a semiconductor device as described in claim 9, characterized in that, The method of forming a storage unit based on the stacked structure further includes: A first element is formed on a semiconductor strip; Etching removes the spacer structure, forming a first space within the trench, the first space being configured to divide the semiconductor strip into two semiconductor pillars spaced apart in the first direction; A second conductive layer is deposited within the first space to form a bit line.

11. The method for fabricating a semiconductor device as described in claim 4, characterized in that, The formation of storage cells based on the stacked structure includes: Support structures are deposited at both ends of the stacked structure to form support structures; The stacked structure is etched to form multiple semiconductor strips, the extension direction of the semiconductor strips is set to be consistent with the first direction or the second direction, and the support structure is located at both ends of the extension direction of the semiconductor strips; Etching removes the sacrificial layer; A first element is formed on the semiconductor strip.

12. The method for fabricating a semiconductor device as described in claim 11, characterized in that, Each of the semiconductor strips includes two semiconductor pillars arranged sequentially in the extending direction of the semiconductor strip; The method of forming a memory cell based on the stacked structure further includes: depositing a second conductive layer at the junction of two semiconductor pillars to form a bit line, wherein the bit line is configured to be shared by a plurality of semiconductor strips arranged sequentially in a third direction, the third direction being perpendicular to the substrate.

13. The method for fabricating a semiconductor device as described in claim 12, characterized in that, The formation of the first element on the semiconductor strip includes: A dielectric layer, a first conductive layer, and a second insulating layer are sequentially deposited on the outer periphery of the semiconductor pillars. The second insulating layer is configured to separate first elements adjacent to each other in the third direction. The first conductive layers on a plurality of semiconductor pillars arranged sequentially in a direction perpendicular to the extension direction are connected to form word lines that are perpendicular to the extension direction and parallel to the substrate.

14. A semiconductor device, characterized in that, The semiconductor device is prepared according to the method for fabricating a semiconductor device according to claim 1, wherein the semiconductor device comprises: Substrate; Multiple rows of memory cells, each of the memory cell rows including multiple memory cells stacked upward along a third direction on the substrate, each memory cell including a first element, the first element including a semiconductor pillar and a gate, the semiconductor pillar extending along a first direction or a second direction; Multiple bit lines, each extending along a third direction, are arrayed in the first and second directions. Multiple semiconductor pillars stacked at the same position along the third direction share the same bit line. The third direction is perpendicular to the substrate. Multiple word lines are provided, the extension direction of which is perpendicular to the extension direction of the semiconductor pillar, and multiple memory cells are arranged at intervals along the extension direction of the word lines. Each word line is formed by connecting the gates of the first elements of multiple memory cells arranged along the extension direction of the word line.

15. The semiconductor device as claimed in claim 14, characterized in that, It also includes a buffer layer and a partition wall disposed on the substrate, wherein multiple partition walls are provided, all of which extend along the first direction and are spaced apart in the second direction, and the multiple partition walls are located between the buffer layer and the substrate; The plurality of the memory cell columns are located on the side of the buffer layer away from the substrate.

16. A semiconductor device, characterized in that, include: Substrate; Multiple partition walls are disposed on the substrate, the multiple partition walls extend along a first direction and are spaced apart in a second direction, and a groove is formed between two adjacent partition walls, the first direction and the second direction are both parallel to the substrate; A buffer layer is disposed in the trench, wherein one end of the buffer layer away from the substrate extends to the side of the partition wall away from the substrate, and the side of the buffer layer away from the substrate is parallel to the substrate; Multiple rows of storage cells are disposed on the side of the buffer layer away from the substrate.

17. The semiconductor device as claimed in claim 15 or 16, characterized in that, The buffer layer includes a gradient layer and a fixing layer, wherein the gradient layer is located on the side of the fixing layer closer to the substrate; Both the gradient layer and the fixed layer are made of silicon and germanium. The germanium content in the gradient layer is set to increase linearly in the direction away from the substrate, and the germanium content in the fixed layer is set to remain unchanged in the direction away from the substrate and be greater than the germanium content in the gradient layer.

18. An electronic device, characterized in that, The semiconductor device includes a semiconductor device obtained by the method of fabrication of a semiconductor device according to any one of claims 1 to 13, or a semiconductor device according to any one of claims 14 to 17.

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