Semiconductor device

Abstract

The embodiment of the invention relates to a semiconductor device. According to one embodiment, a semiconductor device includes: a substrate; and a laminated film including a plurality of electrode layers and a plurality of insulating layers alternately disposed over the substrate. The device is further provided with: a first semiconductor layer provided in the laminated film; and a second semiconductor layer, which is provided on the first semiconductor layer in the laminated film, and which includes a single-crystal semiconductor layer. The device is further provided with a wiring layer which is provided on the laminated film and the second semiconductor layer, and which is electrically connected to the second semiconductor layer.

Description

[0001] Related information of divisional application

[0002] This application is a divisional application. The parent application of this divisional application is the patent application for invention entitled "Semiconductor device and manufacturing method thereof" with the application number 202110172036.8 and the application date of February 8, 2021.

[0003] [CROSS-REFERENCE TO RELATED APPLICATIONS]

[0004] This application claims the benefit of priority based on the prior Japanese patent application No. 2020-154035 filed on September 14, 2020, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0005] Embodiments of the present application relate to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0006] In a semiconductor memory such as a three-dimensional memory, it is desirable to improve the performance of a semiconductor layer such as a channel semiconductor layer. SUMMARY

[0007] According to an embodiment, a semiconductor device includes: a substrate; and a laminate film including a plurality of electrode layers and a plurality of insulating layers alternately arranged above the substrate. The device further includes: a first semiconductor layer arranged in the laminate film; and a second semiconductor layer arranged on the first semiconductor layer in the laminate film and including a single-crystal semiconductor layer. The device further includes a wiring layer arranged on the laminate film and the second semiconductor layer and electrically connected to the second semiconductor layer. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to a first embodiment.

[0009] Figure 2 FIG. 2 is an enlarged cross-sectional view showing the configuration of a columnar portion according to the first embodiment.

[0010] Figure 3 FIG. 3 is an enlarged cross-sectional view showing the configuration of the semiconductor device according to the first embodiment.

[0011] Figure 4 FIG. 4 is an enlarged cross-sectional view showing the configuration of a semiconductor device according to a comparative example of the first embodiment.

[0012] Figure 5 (a) and (b) of FIG. 1, Figure 6 (a) and (b) of FIG. 2, Figure 7 (a) and (b) of FIG. 3, Figure 8(a) and (b) of FIG. 1, Figure 9 (a) and (b) of FIG. 1, Figure 10 (a) and (b) of FIG. 1 are cross-sectional views that show a manufacturing method of a semiconductor device of the first embodiment.

[0013] Figure 11 (a) and (b) of FIG. 1 are cross-sectional views that show a manufacturing method of a semiconductor device of the first embodiment.

[0014] Figure 12 is a cross-sectional view that shows an entire configuration of a semiconductor device of the first embodiment. DETAILED DESCRIPTION

[0015] Hereinafter, an embodiment of the present application will be described in detail with reference to the accompanying drawings. In the drawings: Figures 1 to 12 In the drawings, the same components are denoted by the same symbols, and overlapping descriptions will be omitted.

[0016] (First Embodiment)

[0017] Figure 1 is a cross-sectional view that shows a configuration of a semiconductor device of the first embodiment.

[0018] The semiconductor device of the present embodiment is, for example, a three-dimensional memory, and has a circuit region 1 and an array region 2 provided on the circuit region 1. For example, as described below, the semiconductor device of the present embodiment is manufactured by bonding a circuit wafer including the circuit region 1 and an array wafer including the array region 2. Figure 1 The bonding surface S of the circuit region 1 (circuit wafer) and the array region 2 (array wafer) is shown.

[0019] The semiconductor device of the present embodiment has a substrate 11, a transistor 12, and an interlayer insulating layer 13 in the circuit region 1, and has an interlayer insulating film 21, a laminate film 22, an interlayer insulating film 23, and a plurality of columnar portions 24 in the array region 2. The transistor 12 includes a gate insulating film 12a, a gate electrode 12b, and an insulating film 12c. The laminate film 22 includes a multilayer electrode layer 22a and a multilayer insulating layer 22b. Each of the columnar portions 24 includes a memory insulating film 24a, a semiconductor layer 24b, a channel semiconductor layer 24c, and a core insulating film 24d. The channel semiconductor layer 24c is an example of a first semiconductor layer, and the semiconductor layer 24b is an example of a second semiconductor layer.

[0020] The semiconductor device of this embodiment further includes a contact plug 31, a wiring layer 32 including one or more wirings, a via plug 33, a wiring layer 34 including one or more wirings, a via plug 35, a wiring layer 36 including one or more wirings, a via plug 37, and a metal pad 38 in the circuit region 1, and further includes a metal pad 41, a via plug 42, a wiring layer 43 including one or more wirings, a wiring layer 51, and a passivation film 52 in the array region 2. The wiring layer 51 includes a semiconductor layer 51a and a metal layer 51b. The semiconductor layer 51a is an example of the third semiconductor layer.

[0021] Figure 1 An X direction, a Y direction, and a Z direction perpendicular to each other are shown. In this specification, the +Z direction is regarded as an upward direction, and the -Z direction is regarded as a downward direction. The -Z direction can coincide with the direction of gravity or can not coincide with the direction of gravity. The Z direction is an example of the first direction.

[0022] The substrate 11 is a semiconductor substrate such as a silicon substrate. The transistor 12 includes a gate insulating film 12a formed over the substrate 11, a gate electrode 12b formed over the gate insulating film 12a, and an insulating film 12c formed on side surfaces of the gate electrode 12b. The semiconductor device of this embodiment includes a plurality of transistors 12 over the substrate 11, Figure 1 One of the transistors 12 is shown. The transistors 12 form, for example, a control circuit (a logic circuit) which controls the operation of the semiconductor device of this embodiment. The interlayer insulating layer 13 is formed over the substrate 11 so as to cover the transistors 12.

[0023] The interlayer insulating film 21 is formed over the interlayer insulating layer 13. The stacked film 22 includes a plurality of electrode layers 22a and a plurality of insulating layers 22b which are alternately stacked over the interlayer insulating film 21. The electrode layers 22a of this embodiment include a plurality of word lines, one or more source side selection lines, and one or more drain side selection lines as described below. Each of the electrode layers 22a includes, for example, a metal layer such as a tungsten (W) layer. Each of the insulating layers 22b is, for example, a silicon oxide film. The interlayer insulating film 23 is formed over the stacked film 22.

[0024] Each of the columnar portions 24 has a columnar shape extending in the Z direction and is formed in the interlayer insulating film 21, the stacked film 22, and the interlayer insulating film 23. Each of the columnar portions 24 includes a memory insulating film 24a formed on side surfaces of the interlayer insulating film 21, the stacked film 22, and the interlayer insulating film 23, a semiconductor layer 24b and a channel semiconductor layer 24c formed on side surfaces of the memory insulating film 24a, and a core insulating film 24d formed on side surfaces of the channel semiconductor layer 24c.

[0025] The memory insulating film 24a has a tubular shape extending in the Z direction and surrounds the semiconductor layer 24b and the channel semiconductor layer 24c. As described below, the memory insulating film 24a includes a barrier insulating film, a charge storage layer, and a tunnel insulating film.

[0026] The channel semiconductor layer 24c has a tubular shape extending in the Z direction, surrounding the core insulating film 24d. Specifically, the channel semiconductor layer 24c includes: a side portion P1 having a tubular shape extending in the Z direction; and a bottom portion P2 having a bottom shape disposed at the upper end of the tube. The channel semiconductor layer 24c is, for example, a polycrystalline semiconductor layer such as a polysilicon layer. The side portion P1 is an example of the first portion, and the bottom portion P2 is an example of the second portion. Furthermore, the channel semiconductor layer 24c may contain n-type impurity atoms or p-type impurity atoms, or may not contain either n-type or p-type impurity atoms.

[0027] Semiconductor layer 24b has a non-tubular shape extending in the Z direction and is formed on the bottom portion P2 of channel semiconductor layer 24c. The side portion P1 of channel semiconductor layer 24c has a tubular shape, i.e., a hollow columnar shape, while semiconductor layer 24b has a non-tubular shape, i.e., a solid columnar shape. Semiconductor layer 24b is, for example, a monocrystalline silicon layer or a single-crystal semiconductor layer. In this embodiment, semiconductor layer 24b has an upper surface at the same height as the upper surface of interlayer insulating film 23, and a lower surface at a height lower than the lower surface of interlayer insulating film 23. Details regarding the height of the lower surface of semiconductor layer 24b in this embodiment will be described below.

[0028] Semiconductor layer 24b contains, for example, n-type or p-type impurity atoms. The concentration of n-type or p-type impurity atoms in semiconductor layer 24b is, for example, 1.0 × 10⁻⁶. 19 cm -3 That's all. The semiconductor layer 24b in this embodiment contains a concentration of 1.0 × 10⁻⁶. 19 cm -3 Up to 5.0×10 19 cm -3 The P (phosphorus) atom.

[0029] The core insulating film 24d has a non-tubular shape extending in the Z direction and is formed within the side portion P1 of the channel semiconductor layer 24c. The core insulating film 24d is, for example, a silicon oxide film.

[0030] In each of the columnar portions 24, a plurality of memory cell transistors or a plurality of selection transistors are constituted by the memory insulating film 24a, the semiconductor layer 24b, the channel semiconductor layer 24c, and the core insulating film 24d. These memory cell transistors or selection transistors constitute a memory cell array of the three-dimensional memory.

[0031] The contact plug 31, the wiring layer 32, the interlayer plug 33, the wiring layer 34, the interlayer plug 35, the wiring layer 36, the interlayer plug 37, the metal pad 38, the metal pad 41, the interlayer plug 42, and the wiring layer 43 are sequentially provided in the interlayer insulating films 13 and 21 on the substrate 11. The semiconductor device of this embodiment is provided with a plurality of contact plugs 31, a plurality of interlayer plugs 33, a plurality of interlayer plugs 35, a plurality of interlayer plugs 37, a plurality of metal pads 38, a plurality of metal pads 41, and a plurality of interlayer plugs 42, Figure 1 Some of these plugs and pads are shown. The control circuit is electrically connected to the memory cell array via these plugs, pads, and wiring layers, and controls the operation of the memory cell array via these plugs, pads, and wiring layers.

[0032] Each of the metal pads 38 and 41 includes, for example, a metal layer such as a Cu (copper) layer. In the semiconductor device of this embodiment, the metal pad 38 and the metal pad 41 are joined to each other, and the interlayer insulating film 13 and the interlayer insulating film 21 are adhered to each other. In this embodiment, each of the columnar portions 24 is formed on the wiring layer 43, and thus the channel semiconductor layer 24c of each of the columnar portions 24 is electrically connected to the wiring layer 43.

[0033] The wiring layer 51 includes a semiconductor layer 51a formed on the interlayer insulating film 23 and each of the columnar portions 24, and a metal layer 51b formed on the semiconductor layer 51a. In this embodiment, the semiconductor layer 51a is in contact with the semiconductor layer 24b of each of the columnar portions 24, and thus the wiring layer 51 is electrically connected to the semiconductor layer 24b of each of the columnar portions 24. The semiconductor layer 51a is, for example, a polysilicon layer doped with P atoms.

[0034] A passivation film 52 is formed on the wiring layer 51. The passivation film 52 is, for example, an insulating film such as a silicon oxide film. The passivation film 52 can include a silicon oxide film and other insulating films.

[0035] Figure 2 is an enlarged cross-sectional view showing the configuration of the columnar portion 24 of the first embodiment.

[0036] As Figure 2 shown, the columnar portion 24 includes, in order, a memory insulating film 24a, a channel semiconductor layer 24c (a side surface portion P1), and a core insulating film 24d formed in the laminate film 22. The memory insulating film 24a includes, in order, a barrier insulating film 61, a charge accumulation layer 62, and a tunnel insulating film 63 formed in the laminate film 22.

[0037] The barrier insulating film 61 is, for example, a silicon oxide film. The charge accumulation layer 62 is, for example, an insulating film such as a silicon nitride film, and has a function of accumulating signal charges. The charge accumulation layer 62 can also be a semiconductor layer such as a polysilicon layer. The tunnel insulating film 63 is, for example, a silicon oxide film. The barrier insulating film 61, the charge accumulation layer 62, and the tunnel insulating film 63 each have a tubular shape extending in the Z direction, and surround the channel semiconductor layer 24c and the semiconductor layer 24b (see FIG. 2). Figure 1 ).

[0038] Figure 3 is an enlarged sectional view showing the configuration of the semiconductor device of the first embodiment.

[0039] Figure 3 The laminated film 22 in which the multilayer electrode layers 22a and the multilayer insulating layers 22b are alternately included, and the columnar portion 24 provided in the laminated film 22 are shown. These electrode layers 22a include one or more drain side selection lines SGD, a plurality of word lines WL disposed above the drain side selection lines SGD, and one or more source side selection lines SGS provided above the word lines WL. Figure 3 These electrode layers 22a shown include one drain side selection line SGD and five source side selection lines SGS as an example, but the number of drain side selection lines SGD and the number of source side selection lines SGS are not limited thereto. The drain side selection line SGD is an example of the first selection line, and the source side selection line SGS is an example of the second selection line.

[0040] The semiconductor layer 24b of the present embodiment has an upper surface at the same height as the upper surface of the interlayer insulating film 23, and has a lower surface at a lower height than the lower surface of the interlayer insulating film 23. For example, Figure 3 The lower surface of the semiconductor layer 24b shown is at a height between the lower surface of the lowermost source side selection line SGS and the upper surface of the uppermost source side selection line SGS, and here, at a height between the lower surface and the upper surface of the third source side selection line SGS counted from the bottom (or the third source side selection line SGS counted from the top).

[0041] When erasing the stored data of each memory cell of a certain columnar portion 24 (NAND (Not AND) string), the semiconductor device of the present embodiment applies an erase voltage to the designated source side selection line SGS for the columnar portion 24. Thereby, a GIDL (Gate Induced Drain Leakage) current is generated in the designated selection transistor of the columnar portion 24, and flows to each memory cell. The stored data of each memory cell is erased by the GIDL current.

[0042] The specified source side selection lines SGS of this embodiment are source side selection lines SGS which are opposed to the semiconductor layer 24b, and specifically, the 1st (uppermost) source side selection line SGS counted from the top, the 2nd source side selection line SGS counted from the top, and the 3rd source side selection line SGS counted from the top. When an erase voltage is applied to these source side selection lines SGS, GIDL current is generated in the selection transistors corresponding to these source side selection lines SGS, and more specifically, GIDL current is generated in the semiconductor layer 24b. These source side selection lines SGS are referred to as GIDL generators.

[0043] The semiconductor layer 24b of this embodiment is provided in order to facilitate the generation of the GIDL current. Therefore, as described above, the semiconductor layer 24b contains a high concentration of P atoms. According to this embodiment, by taking the channel region of the selection transistor corresponding to the specified source side selection line SGS (GIDL generator) as the semiconductor layer 24b, the GIDL current can be efficiently generated.

[0044] Figure 4 FIG. 1 is an enlarged sectional view showing the configuration of a semiconductor device of a comparative example of the 1st embodiment.

[0045] Figure 4 A laminated film 22 in which multilayer electrode layers 22a and multilayer insulating layers 22b are alternately contained, and a columnar portion 24 provided in the laminated film 22 are shown. These electrode layers 22a contain one or more drain side selection lines SGD, a plurality of word lines WL disposed above the drain side selection lines SGD, and one or more source side selection lines SGS provided above the word lines WL. Figure 4 These electrode layers 22a shown contain one drain side selection line SGD and four source side selection lines SGS as an example.

[0046] The columnar portion 24 of this comparative example does not contain a semiconductor layer 24b. Therefore, in the channel semiconductor layer 24c of this comparative example, the side surface portion P1 extends to the lower surface of the wiring layer 51, and the bottom surface portion P2 is in contact with the lower surface of the wiring layer 51.

[0047] The columnar portion 24 of this comparative example is provided with an impurity diffusion layer 25 provided in the channel semiconductor layer 24c instead of the semiconductor layer 24b. The impurity diffusion layer 25 is, for example, a polysilicon layer doped with P atoms. In this comparative example, the source side selection line SGS opposed to the impurity diffusion layer 25, that is, the uppermost source side selection line SGS functions as a GIDL generator. The GIDL current of this comparative example is generated in the impurity diffusion layer 25.

[0048] Here, the semiconductor device of the 1st embodiment shown in FIG. 1 and the semiconductor device of the comparative example shown in FIG. 1 will be compared. Figure 3 Figure 4 ​The semiconductor device of the comparative example shown is compared.

[0049] In Figure 4 In the comparative example shown, the impurity diffusion layer 25 is formed, for example, by implanting P atoms into the channel semiconductor layer 24c. In this case, the position where the impurity diffusion layer 25 is formed varies depending on the position where the P atoms are implanted. In general, since it is desirable that the values of the GIDL currents generated in the different columnar portions 24 be close to the same value, it is desirable that the positions of the impurity diffusion layers 25 of the different columnar portions 24 be close to the same position. However, the positions where the P atoms are implanted generally differ among the different impurity diffusion layers 25, and thus it is difficult to make the positions of the impurity diffusion layers 25 of the different columnar portions 24 close to the same position. Furthermore, if the P atoms implanted into the channel semiconductor layer 24c are diffused by annealing, the positions of the P atoms can differ even more.

[0050] On the other hand, in Figure 3 In the first embodiment shown, the GIDL current is generated using the impurity diffusion layer 25 formed in the semiconductor layer 24b that is formed separately from the channel semiconductor layer 24c, rather than the channel semiconductor layer 24c. Thus, according to the present embodiment, it is easy to make the positions of the semiconductor layers 24b of the different columnar portions 24 close to the same position, and thus it is easy to make the values of the GIDL currents generated in the different columnar portions 24 close to the same value. As described below, the semiconductor layer 24b of the present embodiment is formed by epitaxial growth, and thus it is easy to make the positions of the semiconductor layers 24b of the different columnar portions 24 close to the same position.

[0051] Figure 12 is a cross-sectional view showing the overall configuration of the semiconductor device of the first embodiment.

[0052] The array region 2 includes a memory cell array 111 including a plurality of memory cells, a semiconductor layer 112 over the memory cell array 111, a back gate insulating film 113 over the semiconductor layer 112, and a back gate electrode 114 over the back gate insulating film 113. The back gate electrode 114 is used for electric field control of the semiconductor layer 112, like a selection gate electrode SG described below. The array region 2 further includes an interlayer insulating film 21a below the memory cell array 111 and an insulating film 21b below the interlayer insulating film 21a as an interlayer insulating film 21. The insulating film 21b is, for example, a silicon oxide film.

[0053] The circuit region 1 is provided below the array region 2. The circuit region 1 includes an insulating film 13a below the insulating film 21b, an interlayer insulating film 13b below the insulating film 13a, and a substrate 11 below the interlayer insulating film 13b as an interlayer insulating film 13. The insulating film 13a is, for example, a silicon oxide film. The substrate 11 is, for example, a semiconductor substrate such as a silicon substrate.

[0054] The array region 2 has a plurality of word lines WL and selection gates SG as electrode layers within the memory cell array 111. Figure 12 A stepped structure portion 121 of the memory cell array 111 is shown. The array region 2 also has the back gate electrode 114 as an electrode layer outside the memory cell array 111. As shown, each word line WL is electrically connected to a word line wiring layer 123 via a contact plug 122, the back gate electrode 114 is electrically connected to a back gate wiring layer 125 via a contact plug 124, and the selection gate SG is electrically connected to a selection gate wiring layer 127 via a contact plug 126. The columnar portions 24 that penetrate the word lines WL and the selection gates SG are electrically connected to the bit lines BL within the wiring layer 43 via the contact plugs 43', and are electrically connected to the semiconductor layer 112. In addition, the word line WL corresponds to a specific example of the electrode layer 22a. Figure 12

[0055] The circuit region 1 has a plurality of transistors 12. Each transistor 12 has a gate electrode 12b provided on a substrate 11 with a gate insulating film 12a interposed therebetween, and a source diffusion layer and a drain diffusion layer, not shown, provided within the substrate 11. The circuit region 1 also has a plurality of contact plugs 31 provided on the source diffusion layer or the drain diffusion layer of these transistors 12, a wiring layer 32 provided on these contact plugs 31 and including a plurality of wirings, and a plurality of via plugs 35 provided on the wiring layer 32. The circuit region 1 also has a wiring layer 36 provided on these via plugs 35 and including a plurality of wirings, a plurality of via plugs 37 provided on the wiring layer 36, and a plurality of metal pads 38 provided on these via plugs 37 within an insulating film 13a. In addition, the illustration of the via plugs 33 and the wiring layer 34 is omitted. The circuit region 1 functions as a control circuit (logic circuit) that controls the array region 2.

[0056] The array region 2 has a plurality of metal pads 41 provided on the metal pads 38 within an insulating film 21b, a plurality of via plugs 42 provided on the metal pads 41, and a wiring layer 131 provided on these via plugs 42 and including a plurality of wirings. Each word line WL or each bit line BL is electrically connected to a corresponding wiring within the wiring layer 131. The array region 2 also has a wiring layer 132 provided on the wiring layer 131 and including a plurality of wirings, a wiring layer 133 provided on the wiring layer 132 and including a plurality of wirings, and a via plug 134 provided on the wiring 133. The array region 2 also has a metal pad 135 provided on the via plug 134, and a passivation film 136 covering the metal pad 135 and the back gate electrode 114. The passivation film 136 is, for example, a silicon oxide film, and has an opening portion P exposing an upper surface of the metal pad 136. The metal pad 136 is an external connection pad of the semiconductor device, and can be connected to a mounting substrate or another device via a solder ball, a metal bump, a bonding wire, or the like. Figure 12 The array region 2 has a plurality of metal pads 41 provided on the metal pads 38 within an insulating film 21b, a plurality of via plugs 42 provided on the metal pads 41, and a wiring layer 131 provided on these via plugs 42 and including a plurality of wirings. Each word line WL or each bit line BL is electrically connected to a corresponding wiring within the wiring layer 131. The array region 2 also has a wiring layer 132 provided on the wiring layer 131 and including a plurality of wirings, a wiring layer 133 provided on the wiring layer 132 and including a plurality of wirings, and a via plug 134 provided on the wiring 133. The array region 2 also has a metal pad 135 provided on the via plug 134, and a passivation film 136 covering the metal pad 135 and the back gate electrode 114. The passivation film 136 is, for example, a silicon oxide film, and has an opening portion P exposing an upper surface of the metal pad 136. The metal pad 136 is an external connection pad of the semiconductor device, and can be connected to a mounting substrate or another device via a solder ball, a metal bump, a bonding wire, or the like.​

[0057] Figures 5 to 10 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to the first embodiment.

[0058] First, a substrate 26 for array wafer 4 is prepared, and an interlayer insulating film 23, a multilayer film 22', and an insulating film 21a (which is part of the interlayer insulating film 21) are sequentially formed on the substrate 26. Figure 5 (a)). The substrate 26 is, for example, a semiconductor substrate such as a silicon substrate. The multilayer film 22' is formed in such a manner that it alternately includes multiple sacrificial layers 22a' and multiple insulating layers 22b. Each sacrificial layer 22a' is, for example, a silicon nitride film. The substrate 26 is an example of a first substrate. These sacrificial layers 22a' are examples of a first film, and these insulating layers 22b are examples of a second film.

[0059] These sacrificial layers 22a' are in the following steps ( Figure 8 In step (a), the electrode layer 22a is replaced by a multilayer electrode layer 22a. As a result, a multilayer film 22, which alternately contains multilayer electrode layers 22a and multilayer insulating layers 22b, is formed between the interlayer insulating film 23 and the insulating film 21a.

[0060] Secondly, multiple memory holes H1 are formed within the insulating film 21a, the laminated film 22', and the interlayer insulating film 23. Figure 5 (b)). As a result, the upper surface of substrate 26 is exposed within these memory holes H1. These memory holes H1 are examples of recesses.

[0061] Secondly, a memory insulating film 24a is formed on the entire surface of the substrate 26. Figure 6 (a) As a result, a memory insulating film 24a is formed on the upper surface of the substrate 26 inside the memory hole H1, the side surface of the insulating film 21a, the stacked film 22' and the interlayer insulating film 23 inside the memory hole H1, and the upper surface of the insulating film 21a outside the memory hole H1. The memory insulating film 24a is formed by sequentially forming a barrier insulating film 61, a charge storage layer 62 and a tunnel insulating film 63 on the entire surface of the substrate 26. Figure 2 It is formed by ).

[0062] Secondly, the memory insulating film 24a is removed from the upper surface of the substrate 26 inside the memory hole H1 and the upper surface of the insulating film 21a outside the memory hole H1 by dry etching. Figure 6 (b)). As a result, the upper surface of substrate 26 is exposed again within memory hole H1. In this way, memory insulating film 24a is processed into a tubular shape extending in the Z direction.

[0063] Secondly, a semiconductor layer 24b is formed on the upper surface of the substrate 26 within the memory hole H1 by epitaxial growth from the substrate 26. Figure 7of (a)). The semiconductor layer 24b is, for example, a single-crystal silicon layer doped with P atoms. The concentration of P atoms in the semiconductor layer 24b is, for example, 1.0 x 1018atoms / cm3. 19 cm -3 The above is preferably 1.0 x 1018atoms / cm3 19 cm -3 to 5.0 x 1018atoms / cm3 19 cm -3 . In this way, the semiconductor layer 24b is processed to have a non-tubular shape extending in the Z direction.

[0064] In addition, Figure 7 the orientation of the up-down direction of the array wafer 4 shown in (a) is opposite to the orientation of the up-down direction of the array region 2 shown in (b). Therefore, Figure 3 the upper surface of the semiconductor layer 24b shown in (a) corresponds to the lower surface of the semiconductor layer 24b shown in (b). In Figure 7 the step of (a), the semiconductor layer 24b is formed in such a way that the position of the upper surface of the semiconductor layer 24b comes to the position of the lower surface of the semiconductor layer 24b shown in (b). Therefore, Figure 3 the upper surface of the semiconductor layer 24b shown in (a) is positioned at a height between the upper surface of the source side selection line SGS at the uppermost (in the case of (b), the lowermost) and the lower surface of the source side selection line SGS at the lowermost (in the case of (b), the uppermost). However, at the stage shown in (a), the sacrificial layer 22a' has not yet been replaced with the electrode layer 22, and thus, more accurately, Figure 7 the upper surface of the semiconductor layer 24b shown in (a) is the upper surface of the sacrificial layer 22a' corresponding to the source side selection line SGS at the uppermost and the lower surface of the sacrificial layer 22a' corresponding to the source side selection line SGS at the lowermost. Figure 3 Figure 3 the upper surface of the semiconductor layer 24b shown in (a) is positioned at a height between the upper surface of the source side selection line SGS at the uppermost (in the case of (b), the lowermost) and the lower surface of the source side selection line SGS at the lowermost (in the case of (b), the uppermost). However, at the stage shown in (a), the sacrificial layer 22a' has not yet been replaced with the electrode layer 22, and thus, more accurately, Figure 7 Figure 7 the upper surface of the semiconductor layer 24b shown in (a) is the upper surface of the sacrificial layer 22a' corresponding to the source side selection line SGS at the uppermost and the lower surface of the sacrificial layer 22a' corresponding to the source side selection line SGS at the lowermost. Figure 7 Figure 8 Next, a channel semiconductor layer 24c and a core insulating film 24d are sequentially formed over the entire surface of the substrate 26, and the channel semiconductor layer 24c and the core insulating film 24d outside the memory holes H1 are removed

[0065] Next, a channel semiconductor layer 24c and a core insulating film 24d are sequentially formed over the entire surface of the substrate 26, and the channel semiconductor layer 24c and the core insulating film 24d outside the memory holes H1 are removed Figure 3 ​​​(b) As a result, a channel semiconductor layer 24c is formed on the upper surface of the semiconductor layer 24b within the memory hole H1, the side surface of the stacked film 22' within the memory hole H1, and the side surface of the interlayer insulating film 23. Furthermore, a core insulating film 24d is formed on the upper surface and side surface of the channel semiconductor layer 24c within the memory hole H1. In this way, the channel semiconductor layer 24c is formed in a tubular shape extending in the Z direction, and the core insulating film 24d is formed in a non-tubular shape extending in the Z direction. Specifically, the channel semiconductor layer 24c is formed in a manner including a side portion P1 and a bottom portion P2, wherein the side portion P1 has a tubular shape extending in the Z direction, and the bottom portion P2 has a bottom shape disposed at the lower end of the tube. In this way, a plurality of columnar portions 24 are formed within the plurality of memory holes H1.

[0066] Secondly, the sacrificial layer 22a' is replaced with the electrode layer 22 ( Figure 5 (a) Specifically, slits are formed within the insulating film 21a and the stacked film 22', and the sacrificial layer 22a' is removed by wet etching using the slits. Multiple electrode layers 22 are embedded within the multiple recesses formed by removing the sacrificial layer 22a'. As a result, a stacked film 22 alternating between the interlayer insulating film 23 and the insulating film 21a is formed, comprising multiple electrode layers 22a and multiple insulating layers 22b. These electrode layers 22a, for example, include multiple word lines WL, one or more source-side select lines SDS, and one or more drain-side select lines SDG (see reference). Figure 8 ).

[0067] In addition, Figure 8 In step (a), instead of forming a multilayer film 22' that alternately comprises multiple sacrificial layers 22a' and multiple insulating layers 22b, a multilayer film 22 that alternately comprises multiple electrode layers 22a and multiple insulating layers 22b may be formed. In this case, it is not necessary to... Figure 8 In step (a), the sacrificial layer 22a' is replaced with the electrode layer 22a. In this case, the electrode layer 22a and the insulating layer 22b are examples of the first film and the second film.

[0068] Secondly, on the insulating film 21a and each columnar portion 24, an insulating film 21b, a wiring layer 43, a dielectric plug 42, and a metal pad 41, which are part of the interlayer insulating film 21, are formed. Figure 8 (a)). In this way, an array of wafers 4 are manufactured to become the object to be bonded. Figure 8 (a) shows the upper surface S2 of the array wafer 4, which becomes the bonding surface S of the array wafer 4.

[0069] Next, a substrate 11 for the circuit wafer 3 is prepared, and transistors 12, interlayer insulating film 13, contact plugs 31, wiring layers 32, dielectric plugs 33, wiring layers 34, dielectric plugs 35, wiring layers 36, dielectric plugs 37, and metal pads 38 are formed on the substrate 11. Figure 9 (b)). In this way, a circuit wafer 3 is manufactured to become the object to be bonded. Figure 9 (b) shows the upper surface S1 of the circuit wafer 3, which becomes the bonding surface S of the circuit wafer 3.

[0070] Next, the circuit wafer 3 is bonded to the array wafer 4, and the array wafer 4 is disposed on the circuit wafer 3. Figure 10 (a)). The circuit wafer 3 and the array wafer 4 are bonded together by sandwiching transistor 12, multilayer film 22, columnar portion 24, etc., between substrate 11 and substrate 26. Through this bonding, metal pad 38 and metal pad 41 are joined together, and interlayer insulating film 13 and interlayer insulating film 21 are bonded together.

[0071] Secondly, substrate 26 was removed by CPM (Chemical Mechanical Polishing). Figure 10 (b)). As a result, the semiconductor layer 24b of each columnar portion 24 is exposed.

[0072] Next, a semiconductor layer 51a of a wiring layer 51 is formed on the interlayer insulating film 23 and each columnar portion 24. Figure 10 (a) Figure 1 The semiconductor layer 51a formed in step (a) is, for example, an amorphous silicon layer doped with P atoms. The semiconductor layer 51a is formed in a manner that is connected to the semiconductor layer 24b of each pillar 24, thereby being electrically connected to the semiconductor layer 24b of each pillar 24.

[0073] Secondly, the semiconductor layer 51a is annealed by laser annealing. Figure 4 (b)). As a result, the semiconductor layer 51a, which is an amorphous silicon layer, becomes a polycrystalline silicon layer.

[0074] Subsequently, a metal layer 51b of the wiring layer 51 is formed on the semiconductor layer 51a, and a passivation film 52 is formed on the metal layer 51b (see reference). Figure 10 In this way, the semiconductor device of this embodiment is manufactured.

[0075] In addition, in manufacturing Figure 10 When using the semiconductor device of the comparative example shown, for example by... Figure 11The annealing in step (b) causes P atoms to diffuse from semiconductor layer 51a to channel semiconductor layer 24c, forming an impurity diffusion layer 25 within channel semiconductor layer 24c. However, this method makes it difficult to ensure that the positions of the impurity diffusion layers 25 on different pillars 24 are close to the same location. Furthermore, to suppress the adverse effects of annealing on metal pads 38 and 41, it is desirable to... Figure 5 The annealing in step (b) is performed for only a short time. This also becomes an obstacle to the diffusion of P atoms from semiconductor layer 51a to channel semiconductor layer 24c.

[0076] On the other hand, in this embodiment, a semiconductor layer 24b, different from the channel semiconductor layer 24c, is formed instead of forming an impurity diffusion layer 25 within the channel semiconductor layer 24c. This eliminates problems similar to those in the comparative example semiconductor device.

[0077] Figure 9 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to a variation of the first embodiment.

[0078] First, in implementation Figure 11 (a)~ Figure 11 Following step (b), substrate 26 is removed by wet etching. Figure 11 (a)). As a result, the semiconductor layer 24b of each columnar portion 24 is exposed. Figure 10 In step (a), a portion of the interlayer insulating film 23 and the memory insulating film 24a may also be removed together with the substrate 26. In this case, as Figure 11 As shown in (a), a portion K1 of the semiconductor layer 24b of each columnar portion 24 protrudes from the interlayer insulating film 23 and the memory insulating film 24a.

[0079] Secondly, with Figure 11 The semiconductor layer 51a of the wiring layer 51 is formed on the interlayer insulating film 23 and each columnar portion 24, which is the same as step (a). Figure 10 (b)). As a result, semiconductor layer 51a is formed such that multiple portions K2 of semiconductor layer 51a protrude in the +Z direction. These portions K2 of semiconductor layer 51a are respectively formed in the +Z direction of portions K1 of semiconductor layer 24b of the corresponding columnar portion 24. Figure 1 In (b), part K1 protrudes into the semiconductor layer 51a.

[0080] Secondly, in implementation ​ Following step (b), a metal layer 51b of the wiring layer 51 is formed on the semiconductor layer 51a, and a passivation film 52 is formed on the metal layer 51b (see reference). ​). In this way, the semiconductor device of this modification example is manufactured. The configuration of the semiconductor device of this modification example is different from that of the semiconductor device of the present embodiment in that it includes the above-described portions K1 and K2.

[0081] As described above, each columnar portion 24 of the semiconductor device of the present embodiment includes the semiconductor layer 24b in addition to the channel semiconductor layer 24c. Therefore, according to the present embodiment, it is possible to improve the performance of the semiconductor layers (the channel semiconductor layer 24c and the semiconductor layer 24b) in each columnar portion 24. For example, according to the present embodiment, it is possible to easily make the positions of the semiconductor layers 24b of different columnar portions 24 close to the same position, and thereby make the values of the GIDL currents generated in different columnar portions 24 close to the same value.

[0082] The embodiments of the present application have been described, but these embodiments are presented as examples, and are not intended to limit the scope of the application. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the application. These embodiments and variations are included in the scope and spirit of the application, and are included in the application described in the claims and the equivalent scope thereof.

Claims

1. A semiconductor device comprising: Substrate; A circuit region is disposed on the substrate; The multilayer film comprises: multiple electrode layers and multiple insulating layers alternately disposed in a first direction above the circuit region; The first semiconductor layer is disposed within the stacked film and contains n-type or p-type impurity atoms; as well as A second semiconductor layer is disposed on the laminated film and the first semiconductor layer, electrically connected to the first semiconductor layer, and extends in a second direction intersecting the first direction; and The first semiconductor layer includes: a first portion that protrudes upward relative to the laminated film; The second semiconductor layer has a first surface that is in contact with the first portion and a second surface on the opposite side of the first portion, wherein a second portion of the second surface protrudes in the first direction.

2. The semiconductor device according to claim 1, wherein The first semiconductor layer has a solid columnar shape extending in the first direction.

3. The semiconductor device according to claim 1, further comprising a charge storage layer extending in the first direction in the stacked film.

4. The semiconductor device according to claim 1, wherein the concentration of the n-type impurity atoms or the p-type impurity atoms in the first semiconductor layer is 1.0 × 10⁻⁶. 19 cm -3 above.

5. The semiconductor device according to claim 1, further comprising a metal layer disposed on the second semiconductor layer.

6. The semiconductor device according to claim 1, wherein The multilayer electrode layer includes: one or more first selection lines; multiple word lines disposed above the first selection lines; and one or more second selection lines disposed above the word lines.

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