Semiconductor element and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and the method for manufacturing the semiconductor device mainly comprises the steps: forming a channel structure on a substrate, forming a channel extension part beside the channel structure after the channel structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers which are stacked in a staggered manner, a first gate structure is formed over the channel structure and the channel extension, and a first source / drain structure is formed aside the first gate structure.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for fabricating the same, and more particularly to a semiconductor device combining a nanowire transistor and a laterally diffused metal oxide semiconductor and a method for fabricating the same. Background Technology

[0002] In recent years, the semiconductor industry has been continuously shrinking the size of metal-oxide-semiconductor field-effect transistors (MOSFETs) to achieve high operating speeds and high device density. However, device size cannot be shrunk indefinitely. When shrunk to below 30 nanometers, severe short-channel effects and leakage current caused by the thickness of the gate dielectric layer increase the static power consumption of the device, and may even cause the device to completely lose its function. One-dimensional devices constructed from nanowires or nanotubes are considered to have the best chance of replacing the existing silicon technology due to their lower technological risks. Among them, nanowire transistors have high channel carrier mobility, and quantum effects can further enhance carrier mobility. Combined with the use of high dielectric constant dielectric layers, the gate control capability can be improved, making them a very promising transistor device. Summary of the Invention

[0003] An embodiment of the present invention discloses a method for fabricating a semiconductor device, which mainly involves first forming a channel structure on a substrate, wherein the channel structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately, then forming a channel extension next to the channel structure, forming a first gate structure on the channel structure and the channel extension, and then forming a first source / drain structure next to the first gate structure.

[0004] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a channel structure disposed on a substrate, a channel extension disposed beside the channel structure, a first gate structure disposed on the channel structure and the channel extension, and a first source / drain structure disposed beside the first gate structure. Attached Figure Description

[0005] Figures 1 to 10 This is a schematic diagram of a method for fabricating a nanowire transistor according to an embodiment of the present invention.

[0006] Symbol Explanation

[0007] 12: Base

[0008] 14: Channel Structure

[0009] 16: First semiconductor layer

[0010] 18: first semiconductor layer

[0011] 20: first semiconductor layer

[0012] 22: second semiconductor layer

[0013] 24: second semiconductor layer

[0014] 26: second semiconductor layer

[0015] 28: gate structure

[0016] 32: hard mask

[0017] 34: spacer

[0018] 36: spacer

[0019] 40: source / drain structure

[0020] 44: recess

[0021] 46: recess

[0022] 48: high-k dielectric layer

[0023] 50: work function metal layer

[0024] 52: low impedance metal layer

[0025] 54: gate structure

[0026] 56: first portion

[0027] 58: second portion

[0028] 60: interlayer dielectric layer

[0029] 62: contact plug

[0030] 102: shallow trench isolation

[0031] 104: P-well

[0032] 106: N-type drift region

[0033] 108: opening

[0034] 110: third semiconductor layer

[0035] 112: channel extension

[0036] 114: patterned mask

[0037] 128: gate structure

[0038] 132: hard mask

[0039] 154: Gate Structure Detailed Implementation

[0040] Please refer to Figures 1 to 10 , Figures 1 to 10 This is a schematic diagram illustrating a method for fabricating a nanowire transistor according to an embodiment of the present invention. Figure 1 As shown, a substrate 12, such as a silicon substrate, is first provided, and then a shallow trench isolation (STI) 102 is formed in the substrate 12. A well region, such as a P-well 104, is formed next to the shallow trench isolation 102, and a drift region, such as an N-type drift region 106, is formed around the shallow trench isolation. The shallow trench isolation 102 preferably contains silicon oxide.

[0041] Next, a stacked structure or channel structure 14 is formed on the substrate 12. In this embodiment, the channel structure 14 is preferably formed by alternating stacks of multiple first semiconductor layers 16, 18, 20 and second semiconductor layers 22, 24, 26. The first semiconductor layers 16, 18, 20 and the second semiconductor layers 22, 24, 26 preferably contain different materials or different lattice constants, and the first semiconductor layers 16, 18, 20 and the second semiconductor layers 22, 24, 26 can all be selected from the group consisting of silicon, germanium, doped silicon, doped germanium, and silicon germanide. In this embodiment, the first semiconductor layers 16, 18, 20 preferably contain silicon germanide and the second semiconductor layers 22, 24, 26 contain silicon, but are not limited thereto. It should be noted that although the channel structure 14 disclosed in this embodiment takes three first semiconductor layers 16, 18, 20 interspersed with three second semiconductor layers 22, 24, 26 as an example, the number of first semiconductor layers 16, 18, 20 and second semiconductor layers 22, 24, 26 is not limited to this, and can be arbitrarily adjusted according to the manufacturing process or product requirements.

[0042] Subsequently, as Figure 2 As shown, a photolithography and etching process is performed, for example, using a patterned photoresist (not shown) as a mask to remove part of the channel structure 14 to form an opening 108 on the substrate 12 to expose the P-well 104 and the N-type drift region 106.

[0043] Then as Figure 3 As shown, an epitaxial growth process is performed to form a third semiconductor layer 110 within the opening 108, wherein the third semiconductor layer 110 preferably constitutes a channel extension 112. In this embodiment, the second semiconductor layers 22, 24, 26 and the third semiconductor layer 110 preferably contain the same material, such as silicon, but are not limited thereto. For example, according to other embodiments of the present invention, the third semiconductor layer 110 may contain the same material as the first semiconductor layers 16, 18, 20, such as silicon germanide, and this variation is also within the scope of the present invention.

[0044] Please continue to refer to Figures 4 to 6 , Figures 4 to 6 This is a schematic diagram of a method for preparing the channel structure 14 according to another embodiment of the present invention. Figure 4 As shown, compared to the previous embodiment where the first semiconductor layers 16, 18, 20 and the second semiconductor layers 22, 24, 26 are first formed in an alternating stack and then the second semiconductor layers 22, 24, 26 and the first semiconductor layers 16, 18, 20 are patterned using photolithography and etching processes, this embodiment can first form a patterned mask 114 on the substrate 12, wherein the patterned mask 114 can simultaneously overlap the P-well 104 and the N-type drift region 106.

[0045] Then, as follows Figure 5 As shown, an epitaxial growth process is used to form a channel structure 14 on both sides of a patterned mask 114, which is formed by alternating stacking of patterned first semiconductor layers 16, 18, 20 and patterned second semiconductor layers 22, 24, 26. Then, the patterned mask 114 is removed to form an opening 108.

[0046] Then as Figure 6 As shown, another epitaxial growth process is performed to form a third semiconductor layer 110 within the opening 108 as a channel extension 112. As previously mentioned, the second semiconductor layers 22, 24, 26 and the third semiconductor layer 110 preferably contain the same material, such as silicon, but are not limited thereto. For example, according to other embodiments of the present invention, the third semiconductor layer 110 may contain the same material as the first semiconductor layers 16, 18, 20, such as silicon germanide, and this variation is also within the scope of the present invention.

[0047] Subsequently, as Figure 7 As shown, a portion of the channel structure 14 is first removed using photolithography and etching processes to form a gate structure 28 and a selective hard mask 32 on the channel structure 14 and the channel extension 112, and another gate structure 128 and a hard mask 132 next to the gate structure 32. Spacer walls 34 are formed next to each gate structure 28 and 128. A portion of the first semiconductor layers 16, 18, and 20 is removed, and another spacer wall 36 is formed next to the first semiconductor layers 16, 18, and 20. The sidewalls of spacer wall 36 are preferably flush with the sidewalls of the second semiconductor layers 22, 24, and 26 and the sidewall of spacer wall 34 above them. Spacer wall 34 may contain the same or different materials as spacer wall 36.

[0048] In this embodiment, the gate structures 28 and 128 may be made of polysilicon, the hard masks 32 and 132 may contain silicon nitride, and the spacer walls 34 and 36 may be selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, and silicon carbide, but are not limited thereto. It should also be noted that although spacer walls 34 and 36 in this embodiment are each a single-layer spacer wall, they may be composite spacer walls depending on the fabrication process requirements. For example, spacer walls 34 and 36 may further include one or more spacer walls, and the composite spacer walls may be made of the same or different materials. According to one embodiment of the present invention, the composite spacer wall may include, for example, a double-layer composite spacer wall composed of silicon dioxide and silicon nitride, or a triple-layer composite spacer wall composed of silicon oxide-silicon nitride-silicon oxide, all of which are within the scope of the present invention.

[0049] Next, a source / drain structure 40 is formed on the substrate 12 on both sides of the spacer wall 36, such as the left side of the gate structure 28 and the right side of the gate structure 128. The source / drain structure 40 can be made of a semiconductor material or a metal material. In this embodiment, if the source / drain structure 40 is made of a semiconductor material, it can be selected from the group consisting of germanium, doped silicon, germanium-doped silicon, and silicon germanide. If the source / drain structure 40 is made of a metal, it can be selected from the group consisting of tungsten, titanium, titanium nitride, tantalum, tantalum nitride, and aluminum.

[0050] Subsequently, as Figure 8 As shown, an etching process is first performed to remove the hard mask 32 and the gate structure 28 to form a groove 44, and then another selective etching process is performed to remove the first semiconductor layers 16, 18, and 20 to form multiple grooves 46. Since the first semiconductor layers 16, 18, and 20 and the second semiconductor layers 22, 24, and 26 are made of different materials and there is a predetermined etching selectivity between them, in this embodiment, it is preferable that the etching removal of the first semiconductor layers 16, 18, and 20 does not damage any of the second semiconductor layers 22, 24, and 26.

[0051] According to one embodiment of the present invention, the first semiconductor layers 16, 18, 20 and the gate structure 28 can be made of the same material, for example, all containing polycrystalline silicon, while the second semiconductor layers 22, 24, 26 can be selected from the group consisting of single-crystal silicon, germanium, doped silicon, doped germanium, and silicon germanide. In this way, the hard mask 32 and the first semiconductor layers 16, 18, 20 can be removed simultaneously using an etching process. This embodiment is also within the scope of the present invention. Alternatively, after removing the first semiconductor layers 16, 18, 20 by etching, a portion of the second semiconductor layers 22, 24, 26 can be selectively removed by oxidation or another etching process, etching the originally approximately cubic second semiconductor layers 22, 24, 26 into an approximately arc shape to form the nanowire channel structure 14. This embodiment is also within the scope of the present invention.

[0052] Then as Figure 9 As shown, a high-dielectric-constant dielectric layer 48, a work-function metal layer 50, and a low-impedance metal layer 52 are sequentially formed in recesses 44 and 46, and then planarized to form a gate structure 54 and another gate structure 154 beside the gate structure 54. In this embodiment, the gate structure 54 preferably comprises two parts, wherein the first part 56 is disposed directly above the second semiconductor layers 22, 24, and 26, and the second part 58 is staggered with the second semiconductor layers 22, 24, and 26. From another perspective, the high-dielectric-constant dielectric layer 48 and the work-function metal layer 50 cover the second semiconductor layers 22, 24, and 26, while the low-impedance metal layer 52 fills the recesses 44 and 46.

[0053] In this embodiment, the high dielectric constant dielectric layer 48 comprises a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), and strontium bismuth tantalum oxide. SrBi₂Ta₂O₉ (SBT) and lead zirconate titanate (PbZr) x Ti 1-x O3, PZT), barium strontium titanate (Ba x Sr 1-x The group consisting of TiO3, BST, or combinations thereof.

[0054] The work function metal layer 50 is preferably used to adjust the work function of the metal gate to make it suitable for N-type transistors (NMOS) or P-type transistors (PMOS). If the transistor is an N-type transistor, the work function metal layer 50 can be made of a metal material with a work function of 3.9 eV to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide), but is not limited thereto. If the transistor is a P-type transistor, the work function metal layer 50 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but is not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 50 and the low impedance metal layer 52. The barrier layer may be made of materials such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). The low impedance metal layer 52 may be selected from low-resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium-aluminum alloy (TiAl), cobalt-tungsten phosphide (CoWP), or combinations thereof. Since converting a dummy gate into a metal gate using a metal gate replacement process is a well-known technique in this field, it will not be elaborated upon here. Afterwards, a portion of the high dielectric constant dielectric layer 48, a portion of the work function metal layer 50, and a portion of the low impedance metal layer 52 may be removed to form a groove (not shown).

[0055] Then as Figure 10 As shown, an interlayer dielectric layer 60 is formed on the source / drain structure 40 and fills the groove. In this embodiment, the interlayer dielectric layer 60 can be made of any insulating material containing oxides, such as an oxide layer made of tetraethyl orthosilicate (TES), but is not limited thereto. Then, a contact plug fabrication process is performed to form a contact plug 62 that electrically connects the gate structure 54 and the source / drain structure 40. In this embodiment, the contact plug 62 can be formed by first using an etching process to completely remove part of the interlayer dielectric layer 60 to form a contact hole (not shown) and expose the surface of the source / drain structure 40, then sequentially depositing a barrier layer and a metal layer in the contact hole and filling the contact hole, and then using a planarization process, such as a CMP process, to remove part of the metal layer and part of the barrier layer to form the contact plug 62 in the opening, wherein the upper surface of the contact plug 62 is preferably flush with the upper surface of the interlayer dielectric layer 60. In this embodiment, the barrier layer is preferably selected from the group consisting of titanium, tantalum, titanium nitride, tantalum nitride, and tungsten nitride, and the metal layer is preferably selected from the group consisting of aluminum, titanium, tantalum, tungsten, niobium, molybdenum, and copper, but is not limited thereto. This completes the fabrication of a semiconductor device according to a preferred embodiment of the present invention.

[0056] Please continue to refer to Figure 10 , Figure 10 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention is also disclosed. For example... Figure 10 As shown, the semiconductor device mainly includes a shallow trench isolation 102 disposed in the substrate 12, a P-well 104 disposed beside the shallow trench isolation 102, an N-type drift region 106 surrounding the shallow trench isolation 102, a channel structure 14 disposed on the substrate 12, a channel extension 112 disposed beside the channel structure 14, a gate structure 54 disposed on the channel structure 14 and the channel extension 112, another gate structure 154 disposed beside the gate structure 54, and a source / drain structure 40 disposed beside the gate structures 54 and 154.

[0057] In detail, the first portion 56 of the gate structure 54 is preferably disposed on the channel structure 14 and extends to the top surface and sidewall of the channel extension 112. The first portion 56 of the gate structure 54 has an L-shape. The second portion 58 of the gate structure 54 is staggered with the second semiconductor layers 22, 24, and 26 of the channel structure 14. Both the gate structures 54 and 154 each contain a metal gate. The channel extension 112 contains the same material, such as silicon, as the second semiconductor layers 22, 24, and 26 in the channel structure 14. Although the channel extension 112 in this embodiment overlaps both the P-well 104 and the N-type drift region 106, it is not limited to this. According to other embodiments of the present invention, the boundary position between the P-well 104 and the N-type drift region 106 can be adjusted. For example, the boundary between the P-well 104 and the N-type drift region 106 can be moved slightly to the left to align with the right sidewall of the channel structure 14. In other words, under this structure, the left sidewall of the channel extension 112 is aligned with the right sidewall of the P-well 104 so that the channel extension 112 only overlaps the N-type drift region 106 and does not overlap the P-well 104. This variation is also within the scope of the present invention.

[0058] In summary, the present application discloses a semiconductor device and its manufacturing method, which integrates nanowire or gate-all-around (GAA) transistor technology into a lateral diffusion metal oxide semiconductor. The method includes forming a channel structure 14 on a substrate, wherein the channel structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately, forming a channel extension 112 beside the channel structure, forming a gate structure 28 on the channel structure and the channel extension, forming another gate structure 128 beside the gate structure 54, and forming source / drain structures 40 on one side of the gate structure 54 and on the other side of the gate structure 154. Although a general nanowire transistor has better control over the short channel effect (SCE) and has advantages such as low leakage, it is still vulnerable to high voltage applications. Therefore, the present application combines nanowire transistors and lateral diffusion metal oxide semiconductor devices to provide lower electric fields, thereby improving the breakdown voltage and the current (Ioff) when the transistor is off.

[0059] The above description is only the preferred embodiment of the present application, and any equivalent changes and modifications made according to the claims of the present application should be within the scope of the present application.

Claims

1. A method of manufacturing a semiconductor device, characterized by, Comprising: forming a channel structure on a substrate, wherein the channel structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers interleavedly stacked; forming a channel extension next to the channel structure; forming a first gate structure on the channel structure and the channel extension; and forming a first source / drain structure next to the first gate structure.

2. The method of claim 1, further comprising: forming the plurality of first semiconductor layers and the plurality of second semiconductor layers on the substrate; removing the plurality of first semiconductor layers and the plurality of second semiconductor layers to form an opening; and forming a third semiconductor layer within the opening to form the channel extension.

3. The method of claim 2, wherein the plurality of second semiconductor layers and the third semiconductor layer comprise a same material.

4. The method of claim 1, wherein a top surface of the channel structure is flush with a top surface of the channel extension.

5. The method of claim 1, further comprising: forming a shallow trench isolation within the substrate; forming a well region next to the shallow trench isolation; forming a drift region surrounding the shallow trench isolation; forming the channel structure and the channel extension on the well region; forming the first gate structure on the channel structure; forming a second gate structure on the drift region; forming a spacer next to the first gate structure and the second gate structure; forming the first source / drain structure next to the first gate structure; forming a second source / drain structure next to the second gate structure; removing the first gate structure and the second gate structure to form a first recess; removing the plurality of first semiconductor layers to form a second recess between the plurality of second semiconductor layers; and forming a function metal layer within the first recess and the second recess.

6. The method of claim 5, wherein the well region and the drift region comprise different conductivity types.

7. The method of claim 5, wherein the first gate structure overlaps the shallow trench isolation.

8. The method of claim 1, further comprising forming the first gate structure on the channel structure and sidewalls of the channel extension.

9. The method of claim 1, wherein the first gate structure comprises an L-shape. Comprising: a channel structure on a substrate; a channel extension next to the channel structure; 10. A semiconductor element characterized by comprising: a first gate structure on the channel structure and the channel extension; and a first source / drain structure next to the first gate structure.

11. The semiconductor element of claim 10, further comprising: a shallow trench isolation within the substrate; a well region next to the shallow trench isolation; a drift region surrounding the shallow trench isolation; the channel structure and the channel extension on the well region; the first gate structure on the channel structure and the channel extension; a second gate structure on the drift region; the first source / drain structure next to the first gate structure; and a second source / drain structure next to the second gate structure.

12. The semiconductor element of claim 11, wherein the well region and the drift region comprise different conductivity types.

13. The semiconductor element of claim 11, wherein the first gate structure overlaps the shallow trench isolation. ​ ​ ​ 14. The semiconductor device of claim 10, wherein the first gate structure is disposed on the channel structure and the channel extension sidewall.

15. The semiconductor device of claim 10, wherein the first gate structure comprises an L-shape.

16. The semiconductor device of claim 10, wherein the first gate structure comprises a metal gate.

17. The semiconductor device of claim 10, wherein the channel structure comprises a plurality of first semiconductor layers.

18. The semiconductor device of claim 17, wherein the channel extension comprises a second semiconductor layer.

19. The semiconductor device of claim 18, wherein the plurality of first semiconductor layers and the second semiconductor layer comprise the same material.

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