A silicon carbide trench mosfet device with a three-dimensional surround gate structure and a method of fabrication

Abstract

The application discloses a three-dimensional surround gate structure silicon carbide trench MOSFET device and a preparation method, and relates to the technical field of semiconductors. The method comprises the following steps: growing silicon carbide epitaxy on a silicon carbide substrate, and implanting to form a P-well region; forming a first blocking layer on the P-well region, implanting to form a P+ region; removing the first blocking layer, forming a second blocking layer of a surround gate trench array, implanting to form an N+ region; removing the second blocking layer, simultaneously performing rapid thermal annealing on the P-well region, the P+ region and the N+ region; forming a third blocking layer, performing etching to form a gate trench region; removing the third blocking layer, performing dry oxygen thermal oxidation to form a gate oxide layer; using chemical vapor deposition to form polysilicon; after doping the polysilicon, performing etching to form a gate; depositing metal to form a drain and a source, and performing rapid thermal annealing on the drain and the source to form ohmic contact. Arrayed distribution of the gate is constructed, and on-resistance is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a silicon carbide trench MOSFET device with a three-dimensional surrounding gate structure and its fabrication method. Background Technology

[0002] Silicon carbide, as a typical wide-bandgap semiconductor, possesses advantages such as a high critical breakdown electric field, high thermal conductivity, and high carrier saturation velocity, making it naturally suited for high-power power electronics applications involving high voltage, high temperature, and high frequency. Compared to silicon-based power devices, silicon carbide MOSFETs achieve lower conduction losses and faster switching speeds at the same voltage rating, thus becoming an important device choice for scenarios such as electric drive and charging for new energy vehicles, photovoltaic and energy storage inverters, power supplies for communications and data centers, rail transportation, and industrial power supplies.

[0003] Although 4H-SiC-based device technology has been applied on a large scale, carrier scattering and interface state effects at the actual MOS interface result in a significantly low channel electron mobility, which is typically only 10~40 cm2 / V·s. This leads to an increase in the proportion of channel resistance, making it difficult to fully utilize the potential advantages of silicon carbide materials in terms of low on-resistance and low loss.

[0004] In the current commercialization process, horizontal channel MOSFETs with dual-trench designs have found applications in low to medium voltage platforms (hundreds of volts to approximately 1.2 kV) due to their electric field modulation capabilities achieved through the combination of gate-shielded trenches. However, these devices are essentially still dominated by lateral channels and lateral current paths. The length of the drift region and the effective conductive channel are constrained by the chip area. When the voltage rating increases, it is often necessary to lengthen the lateral drift region or reduce doping to meet the breakdown requirements, which leads to problems such as increased specific on-resistance and increased chip area. This makes it difficult to cover industrial applications with higher voltage ratings and presents a structural bottleneck in further reducing on-resistance.

[0005] Vertical trench gate SiC MOSFETs, by embedding the gate in a deep trench and forming an inverted channel on the trench sidewalls, enable current conduction in the vertical direction, significantly increasing the channel area and channel mobility per unit volume, thereby effectively reducing channel-related resistance and increasing current density. Although they have achieved a clear conduction advantage over planar and horizontal channel structures, the channels of mainstream trench gate devices are usually only formed on the two sidewalls of the trench. The two-sided sidewall channel still limits the channel area utilization. After the drift region resistance is further compressed by the high critical electric field of silicon carbide, the channel resistance once again becomes the main component.

[0006] Therefore, how to increase the number of sidewalls formed by the channel and increase the effective channel size that can be connected in parallel per unit area without significantly increasing the chip area has become a key technical problem for reducing on-resistance and improving device power density. Summary of the Invention

[0007] The purpose of this invention is to provide a silicon carbide trench MOSFET device with a three-dimensional surrounding gate structure and a method for its fabrication, aiming to solve or improve at least one of the above-mentioned technical problems.

[0008] To achieve the above objectives, the present invention provides the following solution:

[0009] A method for fabricating a silicon carbide trench MOSFET device with a three-dimensional all-around gate structure, comprising:

[0010] Silicon carbide epitaxial growth is performed on a silicon carbide substrate, and multiple aluminum ion implantations or co-implantation of aluminum and boron ions are performed on the silicon carbide epitaxial growth to form a P-well region.

[0011] A first barrier layer is formed on the P-well region, and multiple aluminum ion implantations or co-implantation of aluminum ions and boron ions are performed to form the P+ region.

[0012] The first barrier layer is removed to form a second barrier layer surrounding the grid trench array, and multiple nitrogen ion implantations are performed to form the N+ region; wherein, the second barrier layer includes an edge and a middle part, the edge is above the P+ region, and the middle part is located in the center of the P-well region, and is distributed in an array in the longitudinal direction.

[0013] Remove the second barrier layer and simultaneously perform rapid thermal annealing on the P-well region, P+ region, and N+ region;

[0014] A third barrier layer is formed, and etching is performed to form the gate trench region;

[0015] Remove the third barrier layer, perform RCA cleaning, and then perform dry oxygen thermal oxidation in the furnace tube to remove the oxide layer above the P+ and N+ regions, forming a gate oxide layer in the gate trench region.

[0016] The gate oxide layer is deposited in multiple steps using chemical vapor deposition to form polycrystalline silicon; after doping the polycrystalline silicon, it is etched to form an array-distributed gate.

[0017] A silicon carbide trench MOSFET device with a three-dimensional surrounding gate structure is fabricated by depositing metal on the back side of a silicon carbide substrate to form a drain, depositing metal on top of the P+ region and part of the N+ region to form a source, and performing rapid thermal annealing on the drain and source to form an ohmic contact.

[0018] Furthermore, the doping concentration of the silicon carbide substrate is 1e. 18 cm -3 ~1e 20 cm -3 The thickness ranges from 200µm to 1000µm; the doping concentration of the silicon carbide epitaxial layer is 1e. 15cm -3 ~5e 16 cm -3 The thickness ranges from 6µm to 40µm; the P-well region is formed at 500℃-800℃, with a net acceptor concentration of 5e. 16 cm -3 ~5e 17 cm -3 .

[0019] Furthermore, the P+ region is formed at 500℃–700℃ with a doping concentration of 1e. 19 cm -3 ~1e 20 cm -3 The thickness is 0.2µm~0.5µm.

[0020] Furthermore, the middle part of the second barrier layer is a rectangle with a horizontal width of 1.4µm and a vertical width of 1.0µm, with a spacing of 0.4µm.

[0021] Furthermore, the middle part of the second barrier layer is a circle with a diameter of 1.0µm and a spacing of 0.4µm.

[0022] Furthermore, the N+ region is formed at 400℃–600℃ with a doping concentration of 1e. 19 cm -3 ~1e 20 cm -3 The injection angle is 7°–10°, and the thickness is 0.2µm~0.5µm.

[0023] Furthermore, the dry oxygen thermal oxidation temperature is between 1000℃ and 1400℃; the sidewall thickness of the gate oxide layer is 0.01µm to 0.5µm, and the bottom thickness is 0.02µm to 0.7µm.

[0024] Furthermore, the chemical vapor deposition temperature is between 550℃ and 700℃; the polycrystalline silicon doping concentration is 1e. 18 ~1e 20 cm -3 .

[0025] Furthermore, the rapid hot annealing temperature is between 900℃ and 1100℃, and the time is between 30 seconds and 2 minutes.

[0026] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0027] This invention discloses a silicon carbide trench MOSFET device with a three-dimensional surrounding gate structure and its fabrication method. The method constructs an array of distributed gates to form a silicon carbide trench MOSFET with a three-dimensional surrounding gate structure, thereby forming multiple additional conductive channels, increasing the channel area, and reducing the on-resistance of the silicon carbide trench MOSFET device.

[0028] The channel resistance can be adjusted by controlling the shape of the arrayed distributed gate. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic flowchart of the method of the present invention;

[0031] Figures 2-12 This is a schematic diagram illustrating the fabrication steps of the silicon carbide trench MOSFET device with a three-dimensional surrounding gate structure in the embodiment;

[0032] Figure 13 This is a top view of the formation of the second barrier layer during the preparation process of Specific Embodiment 2;

[0033] Figure 14 This is a top view of the formation of the third barrier layer during the preparation process of Specific Embodiment 2;

[0034] In the figure, 101 is the silicon carbide substrate; 102 is the silicon carbide epitaxial layer; 103 is the P-well region; 104 is the P+ region; 105 is the N+ region; 106 is the gate trench region; 107 is the gate oxide layer; 108 is the gate; 109 is the drain; 110 is the source; 21 is the first barrier layer; 22 is the second barrier layer; and 23 is the third barrier layer. Detailed Implementation

[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] The purpose of this invention is to provide a silicon carbide trench MOSFET device with a three-dimensional surrounding gate structure and a method for its fabrication, aiming to solve or improve at least one of the above-mentioned technical problems.

[0037] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] like Figure 1 As shown, the present invention provides a silicon carbide trench MOSFET device with a three-dimensional surrounding gate structure and a method for fabricating it, comprising:

[0039] like Figure 2 As shown, in step 1, the silicon carbide substrate 101 is configured to be N-type doped, preferably 3C-SiC, 4H-SiC, or 6H-SiC, with a doping concentration of 1e. 18 cm -3 ~1e 20 cm -3 The thickness is 200~1000µm. Epitaxial growth with a doping concentration of 1e is performed on a silicon carbide substrate 101. 15 cm -3 ~5e 16 cm -3 The silicon carbide epitaxial layer 102, with a thickness of 6µm to 40µm, is the drift region, and the silicon carbide epitaxial layer 102 is set to N-type.

[0040] like Figure 3 As shown, in step 2, the silicon carbide epitaxial layer 102 is subjected to multiple aluminum ion implantations or co-implantation of aluminum and boron ions at 500℃-800℃ to form a P-well region 103; the P-well region 103 has a thickness of 0.5µm~1µm and a net acceptor concentration of 5e. 16 cm -3 ~5e 17 cm -3 .

[0041] like Figure 4 As shown, in step 3, a first barrier layer 21 is formed on the P-well region 103, and multiple aluminum ion implantations or co-implantation of aluminum ions and boron ions are performed on the unbarriered area of ​​the P-well region 103 to form a P+ region 104; the P+ region 104 is formed by multiple aluminum ion implantations or co-implantation of aluminum ions and boron ions at 500℃–700℃, with a doping concentration of 1e. 19 cm -3 ~1e 20 cm -3 The thickness is 0.2µm~0.5µm.

[0042] The P+ region 104 of the silicon carbide MOSFET device is the core of the body contact region, used to achieve a low-resistance connection between the P-well region 103 and the source 110, prevent parasitic BJT conduction, and improve device robustness.

[0043] Step 4: Remove the first barrier layer 21 to form a second barrier layer 22 surrounding the gate trench array. Perform multiple nitrogen ion implantations on the unbarriered region of the P-well region 103 to form the N+ region 105. The N+ region 105 is formed at 400℃–600℃ with a doping concentration of 1e. 19 cm -3 ~1e 20 cm -3 The injection is performed at a 7°–10° tilt angle to avoid channeling effects, with a thickness of 0.2µm–0.5µm. The second barrier layer 22 includes an edge portion and a central portion. The edge portion is located above the P+ region 104, and the central portion is located in the center of the P-well region 103, arranged in an array along the longitudinal direction; as shown... Figure 5 and Figure 6 The images shown are the front view and the top view.

[0044] Step 5: Remove the second barrier layer 22 and simultaneously perform rapid thermal annealing on P-well regions 103, P+ regions 104, and N+ regions 105. The rapid thermal annealing temperature is between 1600℃ and 1800℃, using an inert or protective atmosphere, for 1 to 10 minutes to ensure doping activation and lattice repair while minimizing surface damage. P-well regions 103, P+ regions 104, and N+ regions 105 must be activated in the same annealing step to avoid repeated high-temperature damage.

[0045] Step 6: Form a third barrier layer 23, and etch unbarriered areas on the P-well region 103, P+ region 104, and N+ region 105 to form a gate trench region 106; the gate trench region 106 has a thickness of 0.5µm~1.2µm, and is 0.05µm~0.5µm thicker than the P-well region 103. Figure 7 , Figure 8 and Figure 9 The figures shown are the front view, top view, and cross-sectional view along the middle. The etching process uses either inductively coupled plasma (ICP) etching or inductively coupled plasma combined with reactive ion etching (ICP-RIE).

[0046] Step 7: Remove the third barrier layer 23, perform RCA cleaning, and then perform dry oxygen thermal oxidation in the furnace tube to remove the oxide layer above the P+ region 104 and N+ region 105, forming a gate oxide layer 107 in the gate trench region 106; the dry oxygen thermal oxidation temperature is between 1000℃ and 1400℃; the sidewall thickness of the gate oxide layer 107 is 0.01µm to 0.5µm, and the bottom thickness is 0.02µm to 0.7µm.

[0047] Step 8: The gate oxide layer 107 is deposited in multiple steps using chemical vapor deposition to form polysilicon; after doping the polysilicon, etching is performed to form the gate 108; the chemical vapor deposition temperature is between 550℃ and 700℃, and the pressure is between 27 and 270 Pa; the polysilicon doping concentration is 1e. 18 ~1e 20 cm -3 .like Figure 10 and Figure 11 The images shown are the front view and the top view, respectively.

[0048] like Figure 12 As shown, in step 9, metal is deposited on the back side of the silicon carbide substrate 101 to form a drain 109, and metal is deposited on the P+ region 104 and part of the N+ region 105 to form a source 110. The drain 109 and the source 110 are then subjected to rapid thermal annealing to form an ohmic contact, thus completing the fabrication of a silicon carbide trench MOSFET device with a three-dimensional surrounding gate structure.

[0049] The drain 109 is formed on the back side of the silicon carbide substrate 101 by physical vapor deposition (PVD) through magnetron sputtering of high-energy ions to bombard the target (Ti, Al, Ni). A portion of the N+ region 105 is preferably covered to the center of the N+ region 105. Rapid thermal annealing is performed at a temperature between 900°C and 1100°C for 30 seconds to 2 minutes, forming metal silicides through interfacial reactions, reducing contact resistance, and forming an ohmic contact.

[0050] like Figure 12 The diagram shows a complete three-dimensional surround gate structure silicon carbide trench MOSFET device, including: a silicon carbide substrate 101, a silicon carbide epitaxial layer 102, a P-well region 103, a P+ region 104, an N+ region 105, a gate oxide layer 107, an array-distributed gate 108, a drain 109, and a source 110. The drain 109 is located on the back side of the silicon carbide substrate 101, the silicon carbide epitaxial layer 102 is located on the front side of the silicon carbide substrate 101, the P-well region 103 is formed on the silicon carbide epitaxial layer 102, the P+ region 104 and the N+ region 105 are formed on the P-well region 103, the gate oxide layer 107 is located at the center of the P-well region 103 and the N+ region 105, the gate 108 is located on the gate oxide layer 107, and the source 110 is located on the entire P+ region 104 and a portion of the N+ region 105. Specific Implementation Example 1

[0052] Step 1: Both the silicon carbide substrate 101 and the silicon carbide epitaxial layer 102 are N-type doped. The doping concentration of the silicon carbide substrate 101 is 2e⁻. 18 cm -3 The thickness is 350µm; the silicon carbide epitaxial layer 102 is doped with 5e-. 15cm -3 The thickness is 12µm. At 600℃, the silicon carbide epitaxial layer 102 is subjected to multiple aluminum ion implantations or co-implantation of aluminum and boron ions to form a 0.7µm P-well region 103; the net acceptor concentration of the P-well region 103 is 1e⁻¹. 17 cm -3 .

[0053] Step 2: A first barrier layer 21 is formed above the P-well region 103. Multiple aluminum ion implantations or co-implantation of aluminum and boron ions are performed at 600°C to form the P+ region 104, with a doping concentration of 1e⁻¹. 19 cm -3 The thickness is 0.2µm.

[0054] like Figure 13 As shown, in step 3, the first barrier layer 21 is removed to form a second barrier layer 22 surrounding the gate trench array. Then, multiple nitrogen ion implantations are performed at 600°C to form the N+ region 105, with a doping concentration of 1e. 19 cm -3 The thickness is 0.2µm, and it is injected at an angle of 7°–10°. The edge of the second barrier layer 22 is above the P+ region 104, and the middle part is set as four rectangles with a horizontal width of 1.4µm and a vertical width of 1.0µm, with a spacing of 0.4µm.

[0055] Step 4: Remove the second barrier layer 22 and perform rapid thermal annealing on P-well region 103, P+ region 104 and N+ region 105 simultaneously for 5 minutes at 1700°C in an inert / protective atmosphere.

[0056] like Figure 13 As shown, in step 5, a third barrier layer 23 is formed, and an etching process is performed to form a gate trench region 106. The thickness of the gate trench region 106 is 0.8µm, which is 0.1µm thicker than the thickness of the P-well region 103.

[0057] Step 6: Remove the third barrier layer 23 and perform RCA standard cleaning. Then, perform dry oxygen thermal oxidation at 1200°C in a furnace tube to remove the oxide layers above the P+ region 104 and N+ region 105, forming the gate oxide layer 107. The sidewall thickness of the gate oxide layer 107 is 0.03µm, and the bottom thickness is 0.05µm. Multi-step deposition is performed at 600°C using LPCVD, followed by doping of the polysilicon to a doping concentration of 1e. 19 cm -3 Finally, the polysilicon is etched to form a rectangular array of gates 108.

[0058] Step 7: Using physical vapor deposition, high-energy ions, such as Ti, Al, or Ni, are bombarded onto the target material via magnetron sputtering to deposit atoms onto the back side of the silicon carbide substrate 101, forming the drain 109. A source 110 is also formed by sputtering deposits at the center of the P+ and N+ source regions. Subsequently, rapid thermal annealing at 1000°C for 1 minute is performed to form metal silicides through interfacial reactions, reducing contact resistance and creating an ohmic contact between the drain 109 and the source 110.

[0059] The silicon carbide trench MOSFET device with a three-dimensional surrounding gate structure obtained in the above embodiments has a 71.4% larger vertical channel conduction area and a 41.7% smaller channel resistance compared with the traditional trench structure. Specific Implementation Example 2

[0061] Step 1: Both the silicon carbide substrate 101 and the silicon carbide epitaxial layer 102 are N-type doped. The doping concentration of the silicon carbide substrate 101 is 2e⁻. 18 cm -3 The thickness is 350µm; the silicon carbide epitaxial layer 102 is doped with 5e-. 15 cm -3 The thickness is 12µm. At 600℃, the silicon carbide epitaxial layer 102 is subjected to multiple aluminum ion implantations or co-implantation of aluminum and boron ions to form a 0.7µm P-well region 103; the net acceptor concentration of the P-well region 103 is 1e⁻¹. 17 cm -3 .

[0062] Step 2: A first barrier layer 21 is formed above the P-well region 103. Multiple aluminum ion implantations or co-implantation of aluminum and boron ions are performed at 600°C to form the P+ region 104, with a doping concentration of 1e⁻¹. 19 cm -3 The thickness is 0.2µm.

[0063] Step 3: Remove the first barrier layer 21 to form a second barrier layer 22 surrounding the gate trench array. Then, perform multiple nitrogen ion implantations at 600°C to form the N+ region 105 with a doping concentration of 1e. 19 cm -3 The thickness is 0.2µm, and it is injected at an angle of 7°–10°. The edge of the second barrier layer 22 is above the P+ region 104, and the center is set as four circles with a diameter of 1.0µm and a spacing of 0.4µm.

[0064] Step 4: Remove the second barrier layer 22 and perform rapid thermal annealing on P-well region 103, P+ region 104 and N+ region 105 simultaneously for 5 minutes at 1700°C in an inert / protective atmosphere.

[0065] Step 5: Form the third barrier layer 23 and etch to form the gate trench region 106. The thickness of the gate trench region 106 is 0.8µm, which is 0.1µm thicker than the thickness of the P-well region 103.

[0066] Step 6: Remove the third barrier layer 23 and perform RCA standard cleaning. Then, perform dry oxygen thermal oxidation at 1200°C in a furnace tube to remove the oxide layers above the P+ region 104 and N+ region 105, forming the gate oxide layer 107. The sidewall thickness of the gate oxide layer 107 is 0.03µm, and the bottom thickness is 0.05µm. Multi-step deposition is then performed at 600°C using chemical vapor deposition, followed by doping of the polysilicon to a doping concentration of 1e. 19 cm -3 Finally, the polysilicon is etched to form a circular array of gates 108.

[0067] Step 7: Using physical vapor deposition, high-energy ions, such as Ti, Al, or Ni, are bombarded onto the target material via magnetron sputtering to deposit atoms onto the back side of the silicon carbide substrate 101, forming the drain 109. A source 110 is also formed by sputtering deposits at the center of the P+ and N+ source regions. Subsequently, rapid thermal annealing at 1000°C for 1 minute is performed to form metal silicides through interfacial reactions, reducing contact resistance and creating an ohmic contact between the drain 109 and the source 110.

[0068] The silicon carbide trench MOSFET device with a three-dimensional surrounding gate structure prepared in the above embodiments has a 12.2% increase in vertical channel conduction area and a 10.9% decrease in channel resistance.

[0069] As can be seen from the above two embodiments, the method of the present invention can increase the channel area and reduce the conduction resistance while adjusting the channel resistance by controlling the shape of the three-dimensional surrounding gate structure.

[0070] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0071] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for fabricating a silicon carbide trench MOSFET device with a three-dimensional surrounding gate structure, characterized in that, include: A silicon carbide epitaxial layer (102) is epitaxially grown on a silicon carbide substrate (101), and the silicon carbide epitaxial layer (102) is subjected to multiple aluminum ion implantations or aluminum ion and boron ion co-implantation to form a P-well region (103). A first barrier layer (21) is formed on the P-well region (103), and multiple aluminum ion implantations or aluminum ion and boron ion co-implantation are performed to form a P+ region (104). Remove the first barrier layer (21) to form a second barrier layer (22) surrounding the grid trench array, and perform multiple nitrogen ion implantations to form an N+ region (105); wherein, the second barrier layer (22) includes an edge and a middle part, the edge is above the P+ region (104), and the middle part is located in the center of the P-well region (103), and is distributed in an array in the longitudinal direction; Remove the second barrier layer (22) and simultaneously perform rapid thermal annealing on the P-well region (103), the P+ region (104) and the N+ region (105); A third barrier layer (23) is formed, and etching is performed to form a gate trench region (106). Remove the third barrier layer (23), perform RCA cleaning, and then perform dry oxygen thermal oxidation in the furnace tube to remove the oxide layer above the P+ region (104) and the N+ region (105), and form a gate oxide layer (107) in the gate trench region (106). The gate oxide layer (107) is deposited in multiple steps using chemical vapor deposition to form polycrystalline silicon; after doping the polycrystalline silicon, it is etched to form an array of gates (108). A drain (109) is formed by depositing metal on the back side of the silicon carbide substrate (101), and a source (110) is formed by depositing metal on the P+ region (104) and part of the N+ region (105). The drain (109) and the source (110) are then subjected to rapid thermal annealing to form ohmic contacts, thereby fabricating a silicon carbide trench MOSFET device with a three-dimensional surrounding gate structure. The middle part of the second barrier layer (22) is a rectangle with a horizontal width of 1.4µm and a vertical width of 1.0µm, with a spacing of 0.4µm.

2. The method for fabricating a silicon carbide trench MOSFET device with a three-dimensional surrounding gate structure according to claim 1, characterized in that, The silicon carbide substrate (101) has a doping concentration of 1e. 18 cm -3 ~1e 20 cm -3 The thickness is 200µm~1000µm; the doping concentration of the silicon carbide epitaxial layer (102) is 1e. 15 cm -3 ~5e 16 cm -3 The thickness is 6µm~40µm; the P-well region (103) is formed at 500℃-800℃ with a net acceptor concentration of 5e. 16 cm -3 ~5e 17 cm -3 .

3. The method for fabricating a silicon carbide trench MOSFET device with a three-dimensional surrounding gate structure according to claim 1, characterized in that, The P+ region (104) is formed at 500℃–700℃ with a doping concentration of 1e. 19 cm -3 ~1e 20 cm -3 The thickness is 0.2µm~0.5µm.

4. The method for fabricating a silicon carbide trench MOSFET device with a three-dimensional surrounding gate structure according to claim 1, characterized in that, The middle part of the second barrier layer (22) is a circle with a diameter of 1.0µm and a spacing of 0.4µm.

5. The method for fabricating a silicon carbide trench MOSFET device with a three-dimensional surrounding gate structure according to claim 1, characterized in that, The N+ region (105) is formed at 400℃–600℃ with a doping concentration of 1e. 19 cm -3 ~1e 20 cm -3 The injection angle is 7°–10°, and the thickness is 0.2µm~0.5µm.

6. The method for fabricating a silicon carbide trench MOSFET device with a three-dimensional surrounding gate structure according to claim 1, characterized in that, The dry oxygen thermal oxidation temperature is between 1000℃ and 1400℃; the sidewall thickness of the gate oxide layer (107) is 0.01µm to 0.5µm, and the bottom thickness is 0.02µm to 0.7µm.

7. The method for fabricating a silicon carbide trench MOSFET device with a three-dimensional surrounding gate structure according to claim 1, characterized in that, The chemical vapor deposition temperature is between 550°C and 700°C; the polycrystalline silicon doping concentration is 1e. 18 ~1e 20 cm -3 .

8. The method for fabricating a silicon carbide trench MOSFET device with a three-dimensional surrounding gate structure according to claim 1, characterized in that, The rapid thermal annealing temperature is between 900℃ and 1100℃, and the time is between 30 seconds and 2 minutes.

9. A silicon carbide trench MOSFET device with a three-dimensional all-around gate structure prepared by the method according to any one of claims 1-8, characterized in that, The system includes a silicon carbide substrate (101), a silicon carbide epitaxial layer (102), a P-well region (103), a P+ region (104), an N+ region (105), a gate oxide layer (107), an array of gates (108), drains (109), and sources (110). The drain (109) is located on the back side of the silicon carbide substrate (101), the silicon carbide epitaxial layer (102) is located on the front side of the silicon carbide substrate (101), and the P-well region (103) is shaped like a silicon carbide substrate (104). The P+ region (104) and the N+ region (105) are formed on the silicon carbide epitaxial layer (102), the gate oxide layer (107) is located at the center of the P-well region (103) and the N+ region (105), the gate (108) is located on the gate oxide layer (107), and the source (110) is located on the P+ region (104) in all regions and the N+ region (105) in part of the regions.

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